2 +++ b/Documentation/devicetree/bindings/rtc/armada-380-rtc.txt
4 +* Real Time Clock of the Armada 38x SoCs
6 +RTC controller for the Armada 38x SoCs
9 +- compatible : Should be "marvell,armada-380-rtc"
10 +- reg: a list of base address and size pairs, one for each entry in
12 +- reg names: should contain:
13 + * "rtc" for the RTC registers
14 + * "rtc-soc" for the SoC related registers and among them the one
15 + related to the interrupt.
16 +- interrupts: IRQ line for the RTC.
21 + compatible = "marvell,armada-380-rtc";
22 + reg = <0xa3800 0x20>, <0x184a0 0x0c>;
23 + reg-names = "rtc", "rtc-soc";
24 + interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
26 --- a/drivers/rtc/Kconfig
27 +++ b/drivers/rtc/Kconfig
28 @@ -1262,6 +1262,16 @@ config RTC_DRV_MV
29 This driver can also be built as a module. If so, the module
30 will be called rtc-mv.
32 +config RTC_DRV_ARMADA38X
33 + tristate "Armada 38x Marvell SoC RTC"
34 + depends on ARCH_MVEBU
36 + If you say yes here you will get support for the in-chip RTC
37 + that can be found in the Armada 38x Marvell's SoC device
39 + This driver can also be built as a module. If so, the module
40 + will be called armada38x-rtc.
45 --- a/drivers/rtc/Makefile
46 +++ b/drivers/rtc/Makefile
47 @@ -24,6 +24,7 @@ obj-$(CONFIG_RTC_DRV_88PM860X) += rtc-8
48 obj-$(CONFIG_RTC_DRV_88PM80X) += rtc-88pm80x.o
49 obj-$(CONFIG_RTC_DRV_AB3100) += rtc-ab3100.o
50 obj-$(CONFIG_RTC_DRV_AB8500) += rtc-ab8500.o
51 +obj-$(CONFIG_RTC_DRV_ARMADA38X) += rtc-armada38x.o
52 obj-$(CONFIG_RTC_DRV_AS3722) += rtc-as3722.o
53 obj-$(CONFIG_RTC_DRV_AT32AP700X)+= rtc-at32ap700x.o
54 obj-$(CONFIG_RTC_DRV_AT91RM9200)+= rtc-at91rm9200.o
56 +++ b/drivers/rtc/rtc-armada38x.c
59 + * RTC driver for the Armada 38x Marvell SoCs
61 + * Copyright (C) 2015 Marvell
63 + * Gregory Clement <gregory.clement@free-electrons.com>
65 + * This program is free software; you can redistribute it and/or
66 + * modify it under the terms of the GNU General Public License as
67 + * published by the Free Software Foundation; either version 2 of the
68 + * License, or (at your option) any later version.
72 +#include <linux/delay.h>
73 +#include <linux/io.h>
74 +#include <linux/module.h>
75 +#include <linux/of.h>
76 +#include <linux/platform_device.h>
77 +#include <linux/rtc.h>
79 +#define RTC_STATUS 0x0
80 +#define RTC_STATUS_ALARM1 BIT(0)
81 +#define RTC_STATUS_ALARM2 BIT(1)
82 +#define RTC_IRQ1_CONF 0x4
83 +#define RTC_IRQ1_AL_EN BIT(0)
84 +#define RTC_IRQ1_FREQ_EN BIT(1)
85 +#define RTC_IRQ1_FREQ_1HZ BIT(2)
87 +#define RTC_ALARM1 0x10
89 +#define SOC_RTC_INTERRUPT 0x8
90 +#define SOC_RTC_ALARM1 BIT(0)
91 +#define SOC_RTC_ALARM2 BIT(1)
92 +#define SOC_RTC_ALARM1_MASK BIT(2)
93 +#define SOC_RTC_ALARM2_MASK BIT(3)
95 +struct armada38x_rtc {
96 + struct rtc_device *rtc_dev;
98 + void __iomem *regs_soc;
104 + * According to the datasheet, the OS should wait 5us after every
105 + * register write to the RTC hard macro so that the required update
106 + * can occur without holding off the system bus
108 +static void rtc_delayed_write(u32 val, struct armada38x_rtc *rtc, int offset)
110 + writel(val, rtc->regs + offset);
114 +static int armada38x_rtc_read_time(struct device *dev, struct rtc_time *tm)
116 + struct armada38x_rtc *rtc = dev_get_drvdata(dev);
117 + unsigned long time, time_check, flags;
119 + spin_lock_irqsave(&rtc->lock, flags);
121 + time = readl(rtc->regs + RTC_TIME);
123 + * WA for failing time set attempts. As stated in HW ERRATA if
124 + * more than one second between two time reads is detected
125 + * then read once again.
127 + time_check = readl(rtc->regs + RTC_TIME);
128 + if ((time_check - time) > 1)
129 + time_check = readl(rtc->regs + RTC_TIME);
131 + spin_unlock_irqrestore(&rtc->lock, flags);
133 + rtc_time_to_tm(time_check, tm);
138 +static int armada38x_rtc_set_time(struct device *dev, struct rtc_time *tm)
140 + struct armada38x_rtc *rtc = dev_get_drvdata(dev);
142 + unsigned long time, flags;
144 + ret = rtc_tm_to_time(tm, &time);
149 + * Setting the RTC time not always succeeds. According to the
150 + * errata we need to first write on the status register and
151 + * then wait for 100ms before writing to the time register to be
152 + * sure that the data will be taken into account.
154 + spin_lock_irqsave(&rtc->lock, flags);
156 + rtc_delayed_write(0, rtc, RTC_STATUS);
158 + spin_unlock_irqrestore(&rtc->lock, flags);
162 + spin_lock_irqsave(&rtc->lock, flags);
164 + rtc_delayed_write(time, rtc, RTC_TIME);
166 + spin_unlock_irqrestore(&rtc->lock, flags);
171 +static int armada38x_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
173 + struct armada38x_rtc *rtc = dev_get_drvdata(dev);
174 + unsigned long time, flags;
177 + spin_lock_irqsave(&rtc->lock, flags);
179 + time = readl(rtc->regs + RTC_ALARM1);
180 + val = readl(rtc->regs + RTC_IRQ1_CONF) & RTC_IRQ1_AL_EN;
182 + spin_unlock_irqrestore(&rtc->lock, flags);
184 + alrm->enabled = val ? 1 : 0;
185 + rtc_time_to_tm(time, &alrm->time);
190 +static int armada38x_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
192 + struct armada38x_rtc *rtc = dev_get_drvdata(dev);
193 + unsigned long time, flags;
197 + ret = rtc_tm_to_time(&alrm->time, &time);
202 + spin_lock_irqsave(&rtc->lock, flags);
204 + rtc_delayed_write(time, rtc, RTC_ALARM1);
206 + if (alrm->enabled) {
207 + rtc_delayed_write(RTC_IRQ1_AL_EN, rtc, RTC_IRQ1_CONF);
208 + val = readl(rtc->regs_soc + SOC_RTC_INTERRUPT);
209 + writel(val | SOC_RTC_ALARM1_MASK,
210 + rtc->regs_soc + SOC_RTC_INTERRUPT);
213 + spin_unlock_irqrestore(&rtc->lock, flags);
219 +static int armada38x_rtc_alarm_irq_enable(struct device *dev,
220 + unsigned int enabled)
222 + struct armada38x_rtc *rtc = dev_get_drvdata(dev);
223 + unsigned long flags;
225 + spin_lock_irqsave(&rtc->lock, flags);
228 + rtc_delayed_write(RTC_IRQ1_AL_EN, rtc, RTC_IRQ1_CONF);
230 + rtc_delayed_write(0, rtc, RTC_IRQ1_CONF);
232 + spin_unlock_irqrestore(&rtc->lock, flags);
237 +static irqreturn_t armada38x_rtc_alarm_irq(int irq, void *data)
239 + struct armada38x_rtc *rtc = data;
241 + int event = RTC_IRQF | RTC_AF;
243 + dev_dbg(&rtc->rtc_dev->dev, "%s:irq(%d)\n", __func__, irq);
245 + spin_lock(&rtc->lock);
247 + val = readl(rtc->regs_soc + SOC_RTC_INTERRUPT);
249 + writel(val & ~SOC_RTC_ALARM1, rtc->regs_soc + SOC_RTC_INTERRUPT);
250 + val = readl(rtc->regs + RTC_IRQ1_CONF);
251 + /* disable all the interrupts for alarm 1 */
252 + rtc_delayed_write(0, rtc, RTC_IRQ1_CONF);
253 + /* Ack the event */
254 + rtc_delayed_write(RTC_STATUS_ALARM1, rtc, RTC_STATUS);
256 + spin_unlock(&rtc->lock);
258 + if (val & RTC_IRQ1_FREQ_EN) {
259 + if (val & RTC_IRQ1_FREQ_1HZ)
265 + rtc_update_irq(rtc->rtc_dev, 1, event);
267 + return IRQ_HANDLED;
270 +static struct rtc_class_ops armada38x_rtc_ops = {
271 + .read_time = armada38x_rtc_read_time,
272 + .set_time = armada38x_rtc_set_time,
273 + .read_alarm = armada38x_rtc_read_alarm,
274 + .set_alarm = armada38x_rtc_set_alarm,
275 + .alarm_irq_enable = armada38x_rtc_alarm_irq_enable,
278 +static __init int armada38x_rtc_probe(struct platform_device *pdev)
280 + struct resource *res;
281 + struct armada38x_rtc *rtc;
284 + rtc = devm_kzalloc(&pdev->dev, sizeof(struct armada38x_rtc),
289 + spin_lock_init(&rtc->lock);
291 + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "rtc");
292 + rtc->regs = devm_ioremap_resource(&pdev->dev, res);
293 + if (IS_ERR(rtc->regs))
294 + return PTR_ERR(rtc->regs);
295 + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "rtc-soc");
296 + rtc->regs_soc = devm_ioremap_resource(&pdev->dev, res);
297 + if (IS_ERR(rtc->regs_soc))
298 + return PTR_ERR(rtc->regs_soc);
300 + rtc->irq = platform_get_irq(pdev, 0);
302 + if (rtc->irq < 0) {
303 + dev_err(&pdev->dev, "no irq\n");
306 + if (devm_request_irq(&pdev->dev, rtc->irq, armada38x_rtc_alarm_irq,
307 + 0, pdev->name, rtc) < 0) {
308 + dev_warn(&pdev->dev, "Interrupt not available.\n");
311 + * If there is no interrupt available then we can't
314 + armada38x_rtc_ops.set_alarm = NULL;
315 + armada38x_rtc_ops.alarm_irq_enable = NULL;
317 + platform_set_drvdata(pdev, rtc);
318 + if (rtc->irq != -1)
319 + device_init_wakeup(&pdev->dev, 1);
321 + rtc->rtc_dev = devm_rtc_device_register(&pdev->dev, pdev->name,
322 + &armada38x_rtc_ops, THIS_MODULE);
323 + if (IS_ERR(rtc->rtc_dev)) {
324 + ret = PTR_ERR(rtc->rtc_dev);
325 + dev_err(&pdev->dev, "Failed to register RTC device: %d\n", ret);
331 +#ifdef CONFIG_PM_SLEEP
332 +static int armada38x_rtc_suspend(struct device *dev)
334 + if (device_may_wakeup(dev)) {
335 + struct armada38x_rtc *rtc = dev_get_drvdata(dev);
337 + return enable_irq_wake(rtc->irq);
343 +static int armada38x_rtc_resume(struct device *dev)
345 + if (device_may_wakeup(dev)) {
346 + struct armada38x_rtc *rtc = dev_get_drvdata(dev);
348 + return disable_irq_wake(rtc->irq);
355 +static SIMPLE_DEV_PM_OPS(armada38x_rtc_pm_ops,
356 + armada38x_rtc_suspend, armada38x_rtc_resume);
359 +static const struct of_device_id armada38x_rtc_of_match_table[] = {
360 + { .compatible = "marvell,armada-380-rtc", },
365 +static struct platform_driver armada38x_rtc_driver = {
367 + .name = "armada38x-rtc",
368 + .pm = &armada38x_rtc_pm_ops,
369 + .of_match_table = of_match_ptr(armada38x_rtc_of_match_table),
373 +module_platform_driver_probe(armada38x_rtc_driver, armada38x_rtc_probe);
375 +MODULE_DESCRIPTION("Marvell Armada 38x RTC driver");
376 +MODULE_AUTHOR("Gregory CLEMENT <gregory.clement@free-electrons.com>");
377 +MODULE_LICENSE("GPL");
380 @@ -1136,6 +1136,7 @@ M: Sebastian Hesselbarth <sebastian.hess
381 L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
383 F: arch/arm/mach-mvebu/
384 +F: drivers/rtc/armada38x-rtc
386 ARM/Marvell Berlin SoC support
387 M: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
388 --- a/arch/arm/boot/dts/armada-38x.dtsi
389 +++ b/arch/arm/boot/dts/armada-38x.dtsi
391 clocks = <&gateclk 4>;
395 + compatible = "marvell,armada-380-rtc";
396 + reg = <0xa3800 0x20>, <0x184a0 0x0c>;
397 + reg-names = "rtc", "rtc-soc";
398 + interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
402 compatible = "marvell,armada-380-ahci";
403 reg = <0xa8000 0x2000>;