target/linux/mediatek/patches/0063-arm-mediatek-add-SDK-ethernet.patch

   1 From e3aece79d5003b6879298b05551e113117d5cdd8 Mon Sep 17 00:00:00 2001
   2 From: John Crispin <blogic@openwrt.org>
   3 Date: Sat, 27 Jun 2015 13:13:36 +0200
   4 Subject: [PATCH 63/76] arm: mediatek: add SDK ethernet
   5
   6 Signed-off-by: John Crispin <blogic@openwrt.org>
   7 ---
   8  drivers/net/ethernet/Kconfig                      |    1 +
   9  drivers/net/ethernet/Makefile                     |    1 +
  10  drivers/net/ethernet/raeth/Kconfig                |  415 ++
  11  drivers/net/ethernet/raeth/Makefile               |   67 +
  12  drivers/net/ethernet/raeth/Makefile.release       |   60 +
  13  drivers/net/ethernet/raeth/csr_netlink.h          |   27 +
  14  drivers/net/ethernet/raeth/dvt/pkt_gen.c          |   88 +
  15  drivers/net/ethernet/raeth/dvt/pkt_gen_tcp_frag.c |  138 +
  16  drivers/net/ethernet/raeth/dvt/pkt_gen_udp_frag.c |  191 +
  17  drivers/net/ethernet/raeth/dvt/raether_pdma_dvt.c | 1527 +++++
  18  drivers/net/ethernet/raeth/dvt/raether_pdma_dvt.h |   75 +
  19  drivers/net/ethernet/raeth/ethtool_readme.txt     |   44 +
  20  drivers/net/ethernet/raeth/mcast.c                |  187 +
  21  drivers/net/ethernet/raeth/mii_mgr.c              |  603 ++
  22  drivers/net/ethernet/raeth/ra2882ethreg.h         | 1985 +++++++
  23  drivers/net/ethernet/raeth/ra_ethtool.c           |  515 ++
  24  drivers/net/ethernet/raeth/ra_ethtool.h           |   13 +
  25  drivers/net/ethernet/raeth/ra_ioctl.h             |  102 +
  26  drivers/net/ethernet/raeth/ra_mac.c               | 2645 +++++++++
  27  drivers/net/ethernet/raeth/ra_mac.h               |   57 +
  28  drivers/net/ethernet/raeth/ra_netlink.c           |  142 +
  29  drivers/net/ethernet/raeth/ra_netlink.h           |   10 +
  30  drivers/net/ethernet/raeth/ra_qos.c               |  655 +++
  31  drivers/net/ethernet/raeth/ra_qos.h               |   18 +
  32  drivers/net/ethernet/raeth/ra_rfrw.c              |   66 +
  33  drivers/net/ethernet/raeth/ra_rfrw.h              |    6 +
  34  drivers/net/ethernet/raeth/raether.c              | 6401 +++++++++++++++++++++
  35  drivers/net/ethernet/raeth/raether.h              |  126 +
  36  drivers/net/ethernet/raeth/raether_hwlro.c        |  347 ++
  37  drivers/net/ethernet/raeth/raether_pdma.c         | 1121 ++++
  38  drivers/net/ethernet/raeth/raether_qdma.c         | 1407 +++++
  39  drivers/net/ethernet/raeth/raether_qdma_mt7623.c  | 1020 ++++
  40  drivers/net/ethernet/raeth/smb_hook.c             |   17 +
  41  drivers/net/ethernet/raeth/smb_nf.c               |  177 +
  42  drivers/net/ethernet/raeth/sync_write.h           |  103 +
  43  35 files changed, 20357 insertions(+)
  44  create mode 100644 drivers/net/ethernet/raeth/Kconfig
  45  create mode 100644 drivers/net/ethernet/raeth/Makefile
  46  create mode 100644 drivers/net/ethernet/raeth/Makefile.release
  47  create mode 100644 drivers/net/ethernet/raeth/csr_netlink.h
  48  create mode 100755 drivers/net/ethernet/raeth/dvt/pkt_gen.c
  49  create mode 100755 drivers/net/ethernet/raeth/dvt/pkt_gen_tcp_frag.c
  50  create mode 100755 drivers/net/ethernet/raeth/dvt/pkt_gen_udp_frag.c
  51  create mode 100755 drivers/net/ethernet/raeth/dvt/raether_pdma_dvt.c
  52  create mode 100755 drivers/net/ethernet/raeth/dvt/raether_pdma_dvt.h
  53  create mode 100644 drivers/net/ethernet/raeth/ethtool_readme.txt
  54  create mode 100644 drivers/net/ethernet/raeth/mcast.c
  55  create mode 100644 drivers/net/ethernet/raeth/mii_mgr.c
  56  create mode 100644 drivers/net/ethernet/raeth/ra2882ethreg.h
  57  create mode 100644 drivers/net/ethernet/raeth/ra_ethtool.c
  58  create mode 100644 drivers/net/ethernet/raeth/ra_ethtool.h
  59  create mode 100644 drivers/net/ethernet/raeth/ra_ioctl.h
  60  create mode 100644 drivers/net/ethernet/raeth/ra_mac.c
  61  create mode 100644 drivers/net/ethernet/raeth/ra_mac.h
  62  create mode 100644 drivers/net/ethernet/raeth/ra_netlink.c
  63  create mode 100644 drivers/net/ethernet/raeth/ra_netlink.h
  64  create mode 100644 drivers/net/ethernet/raeth/ra_qos.c
  65  create mode 100644 drivers/net/ethernet/raeth/ra_qos.h
  66  create mode 100644 drivers/net/ethernet/raeth/ra_rfrw.c
  67  create mode 100644 drivers/net/ethernet/raeth/ra_rfrw.h
  68  create mode 100644 drivers/net/ethernet/raeth/raether.c
  69  create mode 100644 drivers/net/ethernet/raeth/raether.h
  70  create mode 100755 drivers/net/ethernet/raeth/raether_hwlro.c
  71  create mode 100755 drivers/net/ethernet/raeth/raether_pdma.c
  72  create mode 100644 drivers/net/ethernet/raeth/raether_qdma.c
  73  create mode 100644 drivers/net/ethernet/raeth/raether_qdma_mt7623.c
  74  create mode 100644 drivers/net/ethernet/raeth/smb_hook.c
  75  create mode 100644 drivers/net/ethernet/raeth/smb_nf.c
  76  create mode 100644 drivers/net/ethernet/raeth/sync_write.h
  77
  78 diff --git a/drivers/net/ethernet/Kconfig b/drivers/net/ethernet/Kconfig
  79 index eadcb05..627e1d4 100644
  80 --- a/drivers/net/ethernet/Kconfig
  81 +++ b/drivers/net/ethernet/Kconfig
  82 @@ -17,6 +17,7 @@ config MDIO
  83  config SUNGEM_PHY
  84         tristate
  85
  86 +source "drivers/net/ethernet/raeth/Kconfig"
  87  source "drivers/net/ethernet/3com/Kconfig"
  88  source "drivers/net/ethernet/adaptec/Kconfig"
  89  source "drivers/net/ethernet/aeroflex/Kconfig"
  90 diff --git a/drivers/net/ethernet/Makefile b/drivers/net/ethernet/Makefile
  91 index 1367afc..abdd636 100644
  92 --- a/drivers/net/ethernet/Makefile
  93 +++ b/drivers/net/ethernet/Makefile
  94 @@ -84,3 +84,4 @@ obj-$(CONFIG_NET_VENDOR_VIA) += via/
  95  obj-$(CONFIG_NET_VENDOR_WIZNET) += wiznet/
  96  obj-$(CONFIG_NET_VENDOR_XILINX) += xilinx/
  97  obj-$(CONFIG_NET_VENDOR_XIRCOM) += xircom/
  98 +obj-$(CONFIG_RAETH) += raeth/
  99 diff --git a/drivers/net/ethernet/raeth/Kconfig b/drivers/net/ethernet/raeth/Kconfig
 100 new file mode 100644
 101 index 0000000..c252c85
 102 --- /dev/null
 103 +++ b/drivers/net/ethernet/raeth/Kconfig
 104 @@ -0,0 +1,415 @@
 105 +config ARCH_MT7623
 106 +       bool
 107 +       default y
 108 +
 109 +config RA_NAT_NONE
 110 +       bool
 111 +       default y
 112 +
 113 +config RAETH
 114 +        tristate "Ralink GMAC"
 115 +       ---help---
 116 +          This driver supports Ralink gigabit ethernet family of
 117 +          adapters.
 118 +
 119 +config PDMA_NEW
 120 +        bool
 121 +       default y if  (RALINK_MT7620 || RALINK_MT7621 || ARCH_MT7623)
 122 +        depends on RAETH
 123 +
 124 +config RAETH_SCATTER_GATHER_RX_DMA
 125 +        bool
 126 +       default y if (RALINK_MT7620 || RALINK_MT7621 || ARCH_MT7623)
 127 +        depends on RAETH
 128 +
 129 +
 130 +choice
 131 +       prompt "Network BottomHalves"
 132 +        depends on RAETH
 133 +       default RA_NETWORK_WORKQUEUE_BH
 134 +
 135 +       config RA_NETWORK_TASKLET_BH
 136 +       bool "Tasklet"
 137 +
 138 +       config RA_NETWORK_WORKQUEUE_BH
 139 +       bool "Work Queue"
 140 +
 141 +       config RAETH_NAPI
 142 +        bool "NAPI"
 143 +
 144 +endchoice
 145 +
 146 +#config TASKLET_WORKQUEUE_SW
 147 +#        bool "Tasklet and Workqueue switch"
 148 +#        depends on RA_NETWORK_TASKLET_BH
 149 +
 150 +config RAETH_SKB_RECYCLE_2K
 151 +        bool "SKB Recycling"
 152 +        depends on RAETH
 153 +
 154 +config RAETH_SPECIAL_TAG
 155 +        bool "Ralink Special Tag (0x810x)"
 156 +        depends on RAETH && RT_3052_ESW
 157 +
 158 +#config RAETH_JUMBOFRAME
 159 +#        bool "Jumbo Frame up to 4K bytes"
 160 +#        depends on RAETH && !(RALINK_RT3052 || RALINK_RT3352 || RALINK_RT5350 || RALINK_MT7628)
 161 +
 162 +config RAETH_CHECKSUM_OFFLOAD
 163 +        bool "TCP/UDP/IP checksum offload"
 164 +       default y
 165 +        depends on RAETH && !RALINK_RT2880
 166 +
 167 +#config RAETH_SW_FC
 168 +#        bool "When TX ring is full, inform kernel stop transmit and stop RX handler"
 169 +#       default n
 170 +#        depends on RAETH
 171 +
 172 +#config RAETH_8023AZ_EEE
 173 +#        bool "Enable Embeded Switch EEE"
 174 +#       default n
 175 +#        depends on RAETH && (RALINK_MT7620 || RALINK_MT7621 || RALINK_MT7628)
 176 +
 177 +
 178 +
 179 +config 32B_DESC
 180 +        bool "32bytes TX/RX description"
 181 +       default n
 182 +        depends on RAETH && (RALINK_MT7620 || RALINK_MT7621)
 183 +        ---help---
 184 +          At this moment, you cannot enable 32B description with Multiple RX ring at the same time.
 185 +
 186 +config RAETH_LRO
 187 +        bool "LRO (Large Receive Offload )"
 188 +       select INET_LRO
 189 +        depends on RAETH && (RALINK_RT6855A || RALINK_MT7620 || RALINK_MT7621 || ARCH_MT7623)
 190 +
 191 +config RAETH_HW_LRO
 192 +        bool "HW LRO (Large Receive Offload)"
 193 +       default n
 194 +        depends on RAETH
 195 +
 196 +config RAETH_HW_LRO_DBG
 197 +        bool "HW LRO Debug"
 198 +       default n
 199 +       depends on RAETH_HW_LRO
 200 +
 201 +config RAETH_HW_LRO_AUTO_ADJ_DBG
 202 +        bool "HW LRO Auto Adjustment Debug"
 203 +       default y
 204 +       depends on RAETH_HW_LRO
 205 +
 206 +config RAETH_HW_LRO_REASON_DBG
 207 +        bool "HW LRO Flush Reason Debug"
 208 +       default n
 209 +       depends on RAETH_HW_LRO
 210 +
 211 +config RAETH_HW_VLAN_TX
 212 +        bool "Transmit VLAN HW (DoubleVLAN is not supported)"
 213 +        depends on RAETH && !(RALINK_RT5350 || RALINK_MT7628)
 214 +        ---help---
 215 +          Please disable HW_VLAN_TX if you need double vlan
 216 +
 217 +config RAETH_HW_VLAN_RX
 218 +        bool "Receive VLAN HW (DoubleVLAN is not supported)"
 219 +        depends on RAETH && RALINK_MT7621
 220 +        ---help---
 221 +          Please disable HW_VLAN_RX if you need double vlan
 222 +
 223 +config RAETH_TSO
 224 +        bool "TSOV4 (Tcp Segmentaton Offload)"
 225 +       depends on (RAETH_HW_VLAN_TX && (RALINK_RT6855 || RALINK_RT6855A || RALINK_MT7620))||((RALINK_MT7621 || ARCH_MT7623) &&(RAETH_HW_VLAN_TX || RAETH_GMAC2 ))
 226 +
 227 +config RAETH_TSOV6
 228 +        bool "TSOV6 (Tcp Segmentaton Offload)"
 229 +       depends on RAETH_TSO
 230 +
 231 +config RAETH_RW_PDMAPTR_FROM_VAR
 232 +       bool
 233 +       default y if RALINK_RT6855A || RALINK_MT7620
 234 +        depends on RAETH
 235 +
 236 +config MTK_SMB_HOOK
 237 +        bool "Samba Speedup Module"
 238 +       depends on RAETH
 239 +
 240 +config SPLICE_NET_SUPPORT
 241 +       default y if MTK_SMB_HOOK
 242 +       depends on MTK_SMB_HOOK
 243 +       bool
 244 +
 245 +
 246 +config RAETH_DVT
 247 +        bool "RAETH DVT"
 248 +       depends on RAETH && (RALINK_MT7621 || ARCH_MT7623)
 249 +
 250 +config RAETH_PDMA_DVT
 251 +        bool "PDMA DVT"
 252 +       depends on RAETH_DVT
 253 +
 254 +config RAETH_PDMA_LEGACY_MODE
 255 +        bool "PDMA legacy mode"
 256 +       depends on RAETH_PDMA_DVT
 257 +
 258 +#config RAETH_QOS
 259 +#        bool "QoS Feature"
 260 +#        depends on RAETH && !RALINK_RT2880 && !RALINK_MT7620 && !RALINK_MT7621 && !RAETH_TSO
 261 +
 262 +choice
 263 +        prompt "QoS Type"
 264 +        depends on RAETH_QOS
 265 +        default DSCP_QOS_DSCP
 266 +
 267 +config  RAETH_QOS_DSCP_BASED
 268 +        bool "DSCP-based"
 269 +        depends on RAETH_QOS
 270 +
 271 +config  RAETH_QOS_VPRI_BASED
 272 +        bool "VPRI-based"
 273 +        depends on RAETH_QOS
 274 +
 275 +endchoice
 276 +
 277 +config RAETH_QDMA
 278 +        bool "Choose QDMA instead PDMA"
 279 +       default n
 280 +        depends on RAETH && (RALINK_MT7621 || ARCH_MT7623)
 281 +
 282 +config RAETH_QDMATX_QDMARX
 283 +        bool "Choose QDMA RX instead PDMA RX"
 284 +       default n
 285 +        depends on RAETH_QDMA && !RALINK_MT7621
 286 +
 287 +
 288 +
 289 +choice
 290 +        prompt "GMAC is connected to"
 291 +        depends on RAETH
 292 +        default GE1_RGMII_FORCE_1000
 293 +
 294 +config  GE1_MII_FORCE_100
 295 +        bool "MII_FORCE_100 (10/100M Switch)"
 296 +        depends on (RALINK_RT2880 || RALINK_RT3883 || RALINK_MT7621)
 297 +
 298 +config  GE1_MII_AN
 299 +        bool "MII_AN (100Phy)"
 300 +        depends on (RALINK_RT2880 || RALINK_RT3883 || RALINK_MT7621)
 301 +
 302 +config  GE1_RVMII_FORCE_100
 303 +        bool "RvMII_FORCE_100 (CPU)"
 304 +        depends on (RALINK_RT2880 || RALINK_RT3883 || RALINK_MT7621)
 305 +
 306 +config  GE1_RGMII_FORCE_1000
 307 +        bool "RGMII_FORCE_1000 (GigaSW, CPU)"
 308 +        depends on (RALINK_RT2880 || RALINK_RT3883)
 309 +       select RALINK_SPI
 310 +
 311 +config  GE1_RGMII_FORCE_1000
 312 +        bool "RGMII_FORCE_1000 (GigaSW, CPU)"
 313 +        depends on (RALINK_MT7621 || ARCH_MT7623)
 314 +       select RT_3052_ESW
 315 +
 316 +config  GE1_TRGMII_FORCE_1200
 317 +        bool "TRGMII_FORCE_1200 (GigaSW, CPU)"
 318 +        depends on (RALINK_MT7621)
 319 +       select RT_3052_ESW
 320 +
 321 +config  GE1_TRGMII_FORCE_2000
 322 +        bool "TRGMII_FORCE_2000 (GigaSW, CPU, for MT7623 and MT7683)"
 323 +        depends on (ARCH_MT7623)
 324 +        select RT_3052_ESW
 325 +
 326 +config  GE1_TRGMII_FORCE_2600
 327 +        bool "TRGMII_FORCE_2600 (GigaSW, CPU, MT7623 only)"
 328 +        depends on (ARCH_MT7623)
 329 +        select RT_3052_ESW
 330 +
 331 +config  GE1_RGMII_AN
 332 +        bool "RGMII_AN (GigaPhy)"
 333 +        depends on (RALINK_RT2880 || RALINK_RT3883 || RALINK_MT7621 || ARCH_MT7623)
 334 +
 335 +config  GE1_RGMII_NONE
 336 +        bool "NONE (NO CONNECT)"
 337 +        depends on (RALINK_MT7621 || ARCH_MT7623)
 338 +
 339 +endchoice
 340 +
 341 +config HW_SFQ
 342 +        bool "HW_SFQ"
 343 +       default n
 344 +        depends on RAETH_QDMA && (ARCH_MT7623)
 345 +
 346 +
 347 +config  RT_3052_ESW
 348 +        bool "Ralink Embedded Switch"
 349 +       default y
 350 +        depends on RAETH && (RALINK_RT3052 || RALINK_RT3352 || RALINK_RT5350 || RALINK_RT6855 || RALINK_RT6855A || RALINK_MT7620 || RALINK_MT7621 || RALINK_MT7628 || ARCH_MT7623)
 351 +
 352 +config LAN_WAN_SUPPORT
 353 +        bool "LAN/WAN Partition"
 354 +        depends on RAETH && (RAETH_ROUTER || RT_3052_ESW)
 355 +
 356 +config ETH_MEMORY_OPTIMIZATION
 357 +       bool "Ethernet memory optimization"
 358 +       depends on RALINK_MT7628
 359 +
 360 +config ETH_ONE_PORT_ONLY
 361 +       bool "One Port Only"
 362 +       depends on RALINK_MT7628
 363 +
 364 +choice
 365 +        prompt "Switch Board Layout Type"
 366 +        depends on LAN_WAN_SUPPORT || P5_RGMII_TO_MAC_MODE ||  GE1_RGMII_FORCE_1000 || GE1_TRGMII_FORCE_1200 || GE2_RGMII_FORCE_1000
 367 +       default WAN_AT_P0
 368 +
 369 +       config  WAN_AT_P4
 370 +               bool "LLLL/W"
 371 +
 372 +       config  WAN_AT_P0
 373 +               bool "W/LLLL"
 374 +endchoice
 375 +
 376 +config RALINK_VISTA_BASIC
 377 +       bool 'Vista Basic Logo for IC+ 175C'
 378 +        depends on LAN_WAN_SUPPORT && (RALINK_RT2880 || RALINK_RT3883)
 379 +
 380 +config ESW_DOUBLE_VLAN_TAG
 381 +       bool
 382 +       default y if RT_3052_ESW
 383 +
 384 +config RAETH_HAS_PORT4
 385 +        bool "Port 4 Support"
 386 +        depends on RAETH && RALINK_MT7620
 387 +choice
 388 +        prompt "Target Mode"
 389 +        depends on RAETH_HAS_PORT4
 390 +       default P4_RGMII_TO_MAC_MODE
 391 +
 392 +       config P4_MAC_TO_PHY_MODE
 393 +               bool "Giga_Phy (RGMII)"
 394 +       config  GE_RGMII_MT7530_P0_AN
 395 +               bool "GE_RGMII_MT7530_P0_AN (MT7530 Internal GigaPhy)"
 396 +       config  GE_RGMII_MT7530_P4_AN
 397 +               bool "GE_RGMII_MT7530_P4_AN (MT7530 Internal GigaPhy)"
 398 +       config P4_RGMII_TO_MAC_MODE
 399 +               bool "Giga_SW/iNIC (RGMII)"
 400 +       config P4_MII_TO_MAC_MODE
 401 +               bool "External_CPU (MII_RvMII)"
 402 +       config P4_RMII_TO_MAC_MODE
 403 +               bool "External_CPU (RvMII_MII)"
 404 +endchoice
 405 +
 406 +config  MAC_TO_GIGAPHY_MODE_ADDR2
 407 +        hex "Port4 Phy Address"
 408 +       default 0x4
 409 +        depends on P4_MAC_TO_PHY_MODE
 410 +
 411 +config RAETH_HAS_PORT5
 412 +        bool "Port 5 Support"
 413 +        depends on RAETH && (RALINK_RT3052 || RALINK_RT3352 || RALINK_RT6855 || RALINK_RT6855A || RALINK_MT7620)
 414 +choice
 415 +        prompt "Target Mode"
 416 +        depends on RAETH_HAS_PORT5
 417 +       default P5_RGMII_TO_MAC_MODE
 418 +
 419 +       config P5_MAC_TO_PHY_MODE
 420 +               bool "Giga_Phy (RGMII)"
 421 +       config P5_RGMII_TO_MAC_MODE
 422 +               bool "Giga_SW/iNIC (RGMII)"
 423 +       config P5_RGMII_TO_MT7530_MODE
 424 +               bool "MT7530 Giga_SW (RGMII)"
 425 +               depends on RALINK_MT7620
 426 +       config P5_MII_TO_MAC_MODE
 427 +               bool "External_CPU (MII_RvMII)"
 428 +       config P5_RMII_TO_MAC_MODE
 429 +               bool "External_CPU (RvMII_MII)"
 430 +endchoice
 431 +
 432 +config  MAC_TO_GIGAPHY_MODE_ADDR
 433 +        hex "GE1 Phy Address"
 434 +       default 0x1F
 435 +        depends on GE1_MII_AN || GE1_RGMII_AN
 436 +
 437 +config  MAC_TO_GIGAPHY_MODE_ADDR
 438 +        hex "Port5 Phy Address"
 439 +       default 0x5
 440 +        depends on P5_MAC_TO_PHY_MODE
 441 +
 442 +config RAETH_GMAC2
 443 +        bool "GMAC2 Support"
 444 +        depends on RAETH && (RALINK_RT3883 || RALINK_MT7621 || ARCH_MT7623)
 445 +
 446 +choice
 447 +        prompt "GMAC2 is connected to"
 448 +        depends on RAETH_GMAC2
 449 +        default GE2_RGMII_AN
 450 +
 451 +config  GE2_MII_FORCE_100
 452 +        bool "MII_FORCE_100 (10/100M Switch)"
 453 +        depends on RAETH_GMAC2
 454 +
 455 +config  GE2_MII_AN
 456 +        bool "MII_AN (100Phy)"
 457 +        depends on RAETH_GMAC2
 458 +
 459 +config  GE2_RVMII_FORCE_100
 460 +        bool "RvMII_FORCE_100 (CPU)"
 461 +        depends on RAETH_GMAC2
 462 +
 463 +config  GE2_RGMII_FORCE_1000
 464 +        bool "RGMII_FORCE_1000 (GigaSW, CPU)"
 465 +        depends on RAETH_GMAC2
 466 +       select RALINK_SPI
 467 +
 468 +config  GE2_RGMII_AN
 469 +        bool "RGMII_AN (External GigaPhy)"
 470 +        depends on RAETH_GMAC2
 471 +
 472 +config  GE2_INTERNAL_GPHY
 473 +        bool "RGMII_AN (Internal GigaPny)"
 474 +        depends on RAETH_GMAC2
 475 +       select LAN_WAN_SUPPORT
 476 +
 477 +endchoice
 478 +
 479 +config  GE_RGMII_INTERNAL_P0_AN
 480 +       bool
 481 +        depends on GE2_INTERNAL_GPHY
 482 +       default y if WAN_AT_P0
 483 +
 484 +config  GE_RGMII_INTERNAL_P4_AN
 485 +       bool
 486 +        depends on GE2_INTERNAL_GPHY
 487 +       default y if WAN_AT_P4
 488 +
 489 +config  MAC_TO_GIGAPHY_MODE_ADDR2
 490 +        hex
 491 +       default 0 if GE_RGMII_INTERNAL_P0_AN
 492 +       default 4 if GE_RGMII_INTERNAL_P4_AN
 493 +        depends on GE_RGMII_INTERNAL_P0_AN || GE_RGMII_INTERNAL_P4_AN
 494 +
 495 +config  MAC_TO_GIGAPHY_MODE_ADDR2
 496 +        hex "GE2 Phy Address"
 497 +       default 0x1E
 498 +        depends on GE2_MII_AN || GE2_RGMII_AN
 499 +
 500 +#force 100M
 501 +config RAETH_ROUTER
 502 +bool
 503 +default y if GE1_MII_FORCE_100 || GE2_MII_FORCE_100 || GE1_RVMII_FORCE_100 || GE2_RVMII_FORCE_100
 504 +
 505 +#force 1000M
 506 +config MAC_TO_MAC_MODE
 507 +bool
 508 +default y if GE1_RGMII_FORCE_1000 || GE2_RGMII_FORCE_1000
 509 +depends on (RALINK_RT2880 || RALINK_RT3883)
 510 +
 511 +#AN
 512 +config GIGAPHY
 513 +bool
 514 +default y if GE1_RGMII_AN || GE2_RGMII_AN
 515 +
 516 +#AN
 517 +config 100PHY
 518 +bool
 519 +default y if GE1_MII_AN || GE2_MII_AN
 520 diff --git a/drivers/net/ethernet/raeth/Makefile b/drivers/net/ethernet/raeth/Makefile
 521 new file mode 100644
 522 index 0000000..563af05
 523 --- /dev/null
 524 +++ b/drivers/net/ethernet/raeth/Makefile
 525 @@ -0,0 +1,67 @@
 526 +obj-$(CONFIG_RAETH) += raeth.o
 527 +raeth-objs := ra_mac.o mii_mgr.o ra_rfrw.o
 528 +
 529 +ifeq ($(CONFIG_MTK_SMB_HOOK),y)
 530 +obj-y += smb_hook.o
 531 +obj-m += smb.o
 532 +smb-objs := smb_nf.o
 533 +endif
 534 +
 535 +#EXTRA_CFLAGS   += -DCONFIG_RAETH_MULTIPLE_RX_RING
 536 +
 537 +ifeq ($(CONFIG_RAETH_QOS),y)
 538 +raeth-objs += ra_qos.o
 539 +endif
 540 +
 541 +ifeq ($(CONFIG_RAETH_QDMA),y)
 542 +raeth-objs += raether_qdma.o
 543 +endif
 544 +
 545 +ifneq ($(CONFIG_RAETH_QDMA),y)
 546 +raeth-objs += raether_pdma.o
 547 +endif
 548 +
 549 +raeth-objs += raether.o
 550 +
 551 +ifeq ($(CONFIG_ETHTOOL),y)
 552 +raeth-objs += ra_ethtool.o
 553 +endif
 554 +
 555 +ifeq ($(CONFIG_RALINK_RT3052_MP2),y)
 556 +raeth-objs += mcast.o
 557 +endif
 558 +
 559 +ifeq ($(CONFIG_RAETH_NETLINK),y)
 560 +raeth-objs += ra_netlink.o
 561 +endif
 562 +
 563 +ifeq ($(CONFIG_RAETH_PDMA_DVT),y)
 564 +raeth-objs += dvt/raether_pdma_dvt.o
 565 +obj-m += dvt/pkt_gen.o
 566 +obj-m += dvt/pkt_gen_udp_frag.o
 567 +obj-m += dvt/pkt_gen_tcp_frag.o
 568 +endif
 569 +
 570 +ifeq ($(CONFIG_RAETH_HW_LRO),y)
 571 +raeth-objs += raether_hwlro.o
 572 +endif
 573 +
 574 +ifeq ($(CONFIG_RAETH_GMAC2),y)
 575 +EXTRA_CFLAGS += -DCONFIG_PSEUDO_SUPPORT
 576 +endif
 577 +
 578 +ifeq ($(CONFIG_ETH_MEMORY_OPTIMIZATION),y)
 579 +EXTRA_CFLAGS   += -DMEMORY_OPTIMIZATION
 580 +endif
 581 +
 582 +ifeq ($(CONFIG_RT2860V2_AP_MEMORY_OPTIMIZATION),y)
 583 +EXTRA_CFLAGS   += -DMEMORY_OPTIMIZATION
 584 +endif
 585 +
 586 +ifeq ($(CONFIG_RA_NETWORK_WORKQUEUE_BH),y)
 587 +EXTRA_CFLAGS   += -DWORKQUEUE_BH
 588 +endif
 589 +
 590 +ifeq ($(CONFIG_TASKLET_WORKQUEUE_SW),y)
 591 +EXTRA_CFLAGS   += -DTASKLET_WORKQUEUE_SW
 592 +endif
 593 diff --git a/drivers/net/ethernet/raeth/Makefile.release b/drivers/net/ethernet/raeth/Makefile.release
 594 new file mode 100644
 595 index 0000000..ecdeeda
 596 --- /dev/null
 597 +++ b/drivers/net/ethernet/raeth/Makefile.release
 598 @@ -0,0 +1,60 @@
 599 +obj-$(CONFIG_RAETH) += raeth.o
 600 +raeth-objs := ra_mac.o mii_mgr.o ra_rfrw.o
 601 +
 602 +ifeq ($(CONFIG_MTK_SMB_HOOK),y)
 603 +obj-y += smb_hook.o
 604 +obj-m += smb.o
 605 +smb-objs := smb_nf.o
 606 +endif
 607 +
 608 +#EXTRA_CFLAGS   += -DCONFIG_RAETH_MULTIPLE_RX_RING
 609 +
 610 +ifeq ($(CONFIG_RAETH_QOS),y)
 611 +raeth-objs += ra_qos.o
 612 +endif
 613 +
 614 +ifeq ($(CONFIG_RAETH_QDMA),y)
 615 +raeth-objs += raether_qdma.o
 616 +endif
 617 +
 618 +ifneq ($(CONFIG_RAETH_QDMA),y)
 619 +raeth-objs += raether_pdma.o
 620 +endif
 621 +
 622 +raeth-objs += raether.o
 623 +
 624 +ifeq ($(CONFIG_ETHTOOL),y)
 625 +raeth-objs += ra_ethtool.o
 626 +endif
 627 +
 628 +ifeq ($(CONFIG_RALINK_RT3052_MP2),y)
 629 +raeth-objs += mcast.o
 630 +endif
 631 +
 632 +ifeq ($(CONFIG_RAETH_NETLINK),y)
 633 +raeth-objs += ra_netlink.o
 634 +endif
 635 +
 636 +ifeq ($(CONFIG_RAETH_HW_LRO),y)
 637 +raeth-objs += raether_hwlro.o
 638 +endif
 639 +
 640 +ifeq ($(CONFIG_RAETH_GMAC2),y)
 641 +EXTRA_CFLAGS += -DCONFIG_PSEUDO_SUPPORT
 642 +endif
 643 +
 644 +ifeq ($(CONFIG_ETH_MEMORY_OPTIMIZATION),y)
 645 +EXTRA_CFLAGS   += -DMEMORY_OPTIMIZATION
 646 +endif
 647 +
 648 +ifeq ($(CONFIG_RT2860V2_AP_MEMORY_OPTIMIZATION),y)
 649 +EXTRA_CFLAGS   += -DMEMORY_OPTIMIZATION
 650 +endif
 651 +
 652 +ifeq ($(CONFIG_RA_NETWORK_WORKQUEUE_BH),y)
 653 +EXTRA_CFLAGS   += -DWORKQUEUE_BH
 654 +endif
 655 +
 656 +ifeq ($(CONFIG_TASKLET_WORKQUEUE_SW),y)
 657 +EXTRA_CFLAGS   += -DTASKLET_WORKQUEUE_SW
 658 +endif
 659 diff --git a/drivers/net/ethernet/raeth/csr_netlink.h b/drivers/net/ethernet/raeth/csr_netlink.h
 660 new file mode 100644
 661 index 0000000..add7745
 662 --- /dev/null
 663 +++ b/drivers/net/ethernet/raeth/csr_netlink.h
 664 @@ -0,0 +1,27 @@
 665 +#ifndef        CSR_NETLINK_H
 666 +#define CSR_NETLINK_H
 667 +
 668 +#define        CSR_NETLINK     30
 669 +#define        CSR_READ        0
 670 +#define        CSR_WRITE       1
 671 +#define        CSR_TEST        2
 672 +
 673 +#define RALINK_CSR_GROUP        2882
 674 +
 675 +typedef struct rt2880_csr_msg {
 676 +       int     enable;
 677 +       char    reg_name[32];
 678 +       unsigned long address;
 679 +       unsigned long default_value;
 680 +       unsigned long reserved_bits;    /* 1 : not reserved, 0 : reserved */
 681 +       unsigned long write_mask;
 682 +       unsigned long write_value;
 683 +       int     status;
 684 +} CSR_MSG;
 685 +
 686 +int csr_msg_send(CSR_MSG* msg);
 687 +int csr_msg_recv(void);
 688 +
 689 +// static CSR_MSG      input_csr_msg;
 690 +
 691 +#endif
 692 diff --git a/drivers/net/ethernet/raeth/dvt/pkt_gen.c b/drivers/net/ethernet/raeth/dvt/pkt_gen.c
 693 new file mode 100755
 694 index 0000000..b351b21
 695 --- /dev/null
 696 +++ b/drivers/net/ethernet/raeth/dvt/pkt_gen.c
 697 @@ -0,0 +1,88 @@
 698 +//#include <linux/config.h>
 699 +#include <linux/version.h>
 700 +#include <linux/module.h>
 701 +#include <linux/skbuff.h>
 702 +#include <linux/kernel.h>
 703 +#include <linux/init.h>
 704 +#include <linux/netfilter.h>
 705 +#include <linux/netdevice.h>
 706 +#include <linux/types.h>
 707 +#include <asm/uaccess.h>
 708 +#include <linux/moduleparam.h>
 709 +
 710 +char *ifname="eth3";
 711 +
 712 +static int32_t PktGenInitMod(void)
 713 +{
 714 +
 715 +    struct net_dev *dev;
 716 +    struct sk_buff *skb;
 717 +    int i=0;
 718 +
 719 +    unsigned char pkt[]={
 720 +       //0xff, 0xff, 0xff, 0xff, 0xff, 0xff, // dest bcast mac
 721 +       0x00, 0x21, 0x86, 0xee, 0xe3, 0x95, // dest macA
 722 +       //0x00, 0x30, 0xdb, 0x02, 0x02, 0x01, // dest macB
 723 +       0x00, 0x0c, 0x43, 0x28, 0x80, 0x33, // src mac
 724 +       0x81, 0x00, // vlan tag
 725 +       //0x81, 0x10, // vlan tag
 726 +       //0x87, 0x39, // do not learn
 727 +       //0xc1, 0x03, // vlan tag SA=0, VID=2, LV=1
 728 +       0x00, 0x03, // pri=0, vlan=3
 729 +       0x08, 0x00, // eth type=ip
 730 +       0x45, 0x00, 0x00, 0x30, 0x12, 0x34, 0x40, 0x00, 0xff, 0x06,
 731 +       0x40, 0x74, 0x0a, 0x0a, 0x1e, 0x0a, 0x0a, 0x0a, 0x1e, 0x0b,
 732 +       0x00, 0x1e, 0x00, 0x28, 0x00, 0x1c, 0x81, 0x06, 0x00, 0x00,
 733 +       0x00, 0x00, 0x50, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 734 +       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00};
 735 +
 736 +    skb = alloc_skb(256, GFP_ATOMIC);
 737 +
 738 +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,35)
 739 +    if((dev=dev_get_by_name(&init_net,ifname))){
 740 +#else
 741 +    if((dev=dev_get_by_name(ifname))){
 742 +#endif
 743 +
 744 +
 745 +
 746 +       skb->dev=dev;
 747 +       skb_put(skb,sizeof(pkt));
 748 +       memcpy(skb->data, pkt, sizeof(pkt));
 749 +
 750 +       printk("send pkt(len=%d) to %s\n", skb->len, skb->dev->name);
 751 +
 752 +
 753 +       for(i=0;i<sizeof(pkt);i++){
 754 +           if(i%16==0) {
 755 +               printk("\n");
 756 +           }
 757 +           printk("%02X-",skb->data[i]);
 758 +       }
 759 +
 760 +       dev_queue_xmit(skb);
 761 +    }else{
 762 +       printk("interface %s not found\n",ifname);
 763 +       return 1;
 764 +    }
 765 +
 766 +    return 0;
 767 +}
 768 +
 769 +static void PktGenCleanupMod(void)
 770 +{
 771 +}
 772 +
 773 +module_init(PktGenInitMod);
 774 +module_exit(PktGenCleanupMod);
 775 +#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,12)
 776 +MODULE_PARM (ifname, "s");
 777 +#else
 778 +module_param (ifname, charp, 0);
 779 +#endif
 780 +
 781 +MODULE_DESCRIPTION("Ralink PktGen Module");
 782 +MODULE_AUTHOR("Steven Liu");
 783 +MODULE_LICENSE("Proprietary");
 784 +MODULE_PARM_DESC (ifname, "interface name");
 785 +
 786 diff --git a/drivers/net/ethernet/raeth/dvt/pkt_gen_tcp_frag.c b/drivers/net/ethernet/raeth/dvt/pkt_gen_tcp_frag.c
 787 new file mode 100755
 788 index 0000000..e78c65a
 789 --- /dev/null
 790 +++ b/drivers/net/ethernet/raeth/dvt/pkt_gen_tcp_frag.c
 791 @@ -0,0 +1,138 @@
 792 +//#include <linux/config.h>
 793 +#include <linux/version.h>
 794 +#include <linux/module.h>
 795 +#include <linux/skbuff.h>
 796 +#include <linux/kernel.h>
 797 +#include <linux/init.h>
 798 +#include <linux/netfilter.h>
 799 +#include <linux/netdevice.h>
 800 +#include <linux/types.h>
 801 +#include <asm/uaccess.h>
 802 +#include <linux/moduleparam.h>
 803 +
 804 +char *ifname="eth3";
 805 +
 806 +
 807 +static int32_t PktGenInitMod(void)
 808 +{
 809 +    unsigned char pkt_1[]={
 810 +    0x00, 0x21, 0x86, 0xee, 0xe3, 0x90, // dest mac
 811 +    0x00, 0x0c, 0x43, 0x28, 0x80, 0x33, // src mac
 812 +    0x08, 0x00, // type: ip
 813 +    0x45, 0x00, 0x00, 0x34, // ip: ..., total len (0x034 = 52)
 814 +    0xa1, 0x78, 0x20, 0x00, // ip: id, frag, frag offset
 815 +    0x80, 0x06, 0x63, 0x07, // ip: ttl, protocol, hdr checksum (0x6307)
 816 +    0x0a, 0x0a, 0x1e, 0x7b, // src ip (10.10.30.123)
 817 +    0x0a, 0x0a, 0x1e, 0x05, // dst ip (10.10.30.5)
 818 +    0x0d, 0xd5,  //tcp src port
 819 +    0x13, 0x89,  //tcp dst port
 820 +    0x40, 0xf5, 0x15, 0x04,  //tcp sequence number
 821 +    0xf6, 0x4f, 0x1e, 0x31,  //tcp ack number
 822 +    0x50, 0x10, 0xfc, 0x00,  //tcp flags, win size
 823 +    0xf1, 0xfe, 0x00, 0x00,  //tcp checksum (0xf1fe)
 824 +    0x01, 0x02, 0x03, 0x04, 0x05,  //payload (12 bytes)
 825 +    0x06, 0x07, 0x08, 0x09, 0x0a,
 826 +    0x0b, 0x0c
 827 +    };
 828 +
 829 +    unsigned char pkt_2[]={
 830 +    0x00, 0x21, 0x86, 0xee, 0xe3, 0x90, // dest mac
 831 +    0x00, 0x0c, 0x43, 0x28, 0x80, 0x33, // src mac
 832 +    0x08, 0x00, // type: ip
 833 +    0x45, 0x00, 0x00, 0x20, // ip: ..., total len (0x020 = 32)
 834 +    0xa1, 0x78, 0x00, 0x04, // ip: id, frag, frag offset (32)
 835 +    0x40, 0x11, 0x63, 0x07, // ip: ttl, protocol, hdr checksum (0x6307)
 836 +    0x0a, 0x0a, 0x1e, 0x7b, // src ip (10.10.30.123)
 837 +    0x0a, 0x0a, 0x1e, 0x05, // dst ip (10.10.30.5)
 838 +    0x11, 0x12, 0x13, 0x14, 0x15,  //payload (12 bytes)
 839 +    0x16, 0x17, 0x18, 0x19, 0x1a,
 840 +    0x1b, 0x1c
 841 +    };
 842 +
 843 +    struct net_dev *dev;
 844 +    struct sk_buff *skb_1;
 845 +    struct sk_buff *skb_2;
 846 +    int i=0;
 847 +
 848 +    skb_1 = alloc_skb(256, GFP_ATOMIC);
 849 +    skb_2 = alloc_skb(256, GFP_ATOMIC);
 850 +
 851 +
 852 +#if 1
 853 +/* send packet 1 */
 854 +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,35)
 855 +    if((dev=dev_get_by_name(&init_net,ifname))){
 856 +#else
 857 +    if((dev=dev_get_by_name(ifname))){
 858 +#endif
 859 +
 860 +       skb_1->dev=dev;
 861 +       skb_put(skb_1,sizeof(pkt_1));
 862 +       memcpy(skb_1->data, pkt_1, sizeof(pkt_1));
 863 +
 864 +       printk("send pkt(len=%d) to %s\n", skb_1->len, skb_1->dev->name);
 865 +
 866 +
 867 +       for(i=0;i<sizeof(pkt_1);i++){
 868 +           if(i%16==0) {
 869 +               printk("\n");
 870 +           }
 871 +           printk("%02X-",skb_1->data[i]);
 872 +       }
 873 +
 874 +       dev_queue_xmit(skb_1);
 875 +    }else{
 876 +       printk("interface %s not found\n",ifname);
 877 +       return 1;
 878 +    }
 879 +#endif
 880 +
 881 +#if 1
 882 +/* send packet 2 */
 883 +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,35)
 884 +        if((dev=dev_get_by_name(&init_net,ifname))){
 885 +#else
 886 +        if((dev=dev_get_by_name(ifname))){
 887 +#endif
 888 +
 889 +       skb_2->dev=dev;
 890 +       skb_put(skb_2,sizeof(pkt_2));
 891 +       memcpy(skb_2->data, pkt_2, sizeof(pkt_2));
 892 +
 893 +       printk("send pkt(len=%d) to %s\n", skb_2->len, skb_2->dev->name);
 894 +
 895 +
 896 +       for(i=0;i<sizeof(pkt_2);i++){
 897 +           if(i%16==0) {
 898 +               printk("\n");
 899 +           }
 900 +           printk("%02X-",skb_2->data[i]);
 901 +       }
 902 +
 903 +       dev_queue_xmit(skb_2);
 904 +    }else{
 905 +       printk("interface %s not found\n",ifname);
 906 +       return 1;
 907 +    }
 908 +#endif
 909 +
 910 +    return 0;
 911 +}
 912 +
 913 +static void PktGenCleanupMod(void)
 914 +{
 915 +}
 916 +
 917 +module_init(PktGenInitMod);
 918 +module_exit(PktGenCleanupMod);
 919 +#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,12)
 920 +MODULE_PARM (ifname, "s");
 921 +#else
 922 +module_param (ifname, charp, 0);
 923 +#endif
 924 +
 925 +MODULE_DESCRIPTION("Ralink PktGen Module");
 926 +MODULE_AUTHOR("Steven Liu");
 927 +MODULE_LICENSE("Proprietary");
 928 +MODULE_PARM_DESC (ifname, "interface name");
 929 +
 930 diff --git a/drivers/net/ethernet/raeth/dvt/pkt_gen_udp_frag.c b/drivers/net/ethernet/raeth/dvt/pkt_gen_udp_frag.c
 931 new file mode 100755
 932 index 0000000..917e7ad
 933 --- /dev/null
 934 +++ b/drivers/net/ethernet/raeth/dvt/pkt_gen_udp_frag.c
 935 @@ -0,0 +1,191 @@
 936 +//#include <linux/config.h>
 937 +#include <linux/version.h>
 938 +#include <linux/module.h>
 939 +#include <linux/skbuff.h>
 940 +#include <linux/kernel.h>
 941 +#include <linux/init.h>
 942 +#include <linux/netfilter.h>
 943 +#include <linux/netdevice.h>
 944 +#include <linux/types.h>
 945 +#include <asm/uaccess.h>
 946 +#include <linux/moduleparam.h>
 947 +
 948 +char *ifname="eth3";
 949 +
 950 +
 951 +static int32_t PktGenInitMod(void)
 952 +{
 953 +#if 0
 954 +    unsigned char pkt_0[]={
 955 +//    0x00, 0x21, 0x86, 0xee, 0xe3, 0x95, // dest mac
 956 +    0x00, 0x21, 0x86, 0xee, 0xe3, 0x90, // dest mac
 957 +    0x00, 0x0c, 0x43, 0x28, 0x80, 0x33, // src mac
 958 +    0x08, 0x00, // type: ip
 959 +    0x45, 0x00, 0x00, 0x26, // ip: ..., total len (0x026 = 38)
 960 +//    0xa1, 0x78, 0x20, 0x00, // ip: id, frag, frag offset
 961 +    0xa1, 0x78, 0x40, 0x00, // ip: id, frag, frag offset
 962 +    0x40, 0x11, 0x63, 0x07, // ip: ttl, protocol, hdr checksum (0x6307)
 963 +    0x0a, 0x0a, 0x1e, 0x7b, // src ip (10.10.30.123)
 964 +//    0x0a, 0x0a, 0x1e, 0x03, // dst ip (10.10.30.3)
 965 +    0x0a, 0x0a, 0x1e, 0x05, // dst ip (10.10.30.5)
 966 +    0xca, 0x7b,  //udp src port
 967 +    0x13, 0x89,  //udp dst port
 968 +    0x00, 0x12,  //udp len (0x01c = 18)
 969 +    0x2f, 0x96,  //udp checksum (0x2f96)
 970 +    0x01, 0x02, 0x03, 0x04, 0x05,  //payload (10 bytes)
 971 +    0x06, 0x07, 0x08, 0x09, 0x0a
 972 +    };
 973 +#endif
 974 +
 975 +    unsigned char pkt_1[]={
 976 +//    0x00, 0x21, 0x86, 0xee, 0xe3, 0x95, // dest mac
 977 +    0x00, 0x21, 0x86, 0xee, 0xe3, 0x90, // dest mac
 978 +    0x00, 0x0c, 0x43, 0x28, 0x80, 0x33, // src mac
 979 +    0x08, 0x00, // type: ip
 980 +    0x45, 0x00, 0x00, 0x24, // ip: ..., total len (0x024 = 36)
 981 +    0xa1, 0x78, 0x20, 0x00, // ip: id, frag, frag offset
 982 +//    0xa1, 0x78, 0x40, 0x00, // ip: id, frag, frag offset
 983 +    0x40, 0x11, 0x63, 0x07, // ip: ttl, protocol, hdr checksum (0x6307)
 984 +    0x0a, 0x0a, 0x1e, 0x7b, // src ip (10.10.30.123)
 985 +//    0x0a, 0x0a, 0x1e, 0x03, // dst ip (10.10.30.3)
 986 +    0x0a, 0x0a, 0x1e, 0x05, // dst ip (10.10.30.5)
 987 +    0xca, 0x7b,  //udp src port
 988 +    0x13, 0x89,  //udp dst port
 989 +    0x00, 0x1a,  //udp len (0x01a = 26)
 990 +    0x2f, 0x96,  //udp checksum (0x2f96)
 991 +    0x01, 0x02, 0x03, 0x04, 0x05,  //payload (8 bytes)
 992 +    0x06, 0x07, 0x08
 993 +    };
 994 +
 995 +    unsigned char pkt_2[]={
 996 +//    0x00, 0x21, 0x86, 0xee, 0xe3, 0x95, // dest mac
 997 +    0x00, 0x21, 0x86, 0xee, 0xe3, 0x90, // dest mac
 998 +    0x00, 0x0c, 0x43, 0x28, 0x80, 0x33, // src mac
 999 +    0x08, 0x00, // type: ip
1000 +    0x45, 0x00, 0x00, 0x1e, // ip: ..., total len (0x01e = 30)
1001 +    0xa1, 0x78, 0x00, 0x02, // ip: id, frag, frag offset (16)
1002 +    0x40, 0x11, 0x63, 0x07, // ip: ttl, protocol, hdr checksum (0x6307)
1003 +    0x0a, 0x0a, 0x1e, 0x7b, // src ip (10.10.30.123)
1004 +//   0x0a, 0x0a, 0x1e, 0x03, // dst ip (10.10.30.3)
1005 +    0x0a, 0x0a, 0x1e, 0x05, // dst ip (10.10.30.5)
1006 +    0x11, 0x12, 0x13, 0x14, 0x15,  //payload (10 bytes)
1007 +    0x16, 0x17, 0x18, 0x19, 0x1a
1008 +    };
1009 +
1010 +    struct net_dev *dev;
1011 +//    struct sk_buff *skb_0;
1012 +    struct sk_buff *skb_1;
1013 +    struct sk_buff *skb_2;
1014 +    int i=0;
1015 +
1016 +//    skb_0 = alloc_skb(256, GFP_ATOMIC);
1017 +    skb_1 = alloc_skb(256, GFP_ATOMIC);
1018 +    skb_2 = alloc_skb(256, GFP_ATOMIC);
1019 +
1020 +#if 0
1021 +/* send packet 0 */
1022 +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,35)
1023 +    if((dev=dev_get_by_name(&init_net,ifname))){
1024 +#else
1025 +    if((dev=dev_get_by_name(ifname))){
1026 +#endif
1027 +
1028 +       skb_0->dev=dev;
1029 +       skb_put(skb_0,sizeof(pkt_0));
1030 +       memcpy(skb_0->data, pkt_0, sizeof(pkt_0));
1031 +
1032 +       printk("send pkt(len=%d) to %s\n", skb_0->len, skb_0->dev->name);
1033 +
1034 +
1035 +       for(i=0;i<sizeof(pkt_0);i++){
1036 +           if(i%16==0) {
1037 +               printk("\n");
1038 +           }
1039 +           printk("%02X-",skb_0->data[i]);
1040 +       }
1041 +
1042 +       dev_queue_xmit(skb_0);
1043 +    }else{
1044 +       printk("interface %s not found\n",ifname);
1045 +       return 1;
1046 +    }
1047 +#endif
1048 +
1049 +#if 1
1050 +/* send packet 1 */
1051 +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,35)
1052 +    if((dev=dev_get_by_name(&init_net,ifname))){
1053 +#else
1054 +    if((dev=dev_get_by_name(ifname))){
1055 +#endif
1056 +
1057 +       skb_1->dev=dev;
1058 +       skb_put(skb_1,sizeof(pkt_1));
1059 +       memcpy(skb_1->data, pkt_1, sizeof(pkt_1));
1060 +
1061 +       printk("send pkt(len=%d) to %s\n", skb_1->len, skb_1->dev->name);
1062 +
1063 +
1064 +       for(i=0;i<sizeof(pkt_1);i++){
1065 +           if(i%16==0) {
1066 +               printk("\n");
1067 +           }
1068 +           printk("%02X-",skb_1->data[i]);
1069 +       }
1070 +
1071 +       dev_queue_xmit(skb_1);
1072 +    }else{
1073 +       printk("interface %s not found\n",ifname);
1074 +       return 1;
1075 +    }
1076 +#endif
1077 +
1078 +#if 1
1079 +/* send packet 2 */
1080 +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,35)
1081 +        if((dev=dev_get_by_name(&init_net,ifname))){
1082 +#else
1083 +        if((dev=dev_get_by_name(ifname))){
1084 +#endif
1085 +
1086 +       skb_2->dev=dev;
1087 +       skb_put(skb_2,sizeof(pkt_2));
1088 +       memcpy(skb_2->data, pkt_2, sizeof(pkt_2));
1089 +
1090 +       printk("send pkt(len=%d) to %s\n", skb_2->len, skb_2->dev->name);
1091 +
1092 +
1093 +       for(i=0;i<sizeof(pkt_2);i++){
1094 +           if(i%16==0) {
1095 +               printk("\n");
1096 +           }
1097 +           printk("%02X-",skb_2->data[i]);
1098 +       }
1099 +
1100 +       dev_queue_xmit(skb_2);
1101 +    }else{
1102 +       printk("interface %s not found\n",ifname);
1103 +       return 1;
1104 +    }
1105 +#endif
1106 +
1107 +    return 0;
1108 +}
1109 +
1110 +static void PktGenCleanupMod(void)
1111 +{
1112 +}
1113 +
1114 +module_init(PktGenInitMod);
1115 +module_exit(PktGenCleanupMod);
1116 +#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,12)
1117 +MODULE_PARM (ifname, "s");
1118 +#else
1119 +module_param (ifname, charp, 0);
1120 +#endif
1121 +
1122 +MODULE_DESCRIPTION("Ralink PktGen Module");
1123 +MODULE_AUTHOR("Steven Liu");
1124 +MODULE_LICENSE("Proprietary");
1125 +MODULE_PARM_DESC (ifname, "interface name");
1126 +
1127 diff --git a/drivers/net/ethernet/raeth/dvt/raether_pdma_dvt.c b/drivers/net/ethernet/raeth/dvt/raether_pdma_dvt.c
1128 new file mode 100755
1129 index 0000000..971a821
1130 --- /dev/null
1131 +++ b/drivers/net/ethernet/raeth/dvt/raether_pdma_dvt.c
1132 @@ -0,0 +1,1527 @@
1133 +#include <linux/module.h>
1134 +#include <linux/version.h>
1135 +#include <linux/kernel.h>
1136 +#include <linux/types.h>
1137 +#include <linux/pci.h>
1138 +#include <linux/init.h>
1139 +#include <linux/skbuff.h>
1140 +#include <linux/if_vlan.h>
1141 +#include <linux/if_ether.h>
1142 +#include <linux/fs.h>
1143 +#include <asm/uaccess.h>
1144 +#include <asm/rt2880/surfboardint.h>
1145 +#if defined(CONFIG_RAETH_TSO)
1146 +#include <linux/tcp.h>
1147 +#include <net/ipv6.h>
1148 +#include <linux/ip.h>
1149 +#include <net/ip.h>
1150 +#include <net/tcp.h>
1151 +#include <linux/in.h>
1152 +#include <linux/ppp_defs.h>
1153 +#include <linux/if_pppox.h>
1154 +#endif
1155 +#if defined(CONFIG_RAETH_LRO)
1156 +#include <linux/inet_lro.h>
1157 +#endif
1158 +#include <linux/delay.h>
1159 +#if LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 35)
1160 +#include <linux/sched.h>
1161 +#endif
1162 +
1163 +#if LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 0)
1164 +#include <asm/rt2880/rt_mmap.h>
1165 +#else
1166 +#include <linux/libata-compat.h>
1167 +#endif
1168 +
1169 +#include "../ra2882ethreg.h"
1170 +#include "../raether.h"
1171 +#include "../ra_mac.h"
1172 +#include "../ra_ioctl.h"
1173 +#include "../ra_rfrw.h"
1174 +#ifdef CONFIG_RAETH_NETLINK
1175 +#include "../ra_netlink.h"
1176 +#endif
1177 +#if defined(CONFIG_RAETH_QOS)
1178 +#include "../ra_qos.h"
1179 +#endif
1180 +#include "raether_pdma_dvt.h"
1181 +
1182 +/* Global variables */
1183 +static unsigned int g_pdma_dvt_show_config;
1184 +static unsigned int g_pdma_dvt_rx_test_config;
1185 +static unsigned int g_pdma_dvt_tx_test_config;
1186 +static unsigned int g_pdma_dvt_debug_test_config;
1187 +static unsigned int g_pdma_dvt_lro_test_config;
1188 +
1189 +unsigned int g_pdma_dev_lanport = 0;
1190 +unsigned int g_pdma_dev_wanport = 0;
1191 +
1192 +void skb_dump(struct sk_buff *sk)
1193 +{
1194 +       unsigned int i;
1195 +
1196 +       printk("skb_dump: from %s with len %d (%d) headroom=%d tailroom=%d\n",
1197 +              sk->dev ? sk->dev->name : "ip stack", sk->len, sk->truesize,
1198 +              skb_headroom(sk), skb_tailroom(sk));
1199 +
1200 +       /* for(i=(unsigned int)sk->head;i<=(unsigned int)sk->tail;i++) { */
1201 +       /* for(i=(unsigned int)sk->head;i<=(unsigned int)sk->data+20;i++) { */
1202 +       for (i = (unsigned int)sk->head; i <= (unsigned int)sk->data + 60; i++) {
1203 +               if ((i % 20) == 0)
1204 +                       printk("\n");
1205 +               if (i == (unsigned int)sk->data)
1206 +                       printk("{");
1207 +#if LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 21)
1208 +               if (i == (unsigned int)sk->transport_header)
1209 +                       printk("#");
1210 +               if (i == (unsigned int)sk->network_header)
1211 +                       printk("|");
1212 +               if (i == (unsigned int)sk->mac_header)
1213 +                       printk("*");
1214 +#else
1215 +               if (i == (unsigned int)sk->h.raw)
1216 +                       printk("#");
1217 +               if (i == (unsigned int)sk->nh.raw)
1218 +                       printk("|");
1219 +               if (i == (unsigned int)sk->mac.raw)
1220 +                       printk("*");
1221 +#endif
1222 +               printk("%02X-", *((unsigned char *)i));
1223 +               if (i == (unsigned int)sk->tail)
1224 +                       printk("}");
1225 +       }
1226 +       printk("\n");
1227 +}
1228 +
1229 +#if defined(CONFIG_RAETH_HW_LRO)
1230 +/* PDMA LRO test functions start */
1231 +int pdma_lro_disable_dvt(void)
1232 +{
1233 +       unsigned int regVal = 0;
1234 +
1235 +       printk("pdma_lro_disable_dvt()\n");
1236 +
1237 +       /* 1. Invalid LRO ring1~3 */
1238 +       SET_PDMA_RXRING_VALID(ADMA_RX_RING1, 0);
1239 +       SET_PDMA_RXRING_VALID(ADMA_RX_RING2, 0);
1240 +       SET_PDMA_RXRING_VALID(ADMA_RX_RING3, 0);
1241 +
1242 +       /* 2 Polling relinguish */
1243 +       while (sysRegRead(ADMA_LRO_CTRL_DW0) & PDMA_LRO_RELINGUISH) {;
1244 +       }
1245 +
1246 +       /* 3. Disable LRO */
1247 +       regVal = sysRegRead(ADMA_LRO_CTRL_DW0);
1248 +       regVal &= ~(PDMA_LRO_EN);
1249 +       sysRegWrite(ADMA_LRO_CTRL_DW0, regVal);
1250 +
1251 +#if 0
1252 +       /* 4. Disable non-lro multiple rx */
1253 +       SET_PDMA_NON_LRO_MULTI_EN(0);
1254 +
1255 +       /* 5.1. Set GDM1 to ring0 */
1256 +       SET_GDM_PID1_RXID_SEL(0);
1257 +       /* 5.2. Set GDM2 to ring0 */
1258 +       SET_GDM_PID2_RXID_SEL(0);
1259 +#endif
1260 +
1261 +       return 0;
1262 +}
1263 +
1264 +int pdma_lro_force_aggre_dvt(void)
1265 +{
1266 +       unsigned int regVal = 0;
1267 +       unsigned int ip;
1268 +
1269 +       printk("pdma_lro_force_aggre_dvt()\n");
1270 +
1271 +/* pdma rx ring1 */
1272 +       /* 1. Set RX ring mode to force port */
1273 +       SET_PDMA_RXRING_MODE(ADMA_RX_RING1, PDMA_RX_FORCE_PORT);
1274 +
1275 +       /* 2. Configure lro ring */
1276 +       /* 2.1 set src/destination TCP ports */
1277 +       SET_PDMA_RXRING_TCP_SRC_PORT(ADMA_RX_RING1, 3423);
1278 +       SET_PDMA_RXRING_TCP_DEST_PORT(ADMA_RX_RING1, 2301);
1279 +       /* 2.2 set src/destination IPs */
1280 +       str_to_ip(&ip, "10.10.10.3");
1281 +       sysRegWrite(LRO_RX_RING1_SIP_DW0, ip);
1282 +       str_to_ip(&ip, "10.10.10.100");
1283 +       sysRegWrite(LRO_RX_RING1_DIP_DW0, ip);
1284 +       SET_PDMA_RXRING_MYIP_VALID(ADMA_RX_RING1, 1);
1285 +
1286 +       /* 2.3 Valid LRO ring */
1287 +       SET_PDMA_RXRING_VALID(ADMA_RX_RING1, 1);
1288 +
1289 +       /* 2.4 Set AGE timer */
1290 +       SET_PDMA_RXRING_AGE_TIME(ADMA_RX_RING1, 0);
1291 +
1292 +       /* 2.5 Set max AGG timer */
1293 +       SET_PDMA_RXRING_AGG_TIME(ADMA_RX_RING1, 0);
1294 +
1295 +       /* 2.6 Set max LRO agg count */
1296 +       SET_PDMA_RXRING_MAX_AGG_CNT(ADMA_RX_RING1, HW_LRO_MAX_AGG_CNT);
1297 +
1298 +       /* 3. IPv4 checksum update enable */
1299 +       SET_PDMA_LRO_IPV4_CSUM_UPDATE_EN(1);
1300 +
1301 +       /* 4. Polling relinguish */
1302 +       while (sysRegRead(ADMA_LRO_CTRL_DW0) & PDMA_LRO_RELINGUISH) {;
1303 +       }
1304 +
1305 +       /* 5. Enable LRO */
1306 +       regVal = sysRegRead(ADMA_LRO_CTRL_DW0);
1307 +       regVal |= PDMA_LRO_EN;
1308 +       sysRegWrite(ADMA_LRO_CTRL_DW0, regVal);
1309 +
1310 +       return 0;
1311 +}
1312 +
1313 +int pdma_lro_auto_aggre_dvt(void)
1314 +{
1315 +       unsigned int regVal = 0;
1316 +       unsigned int ip;
1317 +
1318 +       printk("pdma_lro_auto_aggre_dvt()\n");
1319 +
1320 +       /* 1.1 Set my IP_1 */
1321 +       str_to_ip(&ip, "10.10.10.254");
1322 +       sysRegWrite(LRO_RX_RING0_DIP_DW0, ip);
1323 +       sysRegWrite(LRO_RX_RING0_DIP_DW1, 0);
1324 +       sysRegWrite(LRO_RX_RING0_DIP_DW2, 0);
1325 +       sysRegWrite(LRO_RX_RING0_DIP_DW3, 0);
1326 +       SET_PDMA_RXRING_MYIP_VALID(ADMA_RX_RING0, 1);
1327 +
1328 +       /* 1.2 Set my IP_2 */
1329 +       str_to_ip(&ip, "10.10.20.254");
1330 +       sysRegWrite(LRO_RX_RING1_DIP_DW0, ip);
1331 +       sysRegWrite(LRO_RX_RING1_DIP_DW1, 0);
1332 +       sysRegWrite(LRO_RX_RING1_DIP_DW2, 0);
1333 +       sysRegWrite(LRO_RX_RING1_DIP_DW3, 0);
1334 +       SET_PDMA_RXRING_MYIP_VALID(ADMA_RX_RING1, 1);
1335 +
1336 +       /* 1.3 Set my IP_3 */
1337 +       sysRegWrite(LRO_RX_RING2_DIP_DW3, 0x20010238);
1338 +       sysRegWrite(LRO_RX_RING2_DIP_DW2, 0x08000000);
1339 +       sysRegWrite(LRO_RX_RING2_DIP_DW1, 0x00000000);
1340 +       sysRegWrite(LRO_RX_RING2_DIP_DW0, 0x00000254);
1341 +       SET_PDMA_RXRING_MYIP_VALID(ADMA_RX_RING2, 1);
1342 +
1343 +       /* 1.4 Set my IP_4 */
1344 +       sysRegWrite(LRO_RX_RING3_DIP_DW3, 0x20010238);
1345 +       sysRegWrite(LRO_RX_RING3_DIP_DW2, 0x08010000);
1346 +       sysRegWrite(LRO_RX_RING3_DIP_DW1, 0x00000000);
1347 +       sysRegWrite(LRO_RX_RING3_DIP_DW0, 0x00000254);
1348 +       SET_PDMA_RXRING_MYIP_VALID(ADMA_RX_RING3, 1);
1349 +
1350 +       /* 2.1 Set RX ring1~3 to auto-learn modes */
1351 +       SET_PDMA_RXRING_MODE(ADMA_RX_RING1, PDMA_RX_AUTO_LEARN);
1352 +       SET_PDMA_RXRING_MODE(ADMA_RX_RING2, PDMA_RX_AUTO_LEARN);
1353 +       SET_PDMA_RXRING_MODE(ADMA_RX_RING3, PDMA_RX_AUTO_LEARN);
1354 +
1355 +       /* 2.2 Valid LRO ring */
1356 +       SET_PDMA_RXRING_VALID(ADMA_RX_RING0, 1);
1357 +       SET_PDMA_RXRING_VALID(ADMA_RX_RING1, 1);
1358 +       SET_PDMA_RXRING_VALID(ADMA_RX_RING2, 1);
1359 +       SET_PDMA_RXRING_VALID(ADMA_RX_RING3, 1);
1360 +
1361 +       /* 2.3 Set AGE timer */
1362 +       SET_PDMA_RXRING_AGE_TIME(ADMA_RX_RING1, 0);
1363 +       SET_PDMA_RXRING_AGE_TIME(ADMA_RX_RING2, 0);
1364 +       SET_PDMA_RXRING_AGE_TIME(ADMA_RX_RING3, 0);
1365 +
1366 +       /* 2.4 Set max AGG timer */
1367 +       SET_PDMA_RXRING_AGG_TIME(ADMA_RX_RING1, 0);
1368 +       SET_PDMA_RXRING_AGG_TIME(ADMA_RX_RING2, 0);
1369 +       SET_PDMA_RXRING_AGG_TIME(ADMA_RX_RING3, 0);
1370 +
1371 +       /* 2.5 Set max LRO agg count */
1372 +       SET_PDMA_RXRING_MAX_AGG_CNT(ADMA_RX_RING1, HW_LRO_MAX_AGG_CNT);
1373 +       SET_PDMA_RXRING_MAX_AGG_CNT(ADMA_RX_RING2, HW_LRO_MAX_AGG_CNT);
1374 +       SET_PDMA_RXRING_MAX_AGG_CNT(ADMA_RX_RING3, HW_LRO_MAX_AGG_CNT);
1375 +
1376 +       /* 3.0 IPv6 LRO enable */
1377 +       SET_PDMA_LRO_IPV6_EN(1);
1378 +
1379 +       /* 3.1 IPv4 checksum update disable */
1380 +       SET_PDMA_LRO_IPV4_CSUM_UPDATE_EN(1);
1381 +
1382 +       /* 3.2 switch priority comparision to byte count mode */
1383 +       SET_PDMA_LRO_ALT_SCORE_MODE(PDMA_LRO_ALT_BYTE_CNT_MODE);
1384 +
1385 +       /* 3.3 bandwidth threshold setting */
1386 +       SET_PDMA_LRO_BW_THRESHOLD(0);
1387 +
1388 +       /* 3.4 auto-learn score delta setting */
1389 +       sysRegWrite(LRO_ALT_SCORE_DELTA, 0);
1390 +
1391 +       /* 3.5 Set ALT timer to 20us: (unit: 20us) */
1392 +       SET_PDMA_LRO_ALT_REFRESH_TIMER_UNIT(HW_LRO_TIMER_UNIT);
1393 +       /* 3.6 Set ALT refresh timer to 1 sec. (unit: 20us) */
1394 +       SET_PDMA_LRO_ALT_REFRESH_TIMER(HW_LRO_REFRESH_TIME);
1395 +
1396 +       /* 4. Polling relinguish */
1397 +       while (sysRegRead(ADMA_LRO_CTRL_DW0) & PDMA_LRO_RELINGUISH) {;
1398 +       }
1399 +
1400 +       /* 5. Enable LRO */
1401 +       regVal = sysRegRead(ADMA_LRO_CTRL_DW0);
1402 +       regVal |= PDMA_LRO_EN;
1403 +       sysRegWrite(ADMA_LRO_CTRL_DW0, regVal);
1404 +
1405 +       return 0;
1406 +}
1407 +
1408 +int pdma_lro_auto_ipv6_dvt(void)
1409 +{
1410 +       unsigned int regVal = 0;
1411 +
1412 +       printk("pdma_lro_auto_ipv6_dvt()\n");
1413 +
1414 +       /* 1. Set my IP */
1415 +       sysRegWrite(LRO_RX_RING1_DIP_DW3, 0x20010238);
1416 +       sysRegWrite(LRO_RX_RING1_DIP_DW2, 0x08000000);
1417 +       sysRegWrite(LRO_RX_RING1_DIP_DW1, 0x00000000);
1418 +       sysRegWrite(LRO_RX_RING1_DIP_DW0, 0x00000254);
1419 +
1420 +       /* 2.1 Set RX ring1~3 to auto-learn modes */
1421 +       SET_PDMA_RXRING_MODE(ADMA_RX_RING1, PDMA_RX_AUTO_LEARN);
1422 +       SET_PDMA_RXRING_MODE(ADMA_RX_RING2, PDMA_RX_AUTO_LEARN);
1423 +       SET_PDMA_RXRING_MODE(ADMA_RX_RING3, PDMA_RX_AUTO_LEARN);
1424 +
1425 +       /* 2.2 Valid LRO ring */
1426 +       SET_PDMA_RXRING_VALID(ADMA_RX_RING1, 1);
1427 +       SET_PDMA_RXRING_VALID(ADMA_RX_RING2, 1);
1428 +       SET_PDMA_RXRING_VALID(ADMA_RX_RING3, 1);
1429 +
1430 +       /* 2.3 Set AGE timer */
1431 +       SET_PDMA_RXRING_AGE_TIME(ADMA_RX_RING1, HW_LRO_AGE_TIME);
1432 +       SET_PDMA_RXRING_AGE_TIME(ADMA_RX_RING2, HW_LRO_AGE_TIME);
1433 +       SET_PDMA_RXRING_AGE_TIME(ADMA_RX_RING3, HW_LRO_AGE_TIME);
1434 +
1435 +       /* 3.0 IPv6 LRO enable */
1436 +       SET_PDMA_LRO_IPV6_EN(1);
1437 +
1438 +       /* 3.1 IPv4 checksum update disable */
1439 +       SET_PDMA_LRO_IPV4_CSUM_UPDATE_EN(1);
1440 +
1441 +       /* 3.2 switch priority comparision to byte count mode */
1442 +       SET_PDMA_LRO_ALT_SCORE_MODE(PDMA_LRO_ALT_BYTE_CNT_MODE);
1443 +
1444 +       /* 3.3 bandwidth threshold setting */
1445 +       SET_PDMA_LRO_BW_THRESHOLD(0);
1446 +
1447 +       /* 3.4 auto-learn score delta setting */
1448 +       sysRegWrite(LRO_ALT_SCORE_DELTA, 0);
1449 +
1450 +       /* 3.5 Set ALT timer to 500us: (unit: 20us) */
1451 +       SET_PDMA_LRO_ALT_REFRESH_TIMER_UNIT(25);
1452 +       /* 3.6 Set ALT refresh timer to 1 sec. (unit: 500us) */
1453 +       SET_PDMA_LRO_ALT_REFRESH_TIMER(2000);
1454 +
1455 +       /* 3.7 Set max AGG timer: 10 msec. */
1456 +       SET_PDMA_LRO_MAX_AGG_TIME(HW_LRO_AGG_TIME);
1457 +
1458 +       /* 4. Polling relinguish */
1459 +       while (sysRegRead(ADMA_LRO_CTRL_DW0) & PDMA_LRO_RELINGUISH) {;
1460 +       }
1461 +
1462 +       /* 5. Enable LRO */
1463 +       regVal = sysRegRead(ADMA_LRO_CTRL_DW0);
1464 +       regVal |= PDMA_LRO_EN;
1465 +       sysRegWrite(ADMA_LRO_CTRL_DW0, regVal);
1466 +
1467 +       return 0;
1468 +}
1469 +
1470 +int pdma_lro_auto_myIP_dvt(void)
1471 +{
1472 +       unsigned int regVal = 0;
1473 +       unsigned int ip;
1474 +
1475 +       printk("pdma_lro_auto_myIP_dvt()\n");
1476 +
1477 +       /* 1.1 Set my IP_1 */
1478 +       str_to_ip(&ip, "10.10.10.254");
1479 +       sysRegWrite(LRO_RX_RING0_DIP_DW0, ip);
1480 +       sysRegWrite(LRO_RX_RING0_DIP_DW1, 0);
1481 +       sysRegWrite(LRO_RX_RING0_DIP_DW2, 0);
1482 +       sysRegWrite(LRO_RX_RING0_DIP_DW3, 0);
1483 +       SET_PDMA_RXRING_MYIP_VALID(ADMA_RX_RING0, 1);
1484 +       /* 1.2 Set my IP_2 */
1485 +       str_to_ip(&ip, "10.10.20.254");
1486 +       sysRegWrite(LRO_RX_RING1_DIP_DW0, ip);
1487 +       sysRegWrite(LRO_RX_RING1_DIP_DW1, 0);
1488 +       sysRegWrite(LRO_RX_RING1_DIP_DW2, 0);
1489 +       sysRegWrite(LRO_RX_RING1_DIP_DW3, 0);
1490 +       SET_PDMA_RXRING_MYIP_VALID(ADMA_RX_RING1, 1);
1491 +       /* 1.3 Set my IP_3 */
1492 +       sysRegWrite(LRO_RX_RING2_DIP_DW3, 0x20010238);
1493 +       sysRegWrite(LRO_RX_RING2_DIP_DW2, 0x08000000);
1494 +       sysRegWrite(LRO_RX_RING2_DIP_DW1, 0x00000000);
1495 +       sysRegWrite(LRO_RX_RING2_DIP_DW0, 0x00000254);
1496 +       SET_PDMA_RXRING_MYIP_VALID(ADMA_RX_RING2, 1);
1497 +       /* 1.4 Set my IP_4 */
1498 +       sysRegWrite(LRO_RX_RING3_DIP_DW3, 0x20010238);
1499 +       sysRegWrite(LRO_RX_RING3_DIP_DW2, 0x08010000);
1500 +       sysRegWrite(LRO_RX_RING3_DIP_DW1, 0x00000000);
1501 +       sysRegWrite(LRO_RX_RING3_DIP_DW0, 0x00000254);
1502 +       SET_PDMA_RXRING_MYIP_VALID(ADMA_RX_RING3, 1);
1503 +
1504 +       /* 2.1 Set RX ring1~3 to auto-learn modes */
1505 +       SET_PDMA_RXRING_MODE(ADMA_RX_RING1, PDMA_RX_AUTO_LEARN);
1506 +       SET_PDMA_RXRING_MODE(ADMA_RX_RING2, PDMA_RX_AUTO_LEARN);
1507 +       SET_PDMA_RXRING_MODE(ADMA_RX_RING3, PDMA_RX_AUTO_LEARN);
1508 +
1509 +       /* 2.2 Valid LRO ring */
1510 +       SET_PDMA_RXRING_VALID(ADMA_RX_RING0, 1);
1511 +       SET_PDMA_RXRING_VALID(ADMA_RX_RING1, 1);
1512 +       SET_PDMA_RXRING_VALID(ADMA_RX_RING2, 1);
1513 +       SET_PDMA_RXRING_VALID(ADMA_RX_RING3, 1);
1514 +
1515 +       /* 2.3 Set AGE timer */
1516 +       SET_PDMA_RXRING_AGE_TIME(ADMA_RX_RING1, HW_LRO_AGE_TIME);
1517 +       SET_PDMA_RXRING_AGE_TIME(ADMA_RX_RING2, HW_LRO_AGE_TIME);
1518 +       SET_PDMA_RXRING_AGE_TIME(ADMA_RX_RING3, HW_LRO_AGE_TIME);
1519 +
1520 +       /* 3.0 IPv6 LRO enable */
1521 +       SET_PDMA_LRO_IPV6_EN(1);
1522 +
1523 +       /* 3.1 IPv4 checksum update disable */
1524 +       SET_PDMA_LRO_IPV4_CSUM_UPDATE_EN(1);
1525 +
1526 +       /* 3.2 switch priority comparision to byte count mode */
1527 +       SET_PDMA_LRO_ALT_SCORE_MODE(PDMA_LRO_ALT_BYTE_CNT_MODE);
1528 +
1529 +       /* 3.3 bandwidth threshold setting */
1530 +       SET_PDMA_LRO_BW_THRESHOLD(0);
1531 +
1532 +       /* 3.4 auto-learn score delta setting */
1533 +       sysRegWrite(LRO_ALT_SCORE_DELTA, 0);
1534 +
1535 +       /* 3.5 Set ALT timer to 500us: (unit: 20us) */
1536 +       SET_PDMA_LRO_ALT_REFRESH_TIMER_UNIT(25);
1537 +       /* 3.6 Set ALT refresh timer to 1 sec. (unit: 500us) */
1538 +       SET_PDMA_LRO_ALT_REFRESH_TIMER(2000);
1539 +
1540 +       /* 3.7 Set max AGG timer: 10 msec. */
1541 +       SET_PDMA_LRO_MAX_AGG_TIME(HW_LRO_AGG_TIME);
1542 +
1543 +       /* 4. Polling relinguish */
1544 +       while (sysRegRead(ADMA_LRO_CTRL_DW0) & PDMA_LRO_RELINGUISH) {;
1545 +       }
1546 +
1547 +       /* 5. Enable LRO */
1548 +       regVal = sysRegRead(ADMA_LRO_CTRL_DW0);
1549 +       regVal |= PDMA_LRO_EN;
1550 +       sysRegWrite(ADMA_LRO_CTRL_DW0, regVal);
1551 +
1552 +       return 0;
1553 +}
1554 +
1555 +int pdma_lro_dly_int_dvt(int index)
1556 +{
1557 +       unsigned int regVal = 0;
1558 +       unsigned int ip;
1559 +
1560 +       printk("pdma_lro_dly_int_dvt(%d)\n", index);
1561 +
1562 +#if 0
1563 +       /* 1.1 Set my IP_1 */
1564 +       /* str_to_ip( &ip, "10.10.10.254" ); */
1565 +       str_to_ip(&ip, "10.10.10.100");
1566 +       sysRegWrite(LRO_RX_RING0_DIP_DW0, ip);
1567 +       sysRegWrite(LRO_RX_RING0_DIP_DW1, 0);
1568 +       sysRegWrite(LRO_RX_RING0_DIP_DW2, 0);
1569 +       sysRegWrite(LRO_RX_RING0_DIP_DW3, 0);
1570 +#else
1571 +       /* 1.1 set src/destination TCP ports */
1572 +       SET_PDMA_RXRING_TCP_SRC_PORT(ADMA_RX_RING1, 3423);
1573 +       SET_PDMA_RXRING_TCP_DEST_PORT(ADMA_RX_RING1, 2301);
1574 +       SET_PDMA_RXRING_TCP_SRC_PORT(ADMA_RX_RING2, 3423);
1575 +       SET_PDMA_RXRING_TCP_DEST_PORT(ADMA_RX_RING2, 2301);
1576 +       SET_PDMA_RXRING_TCP_SRC_PORT(ADMA_RX_RING3, 3423);
1577 +       SET_PDMA_RXRING_TCP_DEST_PORT(ADMA_RX_RING3, 2301);
1578 +       /* 1.2 set src/destination IPs */
1579 +       str_to_ip(&ip, "10.10.10.3");
1580 +       sysRegWrite(LRO_RX_RING1_SIP_DW0, ip);
1581 +       str_to_ip(&ip, "10.10.10.100");
1582 +       sysRegWrite(LRO_RX_RING1_DIP_DW0, ip);
1583 +       str_to_ip(&ip, "10.10.10.3");
1584 +       sysRegWrite(LRO_RX_RING2_SIP_DW0, ip);
1585 +       str_to_ip(&ip, "10.10.10.100");
1586 +       sysRegWrite(LRO_RX_RING2_DIP_DW0, ip);
1587 +       str_to_ip(&ip, "10.10.10.3");
1588 +       sysRegWrite(LRO_RX_RING3_SIP_DW0, ip);
1589 +       str_to_ip(&ip, "10.10.10.100");
1590 +       sysRegWrite(LRO_RX_RING3_DIP_DW0, ip);
1591 +       SET_PDMA_RXRING_MYIP_VALID(ADMA_RX_RING1, 1);
1592 +       SET_PDMA_RXRING_MYIP_VALID(ADMA_RX_RING2, 1);
1593 +       SET_PDMA_RXRING_MYIP_VALID(ADMA_RX_RING3, 1);
1594 +#endif
1595 +
1596 +       if (index == 0) {
1597 +               /* 1.2 Disable DLY_INT for lro ring */
1598 +               SET_PDMA_LRO_DLY_INT_EN(0);
1599 +       } else {
1600 +               /* 1.2 Enable DLY_INT for lro ring */
1601 +               SET_PDMA_LRO_DLY_INT_EN(1);
1602 +       }
1603 +
1604 +       /* 1.3 LRO ring DLY_INT setting */
1605 +       if (index == 1) {
1606 +               sysRegWrite(LRO_RX1_DLY_INT, DELAY_INT_INIT);
1607 +       } else if (index == 2) {
1608 +               sysRegWrite(LRO_RX2_DLY_INT, DELAY_INT_INIT);
1609 +       } else if (index == 3) {
1610 +               sysRegWrite(LRO_RX3_DLY_INT, DELAY_INT_INIT);
1611 +       }
1612 +#if 0
1613 +       /* 2.1 Set RX rings to auto-learn modes */
1614 +       SET_PDMA_RXRING_MODE(ADMA_RX_RING1, PDMA_RX_AUTO_LEARN);
1615 +       SET_PDMA_RXRING_MODE(ADMA_RX_RING2, PDMA_RX_AUTO_LEARN);
1616 +       SET_PDMA_RXRING_MODE(ADMA_RX_RING3, PDMA_RX_AUTO_LEARN);
1617 +#else
1618 +       /* 2.0 set rx ring mode */
1619 +       SET_PDMA_RXRING_MODE(ADMA_RX_RING1, PDMA_RX_FORCE_PORT);
1620 +       SET_PDMA_RXRING_MODE(ADMA_RX_RING2, PDMA_RX_FORCE_PORT);
1621 +       SET_PDMA_RXRING_MODE(ADMA_RX_RING3, PDMA_RX_FORCE_PORT);
1622 +
1623 +       /* 2.1 IPv4 force port mode */
1624 +       SET_PDMA_RXRING_IPV4_FORCE_MODE(ADMA_RX_RING1, 1);
1625 +       SET_PDMA_RXRING_IPV4_FORCE_MODE(ADMA_RX_RING2, 1);
1626 +       SET_PDMA_RXRING_IPV4_FORCE_MODE(ADMA_RX_RING3, 1);
1627 +#endif
1628 +
1629 +       /* 2.2 Valid LRO ring */
1630 +       SET_PDMA_RXRING_VALID(ADMA_RX_RING0, 1);
1631 +       if ((index == 0) || (index == 1)) {
1632 +               SET_PDMA_RXRING_VALID(ADMA_RX_RING1, 1);
1633 +               SET_PDMA_RXRING_VALID(ADMA_RX_RING2, 0);
1634 +               SET_PDMA_RXRING_VALID(ADMA_RX_RING3, 0);
1635 +       } else if (index == 2) {
1636 +               SET_PDMA_RXRING_VALID(ADMA_RX_RING1, 0);
1637 +               SET_PDMA_RXRING_VALID(ADMA_RX_RING2, 1);
1638 +               SET_PDMA_RXRING_VALID(ADMA_RX_RING3, 0);
1639 +       } else {
1640 +               SET_PDMA_RXRING_VALID(ADMA_RX_RING1, 0);
1641 +               SET_PDMA_RXRING_VALID(ADMA_RX_RING2, 0);
1642 +               SET_PDMA_RXRING_VALID(ADMA_RX_RING3, 1);
1643 +       }
1644 +
1645 +       /* 2.3 Set AGE timer */
1646 +       SET_PDMA_RXRING_AGE_TIME(ADMA_RX_RING1, HW_LRO_AGE_TIME);
1647 +       SET_PDMA_RXRING_AGE_TIME(ADMA_RX_RING2, HW_LRO_AGE_TIME);
1648 +       SET_PDMA_RXRING_AGE_TIME(ADMA_RX_RING3, HW_LRO_AGE_TIME);
1649 +
1650 +       /* 3.1 IPv4 checksum update enable */
1651 +       SET_PDMA_LRO_IPV4_CSUM_UPDATE_EN(1);
1652 +
1653 +       /* 3.2 switch priority comparision to byte count mode */
1654 +       SET_PDMA_LRO_ALT_SCORE_MODE(PDMA_LRO_ALT_BYTE_CNT_MODE);
1655 +
1656 +       /* 3.3 bandwidth threshold setting */
1657 +       SET_PDMA_LRO_BW_THRESHOLD(0);
1658 +
1659 +       /* 3.4 auto-learn score delta setting */
1660 +       sysRegWrite(LRO_ALT_SCORE_DELTA, 0);
1661 +
1662 +       /* 3.5 Set ALT timer to 500us: (unit: 20us) */
1663 +       SET_PDMA_LRO_ALT_REFRESH_TIMER_UNIT(25);
1664 +       /* 3.6 Set ALT refresh timer to 1 sec. (unit: 500us) */
1665 +       SET_PDMA_LRO_ALT_REFRESH_TIMER(2000);
1666 +
1667 +       /* 3.7 Set max AGG timer */
1668 +       SET_PDMA_LRO_MAX_AGG_TIME(HW_LRO_AGG_TIME);
1669 +
1670 +       /* 4. Polling relinguish */
1671 +       while (sysRegRead(ADMA_LRO_CTRL_DW0) & PDMA_LRO_RELINGUISH) {;
1672 +       }
1673 +
1674 +       /* 5. Enable LRO */
1675 +       regVal = sysRegRead(ADMA_LRO_CTRL_DW0);
1676 +       regVal |= PDMA_LRO_EN;
1677 +       sysRegWrite(ADMA_LRO_CTRL_DW0, regVal);
1678 +
1679 +       return 0;
1680 +}
1681 +
1682 +int pdma_lro_dly_int0_dvt(void)
1683 +{
1684 +       return pdma_lro_dly_int_dvt(0);
1685 +}
1686 +
1687 +int pdma_lro_dly_int1_dvt(void)
1688 +{
1689 +       return pdma_lro_dly_int_dvt(1);
1690 +}
1691 +
1692 +int pdma_lro_dly_int2_dvt(void)
1693 +{
1694 +       return pdma_lro_dly_int_dvt(2);
1695 +}
1696 +
1697 +int pdma_lro_dly_int3_dvt(void)
1698 +{
1699 +       return pdma_lro_dly_int_dvt(3);
1700 +}
1701 +
1702 +#endif /* CONFIG_RAETH_HW_LRO */
1703 +
1704 +#if defined(CONFIG_RAETH_MULTIPLE_RX_RING)
1705 +int pdma_gdm_rxid_config(void)
1706 +{
1707 +       unsigned int regVal = 0;
1708 +
1709 +       printk("pdma_gdm_rxid_config()\n");
1710 +
1711 +       /* 1. Set RX ring1~3 to pse modes */
1712 +       SET_PDMA_RXRING_MODE(ADMA_RX_RING1, PDMA_RX_PSE_MODE);
1713 +       SET_PDMA_RXRING_MODE(ADMA_RX_RING2, PDMA_RX_PSE_MODE);
1714 +       SET_PDMA_RXRING_MODE(ADMA_RX_RING3, PDMA_RX_PSE_MODE);
1715 +
1716 +       /* 2. Enable non-lro multiple rx */
1717 +       SET_PDMA_NON_LRO_MULTI_EN(1);
1718 +
1719 +       return 0;
1720 +}
1721 +
1722 +int pdma_non_lro_portid_dvt(void)
1723 +{
1724 +       unsigned int regVal = 0;
1725 +
1726 +       printk("pdma_non_lro_portid_dvt()\n");
1727 +
1728 +       /* 1. Set GDM1 to ring3 */
1729 +       SET_GDM_PID1_RXID_SEL(3);
1730 +#if 0
1731 +       /* 2. Set GDM2 to ring1 */
1732 +       SET_GDM_PID2_RXID_SEL(1);
1733 +#endif
1734 +
1735 +       /* 3. Set priority rule: pid */
1736 +       SET_GDM_RXID_PRI_SEL(GDM_PRI_PID);
1737 +
1738 +       /* PDMA multi-rx enable */
1739 +       pdma_gdm_rxid_config();
1740 +
1741 +       return 0;
1742 +}
1743 +
1744 +int pdma_non_lro_stag_dvt(void)
1745 +{
1746 +       unsigned int regVal = 0;
1747 +
1748 +       printk("pdma_non_lro_stag_dvt()\n");
1749 +
1750 +       /* 1. Set STAG4 to ring0 */
1751 +       GDM_STAG_RXID_SEL(4, 0);
1752 +       /* 2. Set STAG3 to ring1 */
1753 +       GDM_STAG_RXID_SEL(3, 1);
1754 +       /* 3. Set STAG2 to ring2 */
1755 +       GDM_STAG_RXID_SEL(2, 2);
1756 +       /* 4. Set STAG1 to ring3 */
1757 +       GDM_STAG_RXID_SEL(1, 3);
1758 +
1759 +       /* 5. Set priority rule: stag/pid */
1760 +       SET_GDM_RXID_PRI_SEL(GDM_PRI_PID);
1761 +
1762 +       /* PDMA multi-rx enable */
1763 +       pdma_gdm_rxid_config();
1764 +
1765 +       return 0;
1766 +}
1767 +
1768 +int pdma_non_lro_vlan_dvt(void)
1769 +{
1770 +       unsigned int regVal = 0;
1771 +
1772 +       printk("pdma_non_lro_vlan_dvt()\n");
1773 +
1774 +       /* 1. Set vlan priority=3 to ring1 */
1775 +       SET_GDM_VLAN_PRI_RXID_SEL(3, 1);
1776 +       /* 2. Set vlan priority=2 to ring2 */
1777 +       SET_GDM_VLAN_PRI_RXID_SEL(2, 2);
1778 +       /* 3. Set vlan priority=1 to ring3 */
1779 +       SET_GDM_VLAN_PRI_RXID_SEL(1, 3);
1780 +       /* 4. Set vlan priority=0 to ring3 */
1781 +       SET_GDM_VLAN_PRI_RXID_SEL(0, 3);
1782 +
1783 +       /* 1. Set vlan priority=4 to ring1 */
1784 +       SET_GDM_VLAN_PRI_RXID_SEL(4, 1);
1785 +       /* 2. Set vlan priority=5 to ring2 */
1786 +       SET_GDM_VLAN_PRI_RXID_SEL(5, 2);
1787 +       /* 3. Set vlan priority=6 to ring3 */
1788 +       SET_GDM_VLAN_PRI_RXID_SEL(6, 3);
1789 +       /* 4. Set vlan priority=7 to ring3 */
1790 +       SET_GDM_VLAN_PRI_RXID_SEL(7, 3);
1791 +
1792 +       /* 4. Set priority rule: vlan > pid */
1793 +       SET_GDM_RXID_PRI_SEL(GDM_PRI_VLAN_PID);
1794 +
1795 +       /* PDMA multi-rx enable */
1796 +       pdma_gdm_rxid_config();
1797 +
1798 +       return 0;
1799 +}
1800 +
1801 +int pdma_non_lro_tcpack_dvt(void)
1802 +{
1803 +       unsigned int regVal = 0;
1804 +
1805 +       printk("pdma_non_lro_tcpack_dvt()\n");
1806 +
1807 +       /* 1. Enable TCP ACK with zero payload check */
1808 +       SET_GDM_TCP_ACK_WZPC(1);
1809 +       /* 2. Set TCP ACK to ring3 */
1810 +       SET_GDM_TCP_ACK_RXID_SEL(3);
1811 +
1812 +       /* 3. Set priority rule: ack > pid */
1813 +       SET_GDM_RXID_PRI_SEL(GDM_PRI_ACK_PID);
1814 +
1815 +       /* PDMA multi-rx enable */
1816 +       pdma_gdm_rxid_config();
1817 +
1818 +       return 0;
1819 +}
1820 +
1821 +int pdma_non_lro_pri1_dvt(void)
1822 +{
1823 +       unsigned int regVal = 0;
1824 +
1825 +       printk("pdma_non_lro_pri1_dvt()\n");
1826 +
1827 +       /* 1. Set GDM1 to ring0 */
1828 +       SET_GDM_PID1_RXID_SEL(0);
1829 +
1830 +       /* 2.1 Disable TCP ACK with zero payload check */
1831 +       SET_GDM_TCP_ACK_WZPC(0);
1832 +       /* 2.2 Set TCP ACK to ring1 */
1833 +       SET_GDM_TCP_ACK_RXID_SEL(1);
1834 +
1835 +       /* 3. Set vlan priority=1 to ring2 */
1836 +       SET_GDM_VLAN_PRI_RXID_SEL(1, 2);
1837 +
1838 +       /* 4. Set priority rule: vlan > ack > pid */
1839 +       SET_GDM_RXID_PRI_SEL(GDM_PRI_VLAN_ACK_PID);
1840 +
1841 +       /* PDMA multi-rx enable */
1842 +       pdma_gdm_rxid_config();
1843 +
1844 +       return 0;
1845 +}
1846 +
1847 +int pdma_non_lro_pri2_dvt(void)
1848 +{
1849 +       unsigned int regVal = 0;
1850 +
1851 +       printk("pdma_non_lro_pri2_dvt()\n");
1852 +
1853 +       /* 1. Set GDM1 to ring0 */
1854 +       SET_GDM_PID1_RXID_SEL(0);
1855 +
1856 +       /* 2.1 Disable TCP ACK with zero payload check */
1857 +       SET_GDM_TCP_ACK_WZPC(0);
1858 +       /* 2.2 Set TCP ACK to ring1 */
1859 +       SET_GDM_TCP_ACK_RXID_SEL(1);
1860 +
1861 +       /* 3. Set vlan priority=1 to ring2 */
1862 +       SET_GDM_VLAN_PRI_RXID_SEL(1, 2);
1863 +
1864 +       /* 4. Set priority rule: ack > vlan > pid */
1865 +       SET_GDM_RXID_PRI_SEL(GDM_PRI_ACK_VLAN_PID);
1866 +
1867 +       /* PDMA multi-rx enable */
1868 +       pdma_gdm_rxid_config();
1869 +
1870 +       return 0;
1871 +}
1872 +#endif /* CONFIG_RAETH_MULTIPLE_RX_RING */
1873 +const static PDMA_LRO_DVT_FUNC pdma_dvt_lro_func[] = {
1874 +#if defined(CONFIG_RAETH_HW_LRO)
1875 +       [0] = pdma_lro_disable_dvt,     /* PDMA_TEST_LRO_DISABLE */
1876 +       [1] = pdma_lro_force_aggre_dvt, /* PDMA_TEST_LRO_FORCE_PORT */
1877 +       [2] = pdma_lro_auto_aggre_dvt,  /* PDMA_TEST_LRO_AUTO_LEARN */
1878 +       [3] = pdma_lro_auto_ipv6_dvt,   /* PDMA_TEST_LRO_AUTO_IPV6 */
1879 +       [4] = pdma_lro_auto_myIP_dvt,   /* PDMA_TEST_LRO_AUTO_MYIP */
1880 +       [5] = pdma_lro_force_aggre_dvt, /* PDMA_TEST_LRO_FORCE_AGGREGATE */
1881 +#endif /* CONFIG_RAETH_HW_LRO */
1882 +#if defined(CONFIG_RAETH_MULTIPLE_RX_RING)
1883 +       [6] = pdma_non_lro_portid_dvt,  /* PDMA_TEST_NON_LRO_PORT_ID */
1884 +       [7] = pdma_non_lro_stag_dvt,    /* PDMA_TEST_NON_LRO_STAG */
1885 +       [8] = pdma_non_lro_vlan_dvt,    /* PDMA_TEST_NON_LRO_VLAN */
1886 +       [9] = pdma_non_lro_tcpack_dvt,  /* PDMA_TEST_NON_LRO_TCP_ACK */
1887 +       [10] = pdma_non_lro_pri1_dvt,   /* PDMA_TEST_NON_LRO_PRI1 */
1888 +       [11] = pdma_non_lro_pri2_dvt,   /* PDMA_TEST_NON_LRO_PRI2 */
1889 +#endif /* CONFIG_RAETH_MULTIPLE_RX_RING */
1890 +#if defined(CONFIG_RAETH_HW_LRO)
1891 +       [12] = pdma_lro_dly_int0_dvt,   /* PDMA_TEST_LRO_DLY_INT0 */
1892 +       [13] = pdma_lro_dly_int1_dvt,   /* PDMA_TEST_LRO_DLY_INT1 */
1893 +       [14] = pdma_lro_dly_int2_dvt,   /* PDMA_TEST_LRO_DLY_INT2 */
1894 +       [15] = pdma_lro_dly_int3_dvt,   /* PDMA_TEST_LRO_DLY_INT3 */
1895 +#endif /* CONFIG_RAETH_HW_LRO */
1896 +};
1897 +
1898 +/* PDMA LRO test functions end */
1899 +
1900 +#if defined(CONFIG_RAETH_HW_LRO) || defined(CONFIG_RAETH_MULTIPLE_RX_RING)
1901 +void raeth_pdma_lro_dvt(int rx_ring_no, END_DEVICE *ei_local,
1902 +                       int rx_dma_owner_idx0)
1903 +{
1904 +       if (pdma_dvt_get_show_config() & PDMA_SHOW_RX_DESC) {
1905 +               if (rx_ring_no == 1) {
1906 +                       printk("------- rt2880_eth_recv (ring1) --------\n");
1907 +                       printk("rx_info1=0x%x\n",
1908 +                              *(unsigned int *)
1909 +                              &ei_local->rx_ring1[rx_dma_owner_idx0].
1910 +                              rxd_info1);
1911 +                       printk("rx_info2=0x%x\n",
1912 +                              *(unsigned int *)
1913 +                              &ei_local->rx_ring1[rx_dma_owner_idx0].
1914 +                              rxd_info2);
1915 +                       printk("rx_info3=0x%x\n",
1916 +                              *(unsigned int *)
1917 +                              &ei_local->rx_ring1[rx_dma_owner_idx0].
1918 +                              rxd_info3);
1919 +                       printk("rx_info4=0x%x\n",
1920 +                              *(unsigned int *)
1921 +                              &ei_local->rx_ring1[rx_dma_owner_idx0].
1922 +                              rxd_info4);
1923 +                       printk("-------------------------------\n");
1924 +               } else if (rx_ring_no == 2) {
1925 +                       printk("------- rt2880_eth_recv (ring2) --------\n");
1926 +                       printk("rx_info1=0x%x\n",
1927 +                              *(unsigned int *)
1928 +                              &ei_local->rx_ring2[rx_dma_owner_idx0].
1929 +                              rxd_info1);
1930 +                       printk("rx_info2=0x%x\n",
1931 +                              *(unsigned int *)
1932 +                              &ei_local->rx_ring2[rx_dma_owner_idx0].
1933 +                              rxd_info2);
1934 +                       printk("rx_info3=0x%x\n",
1935 +                              *(unsigned int *)
1936 +                              &ei_local->rx_ring2[rx_dma_owner_idx0].
1937 +                              rxd_info3);
1938 +                       printk("rx_info4=0x%x\n",
1939 +                              *(unsigned int *)
1940 +                              &ei_local->rx_ring2[rx_dma_owner_idx0].
1941 +                              rxd_info4);
1942 +                       printk("-------------------------------\n");
1943 +               } else if (rx_ring_no == 3) {
1944 +                       printk("------- rt2880_eth_recv (ring3) --------\n");
1945 +                       printk("rx_info1=0x%x\n",
1946 +                              *(unsigned int *)
1947 +                              &ei_local->rx_ring3[rx_dma_owner_idx0].
1948 +                              rxd_info1);
1949 +                       printk("rx_info2=0x%x\n",
1950 +                              *(unsigned int *)
1951 +                              &ei_local->rx_ring3[rx_dma_owner_idx0].
1952 +                              rxd_info2);
1953 +                       printk("rx_info3=0x%x\n",
1954 +                              *(unsigned int *)
1955 +                              &ei_local->rx_ring3[rx_dma_owner_idx0].
1956 +                              rxd_info3);
1957 +                       printk("rx_info4=0x%x\n",
1958 +                              *(unsigned int *)
1959 +                              &ei_local->rx_ring3[rx_dma_owner_idx0].
1960 +                              rxd_info4);
1961 +                       printk("-------------------------------\n");
1962 +               }
1963 +#if 0
1964 +               else {
1965 +                       printk("------- rt2880_eth_recv (ring0) --------\n");
1966 +                       printk("rx_info1=0x%x\n",
1967 +                              *(unsigned int *)
1968 +                              &ei_local->rx_ring0[rx_dma_owner_idx0].
1969 +                              rxd_info1);
1970 +                       printk("rx_info2=0x%x\n",
1971 +                              *(unsigned int *)
1972 +                              &ei_local->rx_ring0[rx_dma_owner_idx0].
1973 +                              rxd_info2);
1974 +                       printk("rx_info3=0x%x\n",
1975 +                              *(unsigned int *)
1976 +                              &ei_local->rx_ring0[rx_dma_owner_idx0].
1977 +                              rxd_info3);
1978 +                       printk("rx_info4=0x%x\n",
1979 +                              *(unsigned int *)
1980 +                              &ei_local->rx_ring0[rx_dma_owner_idx0].
1981 +                              rxd_info4);
1982 +                       printk("-------------------------------\n");
1983 +               }
1984 +#endif
1985 +       }
1986 +       if ((pdma_dvt_get_show_config() & PDMA_SHOW_DETAIL_RX_DESC) ||
1987 +           (pdma_dvt_get_lro_test_config()==PDMA_TEST_LRO_FORCE_PORT)) {
1988 +               if (rx_ring_no == 1) {
1989 +                       printk("------- rt2880_eth_recv (ring1) --------\n");
1990 +                       printk("rx_info1.PDP0=0x%x\n",
1991 +                              ei_local->rx_ring1[rx_dma_owner_idx0].
1992 +                              rxd_info1.PDP0);
1993 +                       printk("rx_info2.DDONE_bit=0x%x\n",
1994 +                              ei_local->rx_ring1[rx_dma_owner_idx0].
1995 +                              rxd_info2.DDONE_bit);
1996 +                       printk("rx_info2.LS0=0x%x\n",
1997 +                              ei_local->rx_ring1[rx_dma_owner_idx0].
1998 +                              rxd_info2.LS0);
1999 +                       printk("rx_info2.PLEN0=0x%x\n",
2000 +                              ei_local->rx_ring1[rx_dma_owner_idx0].
2001 +                              rxd_info2.PLEN0);
2002 +                       printk("rx_info2.TAG=0x%x\n",
2003 +                              ei_local->rx_ring1[rx_dma_owner_idx0].
2004 +                              rxd_info2.TAG);
2005 +#if defined(CONFIG_ARCH_MT7623)
2006 +                       printk("rx_info2.LRO_AGG_CNT=0x%x\n",
2007 +                              ei_local->rx_ring1[rx_dma_owner_idx0].
2008 +                              rxd_info2.LRO_AGG_CNT);
2009 +                       printk("rx_info2.REV=0x%x\n",
2010 +                              ei_local->rx_ring1[rx_dma_owner_idx0].
2011 +                              rxd_info2.REV);
2012 +#else
2013 +                       printk("rx_info2.LS1=0x%x\n",
2014 +                              ei_local->rx_ring1[rx_dma_owner_idx0].
2015 +                              rxd_info2.LS1);
2016 +#endif /* CONFIG_RAETH_HW_LRO */
2017 +                       printk("rx_info2.PLEN1=0x%x\n",
2018 +                              ei_local->rx_ring1[rx_dma_owner_idx0].
2019 +                              rxd_info2.PLEN1);
2020 +                       printk("rx_info3.TPID=0x%x\n",
2021 +                              ei_local->rx_ring1[rx_dma_owner_idx0].
2022 +                              rxd_info3.TPID);
2023 +                       printk("rx_info3.VID=0x%x\n",
2024 +                              ei_local->rx_ring1[rx_dma_owner_idx0].
2025 +                              rxd_info3.VID);
2026 +                       printk("rx_info4.IP6=0x%x\n",
2027 +                              ei_local->rx_ring1[rx_dma_owner_idx0].
2028 +                              rxd_info4.IP6);
2029 +                       printk("rx_info4.IP4=0x%x\n",
2030 +                              ei_local->rx_ring1[rx_dma_owner_idx0].
2031 +                              rxd_info4.IP4);
2032 +                       printk("rx_info4.IP4F=0x%x\n",
2033 +                              ei_local->rx_ring1[rx_dma_owner_idx0].
2034 +                              rxd_info4.IP4F);
2035 +                       printk("rx_info4.TACK=0x%x\n",
2036 +                              ei_local->rx_ring1[rx_dma_owner_idx0].
2037 +                              rxd_info4.TACK);
2038 +                       printk("rx_info4.L4VLD=0x%x\n",
2039 +                              ei_local->rx_ring1[rx_dma_owner_idx0].
2040 +                              rxd_info4.L4VLD);
2041 +                       printk("rx_info4.L4F=0x%x\n",
2042 +                              ei_local->rx_ring1[rx_dma_owner_idx0].
2043 +                              rxd_info4.L4F);
2044 +                       printk("rx_info4.SPORT=0x%x\n",
2045 +                              ei_local->rx_ring1[rx_dma_owner_idx0].
2046 +                              rxd_info4.SP);
2047 +                       printk("rx_info4.CRSN=0x%x\n",
2048 +                              ei_local->rx_ring1[rx_dma_owner_idx0].
2049 +                              rxd_info4.CRSN);
2050 +                       printk("rx_info4.FOE_Entry=0x%x\n",
2051 +                              ei_local->rx_ring1[rx_dma_owner_idx0].
2052 +                              rxd_info4.FOE_Entry);
2053 +                       printk("-------------------------------\n");
2054 +               } else if (rx_ring_no == 2) {
2055 +                       printk("------- rt2880_eth_recv (ring2) --------\n");
2056 +                       printk("rx_info1.PDP0=0x%x\n",
2057 +                              ei_local->rx_ring2[rx_dma_owner_idx0].
2058 +                              rxd_info1.PDP0);
2059 +                       printk("rx_info2.DDONE_bit=0x%x\n",
2060 +                              ei_local->rx_ring2[rx_dma_owner_idx0].
2061 +                              rxd_info2.DDONE_bit);
2062 +                       printk("rx_info2.LS0=0x%x\n",
2063 +                              ei_local->rx_ring2[rx_dma_owner_idx0].
2064 +                              rxd_info2.LS0);
2065 +                       printk("rx_info2.PLEN0=0x%x\n",
2066 +                              ei_local->rx_ring2[rx_dma_owner_idx0].
2067 +                              rxd_info2.PLEN0);
2068 +                       printk("rx_info2.TAG=0x%x\n",
2069 +                              ei_local->rx_ring2[rx_dma_owner_idx0].
2070 +                              rxd_info2.TAG);
2071 +#if defined(CONFIG_ARCH_MT7623)
2072 +                       printk("rx_info2.LRO_AGG_CNT=0x%x\n",
2073 +                              ei_local->rx_ring2[rx_dma_owner_idx0].
2074 +                              rxd_info2.LRO_AGG_CNT);
2075 +                       printk("rx_info2.REV=0x%x\n",
2076 +                              ei_local->rx_ring2[rx_dma_owner_idx0].
2077 +                              rxd_info2.REV);
2078 +#else
2079 +                       printk("rx_info2.LS1=0x%x\n",
2080 +                              ei_local->rx_ring2[rx_dma_owner_idx0].
2081 +                              rxd_info2.LS1);
2082 +#endif /* CONFIG_RAETH_HW_LRO */
2083 +                       printk("rx_info2.PLEN1=0x%x\n",
2084 +                              ei_local->rx_ring2[rx_dma_owner_idx0].
2085 +                              rxd_info2.PLEN1);
2086 +                       printk("rx_info3.TPID=0x%x\n",
2087 +                              ei_local->rx_ring2[rx_dma_owner_idx0].
2088 +                              rxd_info3.TPID);
2089 +                       printk("rx_info3.VID=0x%x\n",
2090 +                              ei_local->rx_ring2[rx_dma_owner_idx0].
2091 +                              rxd_info3.VID);
2092 +                       printk("rx_info4.IP6=0x%x\n",
2093 +                              ei_local->rx_ring2[rx_dma_owner_idx0].
2094 +                              rxd_info4.IP6);
2095 +                       printk("rx_info4.IP4=0x%x\n",
2096 +                              ei_local->rx_ring2[rx_dma_owner_idx0].
2097 +                              rxd_info4.IP4);
2098 +                       printk("rx_info4.IP4F=0x%x\n",
2099 +                              ei_local->rx_ring2[rx_dma_owner_idx0].
2100 +                              rxd_info4.IP4F);
2101 +                       printk("rx_info4.TACK=0x%x\n",
2102 +                              ei_local->rx_ring2[rx_dma_owner_idx0].
2103 +                              rxd_info4.TACK);
2104 +                       printk("rx_info4.L4VLD=0x%x\n",
2105 +                              ei_local->rx_ring2[rx_dma_owner_idx0].
2106 +                              rxd_info4.L4VLD);
2107 +                       printk("rx_info4.L4F=0x%x\n",
2108 +                              ei_local->rx_ring2[rx_dma_owner_idx0].
2109 +                              rxd_info4.L4F);
2110 +                       printk("rx_info4.SPORT=0x%x\n",
2111 +                              ei_local->rx_ring2[rx_dma_owner_idx0].
2112 +                              rxd_info4.SP);
2113 +                       printk("rx_info4.CRSN=0x%x\n",
2114 +                              ei_local->rx_ring2[rx_dma_owner_idx0].
2115 +                              rxd_info4.CRSN);
2116 +                       printk("rx_info4.FOE_Entry=0x%x\n",
2117 +                              ei_local->rx_ring2[rx_dma_owner_idx0].
2118 +                              rxd_info4.FOE_Entry);
2119 +                       printk("-------------------------------\n");
2120 +               } else if (rx_ring_no == 3) {
2121 +                       printk("------- rt2880_eth_recv (ring3) --------\n");
2122 +                       printk("rx_info1.PDP0=0x%x\n",
2123 +                              ei_local->rx_ring3[rx_dma_owner_idx0].
2124 +                              rxd_info1.PDP0);
2125 +                       printk("rx_info2.DDONE_bit=0x%x\n",
2126 +                              ei_local->rx_ring3[rx_dma_owner_idx0].
2127 +                              rxd_info2.DDONE_bit);
2128 +                       printk("rx_info2.LS0=0x%x\n",
2129 +                              ei_local->rx_ring3[rx_dma_owner_idx0].
2130 +                              rxd_info2.LS0);
2131 +                       printk("rx_info2.PLEN0=0x%x\n",
2132 +                              ei_local->rx_ring3[rx_dma_owner_idx0].
2133 +                              rxd_info2.PLEN0);
2134 +                       printk("rx_info2.TAG=0x%x\n",
2135 +                              ei_local->rx_ring3[rx_dma_owner_idx0].
2136 +                              rxd_info2.TAG);
2137 +#if defined(CONFIG_ARCH_MT7623)
2138 +                       printk("rx_info2.LRO_AGG_CNT=0x%x\n",
2139 +                              ei_local->rx_ring3[rx_dma_owner_idx0].
2140 +                              rxd_info2.LRO_AGG_CNT);
2141 +                       printk("rx_info2.REV=0x%x\n",
2142 +                              ei_local->rx_ring3[rx_dma_owner_idx0].
2143 +                              rxd_info2.REV);
2144 +#else
2145 +                       printk("rx_info2.LS1=0x%x\n",
2146 +                              ei_local->rx_ring3[rx_dma_owner_idx0].
2147 +                              rxd_info2.LS1);
2148 +#endif /* CONFIG_RAETH_HW_LRO */
2149 +                       printk("rx_info2.PLEN1=0x%x\n",
2150 +                              ei_local->rx_ring3[rx_dma_owner_idx0].
2151 +                              rxd_info2.PLEN1);
2152 +                       printk("rx_info3.TPID=0x%x\n",
2153 +                              ei_local->rx_ring3[rx_dma_owner_idx0].
2154 +                              rxd_info3.TPID);
2155 +                       printk("rx_info3.VID=0x%x\n",
2156 +                              ei_local->rx_ring3[rx_dma_owner_idx0].
2157 +                              rxd_info3.VID);
2158 +                       printk("rx_info4.IP6=0x%x\n",
2159 +                              ei_local->rx_ring3[rx_dma_owner_idx0].
2160 +                              rxd_info4.IP6);
2161 +                       printk("rx_info4.IP4=0x%x\n",
2162 +                              ei_local->rx_ring3[rx_dma_owner_idx0].
2163 +                              rxd_info4.IP4);
2164 +                       printk("rx_info4.IP4F=0x%x\n",
2165 +                              ei_local->rx_ring3[rx_dma_owner_idx0].
2166 +                              rxd_info4.IP4F);
2167 +                       printk("rx_info4.TACK=0x%x\n",
2168 +                              ei_local->rx_ring3[rx_dma_owner_idx0].
2169 +                              rxd_info4.TACK);
2170 +                       printk("rx_info4.L4VLD=0x%x\n",
2171 +                              ei_local->rx_ring3[rx_dma_owner_idx0].
2172 +                              rxd_info4.L4VLD);
2173 +                       printk("rx_info4.L4F=0x%x\n",
2174 +                              ei_local->rx_ring3[rx_dma_owner_idx0].
2175 +                              rxd_info4.L4F);
2176 +                       printk("rx_info4.SPORT=0x%x\n",
2177 +                              ei_local->rx_ring3[rx_dma_owner_idx0].
2178 +                              rxd_info4.SP);
2179 +                       printk("rx_info4.CRSN=0x%x\n",
2180 +                              ei_local->rx_ring3[rx_dma_owner_idx0].
2181 +                              rxd_info4.CRSN);
2182 +                       printk("rx_info4.FOE_Entry=0x%x\n",
2183 +                              ei_local->rx_ring3[rx_dma_owner_idx0].
2184 +                              rxd_info4.FOE_Entry);
2185 +                       printk("-------------------------------\n");
2186 +               }
2187 +#if 0
2188 +               else {
2189 +                       printk("------- rt2880_eth_recv (ring0) --------\n");
2190 +                       printk("rx_info1.PDP0=0x%x\n",
2191 +                              ei_local->rx_ring0[rx_dma_owner_idx0].
2192 +                              rxd_info1.PDP0);
2193 +                       printk("rx_info2.DDONE_bit=0x%x\n",
2194 +                              ei_local->rx_ring0[rx_dma_owner_idx0].
2195 +                              rxd_info2.DDONE_bit);
2196 +                       printk("rx_info2.LS0=0x%x\n",
2197 +                              ei_local->rx_ring0[rx_dma_owner_idx0].
2198 +                              rxd_info2.LS0);
2199 +                       printk("rx_info2.PLEN0=0x%x\n",
2200 +                              ei_local->rx_ring0[rx_dma_owner_idx0].
2201 +                              rxd_info2.PLEN0);
2202 +                       printk("rx_info2.TAG=0x%x\n",
2203 +                              ei_local->rx_ring0[rx_dma_owner_idx0].
2204 +                              rxd_info2.TAG);
2205 +                       printk("rx_info2.LS1=0x%x\n",
2206 +                              ei_local->rx_ring0[rx_dma_owner_idx0].
2207 +                              rxd_info2.LS1);
2208 +                       printk("rx_info2.PLEN1=0x%x\n",
2209 +                              ei_local->rx_ring0[rx_dma_owner_idx0].
2210 +                              rxd_info2.PLEN1);
2211 +                       printk("rx_info3.TPID=0x%x\n",
2212 +                              ei_local->rx_ring0[rx_dma_owner_idx0].
2213 +                              rxd_info3.TPID);
2214 +                       printk("rx_info3.VID=0x%x\n",
2215 +                              ei_local->rx_ring0[rx_dma_owner_idx0].
2216 +                              rxd_info3.VID);
2217 +                       printk("rx_info4.IP6=0x%x\n",
2218 +                              ei_local->rx_ring0[rx_dma_owner_idx0].
2219 +                              rxd_info4.IP6);
2220 +                       printk("rx_info4.IP4=0x%x\n",
2221 +                              ei_local->rx_ring0[rx_dma_owner_idx0].
2222 +                              rxd_info4.IP4);
2223 +                       printk("rx_info4.IP4F=0x%x\n",
2224 +                              ei_local->rx_ring0[rx_dma_owner_idx0].
2225 +                              rxd_info4.IP4F);
2226 +                       printk("rx_info4.TACK=0x%x\n",
2227 +                              ei_local->rx_ring0[rx_dma_owner_idx0].
2228 +                              rxd_info4.TACK);
2229 +                       printk("rx_info4.L4VLD=0x%x\n",
2230 +                              ei_local->rx_ring0[rx_dma_owner_idx0].
2231 +                              rxd_info4.L4VLD);
2232 +                       printk("rx_info4.L4F=0x%x\n",
2233 +                              ei_local->rx_ring0[rx_dma_owner_idx0].
2234 +                              rxd_info4.L4F);
2235 +                       printk("rx_info4.SPORT=0x%x\n",
2236 +                              ei_local->rx_ring0[rx_dma_owner_idx0].
2237 +                              rxd_info4.SP);
2238 +                       printk("rx_info4.CRSN=0x%x\n",
2239 +                              ei_local->rx_ring0[rx_dma_owner_idx0].
2240 +                              rxd_info4.CRSN);
2241 +                       printk("rx_info4.FOE_Entry=0x%x\n",
2242 +                              ei_local->rx_ring0[rx_dma_owner_idx0].
2243 +                              rxd_info4.FOE_Entry);
2244 +                       printk("-------------------------------\n");
2245 +               }
2246 +#endif
2247 +       }
2248 +       if (pdma_dvt_get_lro_test_config() == PDMA_TEST_LRO_FORCE_AGGREGATE) {
2249 +               if (rx_ring_no == 1) {
2250 +                       printk("PASS!!! => RING1: rxd_info1.PDP0=0x%x\n",
2251 +                              ei_local->rx_ring1[rx_dma_owner_idx0].
2252 +                              rxd_info1.PDP0);
2253 +                       skb_dump(ei_local->netrx1_skbuf[rx_dma_owner_idx0]);
2254 +                       pdma_dvt_reset_config();
2255 +               }
2256 +       }
2257 +}
2258 +#endif
2259 +
2260 +int pdma_dvt_show_ctrl(int par1, int par2)
2261 +{
2262 +       if (par2 == 0)
2263 +               g_pdma_dvt_show_config = 0;
2264 +       else
2265 +               g_pdma_dvt_show_config |= (1 << par2);
2266 +
2267 +       return 0;
2268 +}
2269 +
2270 +int pdma_dvt_test_rx_ctrl(int par1, int par2)
2271 +{
2272 +       if (par2 == 0)
2273 +               g_pdma_dvt_rx_test_config = 0;
2274 +       else
2275 +               g_pdma_dvt_rx_test_config |= (1 << par2);
2276 +
2277 +       return 0;
2278 +}
2279 +
2280 +int pdma_dvt_test_tx_ctrl(int par1, int par2)
2281 +{
2282 +       if (par2 == 0)
2283 +               g_pdma_dvt_tx_test_config = 0;
2284 +       else
2285 +               g_pdma_dvt_tx_test_config |= (1 << par2);
2286 +
2287 +       return 0;
2288 +}
2289 +
2290 +int pdma_dvt_test_debug_ctrl(int par1, int par2)
2291 +{
2292 +       if (par2 == 0)
2293 +               g_pdma_dvt_debug_test_config = 0;
2294 +       else
2295 +               g_pdma_dvt_debug_test_config |= (1 << par2);
2296 +
2297 +       return 0;
2298 +}
2299 +
2300 +int pdma_dvt_test_lro_ctrl(int par1, int par2)
2301 +{
2302 +       g_pdma_dvt_lro_test_config = par2;
2303 +
2304 +#if defined(CONFIG_RAETH_HW_LRO) || defined(CONFIG_RAETH_MULTIPLE_RX_RING)
2305 +       if (pdma_dvt_lro_func[par2])
2306 +               (*pdma_dvt_lro_func[par2]) ();
2307 +#endif /* #if defined (CONFIG_RAETH_HW_LRO) */
2308 +
2309 +       return 0;
2310 +}
2311 +
2312 +unsigned int pdma_dvt_get_show_config()
2313 +{
2314 +       return g_pdma_dvt_show_config;
2315 +}
2316 +
2317 +unsigned int pdma_dvt_get_rx_test_config()
2318 +{
2319 +       return g_pdma_dvt_rx_test_config;
2320 +}
2321 +
2322 +unsigned int pdma_dvt_get_tx_test_config()
2323 +{
2324 +       return g_pdma_dvt_tx_test_config;
2325 +}
2326 +
2327 +unsigned int pdma_dvt_get_debug_test_config()
2328 +{
2329 +       return g_pdma_dvt_debug_test_config;
2330 +}
2331 +
2332 +unsigned int pdma_dvt_get_lro_test_config()
2333 +{
2334 +       return g_pdma_dvt_lro_test_config;
2335 +}
2336 +
2337 +void pdma_dvt_reset_config()
2338 +{
2339 +       g_pdma_dvt_show_config = 0;
2340 +       g_pdma_dvt_rx_test_config = 0;
2341 +       g_pdma_dvt_tx_test_config = 0;
2342 +       g_pdma_dvt_lro_test_config = 0;
2343 +}
2344 +
2345 +void raeth_pdma_rx_desc_dvt(END_DEVICE *ei_local, int rx_dma_owner_idx0)
2346 +{
2347 +#if 0
2348 +       unsigned int udf = 0;
2349 +#endif
2350 +
2351 +       if (pdma_dvt_get_show_config() & PDMA_SHOW_RX_DESC) {
2352 +               printk("------- rt2880_eth_recv --------\n");
2353 +               printk("rx_info1=0x%x\n",
2354 +                      *(unsigned int *)&ei_local->
2355 +                      rx_ring0[rx_dma_owner_idx0].rxd_info1);
2356 +               printk("rx_info2=0x%x\n",
2357 +                      *(unsigned int *)&ei_local->
2358 +                      rx_ring0[rx_dma_owner_idx0].rxd_info2);
2359 +               printk("rx_info3=0x%x\n",
2360 +                      *(unsigned int *)&ei_local->
2361 +                      rx_ring0[rx_dma_owner_idx0].rxd_info3);
2362 +               printk("rx_info4=0x%x\n",
2363 +                      *(unsigned int *)&ei_local->
2364 +                      rx_ring0[rx_dma_owner_idx0].rxd_info4);
2365 +               printk("-------------------------------\n");
2366 +       }
2367 +       if ((pdma_dvt_get_show_config() & PDMA_SHOW_DETAIL_RX_DESC) ||
2368 +           pdma_dvt_get_rx_test_config()) {
2369 +#if 0
2370 +               udf = ei_local->rx_ring0[rx_dma_owner_idx0].rxd_info4.IP6 << 5 |
2371 +                   ei_local->rx_ring0[rx_dma_owner_idx0].rxd_info4.IP4 << 4 |
2372 +                   ei_local->rx_ring0[rx_dma_owner_idx0].rxd_info4.IP4F << 3 |
2373 +                   ei_local->rx_ring0[rx_dma_owner_idx0].rxd_info4.TACK << 2 |
2374 +                   ei_local->rx_ring0[rx_dma_owner_idx0].rxd_info4.L4VLD << 1 |
2375 +                   ei_local->rx_ring0[rx_dma_owner_idx0].rxd_info4.L4F;
2376 +#endif
2377 +               printk("------- rt2880_eth_recv --------\n");
2378 +               printk("rx_info1.PDP0=0x%x\n",
2379 +                      ei_local->rx_ring0[rx_dma_owner_idx0].rxd_info1.PDP0);
2380 +               printk("rx_info2.DDONE_bit=0x%x\n",
2381 +                      ei_local->rx_ring0[rx_dma_owner_idx0].
2382 +                      rxd_info2.DDONE_bit);
2383 +               printk("rx_info2.LS0=0x%x\n",
2384 +                      ei_local->rx_ring0[rx_dma_owner_idx0].rxd_info2.LS0);
2385 +               printk("rx_info2.PLEN0=0x%x\n",
2386 +                      ei_local->rx_ring0[rx_dma_owner_idx0].rxd_info2.PLEN0);
2387 +               printk("rx_info2.TAG=0x%x\n",
2388 +                      ei_local->rx_ring0[rx_dma_owner_idx0].rxd_info2.TAG);
2389 +#if defined(CONFIG_ARCH_MT7623)
2390 +               printk("rx_info2.LRO_AGG_CNT=0x%x\n",
2391 +                      ei_local->rx_ring0[rx_dma_owner_idx0].
2392 +                      rxd_info2.LRO_AGG_CNT);
2393 +#else
2394 +               printk("rx_info2.LS1=0x%x\n",
2395 +                      ei_local->rx_ring0[rx_dma_owner_idx0].rxd_info2.LS1);
2396 +#endif /* CONFIG_RAETH_HW_LRO */
2397 +               printk("rx_info2.PLEN1=0x%x\n",
2398 +                      ei_local->rx_ring0[rx_dma_owner_idx0].rxd_info2.PLEN1);
2399 +               printk("rx_info3.TPID=0x%x\n",
2400 +                      ei_local->rx_ring0[rx_dma_owner_idx0].rxd_info3.TPID);
2401 +               printk("rx_info3.VID=0x%x\n",
2402 +                      ei_local->rx_ring0[rx_dma_owner_idx0].rxd_info3.VID);
2403 +#if 0
2404 +               printk("rx_info4.UDF=0x%x\n", udf);
2405 +#endif
2406 +               printk("rx_info4.IP6=0x%x\n",
2407 +                      ei_local->rx_ring0[rx_dma_owner_idx0].rxd_info4.IP6);
2408 +               printk("rx_info4.IP4=0x%x\n",
2409 +                      ei_local->rx_ring0[rx_dma_owner_idx0].rxd_info4.IP4);
2410 +               printk("rx_info4.IP4F=0x%x\n",
2411 +                      ei_local->rx_ring0[rx_dma_owner_idx0].rxd_info4.IP4F);
2412 +               printk("rx_info4.TACK=0x%x\n",
2413 +                      ei_local->rx_ring0[rx_dma_owner_idx0].rxd_info4.TACK);
2414 +               printk("rx_info4.L4VLD=0x%x\n",
2415 +                      ei_local->rx_ring0[rx_dma_owner_idx0].rxd_info4.L4VLD);
2416 +               printk("rx_info4.L4F=0x%x\n",
2417 +                      ei_local->rx_ring0[rx_dma_owner_idx0].rxd_info4.L4F);
2418 +               printk("rx_info4.SPORT=0x%x\n",
2419 +                      ei_local->rx_ring0[rx_dma_owner_idx0].rxd_info4.SP);
2420 +               printk("rx_info4.CRSN=0x%x\n",
2421 +                      ei_local->rx_ring0[rx_dma_owner_idx0].rxd_info4.CRSN);
2422 +               printk("rx_info4.FOE_Entry=0x%x\n",
2423 +                      ei_local->rx_ring0[rx_dma_owner_idx0].
2424 +                      rxd_info4.FOE_Entry);
2425 +               printk("-------------------------------\n");
2426 +       }
2427 +       if ((pdma_dvt_get_rx_test_config() & PDMA_TEST_RX_IPV6)) {
2428 +               if (ei_local->rx_ring0[rx_dma_owner_idx0].rxd_info4.IP6) {
2429 +                       printk("PASS!!! => rx_info4.IP6=0x%x\n",
2430 +                              ei_local->rx_ring0[rx_dma_owner_idx0].
2431 +                              rxd_info4.IP6);
2432 +                       pdma_dvt_reset_config();
2433 +               }
2434 +       } else if ((pdma_dvt_get_rx_test_config() & PDMA_TEST_RX_IPV4)) {
2435 +               if (ei_local->rx_ring0[rx_dma_owner_idx0].rxd_info4.IP4) {
2436 +                       printk("PASS!!! => rx_info4.IP4=0x%x\n",
2437 +                              ei_local->rx_ring0[rx_dma_owner_idx0].
2438 +                              rxd_info4.IP4);
2439 +                       pdma_dvt_reset_config();
2440 +               }
2441 +       } else if ((pdma_dvt_get_rx_test_config() & PDMA_TEST_RX_IPV4F)) {
2442 +               if (ei_local->rx_ring0[rx_dma_owner_idx0].rxd_info4.IP4F) {
2443 +                       printk("PASS!!! => rx_info4.IP4F=0x%x\n",
2444 +                              ei_local->rx_ring0[rx_dma_owner_idx0].
2445 +                              rxd_info4.IP4F);
2446 +                       pdma_dvt_reset_config();
2447 +               }
2448 +       } else if ((pdma_dvt_get_rx_test_config() & PDMA_TEST_RX_L4VLD)) {
2449 +               if (ei_local->rx_ring0[rx_dma_owner_idx0].rxd_info4.L4VLD) {
2450 +                       printk("PASS!!! => rx_info4.L4VLD=0x%x\n",
2451 +                              ei_local->rx_ring0[rx_dma_owner_idx0].
2452 +                              rxd_info4.L4VLD);
2453 +                       pdma_dvt_reset_config();
2454 +               }
2455 +       } else if ((pdma_dvt_get_rx_test_config() & PDMA_TEST_RX_L4F)) {
2456 +               if (ei_local->rx_ring0[rx_dma_owner_idx0].rxd_info4.L4F) {
2457 +                       printk("PASS!!! => rx_info4.L4F=0x%x\n",
2458 +                              ei_local->rx_ring0[rx_dma_owner_idx0].
2459 +                              rxd_info4.L4F);
2460 +                       pdma_dvt_reset_config();
2461 +               }
2462 +       } else if ((pdma_dvt_get_rx_test_config() & PDMA_TEST_RX_SPORT)) {
2463 +               if (ei_local->rx_ring0[rx_dma_owner_idx0].rxd_info4.SP == 1) {
2464 +                       g_pdma_dev_lanport++;
2465 +               } else if (ei_local->rx_ring0[rx_dma_owner_idx0].rxd_info4.SP ==
2466 +                          2) {
2467 +                       g_pdma_dev_wanport++;
2468 +               }
2469 +               if (g_pdma_dev_lanport && g_pdma_dev_wanport) {
2470 +                       printk
2471 +                           ("PASS!!! => g_pdma_dev_lanport=0x%x, g_pdma_dev_wanport=0x%x",
2472 +                            g_pdma_dev_lanport, g_pdma_dev_wanport);
2473 +
2474 +                       g_pdma_dev_lanport = 0;
2475 +                       g_pdma_dev_wanport = 0;
2476 +                       pdma_dvt_reset_config();
2477 +               }
2478 +       } else if ((pdma_dvt_get_rx_test_config() & PDMA_TEST_RX_VID_OFF)) {
2479 +               if (!ei_local->rx_ring0[rx_dma_owner_idx0].rxd_info3.VID) {
2480 +                       printk("PASS!!! => rxd_info3.VID=0x%x\n",
2481 +                              ei_local->rx_ring0[rx_dma_owner_idx0].
2482 +                              rxd_info3.VID);
2483 +                       pdma_dvt_reset_config();
2484 +               }
2485 +       } else if ((pdma_dvt_get_rx_test_config() & PDMA_TEST_RX_VID_ON)) {
2486 +               printk("RX data: (PDP0=%x)\n",
2487 +                      (unsigned int)ei_local->
2488 +                      netrx0_skbuf[rx_dma_owner_idx0]->data);
2489 +
2490 +               skb_dump(ei_local->netrx0_skbuf[rx_dma_owner_idx0]);
2491 +
2492 +               if (ei_local->rx_ring0[rx_dma_owner_idx0].rxd_info3.VID &&
2493 +                   ei_local->rx_ring0[rx_dma_owner_idx0].rxd_info2.TAG) {
2494 +                       printk("PASS!!! => rxd_info2.TAG=0x%x\n",
2495 +                              ei_local->rx_ring0[rx_dma_owner_idx0].
2496 +                              rxd_info2.TAG);
2497 +                       printk("PASS!!! => rxd_info3.VID=0x%x\n",
2498 +                              ei_local->rx_ring0[rx_dma_owner_idx0].
2499 +                              rxd_info3.VID);
2500 +                       pdma_dvt_reset_config();
2501 +               }
2502 +       }
2503 +}
2504 +
2505 +void raeth_pdma_tx_vlan_dvt(END_DEVICE *ei_local,
2506 +                           unsigned long tx_cpu_owner_idx0)
2507 +{
2508 +       if ((pdma_dvt_get_tx_test_config() & PDMA_TEST_TX_VLAN_ON)) {
2509 +               ei_local->tx_ring0[tx_cpu_owner_idx0].txd_info4.VLAN_TAG = 0x10000 | 0xE007;    /* VLAN_TAG = 0x1E007 */
2510 +       } else if ((pdma_dvt_get_tx_test_config() & PDMA_TEST_TX_VLAN_ZERO)) {
2511 +               ei_local->tx_ring0[tx_cpu_owner_idx0].txd_info4.VLAN_TAG = 0x10000 | 0x0000;    /* VLAN_TAG = 0x10000 */
2512 +       } else if ((pdma_dvt_get_tx_test_config() & PDMA_TEST_TX_VLAN_MAX)) {
2513 +               ei_local->tx_ring0[tx_cpu_owner_idx0].txd_info4.VLAN_TAG = 0x10000 | 0xFFFF;    /* VLAN_TAG = 0x1FFFF */
2514 +       }
2515 +}
2516 +
2517 +void raeth_pdma_tx_desc_dvt(END_DEVICE *ei_local,
2518 +                           unsigned long tx_cpu_owner_idx0)
2519 +{
2520 +       if (PDMA_TEST_RX_UDF == pdma_dvt_get_rx_test_config()) {
2521 +               ei_local->tx_ring0[tx_cpu_owner_idx0].txd_info4.FPORT = 4;      /* PPE */
2522 +               ei_local->tx_ring0[tx_cpu_owner_idx0].txd_info4.UDF = 0x2F;
2523 +       }
2524 +       if (pdma_dvt_get_show_config() & PDMA_SHOW_TX_DESC) {
2525 +               printk("------- rt2880_eth_send --------\n");
2526 +               printk("tx_info1=%x\n",
2527 +                      *(unsigned int *)&ei_local->
2528 +                      tx_ring0[tx_cpu_owner_idx0].txd_info1);
2529 +               printk("tx_info2=%x\n",
2530 +                      *(unsigned int *)&ei_local->
2531 +                      tx_ring0[tx_cpu_owner_idx0].txd_info2);
2532 +               printk("tx_info3=%x\n",
2533 +                      *(unsigned int *)&ei_local->
2534 +                      tx_ring0[tx_cpu_owner_idx0].txd_info3);
2535 +               printk("tx_info4=%x\n",
2536 +                      *(unsigned int *)&ei_local->
2537 +                      tx_ring0[tx_cpu_owner_idx0].txd_info4);
2538 +               printk("--------------------------------\n");
2539 +       }
2540 +       if ((pdma_dvt_get_show_config() & PDMA_SHOW_DETAIL_TX_DESC) ||
2541 +           pdma_dvt_get_tx_test_config()) {
2542 +               printk("------- rt2880_eth_send --------\n");
2543 +               printk("tx_info1.SDP0=%x\n",
2544 +                      ei_local->tx_ring0[tx_cpu_owner_idx0].txd_info1.SDP0);
2545 +               printk("tx_info2.DDONE_bit=%x\n",
2546 +                      ei_local->tx_ring0[tx_cpu_owner_idx0].
2547 +                      txd_info2.DDONE_bit);
2548 +               printk("tx_info2.LS0_bit=%x\n",
2549 +                      ei_local->tx_ring0[tx_cpu_owner_idx0].txd_info2.LS0_bit);
2550 +               printk("tx_info2.SDL0=%x\n",
2551 +                      ei_local->tx_ring0[tx_cpu_owner_idx0].txd_info2.SDL0);
2552 +               printk("tx_info2.BURST_bit=%x\n",
2553 +                      ei_local->tx_ring0[tx_cpu_owner_idx0].
2554 +                      txd_info2.BURST_bit);
2555 +               printk("tx_info2.LS1_bit=%x\n",
2556 +                      ei_local->tx_ring0[tx_cpu_owner_idx0].txd_info2.LS1_bit);
2557 +               printk("tx_info2.SDL1=%x\n",
2558 +                      ei_local->tx_ring0[tx_cpu_owner_idx0].txd_info2.SDL1);
2559 +               printk("tx_info3.SDP1=%x\n",
2560 +                      ei_local->tx_ring0[tx_cpu_owner_idx0].txd_info3.SDP1);
2561 +               printk("tx_info4.TUI_CO=%x\n",
2562 +                      ei_local->tx_ring0[tx_cpu_owner_idx0].txd_info4.TUI_CO);
2563 +               printk("tx_info4.TSO=%x\n",
2564 +                      ei_local->tx_ring0[tx_cpu_owner_idx0].txd_info4.TSO);
2565 +               printk("tx_info4.FPORT=%x\n",
2566 +                      ei_local->tx_ring0[tx_cpu_owner_idx0].txd_info4.FPORT);
2567 +               printk("tx_info4.UDF=%x\n",
2568 +                      ei_local->tx_ring0[tx_cpu_owner_idx0].txd_info4.UDF);
2569 +               printk("tx_info4.RESV=%x\n",
2570 +                      ei_local->tx_ring0[tx_cpu_owner_idx0].txd_info4.RESV);
2571 +               printk("tx_info4.VLAN_TAG=%x\n",
2572 +                      ei_local->tx_ring0[tx_cpu_owner_idx0].
2573 +                      txd_info4.VLAN_TAG);
2574 +               printk("--------------------------------\n");
2575 +       }
2576 +       if ((pdma_dvt_get_tx_test_config() & PDMA_TEST_TX_LAN_SPORT)) {
2577 +               if (ei_local->tx_ring0[tx_cpu_owner_idx0].txd_info4.FPORT == 1) {
2578 +                       printk("PASS!!! => txd_info4.FPORT=0x%x\n",
2579 +                              ei_local->tx_ring0[tx_cpu_owner_idx0].
2580 +                              txd_info4.FPORT);
2581 +                       pdma_dvt_reset_config();
2582 +               }
2583 +       } else if ((pdma_dvt_get_tx_test_config() & PDMA_TEST_TX_WAN_SPORT)) {
2584 +               if (ei_local->tx_ring0[tx_cpu_owner_idx0].txd_info4.FPORT == 2) {
2585 +                       printk("PASS!!! => txd_info4.FPORT=0x%x\n",
2586 +                              ei_local->tx_ring0[tx_cpu_owner_idx0].
2587 +                              txd_info4.FPORT);
2588 +                       pdma_dvt_reset_config();
2589 +               }
2590 +       } else if ((pdma_dvt_get_tx_test_config() & PDMA_TEST_TX_VLAN_ON)) {
2591 +               if (ei_local->tx_ring0[tx_cpu_owner_idx0].txd_info4.VLAN_TAG) {
2592 +                       printk("PASS!!! => txd_info4.VLAN_TAG=0x%x\n",
2593 +                              ei_local->tx_ring0[tx_cpu_owner_idx0].
2594 +                              txd_info4.VLAN_TAG);
2595 +                       /* pdma_dvt_reset_config(); */
2596 +               }
2597 +       } else if ((pdma_dvt_get_tx_test_config() & PDMA_TEST_TX_VLAN_OFF)) {
2598 +               if (!ei_local->tx_ring0[tx_cpu_owner_idx0].txd_info4.VLAN_TAG) {
2599 +                       printk("PASS!!! => txd_info4.VLAN_TAG=0x%x\n",
2600 +                              ei_local->tx_ring0[tx_cpu_owner_idx0].
2601 +                              txd_info4.VLAN_TAG);
2602 +                       pdma_dvt_reset_config();
2603 +               }
2604 +       } else if ((pdma_dvt_get_tx_test_config() & PDMA_TEST_TX_VLAN_ZERO)) {
2605 +               if (ei_local->tx_ring0[tx_cpu_owner_idx0].txd_info4.VLAN_TAG) {
2606 +                       printk("PASS!!! => txd_info4.VLAN_TAG=0x%x\n",
2607 +                              ei_local->tx_ring0[tx_cpu_owner_idx0].
2608 +                              txd_info4.VLAN_TAG);
2609 +                       /* pdma_dvt_reset_config(); */
2610 +               }
2611 +       } else if ((pdma_dvt_get_tx_test_config() & PDMA_TEST_TX_VLAN_MAX)) {
2612 +               if (ei_local->tx_ring0[tx_cpu_owner_idx0].txd_info4.VLAN_TAG) {
2613 +                       printk("PASS!!! => txd_info4.VLAN_TAG=0x%x\n",
2614 +                              ei_local->tx_ring0[tx_cpu_owner_idx0].
2615 +                              txd_info4.VLAN_TAG);
2616 +                       /* pdma_dvt_reset_config(); */
2617 +               }
2618 +       }
2619 +}
2620 +
2621 +void raeth_pdma_lro_dly_int_dvt(void)
2622 +{
2623 +       unsigned int reg_int_val;
2624 +
2625 +       reg_int_val = sysRegRead(RAETH_FE_INT_STATUS);
2626 +
2627 +       if (pdma_dvt_get_lro_test_config() == PDMA_TEST_LRO_DLY_INT0) {
2628 +               if ((reg_int_val & RX_DLY_INT)) {
2629 +                       printk("PASS!!! => reg_int_val=0x%x\n", reg_int_val);
2630 +                       pdma_dvt_reset_config();
2631 +               }
2632 +       } else if (pdma_dvt_get_lro_test_config() == PDMA_TEST_LRO_DLY_INT1) {
2633 +               if ((reg_int_val & RING1_RX_DLY_INT)) {
2634 +                       printk("PASS!!! => reg_int_val=0x%x\n", reg_int_val);
2635 +                       pdma_dvt_reset_config();
2636 +               }
2637 +       } else if (pdma_dvt_get_lro_test_config() == PDMA_TEST_LRO_DLY_INT2) {
2638 +               if ((reg_int_val & RING2_RX_DLY_INT)) {
2639 +                       printk("PASS!!! => reg_int_val=0x%x\n", reg_int_val);
2640 +                       pdma_dvt_reset_config();
2641 +               }
2642 +       } else if (pdma_dvt_get_lro_test_config() == PDMA_TEST_LRO_DLY_INT3) {
2643 +               if ((reg_int_val & RING3_RX_DLY_INT)) {
2644 +                       printk("PASS!!! => reg_int_val=0x%x\n", reg_int_val);
2645 +                       pdma_dvt_reset_config();
2646 +               }
2647 +       }
2648 +}
2649 +
2650 +void pdma_dvt_set_dma_mode(void)
2651 +{
2652 +#if defined(CONFIG_RAETH_PDMA_LEGACY_MODE)
2653 +       unsigned int regVal;
2654 +       regVal = sysRegRead(ADMA_LRO_CTRL_DW3);
2655 +       regVal &= ~(BIT(15));
2656 +       sysRegWrite(ADMA_LRO_CTRL_DW3, regVal);
2657 +#endif  /* CONFIG_RAETH_PDMA_DVT */
2658 +}
2659 +
2660 diff --git a/drivers/net/ethernet/raeth/dvt/raether_pdma_dvt.h b/drivers/net/ethernet/raeth/dvt/raether_pdma_dvt.h
2661 new file mode 100755
2662 index 0000000..600aab7
2663 --- /dev/null
2664 +++ b/drivers/net/ethernet/raeth/dvt/raether_pdma_dvt.h
2665 @@ -0,0 +1,75 @@
2666 +/* Show controls */
2667 +#define PDMA_SHOW_RX_DESC   (1 << 1)
2668 +#define PDMA_SHOW_TX_DESC   (1 << 2)
2669 +#define PDMA_SHOW_DETAIL_RX_DESC   (1 << 3)
2670 +#define PDMA_SHOW_DETAIL_TX_DESC   (1 << 4)
2671 +
2672 +/* Rx test controls */
2673 +#define PDMA_TEST_RX_UDF     (1 << 1)
2674 +#define PDMA_TEST_RX_IPV6    (1 << 2)
2675 +#define PDMA_TEST_RX_IPV4    (1 << 3)
2676 +#define PDMA_TEST_RX_IPV4F   (1 << 4)
2677 +#define PDMA_TEST_RX_L4VLD   (1 << 5)
2678 +#define PDMA_TEST_RX_L4F     (1 << 6)
2679 +#define PDMA_TEST_RX_SPORT   (1 << 7)
2680 +#define PDMA_TEST_RX_VID_ON  (1 << 8)
2681 +#define PDMA_TEST_RX_VID_OFF (1 << 9)
2682 +
2683 +/* Tx test controls */
2684 +#define PDMA_TEST_TX_LAN_SPORT   (1 << 1)
2685 +#define PDMA_TEST_TX_WAN_SPORT   (1 << 2)
2686 +#define PDMA_TEST_TX_VLAN_ON     (1 << 3)
2687 +#define PDMA_TEST_TX_VLAN_OFF    (1 << 4)
2688 +#define PDMA_TEST_TX_VLAN_ZERO   (1 << 5)
2689 +#define PDMA_TEST_TX_VLAN_MAX    (1 << 6)
2690 +#define PDMA_TEST_TX_PDMA_LPK    (1 << 31)
2691 +
2692 +/* Debug controls */
2693 +#define PDMA_TEST_TSO_DEBUG      (1 << 1)
2694 +
2695 +/* LRO test controls */
2696 +typedef int (*PDMA_LRO_DVT_FUNC) (void);
2697 +
2698 +#define PDMA_TEST_LRO_DISABLE           (0)
2699 +#define PDMA_TEST_LRO_FORCE_PORT        (1)
2700 +#define PDMA_TEST_LRO_AUTO_LEARN        (2)
2701 +#define PDMA_TEST_LRO_AUTO_IPV6         (3)
2702 +#define PDMA_TEST_LRO_AUTO_MYIP         (4)
2703 +#define PDMA_TEST_LRO_FORCE_AGGREGATE   (5)
2704 +#define PDMA_TEST_NON_LRO_PORT_ID       (6)
2705 +#define PDMA_TEST_NON_LRO_STAG          (7)
2706 +#define PDMA_TEST_NON_LRO_VLAN          (8)
2707 +#define PDMA_TEST_NON_LRO_TCP_ACK       (9)
2708 +#define PDMA_TEST_NON_LRO_PRI1          (10)
2709 +#define PDMA_TEST_NON_LRO_PRI2          (11)
2710 +#define PDMA_TEST_LRO_DLY_INT0          (12)
2711 +#define PDMA_TEST_LRO_DLY_INT1          (13)
2712 +#define PDMA_TEST_LRO_DLY_INT2          (14)
2713 +#define PDMA_TEST_LRO_DLY_INT3          (15)
2714 +
2715 +void skb_dump(struct sk_buff *sk);
2716 +
2717 +int pdma_dvt_show_ctrl(int par1, int par2);
2718 +int pdma_dvt_test_rx_ctrl(int par1, int par2);
2719 +int pdma_dvt_test_tx_ctrl(int par1, int par2);
2720 +int pdma_dvt_test_debug_ctrl(int par1, int par2);
2721 +int pdma_dvt_test_lro_ctrl(int par1, int par2);
2722 +
2723 +unsigned int pdma_dvt_get_show_config(void);
2724 +unsigned int pdma_dvt_get_rx_test_config(void);
2725 +unsigned int pdma_dvt_get_tx_test_config(void);
2726 +unsigned int pdma_dvt_get_debug_test_config(void);
2727 +unsigned int pdma_dvt_get_lro_test_config(void);
2728 +void pdma_dvt_reset_config(void);
2729 +
2730 +void raeth_pdma_rx_desc_dvt(END_DEVICE *ei_local, int rx_dma_owner_idx0);
2731 +void raeth_pdma_tx_vlan_dvt(END_DEVICE *ei_local,
2732 +                           unsigned long tx_cpu_owner_idx0);
2733 +void raeth_pdma_tx_desc_dvt(END_DEVICE *ei_local,
2734 +                           unsigned long tx_cpu_owner_idx0);
2735 +
2736 +void raeth_pdma_lro_dvt(int rx_ring_no, END_DEVICE *ei_local,
2737 +                       int rx_dma_owner_idx0);
2738 +void raeth_pdma_lro_dly_int_dvt(void);
2739 +void pdma_dvt_set_dma_mode(void);
2740 +
2741 diff --git a/drivers/net/ethernet/raeth/ethtool_readme.txt b/drivers/net/ethernet/raeth/ethtool_readme.txt
2742 new file mode 100644
2743 index 0000000..10e918b
2744 --- /dev/null
2745 +++ b/drivers/net/ethernet/raeth/ethtool_readme.txt
2746 @@ -0,0 +1,44 @@
2747 +
2748 +Ethtool readme for selecting different PHY address.
2749 +
2750 +Before doing any ethtool command you should make sure the current PHY
2751 +address is expected. The default PHY address is 1(port 1).
2752 +
2753 +You can change current PHY address to X(0~4) by doing follow command:
2754 +# echo X > /proc/rt2880/gmac
2755 +
2756 +Ethtool command also would show the current PHY address as following.
2757 +
2758 +# ethtool  eth2
2759 +Settings for eth2:
2760 +        Supported ports: [ TP MII ]
2761 +        Supported link modes:   10baseT/Half 10baseT/Full
2762 +                                100baseT/Half 100baseT/Full
2763 +        Supports auto-negotiation: Yes
2764 +        Advertised link modes:  10baseT/Half 10baseT/Full
2765 +                                100baseT/Half 100baseT/Full
2766 +        Advertised auto-negotiation: No
2767 +        Speed: 10Mb/s
2768 +        Duplex: Full
2769 +        Port: MII
2770 +        PHYAD: 1
2771 +        Transceiver: internal
2772 +        Auto-negotiation: off
2773 +        Current message level: 0x00000000 (0)
2774 +        Link detected: no
2775 +
2776 +
2777 +The "PHYAD" field shows the current PHY address.
2778 +
2779 +
2780 +
2781 +Usage example
2782 +1) show port1 info
2783 +# echo 1 > /proc/rt2880/gmac           # change phy address to 1
2784 +# ethtool eth2
2785 +
2786 +2) show port0 info
2787 +# echo 0 > /proc/rt2880/gmac           # change phy address to 0
2788 +# ethtool eth2
2789 +
2790 +
2791 diff --git a/drivers/net/ethernet/raeth/mcast.c b/drivers/net/ethernet/raeth/mcast.c
2792 new file mode 100644
2793 index 0000000..d796b03
2794 --- /dev/null
2795 +++ b/drivers/net/ethernet/raeth/mcast.c
2796 @@ -0,0 +1,187 @@
2797 +#include <linux/config.h>
2798 +#include <linux/version.h>
2799 +#include <linux/module.h>
2800 +#include <linux/skbuff.h>
2801 +#include <linux/kernel.h>
2802 +#include <linux/init.h>
2803 +#include <linux/types.h>
2804 +#include <linux/netdevice.h>
2805 +#include <linux/if_vlan.h>
2806 +
2807 +
2808 +#define MAX_MCAST_ENTRY            16
2809 +#define AGEING_TIME        5  //Unit: Sec
2810 +#define MAC_ARG(x) ((u8*)(x))[0],((u8*)(x))[1],((u8*)(x))[2], \
2811 +    ((u8*)(x))[3],((u8*)(x))[4],((u8*)(x))[5]
2812 +
2813 +//#define MCAST_DEBUG
2814 +#ifdef MCAST_DEBUG
2815 +#define MCAST_PRINT(fmt, args...) printk(KERN_INFO fmt, ## args)
2816 +#else
2817 +#define MCAST_PRINT(fmt, args...) { }
2818 +#endif
2819 +
2820 +typedef struct {
2821 +    uint8_t    src_mac[6];
2822 +    uint8_t    dst_mac[6];
2823 +    uint16_t    vlan_id;
2824 +    uint32_t   valid;
2825 +    uint32_t   use_count;
2826 +    unsigned long ageout;
2827 +} mcast_entry;
2828 +
2829 +mcast_entry mcast_tbl[MAX_MCAST_ENTRY];
2830 +atomic_t mcast_entry_num=ATOMIC_INIT(0);
2831 +DECLARE_MUTEX(mtbl_lock);
2832 +
2833 +uint32_t inline is_multicast_pkt(uint8_t *mac)
2834 +{
2835 +    if(mac[0]==0x01 && mac[1]==0x00 && mac[2]==0x5E) {
2836 +       return 1;
2837 +    }else{
2838 +       return 0;
2839 +    }
2840 +}
2841 +
2842 +int32_t inline mcast_entry_get(uint16_t vlan_id, uint8_t *src_mac, uint8_t *dst_mac)
2843 +{
2844 +    int i=0;
2845 +
2846 +    for(i=0;i<MAX_MCAST_ENTRY;i++) {
2847 +       if( (mcast_tbl[i].vlan_id == vlan_id) &&
2848 +           memcmp(mcast_tbl[i].src_mac,src_mac, 6)==0 &&
2849 +           memcmp(mcast_tbl[i].dst_mac, dst_mac, 6)==0 &&
2850 +               mcast_tbl[i].valid == 1) {
2851 +           return i;
2852 +       }
2853 +    }
2854 +    return -1;
2855 +}
2856 +
2857 +int inline __add_mcast_entry(uint16_t vlan_id, uint8_t *src_mac, uint8_t *dst_mac)
2858 +{
2859 +    int i=0;
2860 +
2861 +    // use empty or ageout entry
2862 +    for(i=0;i<MAX_MCAST_ENTRY;i++) {
2863 +       if( mcast_tbl[i].valid==0 ||
2864 +               time_after(jiffies, mcast_tbl[i].ageout)) {
2865 +
2866 +           if(mcast_tbl[i].valid==0) {
2867 +               atomic_inc(&mcast_entry_num);
2868 +           }
2869 +           mcast_tbl[i].vlan_id = vlan_id;
2870 +           memcpy(mcast_tbl[i].src_mac, src_mac, 6);
2871 +           memcpy(mcast_tbl[i].dst_mac, dst_mac, 6);
2872 +           mcast_tbl[i].valid=1;
2873 +           mcast_tbl[i].use_count=1;
2874 +           mcast_tbl[i].ageout=jiffies + AGEING_TIME * HZ;
2875 +
2876 +           return 1;
2877 +       }
2878 +    }
2879 +
2880 +    MCAST_PRINT("RAETH: Multicast Table is FULL!!\n");
2881 +    return 0;
2882 +}
2883 +
2884 +int inline mcast_entry_ins(uint16_t vlan_id, uint8_t *src_mac, uint8_t *dst_mac)
2885 +{
2886 +    int entry_num=0, ret=0;
2887 +
2888 +    down(&mtbl_lock);
2889 +    if((entry_num = mcast_entry_get(vlan_id, src_mac, dst_mac)) >=0) {
2890 +       mcast_tbl[entry_num].use_count++;
2891 +       mcast_tbl[entry_num].ageout=jiffies + AGEING_TIME * HZ;
2892 +       MCAST_PRINT("%s: Update %0X:%0X:%0X:%0X:%0X:%0X's use_count=%d\n" \
2893 +               ,__FUNCTION__, MAC_ARG(dst_mac), mcast_tbl[entry_num].use_count);
2894 +       ret = 1;
2895 +    }else { //if entry not found, create new entry.
2896 +       MCAST_PRINT("%s: Create new entry %0X:%0X:%0X:%0X:%0X:%0X\n", \
2897 +               __FUNCTION__, MAC_ARG(dst_mac));
2898 +       ret = __add_mcast_entry(vlan_id, src_mac,dst_mac);
2899 +    }
2900 +
2901 +    up(&mtbl_lock);
2902 +    return ret;
2903 +
2904 +}
2905 +
2906 +
2907 +/*
2908 + * Return:
2909 + *         0: entry found
2910 + *         1: entry not found
2911 + */
2912 +int inline mcast_entry_del(uint16_t vlan_id, uint8_t *src_mac, uint8_t *dst_mac)
2913 +{
2914 +    int entry_num;
2915 +
2916 +    down(&mtbl_lock);
2917 +    if((entry_num = mcast_entry_get(vlan_id, src_mac, dst_mac)) >=0) {
2918 +       if((--mcast_tbl[entry_num].use_count)==0) {
2919 +           MCAST_PRINT("%s: %0X:%0X:%0X:%0X:%0X:%0X (entry_num=%d)\n", \
2920 +                   __FUNCTION__, MAC_ARG(dst_mac), entry_num);
2921 +           mcast_tbl[entry_num].valid=0;
2922 +           atomic_dec(&mcast_entry_num);
2923 +       }
2924 +       up(&mtbl_lock);
2925 +       return 0;
2926 +    }else {
2927 +       /* this multicast packet was not sent by meself, just ignore it */
2928 +       up(&mtbl_lock);
2929 +       return 1;
2930 +    }
2931 +}
2932 +
2933 +/*
2934 + * Return
2935 + *         0: drop packet
2936 + *         1: continue
2937 + */
2938 +int32_t mcast_rx(struct sk_buff * skb)
2939 +{
2940 +    struct vlan_ethhdr *eth = (struct vlan_ethhdr *)(skb->data-ETH_HLEN);
2941 +
2942 +    /* if we do not send multicast packet before,
2943 +     * we don't need to check re-inject multicast packet.
2944 +     */
2945 +    if (atomic_read(&mcast_entry_num)==0) {
2946 +       return 1;
2947 +    }
2948 +
2949 +
2950 +    if(is_multicast_pkt(eth->h_dest)) {
2951 +       MCAST_PRINT("%s: %0X:%0X:%0X:%0X:%0X:%0X\n", __FUNCTION__, \
2952 +               MAC_ARG(eth->h_dest));
2953 +
2954 +       if(ntohs(eth->h_vlan_proto)==0x8100) {
2955 +           return mcast_entry_del(eth->h_vlan_TCI, eth->h_source, eth->h_dest);
2956 +       } else {
2957 +           return mcast_entry_del(0, eth->h_source, eth->h_dest);
2958 +       }
2959 +    }
2960 +
2961 +    return 1;
2962 +}
2963 +
2964 +
2965 +int32_t mcast_tx(struct sk_buff *skb)
2966 +{
2967 +    struct vlan_ethhdr *eth = (struct vlan_ethhdr *)(skb->data);
2968 +
2969 +
2970 +    if(is_multicast_pkt(eth->h_dest)) {
2971 +       MCAST_PRINT("%s: %0X:%0X:%0X:%0X:%0X:%0X\n", __FUNCTION__,\
2972 +               MAC_ARG(eth->h_dest));
2973 +
2974 +       if(ntohs(eth->h_vlan_proto)==0x8100) {
2975 +           mcast_entry_ins(eth->h_vlan_TCI, eth->h_source, eth->h_dest);
2976 +       } else {
2977 +           mcast_entry_ins(0, eth->h_source, eth->h_dest);
2978 +       }
2979 +    }
2980 +
2981 +    return 1;
2982 +}
2983 +
2984 diff --git a/drivers/net/ethernet/raeth/mii_mgr.c b/drivers/net/ethernet/raeth/mii_mgr.c
2985 new file mode 100644
2986 index 0000000..77a47f1
2987 --- /dev/null
2988 +++ b/drivers/net/ethernet/raeth/mii_mgr.c
2989 @@ -0,0 +1,603 @@
2990 +#include <linux/module.h>
2991 +#include <linux/version.h>
2992 +#include <linux/netdevice.h>
2993 +
2994 +#include <linux/kernel.h>
2995 +#include <linux/sched.h>
2996 +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,0)
2997 +#include <asm/rt2880/rt_mmap.h>
2998 +#endif
2999 +
3000 +#include "ra2882ethreg.h"
3001 +#include "raether.h"
3002 +
3003 +
3004 +#if defined (CONFIG_RALINK_RT3052) || defined (CONFIG_RALINK_RT3352) || defined (CONFIG_RALINK_RT5350) || defined (CONFIG_RALINK_MT7628)
3005 +#define PHY_CONTROL_0          0xC0
3006 +#define PHY_CONTROL_1          0xC4
3007 +#define MDIO_PHY_CONTROL_0     (RALINK_ETH_SW_BASE + PHY_CONTROL_0)
3008 +#define MDIO_PHY_CONTROL_1     (RALINK_ETH_SW_BASE + PHY_CONTROL_1)
3009 +
3010 +#define GPIO_MDIO_BIT          (1<<7)
3011 +#define GPIO_PURPOSE_SELECT    0x60
3012 +#define GPIO_PRUPOSE           (RALINK_SYSCTL_BASE + GPIO_PURPOSE_SELECT)
3013 +
3014 +#elif defined (CONFIG_RALINK_RT6855)  || defined (CONFIG_RALINK_RT6855A)
3015 +
3016 +#define PHY_CONTROL_0          0x7004
3017 +#define MDIO_PHY_CONTROL_0     (RALINK_ETH_SW_BASE + PHY_CONTROL_0)
3018 +#define enable_mdio(x)
3019 +
3020 +#elif defined (CONFIG_RALINK_MT7620)
3021 +
3022 +#define PHY_CONTROL_0          0x7004
3023 +#define MDIO_PHY_CONTROL_0     (RALINK_ETH_SW_BASE + PHY_CONTROL_0)
3024 +#define enable_mdio(x)
3025 +
3026 +#elif defined (CONFIG_RALINK_MT7621) || defined (CONFIG_ARCH_MT7623)
3027 +
3028 +#define PHY_CONTROL_0          0x0004
3029 +#define MDIO_PHY_CONTROL_0     (RALINK_ETH_SW_BASE + PHY_CONTROL_0)
3030 +#define enable_mdio(x)
3031 +
3032 +#else
3033 +#define PHY_CONTROL_0          0x00
3034 +#define PHY_CONTROL_1          0x04
3035 +#define MDIO_PHY_CONTROL_0     (RALINK_FRAME_ENGINE_BASE + PHY_CONTROL_0)
3036 +#define MDIO_PHY_CONTROL_1     (RALINK_FRAME_ENGINE_BASE + PHY_CONTROL_1)
3037 +#define enable_mdio(x)
3038 +#endif
3039 +
3040 +#if defined (CONFIG_RALINK_RT3052) || defined (CONFIG_RALINK_RT3352) || defined (CONFIG_RALINK_RT5350) || defined (CONFIG_RALINK_MT7628)
3041 +void enable_mdio(int enable)
3042 +{
3043 +#if !defined (CONFIG_P5_MAC_TO_PHY_MODE) && !defined(CONFIG_GE1_RGMII_AN) && !defined(CONFIG_GE2_RGMII_AN) && \
3044 +    !defined (CONFIG_GE1_MII_AN) && !defined (CONFIG_GE2_MII_AN) && !defined (CONFIG_RALINK_MT7628)
3045 +       u32 data = sysRegRead(GPIO_PRUPOSE);
3046 +       if (enable)
3047 +               data &= ~GPIO_MDIO_BIT;
3048 +       else
3049 +               data |= GPIO_MDIO_BIT;
3050 +       sysRegWrite(GPIO_PRUPOSE, data);
3051 +#endif
3052 +}
3053 +#endif
3054 +
3055 +#if defined (CONFIG_RALINK_RT6855) || defined (CONFIG_RALINK_RT6855A)
3056 +
3057 +u32 mii_mgr_read(u32 phy_addr, u32 phy_register, u32 *read_data)
3058 +{
3059 +       u32 volatile status = 0;
3060 +       u32 rc = 0;
3061 +       unsigned long volatile t_start = jiffies;
3062 +       u32 volatile data = 0;
3063 +
3064 +       /* We enable mdio gpio purpose register, and disable it when exit. */
3065 +       enable_mdio(1);
3066 +
3067 +       // make sure previous read operation is complete
3068 +       while (1) {
3069 +                       // 0 : Read/write operation complete
3070 +               if(!( sysRegRead(MDIO_PHY_CONTROL_0) & (0x1 << 31)))
3071 +               {
3072 +                       break;
3073 +               }
3074 +               else if (time_after(jiffies, t_start + 5*HZ)) {
3075 +                       enable_mdio(0);
3076 +                       printk("\n MDIO Read operation is ongoing !!\n");
3077 +                       return rc;
3078 +               }
3079 +       }
3080 +
3081 +       data  = (0x01 << 16) | (0x02 << 18) | (phy_addr << 20) | (phy_register << 25);
3082 +       sysRegWrite(MDIO_PHY_CONTROL_0, data);
3083 +       data |= (1<<31);
3084 +       sysRegWrite(MDIO_PHY_CONTROL_0, data);
3085 +       //printk("\n Set Command [0x%08X] to PHY !!\n",MDIO_PHY_CONTROL_0);
3086 +
3087 +
3088 +       // make sure read operation is complete
3089 +       t_start = jiffies;
3090 +       while (1) {
3091 +               if (!(sysRegRead(MDIO_PHY_CONTROL_0) & (0x1 << 31))) {
3092 +                       status = sysRegRead(MDIO_PHY_CONTROL_0);
3093 +                       *read_data = (u32)(status & 0x0000FFFF);
3094 +
3095 +                       enable_mdio(0);
3096 +                       return 1;
3097 +               }
3098 +               else if (time_after(jiffies, t_start+5*HZ)) {
3099 +                       enable_mdio(0);
3100 +                       printk("\n MDIO Read operation is ongoing and Time Out!!\n");
3101 +                       return 0;
3102 +               }
3103 +       }
3104 +}
3105 +
3106 +u32 mii_mgr_write(u32 phy_addr, u32 phy_register, u32 write_data)
3107 +{
3108 +       unsigned long volatile t_start=jiffies;
3109 +       u32 volatile data;
3110 +
3111 +       enable_mdio(1);
3112 +
3113 +       // make sure previous write operation is complete
3114 +       while(1) {
3115 +               if (!(sysRegRead(MDIO_PHY_CONTROL_0) & (0x1 << 31)))
3116 +               {
3117 +                       break;
3118 +               }
3119 +               else if (time_after(jiffies, t_start + 5 * HZ)) {
3120 +                       enable_mdio(0);
3121 +                       printk("\n MDIO Write operation ongoing\n");
3122 +                       return 0;
3123 +               }
3124 +       }
3125 +
3126 +       data = (0x01 << 16)| (1<<18) | (phy_addr << 20) | (phy_register << 25) | write_data;
3127 +       sysRegWrite(MDIO_PHY_CONTROL_0, data);
3128 +       data |= (1<<31);
3129 +       sysRegWrite(MDIO_PHY_CONTROL_0, data); //start operation
3130 +       //printk("\n Set Command [0x%08X] to PHY !!\n",MDIO_PHY_CONTROL_0);
3131 +
3132 +       t_start = jiffies;
3133 +
3134 +       // make sure write operation is complete
3135 +       while (1) {
3136 +               if (!(sysRegRead(MDIO_PHY_CONTROL_0) & (0x1 << 31))) //0 : Read/write operation complete
3137 +               {
3138 +                       enable_mdio(0);
3139 +                       return 1;
3140 +               }
3141 +               else if (time_after(jiffies, t_start + 5 * HZ)) {
3142 +                       enable_mdio(0);
3143 +                       printk("\n MDIO Write operation Time Out\n");
3144 +                       return 0;
3145 +               }
3146 +       }
3147 +}
3148 +#elif defined (CONFIG_RALINK_MT7621) || defined (CONFIG_RALINK_MT7620) || defined (CONFIG_ARCH_MT7623)
3149 +
3150 +u32 __mii_mgr_read(u32 phy_addr, u32 phy_register, u32 *read_data)
3151 +{
3152 +       u32 volatile status = 0;
3153 +       u32 rc = 0;
3154 +       unsigned long volatile t_start = jiffies;
3155 +       u32 volatile data = 0;
3156 +
3157 +       /* We enable mdio gpio purpose register, and disable it when exit. */
3158 +       enable_mdio(1);
3159 +
3160 +       // make sure previous read operation is complete
3161 +       while (1) {
3162 +                       // 0 : Read/write operation complete
3163 +               if(!( sysRegRead(MDIO_PHY_CONTROL_0) & (0x1 << 31)))
3164 +               {
3165 +                       break;
3166 +               }
3167 +               else if (time_after(jiffies, t_start + 5*HZ)) {
3168 +                       enable_mdio(0);
3169 +                       printk("\n MDIO Read operation is ongoing !!\n");
3170 +                       return rc;
3171 +               }
3172 +       }
3173 +
3174 +       data  = (0x01 << 16) | (0x02 << 18) | (phy_addr << 20) | (phy_register << 25);
3175 +       sysRegWrite(MDIO_PHY_CONTROL_0, data);
3176 +       data |= (1<<31);
3177 +       sysRegWrite(MDIO_PHY_CONTROL_0, data);
3178 +       //printk("\n Set Command [0x%08X] = [0x%08X] to PHY !!\n",MDIO_PHY_CONTROL_0, data);
3179 +
3180 +
3181 +       // make sure read operation is complete
3182 +       t_start = jiffies;
3183 +       while (1) {
3184 +               if (!(sysRegRead(MDIO_PHY_CONTROL_0) & (0x1 << 31))) {
3185 +                       status = sysRegRead(MDIO_PHY_CONTROL_0);
3186 +                       *read_data = (u32)(status & 0x0000FFFF);
3187 +
3188 +                       enable_mdio(0);
3189 +                       return 1;
3190 +               }
3191 +               else if (time_after(jiffies, t_start+5*HZ)) {
3192 +                       enable_mdio(0);
3193 +                       printk("\n MDIO Read operation is ongoing and Time Out!!\n");
3194 +                       return 0;
3195 +               }
3196 +       }
3197 +}
3198 +
3199 +u32 __mii_mgr_write(u32 phy_addr, u32 phy_register, u32 write_data)
3200 +{
3201 +       unsigned long volatile t_start=jiffies;
3202 +       u32 volatile data;
3203 +
3204 +       enable_mdio(1);
3205 +
3206 +       // make sure previous write operation is complete
3207 +       while(1) {
3208 +               if (!(sysRegRead(MDIO_PHY_CONTROL_0) & (0x1 << 31)))
3209 +               {
3210 +                       break;
3211 +               }
3212 +               else if (time_after(jiffies, t_start + 5 * HZ)) {
3213 +                       enable_mdio(0);
3214 +                       printk("\n MDIO Write operation ongoing\n");
3215 +                       return 0;
3216 +               }
3217 +       }
3218 +
3219 +       data = (0x01 << 16)| (1<<18) | (phy_addr << 20) | (phy_register << 25) | write_data;
3220 +       sysRegWrite(MDIO_PHY_CONTROL_0, data);
3221 +       data |= (1<<31);
3222 +       sysRegWrite(MDIO_PHY_CONTROL_0, data); //start operation
3223 +       //printk("\n Set Command [0x%08X] to PHY !!\n",MDIO_PHY_CONTROL_0);
3224 +
3225 +       t_start = jiffies;
3226 +
3227 +       // make sure write operation is complete
3228 +       while (1) {
3229 +               if (!(sysRegRead(MDIO_PHY_CONTROL_0) & (0x1 << 31))) //0 : Read/write operation complete
3230 +               {
3231 +                       enable_mdio(0);
3232 +                       return 1;
3233 +               }
3234 +               else if (time_after(jiffies, t_start + 5 * HZ)) {
3235 +                       enable_mdio(0);
3236 +                       printk("\n MDIO Write operation Time Out\n");
3237 +                       return 0;
3238 +               }
3239 +       }
3240 +}
3241 +
3242 +u32 mii_mgr_read(u32 phy_addr, u32 phy_register, u32 *read_data)
3243 +{
3244 +#if defined (CONFIG_GE1_RGMII_FORCE_1000) || defined (CONFIG_GE1_TRGMII_FORCE_1200) || defined (CONFIG_GE1_TRGMII_FORCE_2000) || defined (CONFIG_GE1_TRGMII_FORCE_2600) || defined (CONFIG_P5_RGMII_TO_MT7530_MODE)
3245 +        u32 low_word;
3246 +        u32 high_word;
3247 +        u32 an_status = 0;
3248 +
3249 +       if(phy_addr==31)
3250 +       {
3251 +               an_status = (*(unsigned long *)(ESW_PHY_POLLING) & (1<<31));
3252 +               if(an_status){
3253 +                       *(unsigned long *)(ESW_PHY_POLLING) &= ~(1<<31);//(AN polling off)
3254 +               }
3255 +               //phase1: write page address phase
3256 +                if(__mii_mgr_write(phy_addr, 0x1f, ((phy_register >> 6) & 0x3FF))) {
3257 +                        //phase2: write address & read low word phase
3258 +                        if(__mii_mgr_read(phy_addr, (phy_register >> 2) & 0xF, &low_word)) {
3259 +                                //phase3: write address & read high word phase
3260 +                                if(__mii_mgr_read(phy_addr, (0x1 << 4), &high_word)) {
3261 +                                        *read_data = (high_word << 16) | (low_word & 0xFFFF);
3262 +                                       if(an_status){
3263 +                                               *(unsigned long *)(ESW_PHY_POLLING) |= (1<<31);//(AN polling on)
3264 +                                       }
3265 +                                       return 1;
3266 +                                }
3267 +                        }
3268 +                }
3269 +               if(an_status){
3270 +                       *(unsigned long *)(ESW_PHY_POLLING) |= (1<<31);//(AN polling on)
3271 +               }
3272 +        } else
3273 +#endif
3274 +       {
3275 +                if(__mii_mgr_read(phy_addr, phy_register, read_data)) {
3276 +                        return 1;
3277 +                }
3278 +        }
3279 +
3280 +        return 0;
3281 +}
3282 +
3283 +u32 mii_mgr_write(u32 phy_addr, u32 phy_register, u32 write_data)
3284 +{
3285 +#if defined (CONFIG_GE1_RGMII_FORCE_1000) || defined (CONFIG_GE1_TRGMII_FORCE_1200) || defined (CONFIG_GE1_TRGMII_FORCE_2000) || defined (CONFIG_GE1_TRGMII_FORCE_2600) || defined (CONFIG_P5_RGMII_TO_MT7530_MODE)
3286 +       u32 an_status = 0;
3287 +
3288 +       if(phy_addr == 31)
3289 +       {
3290 +               an_status = (*(unsigned long *)(ESW_PHY_POLLING) & (1<<31));
3291 +               if(an_status){
3292 +                       *(unsigned long *)(ESW_PHY_POLLING) &= ~(1<<31);//(AN polling off)
3293 +               }
3294 +               //phase1: write page address phase
3295 +                if(__mii_mgr_write(phy_addr, 0x1f, (phy_register >> 6) & 0x3FF)) {
3296 +                        //phase2: write address & read low word phase
3297 +                        if(__mii_mgr_write(phy_addr, ((phy_register >> 2) & 0xF), write_data & 0xFFFF)) {
3298 +                                //phase3: write address & read high word phase
3299 +                                if(__mii_mgr_write(phy_addr, (0x1 << 4), write_data >> 16)) {
3300 +                                       if(an_status){
3301 +                                               *(unsigned long *)(ESW_PHY_POLLING) |= (1<<31);//(AN polling on)
3302 +                                       }
3303 +                                   return 1;
3304 +                                }
3305 +                        }
3306 +                }
3307 +               if(an_status){
3308 +                       *(unsigned long *)(ESW_PHY_POLLING) |= (1<<31);//(AN polling on)
3309 +               }
3310 +        } else
3311 +#endif
3312 +       {
3313 +                if(__mii_mgr_write(phy_addr, phy_register, write_data)) {
3314 +                        return 1;
3315 +                }
3316 +        }
3317 +
3318 +        return 0;
3319 +}
3320 +
3321 +u32 mii_mgr_cl45_set_address(u32 port_num, u32 dev_addr, u32 reg_addr)
3322 +{
3323 +       u32 rc = 0;
3324 +       unsigned long volatile t_start = jiffies;
3325 +       u32 volatile data = 0;
3326 +
3327 +       enable_mdio(1);
3328 +
3329 +       while (1) {
3330 +               if(!( sysRegRead(MDIO_PHY_CONTROL_0) & (0x1 << 31)))
3331 +               {
3332 +                       break;
3333 +               }
3334 +               else if (time_after(jiffies, t_start + 5*HZ)) {
3335 +                       enable_mdio(0);
3336 +                       printk("\n MDIO Read operation is ongoing !!\n");
3337 +                       return rc;
3338 +               }
3339 +       }
3340 +       data = (dev_addr << 25) | (port_num << 20) | (0x00 << 18) | (0x00 << 16) | reg_addr;
3341 +       sysRegWrite(MDIO_PHY_CONTROL_0, data);
3342 +       data |= (1<<31);
3343 +       sysRegWrite(MDIO_PHY_CONTROL_0, data);
3344 +
3345 +       t_start = jiffies;
3346 +       while (1) {
3347 +               if (!(sysRegRead(MDIO_PHY_CONTROL_0) & (0x1 << 31))) //0 : Read/write operation complete
3348 +               {
3349 +                       enable_mdio(0);
3350 +                       return 1;
3351 +               }
3352 +               else if (time_after(jiffies, t_start + 5 * HZ)) {
3353 +                       enable_mdio(0);
3354 +                       printk("\n MDIO Write operation Time Out\n");
3355 +                       return 0;
3356 +               }
3357 +       }
3358 +
3359 +}
3360 +
3361 +
3362 +u32 mii_mgr_read_cl45(u32 port_num, u32 dev_addr, u32 reg_addr, u32 *read_data)
3363 +{
3364 +       u32 volatile status = 0;
3365 +       u32 rc = 0;
3366 +       unsigned long volatile t_start = jiffies;
3367 +       u32 volatile data = 0;
3368 +
3369 +        // set address first
3370 +       mii_mgr_cl45_set_address(port_num, dev_addr, reg_addr);
3371 +       //udelay(10);
3372 +
3373 +       enable_mdio(1);
3374 +
3375 +       while (1) {
3376 +               if(!( sysRegRead(MDIO_PHY_CONTROL_0) & (0x1 << 31)))
3377 +               {
3378 +                       break;
3379 +               }
3380 +               else if (time_after(jiffies, t_start + 5*HZ)) {
3381 +                       enable_mdio(0);
3382 +                       printk("\n MDIO Read operation is ongoing !!\n");
3383 +                       return rc;
3384 +               }
3385 +       }
3386 +       data = (dev_addr << 25) | (port_num << 20) | (0x03 << 18) | (0x00 << 16) | reg_addr;
3387 +       sysRegWrite(MDIO_PHY_CONTROL_0, data);
3388 +       data |= (1<<31);
3389 +       sysRegWrite(MDIO_PHY_CONTROL_0, data);
3390 +       t_start = jiffies;
3391 +       while (1) {
3392 +               if (!(sysRegRead(MDIO_PHY_CONTROL_0) & (0x1 << 31))) {
3393 +                       *read_data = (sysRegRead(MDIO_PHY_CONTROL_0) & 0x0000FFFF);
3394 +                       enable_mdio(0);
3395 +                       return 1;
3396 +               }
3397 +               else if (time_after(jiffies, t_start+5*HZ)) {
3398 +                       enable_mdio(0);
3399 +                       printk("\n Set Operation: MDIO Read operation is ongoing and Time Out!!\n");
3400 +                       return 0;
3401 +               }
3402 +               status = sysRegRead(MDIO_PHY_CONTROL_0);
3403 +       }
3404 +
3405 +}
3406 +
3407 +u32 mii_mgr_write_cl45 (u32 port_num, u32 dev_addr, u32 reg_addr, u32 write_data)
3408 +{
3409 +       u32 rc = 0;
3410 +       unsigned long volatile t_start = jiffies;
3411 +       u32 volatile data = 0;
3412 +
3413 +       // set address first
3414 +       mii_mgr_cl45_set_address(port_num, dev_addr, reg_addr);
3415 +       //udelay(10);
3416 +
3417 +       enable_mdio(1);
3418 +       while (1) {
3419 +               if(!( sysRegRead(MDIO_PHY_CONTROL_0) & (0x1 << 31)))
3420 +               {
3421 +                       break;
3422 +               }
3423 +               else if (time_after(jiffies, t_start + 5*HZ)) {
3424 +                       enable_mdio(0);
3425 +                       printk("\n MDIO Read operation is ongoing !!\n");
3426 +                       return rc;
3427 +               }
3428 +       }
3429 +
3430 +       data = (dev_addr << 25) | (port_num << 20) | (0x01 << 18) | (0x00 << 16) | write_data;
3431 +       sysRegWrite(MDIO_PHY_CONTROL_0, data);
3432 +       data |= (1<<31);
3433 +       sysRegWrite(MDIO_PHY_CONTROL_0, data);
3434 +
3435 +       t_start = jiffies;
3436 +
3437 +       while (1) {
3438 +               if (!(sysRegRead(MDIO_PHY_CONTROL_0) & (0x1 << 31)))
3439 +               {
3440 +                       enable_mdio(0);
3441 +                       return 1;
3442 +               }
3443 +               else if (time_after(jiffies, t_start + 5 * HZ)) {
3444 +                       enable_mdio(0);
3445 +                       printk("\n MDIO Write operation Time Out\n");
3446 +                       return 0;
3447 +               }
3448 +
3449 +       }
3450 +}
3451 +
3452 +#else // not rt6855
3453 +
3454 +u32 mii_mgr_read(u32 phy_addr, u32 phy_register, u32 *read_data)
3455 +{
3456 +       u32 volatile status = 0;
3457 +       u32 rc = 0;
3458 +       unsigned long volatile t_start = jiffies;
3459 +#if !defined (CONFIG_RALINK_RT3052) && !defined (CONFIG_RALINK_RT3352) && !defined (CONFIG_RALINK_RT5350) && !defined (CONFIG_RALINK_MT7628)
3460 +       u32 volatile data = 0;
3461 +#endif
3462 +
3463 +       /* We enable mdio gpio purpose register, and disable it when exit. */
3464 +       enable_mdio(1);
3465 +
3466 +       // make sure previous read operation is complete
3467 +       while (1) {
3468 +#if defined (CONFIG_RALINK_RT3052) || defined (CONFIG_RALINK_RT3352) || defined (CONFIG_RALINK_RT5350) || defined (CONFIG_RALINK_MT7628)
3469 +               // rd_rdy: read operation is complete
3470 +               if(!( sysRegRead(MDIO_PHY_CONTROL_1) & (0x1 << 1)))
3471 +#else
3472 +                       // 0 : Read/write operation complet
3473 +               if(!( sysRegRead(MDIO_PHY_CONTROL_0) & (0x1 << 31)))
3474 +#endif
3475 +               {
3476 +                       break;
3477 +               }
3478 +               else if (time_after(jiffies, t_start + 5*HZ)) {
3479 +                       enable_mdio(0);
3480 +                       printk("\n MDIO Read operation is ongoing !!\n");
3481 +                       return rc;
3482 +               }
3483 +       }
3484 +
3485 +#if defined (CONFIG_RALINK_RT3052) || defined (CONFIG_RALINK_RT3352) || defined (CONFIG_RALINK_RT5350) || defined (CONFIG_RALINK_MT7628)
3486 +       sysRegWrite(MDIO_PHY_CONTROL_0 , (1<<14) | (phy_register << 8) | (phy_addr));
3487 +#else
3488 +       data  = (phy_addr << 24) | (phy_register << 16);
3489 +       sysRegWrite(MDIO_PHY_CONTROL_0, data);
3490 +       data |= (1<<31);
3491 +       sysRegWrite(MDIO_PHY_CONTROL_0, data);
3492 +#endif
3493 +       //printk("\n Set Command [0x%08X] to PHY !!\n",MDIO_PHY_CONTROL_0);
3494 +
3495 +
3496 +       // make sure read operation is complete
3497 +       t_start = jiffies;
3498 +       while (1) {
3499 +#if defined (CONFIG_RALINK_RT3052) || defined (CONFIG_RALINK_RT3352) || defined (CONFIG_RALINK_RT5350) || defined (CONFIG_RALINK_MT7628)
3500 +               if (sysRegRead(MDIO_PHY_CONTROL_1) & (0x1 << 1)) {
3501 +                       status = sysRegRead(MDIO_PHY_CONTROL_1);
3502 +                       *read_data = (u32)(status >>16);
3503 +
3504 +                       enable_mdio(0);
3505 +                       return 1;
3506 +               }
3507 +#else
3508 +               if (!(sysRegRead(MDIO_PHY_CONTROL_0) & (0x1 << 31))) {
3509 +                       status = sysRegRead(MDIO_PHY_CONTROL_0);
3510 +                       *read_data = (u32)(status & 0x0000FFFF);
3511 +
3512 +                       enable_mdio(0);
3513 +                       return 1;
3514 +               }
3515 +#endif
3516 +               else if (time_after(jiffies, t_start+5*HZ)) {
3517 +                       enable_mdio(0);
3518 +                       printk("\n MDIO Read operation is ongoing and Time Out!!\n");
3519 +                       return 0;
3520 +               }
3521 +       }
3522 +}
3523 +
3524 +
3525 +u32 mii_mgr_write(u32 phy_addr, u32 phy_register, u32 write_data)
3526 +{
3527 +       unsigned long volatile t_start=jiffies;
3528 +       u32 volatile data;
3529 +
3530 +       enable_mdio(1);
3531 +
3532 +       // make sure previous write operation is complete
3533 +       while(1) {
3534 +#if defined (CONFIG_RALINK_RT3052) || defined (CONFIG_RALINK_RT3352) || defined (CONFIG_RALINK_RT5350) || defined (CONFIG_RALINK_MT7628)
3535 +               if (!(sysRegRead(MDIO_PHY_CONTROL_1) & (0x1 << 0)))
3536 +#else
3537 +               if (!(sysRegRead(MDIO_PHY_CONTROL_0) & (0x1 << 31)))
3538 +#endif
3539 +               {
3540 +                       break;
3541 +               }
3542 +               else if (time_after(jiffies, t_start + 5 * HZ)) {
3543 +                       enable_mdio(0);
3544 +                       printk("\n MDIO Write operation ongoing\n");
3545 +                       return 0;
3546 +               }
3547 +       }
3548 +
3549 +#if defined (CONFIG_RALINK_RT3052) || defined (CONFIG_RALINK_RT3352) || defined (CONFIG_RALINK_RT5350) || defined (CONFIG_RALINK_MT7628)
3550 +       data = ((write_data & 0xFFFF) << 16);
3551 +       data |= (phy_register << 8) | (phy_addr);
3552 +       data |= (1<<13);
3553 +       sysRegWrite(MDIO_PHY_CONTROL_0, data);
3554 +#else
3555 +       data = (1<<30) | (phy_addr << 24) | (phy_register << 16) | write_data;
3556 +       sysRegWrite(MDIO_PHY_CONTROL_0, data);
3557 +       data |= (1<<31);
3558 +       sysRegWrite(MDIO_PHY_CONTROL_0, data); //start operation
3559 +#endif
3560 +       //printk("\n Set Command [0x%08X] to PHY !!\n",MDIO_PHY_CONTROL_0);
3561 +
3562 +       t_start = jiffies;
3563 +
3564 +       // make sure write operation is complete
3565 +       while (1) {
3566 +#if defined (CONFIG_RALINK_RT3052) || defined (CONFIG_RALINK_RT3352) || defined (CONFIG_RALINK_RT5350) || defined (CONFIG_RALINK_MT7628)
3567 +               if (sysRegRead(MDIO_PHY_CONTROL_1) & (0x1 << 0)) //wt_done ?= 1
3568 +#else
3569 +               if (!(sysRegRead(MDIO_PHY_CONTROL_0) & (0x1 << 31))) //0 : Read/write operation complete
3570 +#endif
3571 +               {
3572 +                       enable_mdio(0);
3573 +                       return 1;
3574 +               }
3575 +               else if (time_after(jiffies, t_start + 5 * HZ)) {
3576 +                       enable_mdio(0);
3577 +                       printk("\n MDIO Write operation Time Out\n");
3578 +                       return 0;
3579 +               }
3580 +       }
3581 +}
3582 +
3583 +
3584 +
3585 +
3586 +#endif
3587 +
3588 +
3589 +
3590 +
3591 +EXPORT_SYMBOL(mii_mgr_write);
3592 +EXPORT_SYMBOL(mii_mgr_read);
3593 diff --git a/drivers/net/ethernet/raeth/ra2882ethreg.h b/drivers/net/ethernet/raeth/ra2882ethreg.h
3594 new file mode 100644
3595 index 0000000..c67a042
3596 --- /dev/null
3597 +++ b/drivers/net/ethernet/raeth/ra2882ethreg.h
3598 @@ -0,0 +1,1985 @@
3599 +#ifndef RA2882ETHREG_H
3600 +#define RA2882ETHREG_H
3601 +
3602 +#include <linux/mii.h>         // for struct mii_if_info in ra2882ethreg.h
3603 +#include <linux/version.h>     /* check linux version for 2.4 and 2.6 compatibility */
3604 +#include <linux/interrupt.h>   /* for "struct tasklet_struct" in linux-3.10.14 */
3605 +#if defined (CONFIG_HW_SFQ)
3606 +#include <linux/ip.h>
3607 +#include <linux/ipv6.h>
3608 +#endif
3609 +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
3610 +#include <asm/rt2880/rt_mmap.h>
3611 +#endif
3612 +#include "raether.h"
3613 +
3614 +#ifdef WORKQUEUE_BH
3615 +#include <linux/workqueue.h>
3616 +#endif // WORKQUEUE_BH //
3617 +#ifdef CONFIG_RAETH_LRO
3618 +#include <linux/inet_lro.h>
3619 +#endif
3620 +
3621 +#define MAX_PACKET_SIZE        1514
3622 +#define        MIN_PACKET_SIZE 60
3623 +#define MAX_TXD_LEN 0x3fff
3624 +
3625 +#if defined (CONFIG_ARCH_MT7623)
3626 +#define phys_to_bus(a) (a)
3627 +#else
3628 +#define phys_to_bus(a) (a & 0x1FFFFFFF)
3629 +#endif
3630 +
3631 +
3632 +
3633 +
3634 +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,36)
3635 +#define BIT(x)     ((1 << x))
3636 +#endif
3637 +/* bits range: for example BITS(16,23) = 0xFF0000
3638 + *   ==>  (BIT(m)-1)   = 0x0000FFFF     ~(BIT(m)-1)   => 0xFFFF0000
3639 + *   ==>  (BIT(n+1)-1) = 0x00FFFFFF
3640 + */
3641 +#define BITS(m,n)   (~(BIT(m)-1) & ((BIT(n) - 1) | BIT(n)))
3642 +
3643 +#define ETHER_ADDR_LEN  6
3644 +
3645 +/*  Phy Vender ID list */
3646 +
3647 +#define EV_ICPLUS_PHY_ID0 0x0243
3648 +#define EV_ICPLUS_PHY_ID1 0x0D90
3649 +#define EV_MARVELL_PHY_ID0 0x0141
3650 +#define EV_MARVELL_PHY_ID1 0x0CC2
3651 +#define EV_VTSS_PHY_ID0 0x0007
3652 +#define EV_VTSS_PHY_ID1 0x0421
3653 +
3654 +/*
3655 +     FE_INT_STATUS
3656 +*/
3657 +#if defined (CONFIG_RALINK_RT5350) || defined (CONFIG_RALINK_RT6855) || defined(CONFIG_RALINK_RT6855A) || \
3658 +    defined (CONFIG_RALINK_MT7620) || defined (CONFIG_RALINK_MT7621) || defined (CONFIG_RALINK_MT7628) || \
3659 +    defined (CONFIG_ARCH_MT7623)
3660 +
3661 +#define RX_COHERENT      BIT(31)
3662 +#define RX_DLY_INT       BIT(30)
3663 +#define TX_COHERENT      BIT(29)
3664 +#define TX_DLY_INT       BIT(28)
3665 +#define RING3_RX_DLY_INT    BIT(27)
3666 +#define RING2_RX_DLY_INT    BIT(26)
3667 +#define RING1_RX_DLY_INT    BIT(25)
3668 +
3669 +#define ALT_RPLC_INT3    BIT(23)
3670 +#define ALT_RPLC_INT2    BIT(22)
3671 +#define ALT_RPLC_INT1    BIT(21)
3672 +
3673 +#define RX_DONE_INT3     BIT(19)
3674 +#define RX_DONE_INT2     BIT(18)
3675 +#define RX_DONE_INT1     BIT(17)
3676 +#define RX_DONE_INT0     BIT(16)
3677 +
3678 +#define TX_DONE_INT3     BIT(3)
3679 +#define TX_DONE_INT2     BIT(2)
3680 +#define TX_DONE_INT1     BIT(1)
3681 +#define TX_DONE_INT0     BIT(0)
3682 +
3683 +#if defined (CONFIG_RALINK_MT7621) || defined (CONFIG_ARCH_MT7623)
3684 +#define RLS_COHERENT     BIT(29)
3685 +#define RLS_DLY_INT      BIT(28)
3686 +#define RLS_DONE_INT     BIT(0)
3687 +#endif
3688 +
3689 +#else
3690 +//#define CNT_PPE_AF       BIT(31)
3691 +//#define CNT_GDM_AF       BIT(29)
3692 +#define PSE_P2_FC       BIT(26)
3693 +#define GDM_CRC_DROP     BIT(25)
3694 +#define PSE_BUF_DROP     BIT(24)
3695 +#define GDM_OTHER_DROP  BIT(23)
3696 +#define PSE_P1_FC        BIT(22)
3697 +#define PSE_P0_FC        BIT(21)
3698 +#define PSE_FQ_EMPTY     BIT(20)
3699 +#define GE1_STA_CHG      BIT(18)
3700 +#define TX_COHERENT      BIT(17)
3701 +#define RX_COHERENT      BIT(16)
3702 +
3703 +#define TX_DONE_INT3     BIT(11)
3704 +#define TX_DONE_INT2     BIT(10)
3705 +#define TX_DONE_INT1     BIT(9)
3706 +#define TX_DONE_INT0     BIT(8)
3707 +#define RX_DONE_INT1     RX_DONE_INT0
3708 +#define RX_DONE_INT0     BIT(2)
3709 +#define TX_DLY_INT       BIT(1)
3710 +#define RX_DLY_INT       BIT(0)
3711 +#endif
3712 +
3713 +#define FE_INT_ALL             (TX_DONE_INT3 | TX_DONE_INT2 | \
3714 +                                TX_DONE_INT1 | TX_DONE_INT0 | \
3715 +                                RX_DONE_INT0 | RX_DONE_INT1 | \
3716 +                                RX_DONE_INT2 | RX_DONE_INT3)
3717 +
3718 +#if defined (CONFIG_RALINK_MT7621) || defined (CONFIG_ARCH_MT7623)
3719 +#define QFE_INT_ALL            (RLS_DONE_INT | RX_DONE_INT0 | RX_DONE_INT1)
3720 +#define QFE_INT_DLY_INIT       (RLS_DLY_INT | RX_DLY_INT)
3721 +
3722 +#define NUM_QDMA_PAGE      512
3723 +#define QDMA_PAGE_SIZE      2048
3724 +#endif
3725 +/*
3726 + * SW_INT_STATUS
3727 + */
3728 +#if defined (CONFIG_RALINK_RT3052) || defined (CONFIG_RALINK_RT3352) || defined (CONFIG_RALINK_RT5350) || defined (CONFIG_RALINK_MT7628)
3729 +#define PORT0_QUEUE_FULL        BIT(14) //port0 queue full
3730 +#define PORT1_QUEUE_FULL        BIT(15) //port1 queue full
3731 +#define PORT2_QUEUE_FULL        BIT(16) //port2 queue full
3732 +#define PORT3_QUEUE_FULL        BIT(17) //port3 queue full
3733 +#define PORT4_QUEUE_FULL        BIT(18) //port4 queue full
3734 +#define PORT5_QUEUE_FULL        BIT(19) //port5 queue full
3735 +#define PORT6_QUEUE_FULL        BIT(20) //port6 queue full
3736 +#define SHARED_QUEUE_FULL       BIT(23) //shared queue full
3737 +#define QUEUE_EXHAUSTED         BIT(24) //global queue is used up and all packets are dropped
3738 +#define BC_STROM                BIT(25) //the device is undergoing broadcast storm
3739 +#define PORT_ST_CHG             BIT(26) //Port status change
3740 +#define UNSECURED_ALERT         BIT(27) //Intruder alert
3741 +#define ABNORMAL_ALERT          BIT(28) //Abnormal
3742 +
3743 +#define ESW_ISR                        (RALINK_ETH_SW_BASE + 0x00)
3744 +#define ESW_IMR                        (RALINK_ETH_SW_BASE + 0x04)
3745 +#define ESW_INT_ALL            (PORT_ST_CHG)
3746 +
3747 +#elif defined (CONFIG_RALINK_RT6855) || defined(CONFIG_RALINK_RT6855A) || \
3748 +      defined (CONFIG_RALINK_MT7620)
3749 +#define MIB_INT                 BIT(25)
3750 +#define ACL_INT                        BIT(24)
3751 +#define P5_LINK_CH             BIT(5)
3752 +#define P4_LINK_CH             BIT(4)
3753 +#define P3_LINK_CH             BIT(3)
3754 +#define P2_LINK_CH             BIT(2)
3755 +#define P1_LINK_CH             BIT(1)
3756 +#define P0_LINK_CH             BIT(0)
3757 +
3758 +#define RX_GOCT_CNT            BIT(4)
3759 +#define RX_GOOD_CNT            BIT(6)
3760 +#define TX_GOCT_CNT            BIT(17)
3761 +#define TX_GOOD_CNT            BIT(19)
3762 +
3763 +#define MSK_RX_GOCT_CNT                BIT(4)
3764 +#define MSK_RX_GOOD_CNT                BIT(6)
3765 +#define MSK_TX_GOCT_CNT                BIT(17)
3766 +#define MSK_TX_GOOD_CNT                BIT(19)
3767 +#define MSK_CNT_INT_ALL                (MSK_RX_GOCT_CNT | MSK_RX_GOOD_CNT | MSK_TX_GOCT_CNT | MSK_TX_GOOD_CNT)
3768 +//#define MSK_CNT_INT_ALL              (MSK_RX_GOOD_CNT | MSK_TX_GOOD_CNT)
3769 +
3770 +
3771 +#define ESW_IMR                        (RALINK_ETH_SW_BASE + 0x7000 + 0x8)
3772 +#define ESW_ISR                        (RALINK_ETH_SW_BASE + 0x7000 + 0xC)
3773 +#define ESW_INT_ALL            (P0_LINK_CH | P1_LINK_CH | P2_LINK_CH | P3_LINK_CH | P4_LINK_CH | P5_LINK_CH | ACL_INT | MIB_INT)
3774 +#define ESW_AISR               (RALINK_ETH_SW_BASE + 0x8)
3775 +#define ESW_P0_IntSn           (RALINK_ETH_SW_BASE + 0x4004)
3776 +#define ESW_P1_IntSn           (RALINK_ETH_SW_BASE + 0x4104)
3777 +#define ESW_P2_IntSn           (RALINK_ETH_SW_BASE + 0x4204)
3778 +#define ESW_P3_IntSn           (RALINK_ETH_SW_BASE + 0x4304)
3779 +#define ESW_P4_IntSn           (RALINK_ETH_SW_BASE + 0x4404)
3780 +#define ESW_P5_IntSn           (RALINK_ETH_SW_BASE + 0x4504)
3781 +#define ESW_P6_IntSn           (RALINK_ETH_SW_BASE + 0x4604)
3782 +#define ESW_P0_IntMn           (RALINK_ETH_SW_BASE + 0x4008)
3783 +#define ESW_P1_IntMn           (RALINK_ETH_SW_BASE + 0x4108)
3784 +#define ESW_P2_IntMn           (RALINK_ETH_SW_BASE + 0x4208)
3785 +#define ESW_P3_IntMn           (RALINK_ETH_SW_BASE + 0x4308)
3786 +#define ESW_P4_IntMn           (RALINK_ETH_SW_BASE + 0x4408)
3787 +#define ESW_P5_IntMn           (RALINK_ETH_SW_BASE + 0x4508)
3788 +#define ESW_P6_IntMn           (RALINK_ETH_SW_BASE + 0x4608)
3789 +
3790 +#if defined (CONFIG_RALINK_MT7620)
3791 +#define ESW_P7_IntSn           (RALINK_ETH_SW_BASE + 0x4704)
3792 +#define ESW_P7_IntMn           (RALINK_ETH_SW_BASE + 0x4708)
3793 +#endif
3794 +
3795 +
3796 +#define ESW_PHY_POLLING                (RALINK_ETH_SW_BASE + 0x7000)
3797 +
3798 +#elif defined (CONFIG_RALINK_MT7621) || defined (CONFIG_ARCH_MT7623)
3799 +
3800 +#define ESW_PHY_POLLING                (RALINK_ETH_SW_BASE + 0x0000)
3801 +
3802 +#define P5_LINK_CH             BIT(5)
3803 +#define P4_LINK_CH             BIT(4)
3804 +#define P3_LINK_CH             BIT(3)
3805 +#define P2_LINK_CH             BIT(2)
3806 +#define P1_LINK_CH             BIT(1)
3807 +#define P0_LINK_CH             BIT(0)
3808 +
3809 +
3810 +#endif // CONFIG_RALINK_RT3052 || CONFIG_RALINK_RT3352 || CONFIG_RALINK_RT5350 || defined (CONFIG_RALINK_MT7628)//
3811 +
3812 +#define RX_BUF_ALLOC_SIZE      2000
3813 +#define FASTPATH_HEADROOM      64
3814 +
3815 +#define ETHER_BUFFER_ALIGN     32              ///// Align on a cache line
3816 +
3817 +#define ETHER_ALIGNED_RX_SKB_ADDR(addr) \
3818 +        ((((unsigned long)(addr) + ETHER_BUFFER_ALIGN - 1) & \
3819 +        ~(ETHER_BUFFER_ALIGN - 1)) - (unsigned long)(addr))
3820 +
3821 +#ifdef CONFIG_PSEUDO_SUPPORT
3822 +typedef struct _PSEUDO_ADAPTER {
3823 +    struct net_device *RaethDev;
3824 +    struct net_device *PseudoDev;
3825 +    struct net_device_stats stat;
3826 +#if defined (CONFIG_ETHTOOL) /*&& defined (CONFIG_RAETH_ROUTER)*/
3827 +       struct mii_if_info      mii_info;
3828 +#endif
3829 +
3830 +} PSEUDO_ADAPTER, PPSEUDO_ADAPTER;
3831 +
3832 +#define MAX_PSEUDO_ENTRY               1
3833 +#endif
3834 +
3835 +
3836 +
3837 +/* Register Categories Definition */
3838 +#define RAFRAMEENGINE_OFFSET   0x0000
3839 +#define RAGDMA_OFFSET          0x0020
3840 +#define RAPSE_OFFSET           0x0040
3841 +#define RAGDMA2_OFFSET         0x0060
3842 +#define RACDMA_OFFSET          0x0080
3843 +#if defined (CONFIG_RALINK_RT5350) || defined (CONFIG_RALINK_RT6855) || defined(CONFIG_RALINK_RT6855A) || \
3844 +    defined (CONFIG_RALINK_MT7620) || defined (CONFIG_RALINK_MT7621) || defined (CONFIG_RALINK_MT7628) || \
3845 +    defined (CONFIG_ARCH_MT7623)
3846 +
3847 +#define RAPDMA_OFFSET          0x0800
3848 +#define SDM_OFFSET             0x0C00
3849 +#else
3850 +#define RAPDMA_OFFSET          0x0100
3851 +#endif
3852 +#define RAPPE_OFFSET           0x0200
3853 +#define RACMTABLE_OFFSET       0x0400
3854 +#define RAPOLICYTABLE_OFFSET   0x1000
3855 +
3856 +
3857 +/* Register Map Detail */
3858 +/* RT3883 */
3859 +#define SYSCFG1                        (RALINK_SYSCTL_BASE + 0x14)
3860 +
3861 +#if defined (CONFIG_RALINK_RT5350) || defined (CONFIG_RALINK_MT7628)
3862 +
3863 +/* 1. PDMA */
3864 +#define TX_BASE_PTR0           (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x000)
3865 +#define TX_MAX_CNT0            (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x004)
3866 +#define TX_CTX_IDX0            (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x008)
3867 +#define TX_DTX_IDX0            (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x00C)
3868 +
3869 +#define TX_BASE_PTR1           (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x010)
3870 +#define TX_MAX_CNT1            (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x014)
3871 +#define TX_CTX_IDX1            (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x018)
3872 +#define TX_DTX_IDX1            (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x01C)
3873 +
3874 +#define TX_BASE_PTR2           (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x020)
3875 +#define TX_MAX_CNT2            (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x024)
3876 +#define TX_CTX_IDX2            (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x028)
3877 +#define TX_DTX_IDX2            (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x02C)
3878 +
3879 +#define TX_BASE_PTR3           (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x030)
3880 +#define TX_MAX_CNT3            (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x034)
3881 +#define TX_CTX_IDX3            (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x038)
3882 +#define TX_DTX_IDX3            (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x03C)
3883 +
3884 +#define RX_BASE_PTR0           (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x100)
3885 +#define RX_MAX_CNT0            (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x104)
3886 +#define RX_CALC_IDX0           (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x108)
3887 +#define RX_DRX_IDX0            (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x10C)
3888 +
3889 +#define RX_BASE_PTR1           (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x110)
3890 +#define RX_MAX_CNT1            (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x114)
3891 +#define RX_CALC_IDX1           (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x118)
3892 +#define RX_DRX_IDX1            (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x11C)
3893 +
3894 +#define PDMA_INFO              (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x200)
3895 +#define PDMA_GLO_CFG           (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x204)
3896 +#define PDMA_RST_IDX           (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x208)
3897 +#define PDMA_RST_CFG           (PDMA_RST_IDX)
3898 +#define DLY_INT_CFG            (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x20C)
3899 +#define FREEQ_THRES            (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x210)
3900 +#define INT_STATUS             (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x220)
3901 +#define FE_INT_STATUS          (INT_STATUS)
3902 +#define INT_MASK               (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x228)
3903 +#define FE_INT_ENABLE          (INT_MASK)
3904 +#define PDMA_WRR               (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x280)
3905 +#define PDMA_SCH_CFG           (PDMA_WRR)
3906 +
3907 +#define SDM_CON                        (RALINK_FRAME_ENGINE_BASE+SDM_OFFSET+0x00)  //Switch DMA configuration
3908 +#define SDM_RRING              (RALINK_FRAME_ENGINE_BASE+SDM_OFFSET+0x04)  //Switch DMA Rx Ring
3909 +#define SDM_TRING              (RALINK_FRAME_ENGINE_BASE+SDM_OFFSET+0x08)  //Switch DMA Tx Ring
3910 +#define SDM_MAC_ADRL           (RALINK_FRAME_ENGINE_BASE+SDM_OFFSET+0x0C)  //Switch MAC address LSB
3911 +#define SDM_MAC_ADRH           (RALINK_FRAME_ENGINE_BASE+SDM_OFFSET+0x10)  //Switch MAC Address MSB
3912 +#define SDM_TPCNT              (RALINK_FRAME_ENGINE_BASE+SDM_OFFSET+0x100) //Switch DMA Tx packet count
3913 +#define SDM_TBCNT              (RALINK_FRAME_ENGINE_BASE+SDM_OFFSET+0x104) //Switch DMA Tx byte count
3914 +#define SDM_RPCNT              (RALINK_FRAME_ENGINE_BASE+SDM_OFFSET+0x108) //Switch DMA rx packet count
3915 +#define SDM_RBCNT              (RALINK_FRAME_ENGINE_BASE+SDM_OFFSET+0x10C) //Switch DMA rx byte count
3916 +#define SDM_CS_ERR             (RALINK_FRAME_ENGINE_BASE+SDM_OFFSET+0x110) //Switch DMA rx checksum error count
3917 +
3918 +#elif defined (CONFIG_RALINK_RT6855) || defined(CONFIG_RALINK_RT6855A) || \
3919 +      defined (CONFIG_RALINK_MT7620) || defined (CONFIG_RALINK_MT7621) || \
3920 +      defined (CONFIG_ARCH_MT7623)
3921 +
3922 +/* Old FE with New PDMA */
3923 +#define PDMA_RELATED            0x0800
3924 +/* 1. PDMA */
3925 +#define TX_BASE_PTR0            (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x000)
3926 +#define TX_MAX_CNT0             (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x004)
3927 +#define TX_CTX_IDX0             (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x008)
3928 +#define TX_DTX_IDX0             (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x00C)
3929 +
3930 +#define TX_BASE_PTR1            (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x010)
3931 +#define TX_MAX_CNT1             (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x014)
3932 +#define TX_CTX_IDX1             (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x018)
3933 +#define TX_DTX_IDX1             (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x01C)
3934 +
3935 +#define TX_BASE_PTR2            (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x020)
3936 +#define TX_MAX_CNT2             (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x024)
3937 +#define TX_CTX_IDX2             (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x028)
3938 +#define TX_DTX_IDX2             (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x02C)
3939 +
3940 +#define TX_BASE_PTR3            (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x030)
3941 +#define TX_MAX_CNT3             (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x034)
3942 +#define TX_CTX_IDX3             (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x038)
3943 +#define TX_DTX_IDX3             (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x03C)
3944 +
3945 +#define RX_BASE_PTR0            (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x100)
3946 +#define RX_MAX_CNT0             (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x104)
3947 +#define RX_CALC_IDX0            (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x108)
3948 +#define RX_DRX_IDX0             (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x10C)
3949 +
3950 +#define RX_BASE_PTR1            (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x110)
3951 +#define RX_MAX_CNT1             (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x114)
3952 +#define RX_CALC_IDX1            (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x118)
3953 +#define RX_DRX_IDX1             (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x11C)
3954 +
3955 +#define RX_BASE_PTR2            (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x120)
3956 +#define RX_MAX_CNT2             (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x124)
3957 +#define RX_CALC_IDX2            (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x128)
3958 +#define RX_DRX_IDX12            (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x12C)
3959 +
3960 +#define RX_BASE_PTR3            (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x130)
3961 +#define RX_MAX_CNT3             (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x134)
3962 +#define RX_CALC_IDX3            (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x138)
3963 +#define RX_DRX_IDX3             (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x13C)
3964 +
3965 +#define PDMA_INFO               (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x200)
3966 +#define PDMA_GLO_CFG            (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x204)
3967 +#define PDMA_RST_IDX            (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x208)
3968 +#define PDMA_RST_CFG            (PDMA_RST_IDX)
3969 +#define DLY_INT_CFG             (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x20C)
3970 +#define FREEQ_THRES             (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x210)
3971 +#define INT_STATUS              (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x220)
3972 +#define FE_INT_STATUS          (INT_STATUS)
3973 +#define INT_MASK                (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x228)
3974 +#define FE_INT_ENABLE          (INT_MASK)
3975 +#define SCH_Q01_CFG            (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x280)
3976 +#define SCH_Q23_CFG            (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x284)
3977 +
3978 +#define FE_GLO_CFG          RALINK_FRAME_ENGINE_BASE + 0x00
3979 +#define FE_RST_GL           RALINK_FRAME_ENGINE_BASE + 0x04
3980 +#define FE_INT_STATUS2     RALINK_FRAME_ENGINE_BASE + 0x08
3981 +#define FE_INT_ENABLE2     RALINK_FRAME_ENGINE_BASE + 0x0c
3982 +//#define FC_DROP_STA         RALINK_FRAME_ENGINE_BASE + 0x18
3983 +#define FOE_TS_T            RALINK_FRAME_ENGINE_BASE + 0x10
3984 +
3985 +#if defined (CONFIG_RALINK_MT7620)
3986 +#define GDMA1_RELATED       0x0600
3987 +#define GDMA1_FWD_CFG       (RALINK_FRAME_ENGINE_BASE + GDMA1_RELATED + 0x00)
3988 +#define GDMA1_SHPR_CFG      (RALINK_FRAME_ENGINE_BASE + GDMA1_RELATED + 0x04)
3989 +#define GDMA1_MAC_ADRL      (RALINK_FRAME_ENGINE_BASE + GDMA1_RELATED + 0x08)
3990 +#define GDMA1_MAC_ADRH      (RALINK_FRAME_ENGINE_BASE + GDMA1_RELATED + 0x0C)
3991 +#elif defined (CONFIG_RALINK_MT7621) || defined (CONFIG_ARCH_MT7623)
3992 +#define GDMA1_RELATED       0x0500
3993 +#define GDMA1_FWD_CFG       (RALINK_FRAME_ENGINE_BASE + GDMA1_RELATED + 0x00)
3994 +#define GDMA1_SHPR_CFG      (RALINK_FRAME_ENGINE_BASE + GDMA1_RELATED + 0x04)
3995 +#define GDMA1_MAC_ADRL      (RALINK_FRAME_ENGINE_BASE + GDMA1_RELATED + 0x08)
3996 +#define GDMA1_MAC_ADRH      (RALINK_FRAME_ENGINE_BASE + GDMA1_RELATED + 0x0C)
3997 +
3998 +#define GDMA2_RELATED       0x1500
3999 +#define GDMA2_FWD_CFG       (RALINK_FRAME_ENGINE_BASE + GDMA2_RELATED + 0x00)
4000 +#define GDMA2_SHPR_CFG      (RALINK_FRAME_ENGINE_BASE + GDMA2_RELATED + 0x04)
4001 +#define GDMA2_MAC_ADRL      (RALINK_FRAME_ENGINE_BASE + GDMA2_RELATED + 0x08)
4002 +#define GDMA2_MAC_ADRH      (RALINK_FRAME_ENGINE_BASE + GDMA2_RELATED + 0x0C)
4003 +#else
4004 +#define GDMA1_RELATED       0x0020
4005 +#define GDMA1_FWD_CFG       (RALINK_FRAME_ENGINE_BASE + GDMA1_RELATED + 0x00)
4006 +#define GDMA1_SCH_CFG       (RALINK_FRAME_ENGINE_BASE + GDMA1_RELATED + 0x04)
4007 +#define GDMA1_SHPR_CFG      (RALINK_FRAME_ENGINE_BASE + GDMA1_RELATED + 0x08)
4008 +#define GDMA1_MAC_ADRL      (RALINK_FRAME_ENGINE_BASE + GDMA1_RELATED + 0x0C)
4009 +#define GDMA1_MAC_ADRH      (RALINK_FRAME_ENGINE_BASE + GDMA1_RELATED + 0x10)
4010 +
4011 +#define GDMA2_RELATED       0x0060
4012 +#define GDMA2_FWD_CFG       (RALINK_FRAME_ENGINE_BASE + GDMA2_RELATED + 0x00)
4013 +#define GDMA2_SCH_CFG       (RALINK_FRAME_ENGINE_BASE + GDMA2_RELATED + 0x04)
4014 +#define GDMA2_SHPR_CFG      (RALINK_FRAME_ENGINE_BASE + GDMA2_RELATED + 0x08)
4015 +#define GDMA2_MAC_ADRL      (RALINK_FRAME_ENGINE_BASE + GDMA2_RELATED + 0x0C)
4016 +#define GDMA2_MAC_ADRH      (RALINK_FRAME_ENGINE_BASE + GDMA2_RELATED + 0x10)
4017 +#endif
4018 +
4019 +#if defined (CONFIG_RALINK_MT7620)
4020 +#define PSE_RELATED         0x0500
4021 +#define PSE_FQFC_CFG        (RALINK_FRAME_ENGINE_BASE + PSE_RELATED + 0x00)
4022 +#define PSE_IQ_CFG          (RALINK_FRAME_ENGINE_BASE + PSE_RELATED + 0x04)
4023 +#define PSE_QUE_STA         (RALINK_FRAME_ENGINE_BASE + PSE_RELATED + 0x08)
4024 +#else
4025 +#define PSE_RELATED         0x0040
4026 +#define PSE_FQ_CFG          (RALINK_FRAME_ENGINE_BASE + PSE_RELATED + 0x00)
4027 +#define CDMA_FC_CFG         (RALINK_FRAME_ENGINE_BASE + PSE_RELATED + 0x04)
4028 +#define GDMA1_FC_CFG        (RALINK_FRAME_ENGINE_BASE + PSE_RELATED + 0x08)
4029 +#define GDMA2_FC_CFG        (RALINK_FRAME_ENGINE_BASE + PSE_RELATED + 0x0C)
4030 +#define CDMA_OQ_STA         (RALINK_FRAME_ENGINE_BASE + PSE_RELATED + 0x10)
4031 +#define GDMA1_OQ_STA        (RALINK_FRAME_ENGINE_BASE + PSE_RELATED + 0x14)
4032 +#define GDMA2_OQ_STA        (RALINK_FRAME_ENGINE_BASE + PSE_RELATED + 0x18)
4033 +#define PSE_IQ_STA          (RALINK_FRAME_ENGINE_BASE + PSE_RELATED + 0x1C)
4034 +#endif
4035 +
4036 +
4037 +#if defined (CONFIG_RALINK_MT7620)
4038 +#define CDMA_RELATED        0x0400
4039 +#define CDMA_CSG_CFG        (RALINK_FRAME_ENGINE_BASE + CDMA_RELATED + 0x00)
4040 +#define SMACCR0                    (RALINK_ETH_SW_BASE + 0x3FE4)
4041 +#define SMACCR1                    (RALINK_ETH_SW_BASE + 0x3FE8)
4042 +#define CKGCR               (RALINK_ETH_SW_BASE + 0x3FF0)
4043 +#elif defined (CONFIG_RALINK_MT7621) || defined (CONFIG_ARCH_MT7623)
4044 +#define CDMA_RELATED        0x0400
4045 +#define CDMA_CSG_CFG        (RALINK_FRAME_ENGINE_BASE + CDMA_RELATED + 0x00) //fake definition
4046 +#define CDMP_IG_CTRL        (RALINK_FRAME_ENGINE_BASE + CDMA_RELATED + 0x00)
4047 +#define CDMP_EG_CTRL        (RALINK_FRAME_ENGINE_BASE + CDMA_RELATED + 0x04)
4048 +#else
4049 +#define CDMA_RELATED        0x0080
4050 +#define CDMA_CSG_CFG        (RALINK_FRAME_ENGINE_BASE + CDMA_RELATED + 0x00)
4051 +#define CDMA_SCH_CFG        (RALINK_FRAME_ENGINE_BASE + CDMA_RELATED + 0x04)
4052 +#define SMACCR0                    (RALINK_ETH_SW_BASE + 0x30E4)
4053 +#define SMACCR1                    (RALINK_ETH_SW_BASE + 0x30E8)
4054 +#define CKGCR               (RALINK_ETH_SW_BASE + 0x30F0)
4055 +#endif
4056 +
4057 +#define PDMA_FC_CFG        (RALINK_FRAME_ENGINE_BASE+0x100)
4058 +
4059 +
4060 +#if defined (CONFIG_RALINK_MT7621) || defined (CONFIG_ARCH_MT7623)
4061 +/*kurtis: add QDMA define*/
4062 +
4063 +#define CLK_CFG_0              (RALINK_SYSCTL_BASE + 0x2C)
4064 +#define PAD_RGMII2_MDIO_CFG     (RALINK_SYSCTL_BASE + 0x58)
4065 +
4066 +#define QDMA_RELATED            0x1800
4067 +#define  QTX_CFG_0          (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x000)
4068 +#define  QTX_SCH_0          (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x004)
4069 +#define  QTX_HEAD_0         (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x008)
4070 +#define  QTX_TAIL_0         (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x00C)
4071 +#define  QTX_CFG_1          (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x010)
4072 +#define  QTX_SCH_1          (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x014)
4073 +#define  QTX_HEAD_1         (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x018)
4074 +#define  QTX_TAIL_1         (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x01C)
4075 +#define  QTX_CFG_2          (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x020)
4076 +#define  QTX_SCH_2          (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x024)
4077 +#define  QTX_HEAD_2         (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x028)
4078 +#define  QTX_TAIL_2         (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x02C)
4079 +#define  QTX_CFG_3          (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x030)
4080 +#define  QTX_SCH_3          (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x034)
4081 +#define  QTX_HEAD_3         (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x038)
4082 +#define  QTX_TAIL_3         (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x03C)
4083 +#define  QTX_CFG_4          (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x040)
4084 +#define  QTX_SCH_4          (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x044)
4085 +#define  QTX_HEAD_4         (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x048)
4086 +#define  QTX_TAIL_4         (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x04C)
4087 +#define  QTX_CFG_5          (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x050)
4088 +#define  QTX_SCH_5          (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x054)
4089 +#define  QTX_HEAD_5         (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x058)
4090 +#define  QTX_TAIL_5         (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x05C)
4091 +#define  QTX_CFG_6          (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x060)
4092 +#define  QTX_SCH_6          (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x064)
4093 +#define  QTX_HEAD_6         (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x068)
4094 +#define  QTX_TAIL_6         (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x06C)
4095 +#define  QTX_CFG_7          (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x070)
4096 +#define  QTX_SCH_7          (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x074)
4097 +#define  QTX_HEAD_7         (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x078)
4098 +#define  QTX_TAIL_7         (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x07C)
4099 +#define  QTX_CFG_8          (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x080)
4100 +#define  QTX_SCH_8          (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x084)
4101 +#define  QTX_HEAD_8         (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x088)
4102 +#define  QTX_TAIL_8         (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x08C)
4103 +#define  QTX_CFG_9          (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x090)
4104 +#define  QTX_SCH_9          (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x094)
4105 +#define  QTX_HEAD_9         (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x098)
4106 +#define  QTX_TAIL_9         (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x09C)
4107 +#define  QTX_CFG_10         (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x0A0)
4108 +#define  QTX_SCH_10         (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x0A4)
4109 +#define  QTX_HEAD_10        (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x0A8)
4110 +#define  QTX_TAIL_10        (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x0AC)
4111 +#define  QTX_CFG_11         (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x0B0)
4112 +#define  QTX_SCH_11         (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x0B4)
4113 +#define  QTX_HEAD_11        (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x0B8)
4114 +#define  QTX_TAIL_11        (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x0BC)
4115 +#define  QTX_CFG_12         (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x0C0)
4116 +#define  QTX_SCH_12         (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x0C4)
4117 +#define  QTX_HEAD_12        (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x0C8)
4118 +#define  QTX_TAIL_12        (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x0CC)
4119 +#define  QTX_CFG_13         (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x0D0)
4120 +#define  QTX_SCH_13         (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x0D4)
4121 +#define  QTX_HEAD_13        (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x0D8)
4122 +#define  QTX_TAIL_13        (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x0DC)
4123 +#define  QTX_CFG_14         (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x0E0)
4124 +#define  QTX_SCH_14         (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x0E4)
4125 +#define  QTX_HEAD_14        (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x0E8)
4126 +#define  QTX_TAIL_14        (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x0EC)
4127 +#define  QTX_CFG_15         (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x0F0)
4128 +#define  QTX_SCH_15         (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x0F4)
4129 +#define  QTX_HEAD_15        (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x0F8)
4130 +#define  QTX_TAIL_15        (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x0FC)
4131 +#define  QRX_BASE_PTR_0     (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x100)
4132 +#define  QRX_MAX_CNT_0      (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x104)
4133 +#define  QRX_CRX_IDX_0      (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x108)
4134 +#define  QRX_DRX_IDX_0      (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x10C)
4135 +#define  QRX_BASE_PTR_1     (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x110)
4136 +#define  QRX_MAX_CNT_1      (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x114)
4137 +#define  QRX_CRX_IDX_1      (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x118)
4138 +#define  QRX_DRX_IDX_1      (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x11C)
4139 +#if defined (CONFIG_ARCH_MT7623)
4140 +#define  VQTX_TB_BASE_0     (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x180)
4141 +#define  VQTX_TB_BASE_1     (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x184)
4142 +#define  VQTX_TB_BASE_2     (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x188)
4143 +#define  VQTX_TB_BASE_3     (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x18C)
4144 +#endif
4145 +#define  QDMA_INFO          (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x200)
4146 +#define  QDMA_GLO_CFG       (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x204)
4147 +#define  QDMA_RST_IDX       (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x208)
4148 +#define  QDMA_RST_CFG       (QDMA_RST_IDX)
4149 +#define  QDMA_DELAY_INT     (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x20C)
4150 +#define  QDMA_FC_THRES      (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x210)
4151 +#define  QDMA_TX_SCH        (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x214)
4152 +#define  QDMA_INT_STS       (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x218)
4153 +#define  QFE_INT_STATUS                  (QDMA_INT_STS)
4154 +#define  QDMA_INT_MASK      (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x21C)
4155 +#define  QFE_INT_ENABLE                  (QDMA_INT_MASK)
4156 +#define  QDMA_TRTCM         (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x220)
4157 +#define  QDMA_DATA0         (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x224)
4158 +#define  QDMA_DATA1         (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x228)
4159 +#define  QDMA_RED_THRES     (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x22C)
4160 +#define  QDMA_TEST          (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x230)
4161 +#define  QDMA_DMA           (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x234)
4162 +#define  QDMA_BMU           (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x238)
4163 +#define  QDMA_HRED1         (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x240)
4164 +#define  QDMA_HRED2         (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x244)
4165 +#define  QDMA_SRED1         (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x248)
4166 +#define  QDMA_SRED2         (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x24C)
4167 +#define  QTX_CTX_PTR        (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x300)
4168 +#define  QTX_DTX_PTR        (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x304)
4169 +#define  QTX_FWD_CNT        (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x308)
4170 +#define  QTX_CRX_PTR        (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x310)
4171 +#define  QTX_DRX_PTR        (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x314)
4172 +#define  QTX_RLS_CNT        (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x318)
4173 +#define  QDMA_FQ_HEAD       (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x320)
4174 +#define  QDMA_FQ_TAIL       (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x324)
4175 +#define  QDMA_FQ_CNT        (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x328)
4176 +#define  QDMA_FQ_BLEN       (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x32C)
4177 +#define  QTX_Q0MIN_BK       (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x350)
4178 +#define  QTX_Q1MIN_BK       (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x354)
4179 +#define  QTX_Q2MIN_BK       (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x358)
4180 +#define  QTX_Q3MIN_BK       (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x35C)
4181 +#define  QTX_Q0MAX_BK       (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x360)
4182 +#define  QTX_Q1MAX_BK       (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x364)
4183 +#define  QTX_Q2MAX_BK       (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x368)
4184 +#define  QTX_Q3MAX_BK       (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x36C)
4185 +
4186 +
4187 +#endif/*MT7621 QDMA*/
4188 +
4189 +#else
4190 +
4191 +/* 1. Frame Engine Global Registers */
4192 +#define MDIO_ACCESS            (RALINK_FRAME_ENGINE_BASE+RAFRAMEENGINE_OFFSET+0x00)
4193 +#define MDIO_CFG               (RALINK_FRAME_ENGINE_BASE+RAFRAMEENGINE_OFFSET+0x04)
4194 +#define FE_GLO_CFG             (RALINK_FRAME_ENGINE_BASE+RAFRAMEENGINE_OFFSET+0x08)
4195 +#define FE_RST_GL              (RALINK_FRAME_ENGINE_BASE+RAFRAMEENGINE_OFFSET+0x0C)
4196 +#define FE_INT_STATUS          (RALINK_FRAME_ENGINE_BASE+RAFRAMEENGINE_OFFSET+0x10)
4197 +#define FE_INT_ENABLE          (RALINK_FRAME_ENGINE_BASE+RAFRAMEENGINE_OFFSET+0x14)
4198 +#define MDIO_CFG2              (RALINK_FRAME_ENGINE_BASE+RAFRAMEENGINE_OFFSET+0x18) //Original:FC_DROP_STA
4199 +#define FOC_TS_T               (RALINK_FRAME_ENGINE_BASE+RAFRAMEENGINE_OFFSET+0x1C)
4200 +
4201 +
4202 +/* 2. GDMA Registers */
4203 +#define        GDMA1_FWD_CFG           (RALINK_FRAME_ENGINE_BASE+RAGDMA_OFFSET+0x00)
4204 +#define GDMA1_SCH_CFG          (RALINK_FRAME_ENGINE_BASE+RAGDMA_OFFSET+0x04)
4205 +#define GDMA1_SHPR_CFG         (RALINK_FRAME_ENGINE_BASE+RAGDMA_OFFSET+0x08)
4206 +#define GDMA1_MAC_ADRL         (RALINK_FRAME_ENGINE_BASE+RAGDMA_OFFSET+0x0C)
4207 +#define GDMA1_MAC_ADRH         (RALINK_FRAME_ENGINE_BASE+RAGDMA_OFFSET+0x10)
4208 +
4209 +#define        GDMA2_FWD_CFG           (RALINK_FRAME_ENGINE_BASE+RAGDMA2_OFFSET+0x00)
4210 +#define GDMA2_SCH_CFG          (RALINK_FRAME_ENGINE_BASE+RAGDMA2_OFFSET+0x04)
4211 +#define GDMA2_SHPR_CFG         (RALINK_FRAME_ENGINE_BASE+RAGDMA2_OFFSET+0x08)
4212 +#define GDMA2_MAC_ADRL         (RALINK_FRAME_ENGINE_BASE+RAGDMA2_OFFSET+0x0C)
4213 +#define GDMA2_MAC_ADRH         (RALINK_FRAME_ENGINE_BASE+RAGDMA2_OFFSET+0x10)
4214 +
4215 +/* 3. PSE */
4216 +#define PSE_FQ_CFG             (RALINK_FRAME_ENGINE_BASE+RAPSE_OFFSET+0x00)
4217 +#define CDMA_FC_CFG            (RALINK_FRAME_ENGINE_BASE+RAPSE_OFFSET+0x04)
4218 +#define GDMA1_FC_CFG           (RALINK_FRAME_ENGINE_BASE+RAPSE_OFFSET+0x08)
4219 +#define GDMA2_FC_CFG           (RALINK_FRAME_ENGINE_BASE+RAPSE_OFFSET+0x0C)
4220 +#define PDMA_FC_CFG            (RALINK_FRAME_ENGINE_BASE+0x1f0)
4221 +
4222 +/* 4. CDMA */
4223 +#define CDMA_CSG_CFG           (RALINK_FRAME_ENGINE_BASE+RACDMA_OFFSET+0x00)
4224 +#define CDMA_SCH_CFG           (RALINK_FRAME_ENGINE_BASE+RACDMA_OFFSET+0x04)
4225 +/* skip ppoe sid and vlan id definition */
4226 +
4227 +
4228 +/* 5. PDMA */
4229 +#define PDMA_GLO_CFG           (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x00)
4230 +#define PDMA_RST_CFG           (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x04)
4231 +#define PDMA_SCH_CFG           (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x08)
4232 +
4233 +#define DLY_INT_CFG            (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x0C)
4234 +
4235 +#define TX_BASE_PTR0           (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x10)
4236 +#define TX_MAX_CNT0            (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x14)
4237 +#define TX_CTX_IDX0            (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x18)
4238 +#define TX_DTX_IDX0            (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x1C)
4239 +
4240 +#define TX_BASE_PTR1           (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x20)
4241 +#define TX_MAX_CNT1            (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x24)
4242 +#define TX_CTX_IDX1            (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x28)
4243 +#define TX_DTX_IDX1            (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x2C)
4244 +
4245 +#define TX_BASE_PTR2           (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x40)
4246 +#define TX_MAX_CNT2            (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x44)
4247 +#define TX_CTX_IDX2            (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x48)
4248 +#define TX_DTX_IDX2            (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x4C)
4249 +
4250 +#define TX_BASE_PTR3           (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x50)
4251 +#define TX_MAX_CNT3            (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x54)
4252 +#define TX_CTX_IDX3            (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x58)
4253 +#define TX_DTX_IDX3            (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x5C)
4254 +
4255 +#define RX_BASE_PTR0           (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x30)
4256 +#define RX_MAX_CNT0            (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x34)
4257 +#define RX_CALC_IDX0           (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x38)
4258 +#define RX_DRX_IDX0            (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x3C)
4259 +
4260 +#define RX_BASE_PTR1           (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x40)
4261 +#define RX_MAX_CNT1            (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x44)
4262 +#define RX_CALC_IDX1           (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x48)
4263 +#define RX_DRX_IDX1            (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x4C)
4264 +
4265 +#endif
4266 +
4267 +#define DELAY_INT_INIT         0x84048404
4268 +#define FE_INT_DLY_INIT                (TX_DLY_INT | RX_DLY_INT)
4269 +
4270 +
4271 +#if !defined (CONFIG_RALINK_RT5350) && !defined (CONFIG_RALINK_MT7628)
4272 +
4273 +/* 6. Counter and Meter Table */
4274 +#define PPE_AC_BCNT0           (RALINK_FRAME_ENGINE_BASE+RACMTABLE_OFFSET+0x000) /* PPE Accounting Group 0 Byte Cnt */
4275 +#define PPE_AC_PCNT0           (RALINK_FRAME_ENGINE_BASE+RACMTABLE_OFFSET+0x004) /* PPE Accounting Group 0 Packet Cnt */
4276 +/* 0 ~ 63 */
4277 +
4278 +#define PPE_MTR_CNT0           (RALINK_FRAME_ENGINE_BASE+RACMTABLE_OFFSET+0x200) /* 0 ~ 63 */
4279 +/* skip... */
4280 +#define PPE_MTR_CNT63          (RALINK_FRAME_ENGINE_BASE+RACMTABLE_OFFSET+0x2FC)
4281 +
4282 +#define GDMA_TX_GBCNT0         (RALINK_FRAME_ENGINE_BASE+RACMTABLE_OFFSET+0x300) /* Transmit good byte cnt for GEport */
4283 +#define GDMA_TX_GPCNT0         (RALINK_FRAME_ENGINE_BASE+RACMTABLE_OFFSET+0x304) /* Transmit good pkt cnt for GEport */
4284 +#define GDMA_TX_SKIPCNT0       (RALINK_FRAME_ENGINE_BASE+RACMTABLE_OFFSET+0x308) /* Transmit skip cnt for GEport */
4285 +#define GDMA_TX_COLCNT0                (RALINK_FRAME_ENGINE_BASE+RACMTABLE_OFFSET+0x30C) /* Transmit collision cnt for GEport */
4286 +
4287 +/* update these address mapping to fit data sheet v0.26, by bobtseng, 2007.6.14 */
4288 +#define GDMA_RX_GBCNT0         (RALINK_FRAME_ENGINE_BASE+RACMTABLE_OFFSET+0x320)
4289 +#define GDMA_RX_GPCNT0         (RALINK_FRAME_ENGINE_BASE+RACMTABLE_OFFSET+0x324)
4290 +#define GDMA_RX_OERCNT0                (RALINK_FRAME_ENGINE_BASE+RACMTABLE_OFFSET+0x328)
4291 +#define GDMA_RX_FERCNT0        (RALINK_FRAME_ENGINE_BASE+RACMTABLE_OFFSET+0x32C)
4292 +#define GDMA_RX_SERCNT0                (RALINK_FRAME_ENGINE_BASE+RACMTABLE_OFFSET+0x330)
4293 +#define GDMA_RX_LERCNT0                (RALINK_FRAME_ENGINE_BASE+RACMTABLE_OFFSET+0x334)
4294 +#define GDMA_RX_CERCNT0                (RALINK_FRAME_ENGINE_BASE+RACMTABLE_OFFSET+0x338)
4295 +#define GDMA_RX_FCCNT1         (RALINK_FRAME_ENGINE_BASE+RACMTABLE_OFFSET+0x33C)
4296 +
4297 +#endif
4298 +
4299 +/* LRO global control */
4300 +/* Bits [15:0]:LRO_ALT_RFSH_TIMER, Bits [20:16]:LRO_ALT_TICK_TIMER */
4301 +#define LRO_ALT_REFRESH_TIMER   (RALINK_FRAME_ENGINE_BASE+0x001C)
4302 +
4303 +/* LRO auto-learn table info */
4304 +#define PDMA_FE_ALT_CF8                (RALINK_FRAME_ENGINE_BASE+0x0300)
4305 +#define PDMA_FE_ALT_SGL_CFC    (RALINK_FRAME_ENGINE_BASE+0x0304)
4306 +#define PDMA_FE_ALT_SEQ_CFC    (RALINK_FRAME_ENGINE_BASE+0x0308)
4307 +
4308 +/* LRO controls */
4309 +#define ADMA_LRO_CTRL_OFFSET    0x0980
4310 +/*
4311 + * Bit [0]:LRO_EN, Bit [1]:LRO_IPv6_EN, Bit [2]:MULTIPLE_NON_LRO_RX_RING_EN, Bit [3]:MULTIPLE_RXD_PREFETCH_EN,
4312 + * Bit [4]:RXD_PREFETCH_EN, Bit [5]:LRO_DLY_INT_EN, Bit [6]:LRO_CRSN_BNW, Bit [7]:L3_CKS_UPD_EN,
4313 + * Bit [20]:first_ineligible_pkt_redirect_en, Bit [21]:cr_lro_alt_score_mode, Bit [22]:cr_lro_alt_rplc_mode,
4314 + * Bit [23]:cr_lro_l4_ctrl_psh_en, Bits [28:26]:LRO_RING_RELINGUISH_REQ, Bits [31:29]:LRO_RING_RELINGUISH_DONE
4315 + */
4316 +#define ADMA_LRO_CTRL_DW0              (RALINK_FRAME_ENGINE_BASE+ADMA_LRO_CTRL_OFFSET+0x00)
4317 +/* Bits [31:0]:LRO_CPU_REASON */
4318 +#define ADMA_LRO_CTRL_DW1              (RALINK_FRAME_ENGINE_BASE+ADMA_LRO_CTRL_OFFSET+0x04)
4319 +/* Bits [31:0]:AUTO_LEARN_LRO_ELIGIBLE_THRESHOLD */
4320 +#define ADMA_LRO_CTRL_DW2              (RALINK_FRAME_ENGINE_BASE+ADMA_LRO_CTRL_OFFSET+0x08)
4321 +/*
4322 + * Bits [7:0]:LRO_MAX_AGGREGATED_CNT, Bits [11:8]:LRO_VLAN_EN, Bits [13:12]:LRO_VLAN_VID_CMP_DEPTH,
4323 + * Bit [14]:ADMA_FW_RSTN_REQ, Bit [15]:ADMA_MODE, Bits [31:16]:LRO_MIN_RXD_SDL0
4324 + */
4325 +#define ADMA_LRO_CTRL_DW3       (RALINK_FRAME_ENGINE_BASE+ADMA_LRO_CTRL_OFFSET+0x0C)
4326 +
4327 +/* LRO RX delay interrupt configurations */
4328 +#define LRO_RX1_DLY_INT        (RALINK_FRAME_ENGINE_BASE+0x0a70)
4329 +#define LRO_RX2_DLY_INT        (RALINK_FRAME_ENGINE_BASE+0x0a74)
4330 +#define LRO_RX3_DLY_INT        (RALINK_FRAME_ENGINE_BASE+0x0a78)
4331 +
4332 +/* LRO auto-learn configurations */
4333 +#define PDMA_LRO_ATL_OVERFLOW_ADJ_OFFSET    0x0990
4334 +#define PDMA_LRO_ATL_OVERFLOW_ADJ   (RALINK_FRAME_ENGINE_BASE+PDMA_LRO_ATL_OVERFLOW_ADJ_OFFSET)
4335 +#define LRO_ALT_SCORE_DELTA   (RALINK_FRAME_ENGINE_BASE+0x0a4c)
4336 +
4337 +/* LRO agg timer configurations */
4338 +#define LRO_MAX_AGG_TIME       (RALINK_FRAME_ENGINE_BASE+0x0a5c)
4339 +
4340 +/* LRO configurations of RX ring #0 */
4341 +#define LRO_RXRING0_OFFSET          0x0b00
4342 +#define LRO_RX_RING0_DIP_DW0           (RALINK_FRAME_ENGINE_BASE+LRO_RXRING0_OFFSET+0x04)
4343 +#define LRO_RX_RING0_DIP_DW1           (RALINK_FRAME_ENGINE_BASE+LRO_RXRING0_OFFSET+0x08)
4344 +#define LRO_RX_RING0_DIP_DW2           (RALINK_FRAME_ENGINE_BASE+LRO_RXRING0_OFFSET+0x0C)
4345 +#define LRO_RX_RING0_DIP_DW3           (RALINK_FRAME_ENGINE_BASE+LRO_RXRING0_OFFSET+0x10)
4346 +#define LRO_RX_RING0_CTRL_DW1          (RALINK_FRAME_ENGINE_BASE+LRO_RXRING0_OFFSET+0x28)
4347 +/* Bit [8]:RING0_VLD, Bit [9]:RING0_MYIP_VLD */
4348 +#define LRO_RX_RING0_CTRL_DW2          (RALINK_FRAME_ENGINE_BASE+LRO_RXRING0_OFFSET+0x2C)
4349 +#define LRO_RX_RING0_CTRL_DW3          (RALINK_FRAME_ENGINE_BASE+LRO_RXRING0_OFFSET+0x30)
4350 +/* LRO configurations of RX ring #1 */
4351 +#define LRO_RXRING1_OFFSET          0x0b40
4352 +#define LRO_RX_RING1_STP_DTP_DW                (RALINK_FRAME_ENGINE_BASE+LRO_RXRING1_OFFSET+0x00)
4353 +#define LRO_RX_RING1_DIP_DW0           (RALINK_FRAME_ENGINE_BASE+LRO_RXRING1_OFFSET+0x04)
4354 +#define LRO_RX_RING1_DIP_DW1           (RALINK_FRAME_ENGINE_BASE+LRO_RXRING1_OFFSET+0x08)
4355 +#define LRO_RX_RING1_DIP_DW2           (RALINK_FRAME_ENGINE_BASE+LRO_RXRING1_OFFSET+0x0C)
4356 +#define LRO_RX_RING1_DIP_DW3           (RALINK_FRAME_ENGINE_BASE+LRO_RXRING1_OFFSET+0x10)
4357 +#define LRO_RX_RING1_SIP_DW0           (RALINK_FRAME_ENGINE_BASE+LRO_RXRING1_OFFSET+0x14)
4358 +#define LRO_RX_RING1_SIP_DW1           (RALINK_FRAME_ENGINE_BASE+LRO_RXRING1_OFFSET+0x18)
4359 +#define LRO_RX_RING1_SIP_DW2           (RALINK_FRAME_ENGINE_BASE+LRO_RXRING1_OFFSET+0x1C)
4360 +#define LRO_RX_RING1_SIP_DW3           (RALINK_FRAME_ENGINE_BASE+LRO_RXRING1_OFFSET+0x20)
4361 +#define LRO_RX_RING1_CTRL_DW0          (RALINK_FRAME_ENGINE_BASE+LRO_RXRING1_OFFSET+0x24)
4362 +#define LRO_RX_RING1_CTRL_DW1          (RALINK_FRAME_ENGINE_BASE+LRO_RXRING1_OFFSET+0x28)
4363 +#define LRO_RX_RING1_CTRL_DW2          (RALINK_FRAME_ENGINE_BASE+LRO_RXRING1_OFFSET+0x2C)
4364 +#define LRO_RX_RING1_CTRL_DW3          (RALINK_FRAME_ENGINE_BASE+LRO_RXRING1_OFFSET+0x30)
4365 +#define LRO_RXRING2_OFFSET          0x0b80
4366 +#define LRO_RX_RING2_STP_DTP_DW                (RALINK_FRAME_ENGINE_BASE+LRO_RXRING2_OFFSET+0x00)
4367 +#define LRO_RX_RING2_DIP_DW0           (RALINK_FRAME_ENGINE_BASE+LRO_RXRING2_OFFSET+0x04)
4368 +#define LRO_RX_RING2_DIP_DW1           (RALINK_FRAME_ENGINE_BASE+LRO_RXRING2_OFFSET+0x08)
4369 +#define LRO_RX_RING2_DIP_DW2           (RALINK_FRAME_ENGINE_BASE+LRO_RXRING2_OFFSET+0x0C)
4370 +#define LRO_RX_RING2_DIP_DW3           (RALINK_FRAME_ENGINE_BASE+LRO_RXRING2_OFFSET+0x10)
4371 +#define LRO_RX_RING2_SIP_DW0           (RALINK_FRAME_ENGINE_BASE+LRO_RXRING2_OFFSET+0x14)
4372 +#define LRO_RX_RING2_SIP_DW1           (RALINK_FRAME_ENGINE_BASE+LRO_RXRING2_OFFSET+0x18)
4373 +#define LRO_RX_RING2_SIP_DW2           (RALINK_FRAME_ENGINE_BASE+LRO_RXRING2_OFFSET+0x1C)
4374 +#define LRO_RX_RING2_SIP_DW3           (RALINK_FRAME_ENGINE_BASE+LRO_RXRING2_OFFSET+0x20)
4375 +#define LRO_RX_RING2_CTRL_DW0          (RALINK_FRAME_ENGINE_BASE+LRO_RXRING2_OFFSET+0x24)
4376 +#define LRO_RX_RING2_CTRL_DW1          (RALINK_FRAME_ENGINE_BASE+LRO_RXRING2_OFFSET+0x28)
4377 +#define LRO_RX_RING2_CTRL_DW2          (RALINK_FRAME_ENGINE_BASE+LRO_RXRING2_OFFSET+0x2C)
4378 +#define LRO_RX_RING2_CTRL_DW3          (RALINK_FRAME_ENGINE_BASE+LRO_RXRING2_OFFSET+0x30)
4379 +#define LRO_RXRING3_OFFSET          0x0bc0
4380 +#define LRO_RX_RING3_STP_DTP_DW                (RALINK_FRAME_ENGINE_BASE+LRO_RXRING3_OFFSET+0x00)
4381 +#define LRO_RX_RING3_DIP_DW0           (RALINK_FRAME_ENGINE_BASE+LRO_RXRING3_OFFSET+0x04)
4382 +#define LRO_RX_RING3_DIP_DW1           (RALINK_FRAME_ENGINE_BASE+LRO_RXRING3_OFFSET+0x08)
4383 +#define LRO_RX_RING3_DIP_DW2           (RALINK_FRAME_ENGINE_BASE+LRO_RXRING3_OFFSET+0x0C)
4384 +#define LRO_RX_RING3_DIP_DW3           (RALINK_FRAME_ENGINE_BASE+LRO_RXRING3_OFFSET+0x10)
4385 +#define LRO_RX_RING3_SIP_DW0           (RALINK_FRAME_ENGINE_BASE+LRO_RXRING3_OFFSET+0x14)
4386 +#define LRO_RX_RING3_SIP_DW1           (RALINK_FRAME_ENGINE_BASE+LRO_RXRING3_OFFSET+0x18)
4387 +#define LRO_RX_RING3_SIP_DW2           (RALINK_FRAME_ENGINE_BASE+LRO_RXRING3_OFFSET+0x1C)
4388 +#define LRO_RX_RING3_SIP_DW3           (RALINK_FRAME_ENGINE_BASE+LRO_RXRING3_OFFSET+0x20)
4389 +#define LRO_RX_RING3_CTRL_DW0          (RALINK_FRAME_ENGINE_BASE+LRO_RXRING3_OFFSET+0x24)
4390 +#define LRO_RX_RING3_CTRL_DW1          (RALINK_FRAME_ENGINE_BASE+LRO_RXRING3_OFFSET+0x28)
4391 +#define LRO_RX_RING3_CTRL_DW2          (RALINK_FRAME_ENGINE_BASE+LRO_RXRING3_OFFSET+0x2C)
4392 +#define LRO_RX_RING3_CTRL_DW3          (RALINK_FRAME_ENGINE_BASE+LRO_RXRING3_OFFSET+0x30)
4393 +
4394 +/* LRO RX ring mode */
4395 +#define PDMA_RX_NORMAL_MODE         (0x0)
4396 +#define PDMA_RX_PSE_MODE            (0x1)
4397 +#define PDMA_RX_FORCE_PORT          (0x2)
4398 +#define PDMA_RX_AUTO_LEARN          (0x3)
4399 +
4400 +#define ADMA_RX_RING0   (0)
4401 +#define ADMA_RX_RING1   (1)
4402 +#define ADMA_RX_RING2   (2)
4403 +#define ADMA_RX_RING3   (3)
4404 +
4405 +#define ADMA_RX_LEN0_MASK   (0x3fff)
4406 +#define ADMA_RX_LEN1_MASK   (0x3)
4407 +
4408 +#define PDMA_LRO_EN             BIT(0)
4409 +#define PDMA_LRO_IPV6_EN        BIT(1)
4410 +#define PDMA_LRO_IPV4_CSUM_UPDATE_EN    BIT(7)
4411 +#define PDMA_LRO_IPV4_CTRL_PUSH_EN     BIT(23)
4412 +#define PDMA_LRO_RXD_PREFETCH_EN        BITS(3,4)
4413 +#define PDMA_NON_LRO_MULTI_EN   BIT(2)
4414 +#define PDMA_LRO_DLY_INT_EN             BIT(5)
4415 +#define PDMA_LRO_FUSH_REQ               BITS(26,28)
4416 +#define PDMA_LRO_RELINGUISH     BITS(29,31)
4417 +#define PDMA_LRO_FREQ_PRI_ADJ   BITS(16,19)
4418 +#define PDMA_LRO_TPUT_PRE_ADJ           BITS(8,11)
4419 +#define PDMA_LRO_TPUT_PRI_ADJ           BITS(12,15)
4420 +#define PDMA_LRO_ALT_SCORE_MODE         BIT(21)
4421 +#define PDMA_LRO_RING_AGE1      BITS(22,31)
4422 +#define PDMA_LRO_RING_AGE2      BITS(0,5)
4423 +#define PDMA_LRO_RING_AGG               BITS(10,25)
4424 +#define PDMA_LRO_RING_AGG_CNT1          BITS(26,31)
4425 +#define PDMA_LRO_RING_AGG_CNT2          BITS(0,1)
4426 +#define PDMA_LRO_ALT_TICK_TIMER         BITS(16,20)
4427 +#define PDMA_LRO_LRO_MIN_RXD_SDL0       BITS(16,31)
4428 +
4429 +#define PDMA_LRO_DLY_INT_EN_OFFSET          (5)
4430 +#define PDMA_LRO_TPUT_PRE_ADJ_OFFSET        (8)
4431 +#define PDMA_LRO_FREQ_PRI_ADJ_OFFSET    (16)
4432 +#define PDMA_LRO_LRO_MIN_RXD_SDL0_OFFSET    (16)
4433 +#define PDMA_LRO_TPUT_PRI_ADJ_OFFSET        (12)
4434 +#define PDMA_LRO_ALT_SCORE_MODE_OFFSET      (21)
4435 +#define PDMA_LRO_FUSH_REQ_OFFSET            (26)
4436 +#define PDMA_NON_LRO_MULTI_EN_OFFSET        (2)
4437 +#define PDMA_LRO_IPV6_EN_OFFSET             (1)
4438 +#define PDMA_LRO_RXD_PREFETCH_EN_OFFSET     (3)
4439 +#define PDMA_LRO_IPV4_CSUM_UPDATE_EN_OFFSET (7)
4440 +#define PDMA_LRO_IPV4_CTRL_PUSH_EN_OFFSET   (23)
4441 +#define PDMA_LRO_ALT_TICK_TIMER_OFFSET      (16)
4442 +
4443 +#define PDMA_LRO_TPUT_OVERFLOW_ADJ  BITS(12,31)
4444 +#define PDMA_LRO_CNT_OVERFLOW_ADJ   BITS(0,11)
4445 +
4446 +#define PDMA_LRO_TPUT_OVERFLOW_ADJ_OFFSET   (12)
4447 +#define PDMA_LRO_CNT_OVERFLOW_ADJ_OFFSET    (0)
4448 +
4449 +#define PDMA_LRO_ALT_BYTE_CNT_MODE  (0)
4450 +#define PDMA_LRO_ALT_PKT_CNT_MODE   (1)
4451 +
4452 +/* LRO_RX_RING1_CTRL_DW1 offsets  */
4453 +#define PDMA_LRO_AGE_H_OFFSET           (10)
4454 +#define PDMA_LRO_RING_AGE1_OFFSET       (22)
4455 +#define PDMA_LRO_RING_AGG_CNT1_OFFSET   (26)
4456 +/* LRO_RX_RING1_CTRL_DW2 offsets  */
4457 +#define PDMA_RX_MODE_OFFSET             (6)
4458 +#define PDMA_RX_PORT_VALID_OFFSET       (8)
4459 +#define PDMA_RX_MYIP_VALID_OFFSET       (9)
4460 +#define PDMA_LRO_RING_AGE2_OFFSET       (0)
4461 +#define PDMA_LRO_RING_AGG_OFFSET        (10)
4462 +#define PDMA_LRO_RING_AGG_CNT2_OFFSET   (0)
4463 +/* LRO_RX_RING1_CTRL_DW3 offsets  */
4464 +#define PDMA_LRO_AGG_CNT_H_OFFSET       (6)
4465 +/* LRO_RX_RING1_STP_DTP_DW offsets */
4466 +#define PDMA_RX_TCP_SRC_PORT_OFFSET     (16)
4467 +#define PDMA_RX_TCP_DEST_PORT_OFFSET    (0)
4468 +/* LRO_RX_RING1_CTRL_DW0 offsets */
4469 +#define PDMA_RX_IPV4_FORCE_OFFSET       (1)
4470 +#define PDMA_RX_IPV6_FORCE_OFFSET       (0)
4471 +
4472 +#define SET_ADMA_RX_LEN0(x)    ((x)&ADMA_RX_LEN0_MASK)
4473 +#define SET_ADMA_RX_LEN1(x)    ((x)&ADMA_RX_LEN1_MASK)
4474 +
4475 +#define SET_PDMA_LRO_MAX_AGG_CNT(x) \
4476 +    { volatile unsigned int *addr = (unsigned int*)ADMA_LRO_CTRL_DW3; \
4477 +        *addr &= ~0xff;   \
4478 +        *addr |= ((x) & 0xff);  \
4479 +    }
4480 +#define SET_PDMA_LRO_FLUSH_REQ(x) \
4481 +    { volatile unsigned int *addr = (unsigned int*)ADMA_LRO_CTRL_DW0; \
4482 +        *addr &= ~PDMA_LRO_FUSH_REQ;   \
4483 +        *addr |= ((x) & 0x7)<<PDMA_LRO_FUSH_REQ_OFFSET;  \
4484 +    }
4485 +#define SET_PDMA_LRO_IPV6_EN(x) \
4486 +    { volatile unsigned int *addr = (unsigned int*)ADMA_LRO_CTRL_DW0; \
4487 +        *addr &= ~PDMA_LRO_IPV6_EN;   \
4488 +        *addr |= ((x) & 0x1)<<PDMA_LRO_IPV6_EN_OFFSET;  \
4489 +    }
4490 +#if defined(CONFIG_RAETH_HW_LRO_PREFETCH)
4491 +#define SET_PDMA_LRO_RXD_PREFETCH_EN(x) \
4492 +    { volatile unsigned int *addr = (unsigned int*)ADMA_LRO_CTRL_DW0; \
4493 +        *addr &= ~PDMA_LRO_RXD_PREFETCH_EN;   \
4494 +        *addr |= ((x) & 0x3)<<PDMA_LRO_RXD_PREFETCH_EN_OFFSET;  \
4495 +    }
4496 +#else
4497 +#define SET_PDMA_LRO_RXD_PREFETCH_EN(x)
4498 +#endif
4499 +#define SET_PDMA_LRO_IPV4_CSUM_UPDATE_EN(x) \
4500 +    { volatile unsigned int *addr = (unsigned int*)ADMA_LRO_CTRL_DW0; \
4501 +        *addr &= ~PDMA_LRO_IPV4_CSUM_UPDATE_EN;   \
4502 +        *addr |= ((x) & 0x1)<<PDMA_LRO_IPV4_CSUM_UPDATE_EN_OFFSET;  \
4503 +    }
4504 +#define SET_PDMA_LRO_IPV4_CTRL_PUSH_EN(x) \
4505 +    { volatile unsigned int *addr = (unsigned int*)ADMA_LRO_CTRL_DW0; \
4506 +        *addr &= ~PDMA_LRO_IPV4_CTRL_PUSH_EN;   \
4507 +        *addr |= ((x) & 0x1)<<PDMA_LRO_IPV4_CTRL_PUSH_EN_OFFSET;  \
4508 +    }
4509 +#define SET_PDMA_NON_LRO_MULTI_EN(x) \
4510 +    { volatile unsigned int *addr = (unsigned int*)ADMA_LRO_CTRL_DW0; \
4511 +        *addr &= ~(PDMA_NON_LRO_MULTI_EN);   \
4512 +        *addr |= ((x) & 0x1)<<PDMA_NON_LRO_MULTI_EN_OFFSET;  \
4513 +    }
4514 +#define SET_PDMA_LRO_FREQ_PRI_ADJ(x) \
4515 +    { volatile unsigned int *addr = (unsigned int*)ADMA_LRO_CTRL_DW0; \
4516 +        *addr &= ~PDMA_LRO_FREQ_PRI_ADJ;   \
4517 +        *addr |= ((x) & 0xf)<<PDMA_LRO_FREQ_PRI_ADJ_OFFSET;  \
4518 +    }
4519 +#define SET_PDMA_LRO_TPUT_PRE_ADJ(x) \
4520 +    { volatile unsigned int *addr = (unsigned int*)ADMA_LRO_CTRL_DW0; \
4521 +        *addr &= ~PDMA_LRO_TPUT_PRE_ADJ;   \
4522 +        *addr |= ((x) & 0xf)<<PDMA_LRO_TPUT_PRE_ADJ_OFFSET;  \
4523 +    }
4524 +#define SET_PDMA_LRO_TPUT_PRI_ADJ(x) \
4525 +    { volatile unsigned int *addr = (unsigned int*)ADMA_LRO_CTRL_DW0; \
4526 +        *addr &= ~PDMA_LRO_TPUT_PRI_ADJ;   \
4527 +        *addr |= ((x) & 0xf)<<PDMA_LRO_TPUT_PRI_ADJ_OFFSET;  \
4528 +    }
4529 +#define SET_PDMA_LRO_ALT_SCORE_MODE(x) \
4530 +    { volatile unsigned int *addr = (unsigned int*)ADMA_LRO_CTRL_DW0; \
4531 +        *addr &= ~PDMA_LRO_ALT_SCORE_MODE;   \
4532 +        *addr |= ((x) & 0x1)<<PDMA_LRO_ALT_SCORE_MODE_OFFSET;  \
4533 +    }
4534 +#define SET_PDMA_LRO_DLY_INT_EN(x) \
4535 +    { volatile unsigned int *addr = (unsigned int*)ADMA_LRO_CTRL_DW0; \
4536 +        *addr &= ~PDMA_LRO_DLY_INT_EN;   \
4537 +        *addr |= ((x) & 0x1)<<PDMA_LRO_DLY_INT_EN_OFFSET;  \
4538 +    }
4539 +#define SET_PDMA_LRO_BW_THRESHOLD(x) \
4540 +    { volatile unsigned int *addr = (unsigned int*)ADMA_LRO_CTRL_DW2; \
4541 +        *addr = (x);  \
4542 +    }
4543 +#define SET_PDMA_LRO_MIN_RXD_SDL(x) \
4544 +    { volatile unsigned int *addr = (unsigned int*)ADMA_LRO_CTRL_DW3; \
4545 +        *addr &= ~PDMA_LRO_LRO_MIN_RXD_SDL0;   \
4546 +        *addr |= ((x) & 0xffff)<<PDMA_LRO_LRO_MIN_RXD_SDL0_OFFSET;  \
4547 +    }
4548 +#define SET_PDMA_LRO_TPUT_OVERFLOW_ADJ(x) \
4549 +    { volatile unsigned int *addr = (unsigned int*)PDMA_LRO_ATL_OVERFLOW_ADJ; \
4550 +        *addr &= ~PDMA_LRO_TPUT_OVERFLOW_ADJ;   \
4551 +        *addr |= ((x) & 0xfffff)<<PDMA_LRO_TPUT_OVERFLOW_ADJ_OFFSET;  \
4552 +    }
4553 +#define SET_PDMA_LRO_CNT_OVERFLOW_ADJ(x) \
4554 +    { volatile unsigned int *addr = (unsigned int*)PDMA_LRO_ATL_OVERFLOW_ADJ; \
4555 +        *addr &= ~PDMA_LRO_CNT_OVERFLOW_ADJ;   \
4556 +        *addr |= ((x) & 0xfff)<<PDMA_LRO_CNT_OVERFLOW_ADJ_OFFSET;  \
4557 +    }
4558 +#define SET_PDMA_LRO_ALT_REFRESH_TIMER_UNIT(x) \
4559 +    { volatile unsigned int *addr = (unsigned int*)LRO_ALT_REFRESH_TIMER; \
4560 +        *addr &= ~PDMA_LRO_ALT_TICK_TIMER;   \
4561 +        *addr |= ((x) & 0x1f)<<PDMA_LRO_ALT_TICK_TIMER_OFFSET;  \
4562 +    }
4563 +#define SET_PDMA_LRO_ALT_REFRESH_TIMER(x) \
4564 +    { volatile unsigned int *addr = (unsigned int*)LRO_ALT_REFRESH_TIMER; \
4565 +        *addr &= ~0xffff;   \
4566 +        *addr |= ((x) & 0xffff);  \
4567 +    }
4568 +#define SET_PDMA_LRO_MAX_AGG_TIME(x) \
4569 +    { volatile unsigned int *addr = (unsigned int*)LRO_MAX_AGG_TIME; \
4570 +        *addr &= ~0xffff;   \
4571 +        *addr |= ((x) & 0xffff);  \
4572 +    }
4573 +#define SET_PDMA_RXRING_MODE(x,y) \
4574 +    { volatile unsigned int *addr = (unsigned int*)(LRO_RX_RING0_CTRL_DW2 + ((x) << 6)); \
4575 +        *addr &= ~(0x3<<PDMA_RX_MODE_OFFSET);   \
4576 +        *addr |= (y)<<PDMA_RX_MODE_OFFSET;  \
4577 +    }
4578 +#define SET_PDMA_RXRING_MYIP_VALID(x,y) \
4579 +    { volatile unsigned int *addr = (unsigned int*)(LRO_RX_RING0_CTRL_DW2 + ((x) << 6)); \
4580 +        *addr &= ~(0x1<<PDMA_RX_MYIP_VALID_OFFSET); \
4581 +        *addr |= ((y)&0x1)<<PDMA_RX_MYIP_VALID_OFFSET;    \
4582 +    }
4583 +#define SET_PDMA_RXRING_VALID(x,y) \
4584 +    { volatile unsigned int *addr = (unsigned int*)(LRO_RX_RING0_CTRL_DW2 + ((x) << 6)); \
4585 +        *addr &= ~(0x1<<PDMA_RX_PORT_VALID_OFFSET); \
4586 +        *addr |= ((y)&0x1)<<PDMA_RX_PORT_VALID_OFFSET;    \
4587 +    }
4588 +#define SET_PDMA_RXRING_TCP_SRC_PORT(x,y) \
4589 +    { volatile unsigned int *addr = (unsigned int*)(LRO_RX_RING1_STP_DTP_DW + (((x)-1) << 6)); \
4590 +        *addr &= ~(0xffff<<PDMA_RX_TCP_SRC_PORT_OFFSET);    \
4591 +        *addr |= (y)<<PDMA_RX_TCP_SRC_PORT_OFFSET;    \
4592 +    }
4593 +#define SET_PDMA_RXRING_TCP_DEST_PORT(x,y) \
4594 +    { volatile unsigned int *addr = (unsigned int*)(LRO_RX_RING1_STP_DTP_DW + (((x)-1) << 6)); \
4595 +        *addr &= ~(0xffff<<PDMA_RX_TCP_DEST_PORT_OFFSET);    \
4596 +        *addr |= (y)<<PDMA_RX_TCP_DEST_PORT_OFFSET;    \
4597 +    }
4598 +#define SET_PDMA_RXRING_IPV4_FORCE_MODE(x,y) \
4599 +    { volatile unsigned int *addr = (unsigned int*)(LRO_RX_RING1_CTRL_DW0 + (((x)-1) << 6)); \
4600 +        *addr &= ~(0x1<<PDMA_RX_IPV4_FORCE_OFFSET);    \
4601 +        *addr |= (y)<<PDMA_RX_IPV4_FORCE_OFFSET;    \
4602 +    }
4603 +#define SET_PDMA_RXRING_IPV6_FORCE_MODE(x,y) \
4604 +    { volatile unsigned int *addr = (unsigned int*)(LRO_RX_RING1_CTRL_DW0 + (((x)-1) << 6)); \
4605 +        *addr &= ~(0x1<<PDMA_RX_IPV6_FORCE_OFFSET);    \
4606 +        *addr |= (y)<<PDMA_RX_IPV6_FORCE_OFFSET;    \
4607 +    }
4608 +#define SET_PDMA_RXRING_AGE_TIME(x,y) \
4609 +    { volatile unsigned int *addr1 = (unsigned int*)(LRO_RX_RING0_CTRL_DW1 + ((x) << 6)); \
4610 +      volatile unsigned int *addr2 = (unsigned int*)(LRO_RX_RING0_CTRL_DW2 + ((x) << 6)); \
4611 +        *addr1 &= ~PDMA_LRO_RING_AGE1;    \
4612 +        *addr2 &= ~PDMA_LRO_RING_AGE2;    \
4613 +        *addr1 |= ((y) & 0x3ff)<<PDMA_LRO_RING_AGE1_OFFSET;    \
4614 +        *addr2 |= (((y)>>PDMA_LRO_AGE_H_OFFSET) & 0x03f)<<PDMA_LRO_RING_AGE2_OFFSET;    \
4615 +    }
4616 +#define SET_PDMA_RXRING_AGG_TIME(x,y) \
4617 +    { volatile unsigned int *addr = (unsigned int*)(LRO_RX_RING0_CTRL_DW2 + ((x) << 6)); \
4618 +        *addr &= ~PDMA_LRO_RING_AGG;    \
4619 +        *addr |= ((y) & 0xffff)<<PDMA_LRO_RING_AGG_OFFSET;    \
4620 +    }
4621 +#define SET_PDMA_RXRING_MAX_AGG_CNT(x,y) \
4622 +    { volatile unsigned int *addr1 = (unsigned int*)(LRO_RX_RING1_CTRL_DW2 + (((x)-1) << 6)); \
4623 +      volatile unsigned int *addr2 = (unsigned int*)(LRO_RX_RING1_CTRL_DW3 + (((x)-1) << 6)); \
4624 +        *addr1 &= ~PDMA_LRO_RING_AGG_CNT1;    \
4625 +        *addr2 &= ~PDMA_LRO_RING_AGG_CNT2;    \
4626 +        *addr1 |= ((y) & 0x3f)<<PDMA_LRO_RING_AGG_CNT1_OFFSET;    \
4627 +        *addr2 |= (((y)>>PDMA_LRO_AGG_CNT_H_OFFSET) & 0x03)<<PDMA_LRO_RING_AGG_CNT2_OFFSET;    \
4628 +    }
4629 +
4630 +typedef struct _PDMA_LRO_AUTO_TLB_INFO0_    PDMA_LRO_AUTO_TLB_INFO0_T;
4631 +typedef struct _PDMA_LRO_AUTO_TLB_INFO1_    PDMA_LRO_AUTO_TLB_INFO1_T;
4632 +typedef struct _PDMA_LRO_AUTO_TLB_INFO2_    PDMA_LRO_AUTO_TLB_INFO2_T;
4633 +typedef struct _PDMA_LRO_AUTO_TLB_INFO3_    PDMA_LRO_AUTO_TLB_INFO3_T;
4634 +typedef struct _PDMA_LRO_AUTO_TLB_INFO4_    PDMA_LRO_AUTO_TLB_INFO4_T;
4635 +typedef struct _PDMA_LRO_AUTO_TLB_INFO5_    PDMA_LRO_AUTO_TLB_INFO5_T;
4636 +typedef struct _PDMA_LRO_AUTO_TLB_INFO6_    PDMA_LRO_AUTO_TLB_INFO6_T;
4637 +typedef struct _PDMA_LRO_AUTO_TLB_INFO7_    PDMA_LRO_AUTO_TLB_INFO7_T;
4638 +typedef struct _PDMA_LRO_AUTO_TLB_INFO8_    PDMA_LRO_AUTO_TLB_INFO8_T;
4639 +
4640 +struct _PDMA_LRO_AUTO_TLB_INFO0_
4641 +{
4642 +    unsigned int    DTP         : 16;
4643 +    unsigned int    STP         : 16;
4644 +};
4645 +struct _PDMA_LRO_AUTO_TLB_INFO1_
4646 +{
4647 +    unsigned int    SIP0        : 32;
4648 +};
4649 +struct _PDMA_LRO_AUTO_TLB_INFO2_
4650 +{
4651 +    unsigned int    SIP1        : 32;
4652 +};
4653 +struct _PDMA_LRO_AUTO_TLB_INFO3_
4654 +{
4655 +    unsigned int    SIP2        : 32;
4656 +};
4657 +struct _PDMA_LRO_AUTO_TLB_INFO4_
4658 +{
4659 +    unsigned int    SIP3        : 32;
4660 +};
4661 +struct _PDMA_LRO_AUTO_TLB_INFO5_
4662 +{
4663 +    unsigned int    VLAN_VID0   : 32;
4664 +};
4665 +struct _PDMA_LRO_AUTO_TLB_INFO6_
4666 +{
4667 +    unsigned int    VLAN_VID1       : 16;
4668 +    unsigned int    VLAN_VID_VLD    : 4;
4669 +    unsigned int    CNT             : 12;
4670 +};
4671 +struct _PDMA_LRO_AUTO_TLB_INFO7_
4672 +{
4673 +    unsigned int    DW_LEN          : 32;
4674 +};
4675 +struct _PDMA_LRO_AUTO_TLB_INFO8_
4676 +{
4677 +    unsigned int    DIP_ID          : 2;
4678 +    unsigned int    IPV6            : 1;
4679 +    unsigned int    IPV4            : 1;
4680 +    unsigned int    RESV            : 27;
4681 +    unsigned int    VALID           : 1;
4682 +};
4683 +struct PDMA_LRO_AUTO_TLB_INFO {
4684 +       PDMA_LRO_AUTO_TLB_INFO0_T auto_tlb_info0;
4685 +       PDMA_LRO_AUTO_TLB_INFO1_T auto_tlb_info1;
4686 +       PDMA_LRO_AUTO_TLB_INFO2_T auto_tlb_info2;
4687 +       PDMA_LRO_AUTO_TLB_INFO3_T auto_tlb_info3;
4688 +    PDMA_LRO_AUTO_TLB_INFO4_T auto_tlb_info4;
4689 +    PDMA_LRO_AUTO_TLB_INFO5_T auto_tlb_info5;
4690 +    PDMA_LRO_AUTO_TLB_INFO6_T auto_tlb_info6;
4691 +    PDMA_LRO_AUTO_TLB_INFO7_T auto_tlb_info7;
4692 +    PDMA_LRO_AUTO_TLB_INFO8_T auto_tlb_info8;
4693 +};
4694 +
4695 +#if defined (CONFIG_HW_SFQ)
4696 +#define VQTX_TB_BASE0 (ETHDMASYS_FRAME_ENGINE_BASE + 0x1980)
4697 +#define VQTX_TB_BASE1 (ETHDMASYS_FRAME_ENGINE_BASE + 0x1984)
4698 +#define VQTX_TB_BASE2 (ETHDMASYS_FRAME_ENGINE_BASE + 0x1988)
4699 +#define VQTX_TB_BASE3 (ETHDMASYS_FRAME_ENGINE_BASE + 0x198C)
4700 +#define SFQ_OFFSET 0x1A80
4701 +#define VQTX_GLO (ETHDMASYS_FRAME_ENGINE_BASE + SFQ_OFFSET)
4702 +#define VQTX_INVLD_PTR (ETHDMASYS_FRAME_ENGINE_BASE + SFQ_OFFSET + 0x0C)
4703 +#define VQTX_NUM (ETHDMASYS_FRAME_ENGINE_BASE + SFQ_OFFSET + 0x10)
4704 +#define VQTX_SCH (ETHDMASYS_FRAME_ENGINE_BASE + SFQ_OFFSET + 0x18)
4705 +#define VQTX_HASH_CFG (ETHDMASYS_FRAME_ENGINE_BASE + SFQ_OFFSET + 0x20)
4706 +#define VQTX_HASH_SD (ETHDMASYS_FRAME_ENGINE_BASE + SFQ_OFFSET + 0x24)
4707 +#define VQTX_VLD_CFG (ETHDMASYS_FRAME_ENGINE_BASE + SFQ_OFFSET + 0x30)
4708 +#define VQTX_MIB_IF (ETHDMASYS_FRAME_ENGINE_BASE + SFQ_OFFSET + 0x3C)
4709 +#define VQTX_MIB_PCNT (ETHDMASYS_FRAME_ENGINE_BASE + SFQ_OFFSET + 0x40)
4710 +#define VQTX_MIB_BCNT0 (ETHDMASYS_FRAME_ENGINE_BASE + SFQ_OFFSET + 0x44)
4711 +#define VQTX_MIB_BCNT1 (ETHDMASYS_FRAME_ENGINE_BASE + SFQ_OFFSET + 0x48)
4712 +
4713 +#define VQTX_MIB_EN (1<<17)
4714 +#define VQTX_NUM_0  (4<<0)
4715 +#define VQTX_NUM_1  (4<<4)
4716 +#define VQTX_NUM_2  (4<<8)
4717 +#define VQTX_NUM_3  (4<<12)
4718 +
4719 +/*=========================================
4720 +      SFQ Table Format define
4721 +=========================================*/
4722 +typedef struct _SFQ_INFO1_  SFQ_INFO1_T;
4723 +
4724 +struct _SFQ_INFO1_
4725 +{
4726 +    unsigned int    VQHPTR;
4727 +};
4728 +//-------------------------------------------------
4729 +typedef struct _SFQ_INFO2_    SFQ_INFO2_T;
4730 +
4731 +struct _SFQ_INFO2_
4732 +{
4733 +    unsigned int    VQTPTR;
4734 +};
4735 +//-------------------------------------------------
4736 +typedef struct _SFQ_INFO3_  SFQ_INFO3_T;
4737 +
4738 +struct _SFQ_INFO3_
4739 +{
4740 +    unsigned int    QUE_DEPTH:16;
4741 +    unsigned int    DEFICIT_CNT:16;
4742 +};
4743 +//-------------------------------------------------
4744 +typedef struct _SFQ_INFO4_    SFQ_INFO4_T;
4745 +
4746 +struct _SFQ_INFO4_
4747 +{
4748 +       unsigned int    RESV;
4749 +};
4750 +//-------------------------------------------------
4751 +
4752 +typedef struct _SFQ_INFO5_    SFQ_INFO5_T;
4753 +
4754 +struct _SFQ_INFO5_
4755 +{
4756 +       unsigned int    PKT_CNT;
4757 +};
4758 +//-------------------------------------------------
4759 +
4760 +typedef struct _SFQ_INFO6_    SFQ_INFO6_T;
4761 +
4762 +struct _SFQ_INFO6_
4763 +{
4764 +       unsigned int    BYTE_CNT;
4765 +};
4766 +//-------------------------------------------------
4767 +
4768 +typedef struct _SFQ_INFO7_    SFQ_INFO7_T;
4769 +
4770 +struct _SFQ_INFO7_
4771 +{
4772 +       unsigned int    BYTE_CNT;
4773 +};
4774 +//-------------------------------------------------
4775 +
4776 +typedef struct _SFQ_INFO8_    SFQ_INFO8_T;
4777 +
4778 +struct _SFQ_INFO8_
4779 +{
4780 +               unsigned int    RESV;
4781 +};
4782 +
4783 +
4784 +struct SFQ_table {
4785 +       SFQ_INFO1_T sfq_info1;
4786 +       SFQ_INFO2_T sfq_info2;
4787 +       SFQ_INFO3_T sfq_info3;
4788 +       SFQ_INFO4_T sfq_info4;
4789 +  SFQ_INFO5_T sfq_info5;
4790 +       SFQ_INFO6_T sfq_info6;
4791 +       SFQ_INFO7_T sfq_info7;
4792 +       SFQ_INFO8_T sfq_info8;
4793 +
4794 +};
4795 +#endif
4796 +#if defined (CONFIG_RAETH_HW_LRO) || defined (CONFIG_RAETH_MULTIPLE_RX_RING)
4797 +#define FE_GDM_RXID1_OFFSET        (0x0130)
4798 +#define FE_GDM_RXID1               (RALINK_FRAME_ENGINE_BASE+FE_GDM_RXID1_OFFSET)
4799 +#define GDM_VLAN_PRI7_RXID_SEL     BITS(30,31)
4800 +#define GDM_VLAN_PRI6_RXID_SEL     BITS(28,29)
4801 +#define GDM_VLAN_PRI5_RXID_SEL     BITS(26,27)
4802 +#define GDM_VLAN_PRI4_RXID_SEL     BITS(24,25)
4803 +#define GDM_VLAN_PRI3_RXID_SEL     BITS(22,23)
4804 +#define GDM_VLAN_PRI2_RXID_SEL     BITS(20,21)
4805 +#define GDM_VLAN_PRI1_RXID_SEL     BITS(18,19)
4806 +#define GDM_VLAN_PRI0_RXID_SEL     BITS(16,17)
4807 +#define GDM_TCP_ACK_RXID_SEL       BITS(4,5)
4808 +#define GDM_TCP_ACK_WZPC           BIT(3)
4809 +#define GDM_RXID_PRI_SEL           BITS(0,2)
4810 +
4811 +#define FE_GDM_RXID2_OFFSET        (0x0134)
4812 +#define FE_GDM_RXID2               (RALINK_FRAME_ENGINE_BASE+FE_GDM_RXID2_OFFSET)
4813 +#define GDM_STAG7_RXID_SEL         BITS(30,31)
4814 +#define GDM_STAG6_RXID_SEL         BITS(28,29)
4815 +#define GDM_STAG5_RXID_SEL         BITS(26,27)
4816 +#define GDM_STAG4_RXID_SEL         BITS(24,25)
4817 +#define GDM_STAG3_RXID_SEL         BITS(22,23)
4818 +#define GDM_STAG2_RXID_SEL         BITS(20,21)
4819 +#define GDM_STAG1_RXID_SEL         BITS(18,19)
4820 +#define GDM_STAG0_RXID_SEL         BITS(16,17)
4821 +#define GDM_PID2_RXID_SEL          BITS(2,3)
4822 +#define GDM_PID1_RXID_SEL          BITS(0,1)
4823 +
4824 +#define GDM_PRI_PID              (0)
4825 +#define GDM_PRI_VLAN_PID         (1)
4826 +#define GDM_PRI_ACK_PID          (2)
4827 +#define GDM_PRI_VLAN_ACK_PID     (3)
4828 +#define GDM_PRI_ACK_VLAN_PID     (4)
4829 +
4830 +#define SET_GDM_VLAN_PRI_RXID_SEL(x,y) \
4831 +    { volatile unsigned int *addr = (unsigned int *)FE_GDM_RXID1; \
4832 +        *addr &= ~(0x03 << (((x) << 1)+16));    \
4833 +        *addr |= ((y) & 0x3) << (((x) << 1)+16); \
4834 +    }
4835 +#define SET_GDM_TCP_ACK_RXID_SEL(x) \
4836 +    { volatile unsigned int *addr = (unsigned int *)FE_GDM_RXID1; \
4837 +        *addr &= ~(GDM_TCP_ACK_RXID_SEL);    \
4838 +        *addr |= ((x) & 0x3) << 4; \
4839 +    }
4840 +#define SET_GDM_TCP_ACK_WZPC(x) \
4841 +    { volatile unsigned int *addr = (unsigned int *)FE_GDM_RXID1; \
4842 +        *addr &= ~(GDM_TCP_ACK_WZPC);    \
4843 +        *addr |= ((x) & 0x1) << 3; \
4844 +    }
4845 +#define SET_GDM_RXID_PRI_SEL(x) \
4846 +    { volatile unsigned int *addr = (unsigned int *)FE_GDM_RXID1; \
4847 +        *addr &= ~(GDM_RXID_PRI_SEL);    \
4848 +        *addr |= (x) & 0x7; \
4849 +    }
4850 +#define GDM_STAG_RXID_SEL(x,y) \
4851 +    { volatile unsigned int *addr = (unsigned int *)FE_GDM_RXID2; \
4852 +        *addr &= ~(0x03 << (((x) << 1)+16));    \
4853 +        *addr |= ((y) & 0x3) << (((x) << 1)+16); \
4854 +    }
4855 +#define SET_GDM_PID2_RXID_SEL(x) \
4856 +    { volatile unsigned int *addr = (unsigned int *)FE_GDM_RXID2; \
4857 +        *addr &= ~(GDM_PID2_RXID_SEL);    \
4858 +        *addr |= ((x) & 0x3) << 2; \
4859 +    }
4860 +#define SET_GDM_PID1_RXID_SEL(x) \
4861 +    { volatile unsigned int *addr = (unsigned int *)FE_GDM_RXID2; \
4862 +        *addr &= ~(GDM_PID1_RXID_SEL);    \
4863 +        *addr |= ((x) & 0x3); \
4864 +    }
4865 +#endif  /* CONFIG_RAETH_MULTIPLE_RX_RING */
4866 +/* Per Port Packet Counts in RT3052, added by bobtseng 2009.4.17. */
4867 +#define        PORT0_PKCOUNT           (0xb01100e8)
4868 +#define        PORT1_PKCOUNT           (0xb01100ec)
4869 +#define        PORT2_PKCOUNT           (0xb01100f0)
4870 +#define        PORT3_PKCOUNT           (0xb01100f4)
4871 +#define        PORT4_PKCOUNT           (0xb01100f8)
4872 +#define        PORT5_PKCOUNT           (0xb01100fc)
4873 +
4874 +#if defined (CONFIG_ARCH_MT7623)
4875 +#include "sync_write.h"
4876 +#define sysRegRead(phys)            (*(volatile unsigned int *)((phys)))
4877 +#define sysRegWrite(phys, val)      mt65xx_reg_sync_writel((val), (phys))
4878 +#else
4879 +#define PHYS_TO_K1(physaddr) KSEG1ADDR(physaddr)
4880 +#define sysRegRead(phys)        (*(volatile unsigned int *)PHYS_TO_K1(phys))
4881 +#define sysRegWrite(phys, val)  ((*(volatile unsigned int *)PHYS_TO_K1(phys)) = (val))
4882 +#endif
4883 +
4884 +#define u_long unsigned long
4885 +#define u32    unsigned int
4886 +#define u16    unsigned short
4887 +
4888 +
4889 +/* ====================================== */
4890 +#define GDM1_DISPAD       BIT(18)
4891 +#define GDM1_DISCRC       BIT(17)
4892 +
4893 +//GDMA1 uni-cast frames destination port
4894 +#define GDM1_ICS_EN       (0x1 << 22)
4895 +#define GDM1_TCS_EN       (0x1 << 21)
4896 +#define GDM1_UCS_EN       (0x1 << 20)
4897 +#define GDM1_JMB_EN       (0x1 << 19)
4898 +#define GDM1_STRPCRC              (0x1 << 16)
4899 +#define GDM1_UFRC_P_CPU     (0 << 12)
4900 +#if defined (CONFIG_RALINK_MT7621) || defined (CONFIG_ARCH_MT7623)
4901 +#define GDM1_UFRC_P_PPE     (4 << 12)
4902 +#else
4903 +#define GDM1_UFRC_P_PPE     (6 << 12)
4904 +#endif
4905 +
4906 +//GDMA1 broad-cast MAC address frames
4907 +#define GDM1_BFRC_P_CPU     (0 << 8)
4908 +#if defined (CONFIG_RALINK_MT7621) || defined (CONFIG_ARCH_MT7623)
4909 +#define GDM1_BFRC_P_PPE     (4 << 8)
4910 +#else
4911 +#define GDM1_BFRC_P_PPE     (6 << 8)
4912 +#endif
4913 +
4914 +//GDMA1 multi-cast MAC address frames
4915 +#define GDM1_MFRC_P_CPU     (0 << 4)
4916 +#if defined (CONFIG_RALINK_MT7621) || defined (CONFIG_ARCH_MT7623)
4917 +#define GDM1_MFRC_P_PPE     (4 << 4)
4918 +#else
4919 +#define GDM1_MFRC_P_PPE     (6 << 4)
4920 +#endif
4921 +
4922 +//GDMA1 other MAC address frames destination port
4923 +#define GDM1_OFRC_P_CPU     (0 << 0)
4924 +#if defined (CONFIG_RALINK_MT7621) || defined (CONFIG_ARCH_MT7623)
4925 +#define GDM1_OFRC_P_PPE     (4 << 0)
4926 +#else
4927 +#define GDM1_OFRC_P_PPE     (6 << 0)
4928 +#endif
4929 +
4930 +#if defined (CONFIG_RALINK_RT6856) || defined (CONFIG_RALINK_MT7620) || defined (CONFIG_RALINK_MT7621) || defined (CONFIG_ARCH_MT7623)
4931 +/* checksum generator registers are removed */
4932 +#define ICS_GEN_EN          (0 << 2)
4933 +#define UCS_GEN_EN          (0 << 1)
4934 +#define TCS_GEN_EN          (0 << 0)
4935 +#else
4936 +#define ICS_GEN_EN          (1 << 2)
4937 +#define UCS_GEN_EN          (1 << 1)
4938 +#define TCS_GEN_EN          (1 << 0)
4939 +#endif
4940 +
4941 +// MDIO_CFG    bit
4942 +#define MDIO_CFG_GP1_FC_TX     (1 << 11)
4943 +#define MDIO_CFG_GP1_FC_RX     (1 << 10)
4944 +
4945 +/* ====================================== */
4946 +/* ====================================== */
4947 +#define GP1_LNK_DWN     BIT(9)
4948 +#define GP1_AN_FAIL     BIT(8)
4949 +/* ====================================== */
4950 +/* ====================================== */
4951 +#define PSE_RESET       BIT(0)
4952 +/* ====================================== */
4953 +#define PST_DRX_IDX3       BIT(19)
4954 +#define PST_DRX_IDX2       BIT(18)
4955 +#define PST_DRX_IDX1       BIT(17)
4956 +#define PST_DRX_IDX0       BIT(16)
4957 +#define PST_DTX_IDX3       BIT(3)
4958 +#define PST_DTX_IDX2       BIT(2)
4959 +#define PST_DTX_IDX1       BIT(1)
4960 +#define PST_DTX_IDX0       BIT(0)
4961 +
4962 +#define RX_2B_OFFSET     BIT(31)
4963 +#define DESC_32B_EN      BIT(8)
4964 +#define TX_WB_DDONE       BIT(6)
4965 +#define RX_DMA_BUSY       BIT(3)
4966 +#define TX_DMA_BUSY       BIT(1)
4967 +#define RX_DMA_EN         BIT(2)
4968 +#define TX_DMA_EN         BIT(0)
4969 +
4970 +#define PDMA_BT_SIZE_4DWORDS     (0<<4)
4971 +#define PDMA_BT_SIZE_8DWORDS     (1<<4)
4972 +#define PDMA_BT_SIZE_16DWORDS    (2<<4)
4973 +#define PDMA_BT_SIZE_32DWORDS    (3<<4)
4974 +
4975 +#define ADMA_RX_BT_SIZE_4DWORDS                (0<<11)
4976 +#define ADMA_RX_BT_SIZE_8DWORDS                (1<<11)
4977 +#define ADMA_RX_BT_SIZE_16DWORDS       (2<<11)
4978 +#define ADMA_RX_BT_SIZE_32DWORDS       (3<<11)
4979 +
4980 +/* Register bits.
4981 + */
4982 +
4983 +#define MACCFG_RXEN            (1<<2)
4984 +#define MACCFG_TXEN            (1<<3)
4985 +#define MACCFG_PROMISC         (1<<18)
4986 +#define MACCFG_RXMCAST         (1<<19)
4987 +#define MACCFG_FDUPLEX         (1<<20)
4988 +#define MACCFG_PORTSEL         (1<<27)
4989 +#define MACCFG_HBEATDIS                (1<<28)
4990 +
4991 +
4992 +#define DMACTL_SR              (1<<1)  /* Start/Stop Receive */
4993 +#define DMACTL_ST              (1<<13) /* Start/Stop Transmission Command */
4994 +
4995 +#define DMACFG_SWR             (1<<0)  /* Software Reset */
4996 +#define DMACFG_BURST32         (32<<8)
4997 +
4998 +#define DMASTAT_TS             0x00700000      /* Transmit Process State */
4999 +#define DMASTAT_RS             0x000e0000      /* Receive Process State */
5000 +
5001 +#define MACCFG_INIT            0 //(MACCFG_FDUPLEX) // | MACCFG_PORTSEL)
5002 +
5003 +
5004 +
5005 +/* Descriptor bits.
5006 + */
5007 +#define R_OWN          0x80000000      /* Own Bit */
5008 +#define RD_RER         0x02000000      /* Receive End Of Ring */
5009 +#define RD_LS          0x00000100      /* Last Descriptor */
5010 +#define RD_ES          0x00008000      /* Error Summary */
5011 +#define RD_CHAIN       0x01000000      /* Chained */
5012 +
5013 +/* Word 0 */
5014 +#define T_OWN          0x80000000      /* Own Bit */
5015 +#define TD_ES          0x00008000      /* Error Summary */
5016 +
5017 +/* Word 1 */
5018 +#define TD_LS          0x40000000      /* Last Segment */
5019 +#define TD_FS          0x20000000      /* First Segment */
5020 +#define TD_TER         0x08000000      /* Transmit End Of Ring */
5021 +#define TD_CHAIN       0x01000000      /* Chained */
5022 +
5023 +
5024 +#define TD_SET         0x08000000      /* Setup Packet */
5025 +
5026 +
5027 +#define POLL_DEMAND 1
5028 +
5029 +#define RSTCTL (0x34)
5030 +#define RSTCTL_RSTENET1        (1<<19)
5031 +#define RSTCTL_RSTENET2        (1<<20)
5032 +
5033 +#define INIT_VALUE_OF_RT2883_PSE_FQ_CFG                0xff908000
5034 +#define INIT_VALUE_OF_PSE_FQFC_CFG             0x80504000
5035 +#define INIT_VALUE_OF_FORCE_100_FD             0x1001BC01
5036 +#define INIT_VALUE_OF_FORCE_1000_FD            0x1F01DC01
5037 +
5038 +// Define Whole FE Reset Register
5039 +#define RSTCTRL                        (RALINK_SYSCTL_BASE + 0x34)
5040 +#define RT2880_AGPIOCFG_REG    (RALINK_SYSCTL_BASE + 0x3C)
5041 +
5042 +/*=========================================
5043 +      PDMA RX Descriptor Format define
5044 +=========================================*/
5045 +
5046 +//-------------------------------------------------
5047 +typedef struct _PDMA_RXD_INFO1_  PDMA_RXD_INFO1_T;
5048 +
5049 +struct _PDMA_RXD_INFO1_
5050 +{
5051 +    unsigned int    PDP0;
5052 +};
5053 +//-------------------------------------------------
5054 +typedef struct _PDMA_RXD_INFO2_    PDMA_RXD_INFO2_T;
5055 +
5056 +struct _PDMA_RXD_INFO2_
5057 +{
5058 +#if defined (CONFIG_ARCH_MT7623)
5059 +    unsigned int    PLEN1                 : 2;
5060 +    unsigned int    LRO_AGG_CNT           : 8;
5061 +    unsigned int    REV                   : 5;
5062 +#else
5063 +    unsigned int    PLEN1                 : 14;
5064 +    unsigned int    LS1                   : 1;
5065 +#endif  /* CONFIG_RAETH_HW_LRO */
5066 +    unsigned int    TAG                   : 1;
5067 +    unsigned int    PLEN0                 : 14;
5068 +    unsigned int    LS0                   : 1;
5069 +    unsigned int    DDONE_bit             : 1;
5070 +};
5071 +//-------------------------------------------------
5072 +typedef struct _PDMA_RXD_INFO3_  PDMA_RXD_INFO3_T;
5073 +
5074 +struct _PDMA_RXD_INFO3_
5075 +{
5076 +    unsigned int    VID:16;
5077 +    unsigned int    TPID:16;
5078 +};
5079 +//-------------------------------------------------
5080 +typedef struct _PDMA_RXD_INFO4_    PDMA_RXD_INFO4_T;
5081 +
5082 +struct _PDMA_RXD_INFO4_
5083 +{
5084 +#if defined (CONFIG_RALINK_MT7620)
5085 +    unsigned int    FOE_Entry           : 14;
5086 +    unsigned int    CRSN               : 5;
5087 +    unsigned int    SPORT              : 3;
5088 +    unsigned int    L4F                        : 1;
5089 +    unsigned int    L4VLD              : 1;
5090 +    unsigned int    TACK               : 1;
5091 +    unsigned int    IP4F               : 1;
5092 +    unsigned int    IP4                        : 1;
5093 +    unsigned int    IP6                        : 1;
5094 +    unsigned int    UN_USE1            : 4;
5095 +#elif defined (CONFIG_RALINK_MT7621) || defined (CONFIG_ARCH_MT7623)
5096 +    unsigned int    FOE_Entry           : 14;
5097 +    unsigned int    CRSN               : 5;
5098 +    unsigned int    SP                 : 4;
5099 +    unsigned int    L4F                        : 1;
5100 +    unsigned int    L4VLD              : 1;
5101 +    unsigned int    TACK               : 1;
5102 +    unsigned int    IP4F               : 1;
5103 +    unsigned int    IP4                        : 1;
5104 +    unsigned int    IP6                        : 1;
5105 +    unsigned int    UN_USE1            : 3;
5106 +#else
5107 +    unsigned int    FOE_Entry           : 14;
5108 +    unsigned int    FVLD                : 1;
5109 +    unsigned int    UN_USE1             : 1;
5110 +    unsigned int    AI                  : 8;
5111 +    unsigned int    SP                  : 3;
5112 +    unsigned int    AIS                 : 1;
5113 +    unsigned int    L4F                 : 1;
5114 +    unsigned int    IPF                  : 1;
5115 +    unsigned int    L4FVLD_bit           : 1;
5116 +    unsigned int    IPFVLD_bit           : 1;
5117 +#endif
5118 +};
5119 +
5120 +
5121 +struct PDMA_rxdesc {
5122 +       PDMA_RXD_INFO1_T rxd_info1;
5123 +       PDMA_RXD_INFO2_T rxd_info2;
5124 +       PDMA_RXD_INFO3_T rxd_info3;
5125 +       PDMA_RXD_INFO4_T rxd_info4;
5126 +#ifdef CONFIG_32B_DESC
5127 +       unsigned int     rxd_info5;
5128 +       unsigned int     rxd_info6;
5129 +       unsigned int     rxd_info7;
5130 +       unsigned int     rxd_info8;
5131 +#endif
5132 +};
5133 +
5134 +/*=========================================
5135 +      PDMA TX Descriptor Format define
5136 +=========================================*/
5137 +//-------------------------------------------------
5138 +typedef struct _PDMA_TXD_INFO1_  PDMA_TXD_INFO1_T;
5139 +
5140 +struct _PDMA_TXD_INFO1_
5141 +{
5142 +    unsigned int    SDP0;
5143 +};
5144 +//-------------------------------------------------
5145 +typedef struct _PDMA_TXD_INFO2_    PDMA_TXD_INFO2_T;
5146 +
5147 +struct _PDMA_TXD_INFO2_
5148 +{
5149 +    unsigned int    SDL1                  : 14;
5150 +    unsigned int    LS1_bit               : 1;
5151 +    unsigned int    BURST_bit             : 1;
5152 +    unsigned int    SDL0                  : 14;
5153 +    unsigned int    LS0_bit               : 1;
5154 +    unsigned int    DDONE_bit             : 1;
5155 +};
5156 +//-------------------------------------------------
5157 +typedef struct _PDMA_TXD_INFO3_  PDMA_TXD_INFO3_T;
5158 +
5159 +struct _PDMA_TXD_INFO3_
5160 +{
5161 +    unsigned int    SDP1;
5162 +};
5163 +//-------------------------------------------------
5164 +typedef struct _PDMA_TXD_INFO4_    PDMA_TXD_INFO4_T;
5165 +
5166 +struct _PDMA_TXD_INFO4_
5167 +{
5168 +#if defined (CONFIG_RALINK_MT7620)
5169 +    unsigned int    VPRI_VIDX           : 8;
5170 +    unsigned int    SIDX                : 4;
5171 +    unsigned int    INSP                : 1;
5172 +    unsigned int    RESV               : 2;
5173 +    unsigned int    UDF                : 5;
5174 +    unsigned int    FP_BMAP                    : 8;
5175 +    unsigned int    TSO                        : 1;
5176 +    unsigned int    TUI_CO             : 3;
5177 +#elif defined (CONFIG_RALINK_MT7621) || defined (CONFIG_ARCH_MT7623)
5178 +    unsigned int    VLAN_TAG           :17; // INSV(1)+VPRI(3)+CFI(1)+VID(12)
5179 +    unsigned int    RESV                : 2;
5180 +    unsigned int    UDF                 : 6;
5181 +    unsigned int    FPORT               : 3;
5182 +    unsigned int    TSO                        : 1;
5183 +    unsigned int    TUI_CO             : 3;
5184 +#else
5185 +    unsigned int    VPRI_VIDX           : 8;
5186 +    unsigned int    SIDX                : 4;
5187 +    unsigned int    INSP                : 1;
5188 +    unsigned int    RESV               : 1;
5189 +    unsigned int    UN_USE3             : 2;
5190 +    unsigned int    QN                  : 3;
5191 +    unsigned int    UN_USE2             : 1;
5192 +    unsigned int    UDF                        : 4;
5193 +    unsigned int    PN                  : 3;
5194 +    unsigned int    UN_USE1             : 1;
5195 +    unsigned int    TSO                        : 1;
5196 +    unsigned int    TUI_CO             : 3;
5197 +#endif
5198 +};
5199 +
5200 +
5201 +struct PDMA_txdesc {
5202 +       PDMA_TXD_INFO1_T txd_info1;
5203 +       PDMA_TXD_INFO2_T txd_info2;
5204 +       PDMA_TXD_INFO3_T txd_info3;
5205 +       PDMA_TXD_INFO4_T txd_info4;
5206 +#ifdef CONFIG_32B_DESC
5207 +       unsigned int     txd_info5;
5208 +       unsigned int     txd_info6;
5209 +       unsigned int     txd_info7;
5210 +       unsigned int     txd_info8;
5211 +#endif
5212 +};
5213 +
5214 +
5215 +#if defined (CONFIG_RALINK_MT7621) || defined (CONFIG_ARCH_MT7623)
5216 +/*=========================================
5217 +      QDMA TX Descriptor Format define
5218 +=========================================*/
5219 +//-------------------------------------------------
5220 +typedef struct _QDMA_TXD_INFO1_  QDMA_TXD_INFO1_T;
5221 +
5222 +struct _QDMA_TXD_INFO1_
5223 +{
5224 +    unsigned int    SDP;
5225 +};
5226 +//-------------------------------------------------
5227 +typedef struct _QDMA_TXD_INFO2_    QDMA_TXD_INFO2_T;
5228 +
5229 +struct _QDMA_TXD_INFO2_
5230 +{
5231 +    unsigned int    NDP;
5232 +};
5233 +//-------------------------------------------------
5234 +typedef struct _QDMA_TXD_INFO3_  QDMA_TXD_INFO3_T;
5235 +
5236 +struct _QDMA_TXD_INFO3_
5237 +{
5238 +    unsigned int    QID                   : 4;
5239 +#if defined (CONFIG_HW_SFQ)
5240 +    //unsigned int    VQID                  : 10;
5241 +    unsigned int    PROT                   : 3;
5242 +    unsigned int    IPOFST                   : 7;
5243 +#else
5244 +    unsigned int    RESV                  : 10;
5245 +#endif
5246 +    unsigned int    SWC_bit               : 1;
5247 +    unsigned int    BURST_bit             : 1;
5248 +    unsigned int    SDL                   : 14;
5249 +    unsigned int    LS_bit               : 1;
5250 +    unsigned int    OWN_bit             : 1;
5251 +};
5252 +//-------------------------------------------------
5253 +typedef struct _QDMA_TXD_INFO4_    QDMA_TXD_INFO4_T;
5254 +
5255 +struct _QDMA_TXD_INFO4_
5256 +{
5257 +    unsigned int    VLAN_TAG           :17; // INSV(1)+VPRI(3)+CFI(1)+VID(12)
5258 +#if defined (CONFIG_RALINK_MT7621)
5259 +    unsigned int    RESV                : 2;
5260 +    unsigned int    UDF                 : 6;
5261 +#elif defined(CONFIG_ARCH_MT7623)
5262 +         unsigned int    VQID0               : 1;
5263 +         unsigned int    RESV                : 7;
5264 +#endif
5265 +    unsigned int    FPORT               : 3;
5266 +    unsigned int    TSO                        : 1;
5267 +    unsigned int    TUI_CO             : 3;
5268 +};
5269 +
5270 +
5271 +struct QDMA_txdesc {
5272 +       QDMA_TXD_INFO1_T txd_info1;
5273 +       QDMA_TXD_INFO2_T txd_info2;
5274 +       QDMA_TXD_INFO3_T txd_info3;
5275 +       QDMA_TXD_INFO4_T txd_info4;
5276 +#ifdef CONFIG_32B_DESC
5277 +       unsigned int     txd_info5;
5278 +       unsigned int     txd_info6;
5279 +       unsigned int     txd_info7;
5280 +       unsigned int     txd_info8;
5281 +#endif
5282 +};
5283 +#endif
5284 +
5285 +#if defined (CONFIG_ARCH_MT7623)
5286 +#define phys_to_bus(a) (a)
5287 +#else
5288 +#define phys_to_bus(a) (a & 0x1FFFFFFF)
5289 +#endif
5290 +
5291 +#define PHY_Enable_Auto_Nego           0x1000
5292 +#define PHY_Restart_Auto_Nego          0x0200
5293 +
5294 +/* PHY_STAT_REG = 1; */
5295 +#define PHY_Auto_Neco_Comp     0x0020
5296 +#define PHY_Link_Status                0x0004
5297 +
5298 +/* PHY_AUTO_NEGO_REG = 4; */
5299 +#define PHY_Cap_10_Half  0x0020
5300 +#define PHY_Cap_10_Full  0x0040
5301 +#define        PHY_Cap_100_Half 0x0080
5302 +#define        PHY_Cap_100_Full 0x0100
5303 +
5304 +/* proc definition */
5305 +
5306 +#if !defined (CONFIG_RALINK_RT6855) && !defined(CONFIG_RALINK_RT6855A) && \
5307 +    !defined (CONFIG_RALINK_MT7620) && !defined (CONFIG_RALINK_MT7621) && \
5308 +    !defined (CONFIG_ARCH_MT7623)
5309 +#define CDMA_OQ_STA    (RALINK_FRAME_ENGINE_BASE+RAPSE_OFFSET+0x4c)
5310 +#define GDMA1_OQ_STA   (RALINK_FRAME_ENGINE_BASE+RAPSE_OFFSET+0x50)
5311 +#define PPE_OQ_STA     (RALINK_FRAME_ENGINE_BASE+RAPSE_OFFSET+0x54)
5312 +#define PSE_IQ_STA     (RALINK_FRAME_ENGINE_BASE+RAPSE_OFFSET+0x58)
5313 +#endif
5314 +
5315 +#define PROCREG_CONTROL_FILE      "/var/run/procreg_control"
5316 +#if defined (CONFIG_RALINK_RT2880)
5317 +#define PROCREG_DIR             "rt2880"
5318 +#elif defined (CONFIG_RALINK_RT3052)
5319 +#define PROCREG_DIR             "rt3052"
5320 +#elif defined (CONFIG_RALINK_RT3352)
5321 +#define PROCREG_DIR             "rt3352"
5322 +#elif defined (CONFIG_RALINK_RT5350)
5323 +#define PROCREG_DIR             "rt5350"
5324 +#elif defined (CONFIG_RALINK_RT2883)
5325 +#define PROCREG_DIR             "rt2883"
5326 +#elif defined (CONFIG_RALINK_RT3883)
5327 +#define PROCREG_DIR             "rt3883"
5328 +#elif defined (CONFIG_RALINK_RT6855)
5329 +#define PROCREG_DIR             "rt6855"
5330 +#elif defined (CONFIG_RALINK_MT7620)
5331 +#define PROCREG_DIR             "mt7620"
5332 +#elif defined (CONFIG_RALINK_MT7621)
5333 +#define PROCREG_DIR             "mt7621"
5334 +#elif defined (CONFIG_ARCH_MT7623)
5335 +#define PROCREG_DIR             "mt7623"
5336 +#elif defined (CONFIG_RALINK_MT7628)
5337 +#define PROCREG_DIR             "mt7628"
5338 +#elif defined (CONFIG_RALINK_RT6855A)
5339 +#define PROCREG_DIR             "rt6855a"
5340 +#else
5341 +#define PROCREG_DIR             "rt2880"
5342 +#endif
5343 +#define PROCREG_SKBFREE                "skb_free"
5344 +#define PROCREG_TXRING         "tx_ring"
5345 +#define PROCREG_RXRING         "rx_ring"
5346 +#define PROCREG_RXRING1                "rx_ring1"
5347 +#define PROCREG_RXRING2                "rx_ring2"
5348 +#define PROCREG_RXRING3                "rx_ring3"
5349 +#define PROCREG_NUM_OF_TXD     "num_of_txd"
5350 +#define PROCREG_TSO_LEN                "tso_len"
5351 +#define PROCREG_LRO_STATS      "lro_stats"
5352 +#define PROCREG_HW_LRO_STATS   "hw_lro_stats"
5353 +#define PROCREG_HW_LRO_AUTO_TLB        "hw_lro_auto_tlb"
5354 +#define PROCREG_GMAC           "gmac"
5355 +#define PROCREG_GMAC2           "gmac2"
5356 +#define PROCREG_CP0            "cp0"
5357 +#define PROCREG_RAQOS          "qos"
5358 +#define PROCREG_READ_VAL       "regread_value"
5359 +#define PROCREG_WRITE_VAL      "regwrite_value"
5360 +#define PROCREG_ADDR           "reg_addr"
5361 +#define PROCREG_CTL            "procreg_control"
5362 +#define PROCREG_RXDONE_INTR    "rxdone_intr_count"
5363 +#define PROCREG_ESW_INTR       "esw_intr_count"
5364 +#define PROCREG_ESW_CNT                "esw_cnt"
5365 +#define PROCREG_SNMP           "snmp"
5366 +#if defined (TASKLET_WORKQUEUE_SW)
5367 +#define PROCREG_SCHE           "schedule"
5368 +#endif
5369 +#define PROCREG_QDMA            "qdma"
5370 +#if defined(CONFIG_RAETH_PDMA_DVT)
5371 +#define PROCREG_PDMA_DVT               "pdma_dvt"
5372 +#endif  //#if defined(CONFIG_RAETH_PDMA_DVT)
5373 +struct rt2880_reg_op_data {
5374 +  char name[64];
5375 +  unsigned int reg_addr;
5376 +  unsigned int op;
5377 +  unsigned int reg_value;
5378 +};
5379 +
5380 +#ifdef CONFIG_RAETH_LRO
5381 +struct lro_counters {
5382 +        u32 lro_aggregated;
5383 +        u32 lro_flushed;
5384 +        u32 lro_no_desc;
5385 +};
5386 +
5387 +struct lro_para_struct {
5388 +       unsigned int lan_ip1;
5389 +};
5390 +
5391 +#endif // CONFIG_RAETH_LRO //
5392 +
5393 +
5394 +#if defined (CONFIG_HW_SFQ)
5395 +typedef struct {
5396 +       //layer2 header
5397 +       uint8_t dmac[6];
5398 +       uint8_t smac[6];
5399 +
5400 +       //vlan header
5401 +       uint16_t vlan_tag;
5402 +       uint16_t vlan1_gap;
5403 +       uint16_t vlan1;
5404 +       uint16_t vlan2_gap;
5405 +       uint16_t vlan2;
5406 +       uint16_t vlan_layer;
5407 +
5408 +       //pppoe header
5409 +       uint32_t pppoe_gap;
5410 +       uint16_t ppp_tag;
5411 +       uint16_t pppoe_sid;
5412 +
5413 +       //layer3 header
5414 +       uint16_t eth_type;
5415 +       struct iphdr iph;
5416 +       struct ipv6hdr ip6h;
5417 +
5418 +       //layer4 header
5419 +       struct tcphdr th;
5420 +       struct udphdr uh;
5421 +
5422 +       uint32_t pkt_type;
5423 +       uint8_t is_mcast;
5424 +
5425 +} ParseResult;
5426 +#endif
5427 +typedef struct end_device
5428 +{
5429 +
5430 +    unsigned int        tx_cpu_owner_idx0;
5431 +    unsigned int        rx_cpu_owner_idx0;
5432 +    unsigned int        fe_int_status;
5433 +    unsigned int        tx_full;
5434 +
5435 +#if !defined (CONFIG_RAETH_QDMA)
5436 +    unsigned int       phy_tx_ring0;
5437 +#else
5438 +    /* QDMA Tx  PTR */
5439 +    struct sk_buff *free_skb[NUM_TX_DESC];
5440 +    unsigned int tx_dma_ptr;
5441 +    unsigned int tx_cpu_ptr;
5442 +    unsigned int free_txd_num;
5443 +    unsigned int free_txd_head;
5444 +    unsigned int free_txd_tail;
5445 +    struct QDMA_txdesc *txd_pool;
5446 +    dma_addr_t phy_txd_pool;
5447 +    unsigned int txd_pool_info[NUM_TX_DESC];
5448 +    struct QDMA_txdesc *free_head;
5449 +    unsigned int phy_free_head;
5450 +    unsigned int *free_page_head;
5451 +    unsigned int phy_free_page_head;
5452 +    struct PDMA_rxdesc *qrx_ring;
5453 +    unsigned int phy_qrx_ring;
5454 +#ifdef CONFIG_RAETH_PDMATX_QDMARX      /* QDMA RX */
5455 +    unsigned int phy_tx_ring0;
5456 +#endif
5457 +#endif
5458 +
5459 +    unsigned int       phy_rx_ring0, phy_rx_ring1, phy_rx_ring2, phy_rx_ring3;
5460 +
5461 +#if defined (CONFIG_RALINK_RT3052) || defined (CONFIG_RALINK_RT3352) || \
5462 +    defined (CONFIG_RALINK_RT5350) || defined (CONFIG_RALINK_RT6855) || \
5463 +    defined(CONFIG_RALINK_RT6855A) || defined (CONFIG_RALINK_MT7620) || \
5464 +    defined(CONFIG_RALINK_MT7621) || defined (CONFIG_RALINK_MT7628)  || \
5465 +    defined (CONFIG_ARCH_MT7623)
5466 +    //send signal to user application to notify link status changed
5467 +    struct work_struct  kill_sig_wq;
5468 +#endif
5469 +
5470 +    struct work_struct  reset_task;
5471 +#ifdef WORKQUEUE_BH
5472 +    struct work_struct  rx_wq;
5473 +#else
5474 +#if defined (TASKLET_WORKQUEUE_SW)
5475 +    struct work_struct  rx_wq;
5476 +#endif
5477 +    struct              tasklet_struct     rx_tasklet;
5478 +    struct              tasklet_struct     tx_tasklet;
5479 +#endif // WORKQUEUE_BH //
5480 +
5481 +#if defined(CONFIG_RAETH_QOS)
5482 +    struct             sk_buff *          skb_free[NUM_TX_RINGS][NUM_TX_DESC];
5483 +    unsigned int       free_idx[NUM_TX_RINGS];
5484 +#else
5485 +    struct             sk_buff*           skb_free[NUM_TX_DESC];
5486 +    unsigned int       free_idx;
5487 +#endif
5488 +
5489 +    struct              net_device_stats stat;  /* The new statistics table. */
5490 +    spinlock_t          page_lock;              /* Page register locks */
5491 +    struct PDMA_txdesc *tx_ring0;
5492 +#if defined(CONFIG_RAETH_QOS)
5493 +    struct PDMA_txdesc *tx_ring1;
5494 +    struct PDMA_txdesc *tx_ring2;
5495 +    struct PDMA_txdesc *tx_ring3;
5496 +#endif
5497 +    struct PDMA_rxdesc *rx_ring0;
5498 +    struct sk_buff     *netrx0_skbuf[NUM_RX_DESC];
5499 +#if defined (CONFIG_RAETH_HW_LRO)
5500 +    struct PDMA_rxdesc *rx_ring3;
5501 +    struct sk_buff     *netrx3_skbuf[NUM_RX_DESC];
5502 +    struct PDMA_rxdesc *rx_ring2;
5503 +    struct sk_buff     *netrx2_skbuf[NUM_RX_DESC];
5504 +    struct PDMA_rxdesc *rx_ring1;
5505 +    struct sk_buff     *netrx1_skbuf[NUM_RX_DESC];
5506 +#elif defined (CONFIG_RAETH_MULTIPLE_RX_RING)
5507 +    struct PDMA_rxdesc *rx_ring1;
5508 +    struct sk_buff     *netrx1_skbuf[NUM_RX_DESC];
5509 +#if defined(CONFIG_ARCH_MT7623)
5510 +    struct PDMA_rxdesc *rx_ring2;
5511 +    struct sk_buff     *netrx2_skbuf[NUM_RX_DESC];
5512 +    struct PDMA_rxdesc *rx_ring3;
5513 +    struct sk_buff     *netrx3_skbuf[NUM_RX_DESC];
5514 +#endif  /* CONFIG_ARCH_MT7623 */
5515 +#endif
5516 +#ifdef CONFIG_RAETH_NAPI
5517 +    atomic_t irq_sem;
5518 +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,35)
5519 +    struct napi_struct napi;
5520 +#endif
5521 +#endif
5522 +#ifdef CONFIG_PSEUDO_SUPPORT
5523 +    struct net_device *PseudoDev;
5524 +    unsigned int isPseudo;
5525 +#endif
5526 +#if defined (CONFIG_ETHTOOL) /*&& defined (CONFIG_RAETH_ROUTER)*/
5527 +       struct mii_if_info      mii_info;
5528 +#endif
5529 +#ifdef CONFIG_RAETH_LRO
5530 +    struct lro_counters lro_counters;
5531 +    struct net_lro_mgr lro_mgr;
5532 +    struct net_lro_desc lro_arr[8];
5533 +#endif
5534 +#ifdef CONFIG_RAETH_HW_VLAN_RX
5535 +    struct vlan_group *vlgrp;
5536 +#endif
5537 +#if defined (CONFIG_RAETH_HW_LRO)
5538 +    struct work_struct hw_lro_wq;
5539 +    unsigned int hw_lro_pkt_interval[3];
5540 +    unsigned int hw_lro_alpha;  /* 0 < packet interval alpha <= 10 */
5541 +    unsigned int hw_lro_fix_setting;  /* 0: dynamical AGG/AGE time, 1: fixed AGG/AGE time */
5542 +#endif  /* CONFIG_RAETH_HW_LRO */
5543 +} END_DEVICE, *pEND_DEVICE;
5544 +
5545 +
5546 +#define RAETH_VERSION  "v3.1"
5547 +
5548 +#endif
5549 +
5550 +#define DMA_GLO_CFG PDMA_GLO_CFG
5551 +
5552 +#if defined(CONFIG_RAETH_QDMATX_QDMARX)
5553 +#define GDMA1_FWD_PORT 0x5555
5554 +#define GDMA2_FWD_PORT 0x5555
5555 +#elif defined(CONFIG_RAETH_PDMATX_QDMARX)
5556 +#define GDMA1_FWD_PORT 0x5555
5557 +#define GDMA2_FWD_PORT 0x5555
5558 +#else
5559 +#define GDMA1_FWD_PORT 0x0000
5560 +#define GDMA2_FWD_PORT 0x0000
5561 +#endif
5562 +
5563 +#if defined(CONFIG_RAETH_QDMATX_QDMARX)
5564 +#define RAETH_RX_CALC_IDX0 QRX_CRX_IDX_0
5565 +#define RAETH_RX_CALC_IDX1 QRX_CRX_IDX_1
5566 +#elif defined(CONFIG_RAETH_PDMATX_QDMARX)
5567 +#define RAETH_RX_CALC_IDX0 QRX_CRX_IDX_0
5568 +#define RAETH_RX_CALC_IDX1 QRX_CRX_IDX_1
5569 +#else
5570 +#define RAETH_RX_CALC_IDX0 RX_CALC_IDX0
5571 +#define RAETH_RX_CALC_IDX1 RX_CALC_IDX1
5572 +#endif
5573 +#define RAETH_RX_CALC_IDX2 RX_CALC_IDX2
5574 +#define RAETH_RX_CALC_IDX3 RX_CALC_IDX3
5575 +#define RAETH_FE_INT_STATUS FE_INT_STATUS
5576 +#define RAETH_FE_INT_ALL FE_INT_ALL
5577 +#define RAETH_FE_INT_ENABLE FE_INT_ENABLE
5578 +#define RAETH_FE_INT_DLY_INIT FE_INT_DLY_INIT
5579 +#define RAETH_FE_INT_SETTING RX_DONE_INT0 | RX_DONE_INT1 | TX_DONE_INT0 | TX_DONE_INT1 | TX_DONE_INT2 | TX_DONE_INT3
5580 +#define QFE_INT_SETTING RX_DONE_INT0 | RX_DONE_INT1 | TX_DONE_INT0 | TX_DONE_INT1 | TX_DONE_INT2 | TX_DONE_INT3
5581 +#define RAETH_TX_DLY_INT TX_DLY_INT
5582 +#define RAETH_TX_DONE_INT0 TX_DONE_INT0
5583 +#define RAETH_DLY_INT_CFG DLY_INT_CFG
5584 diff --git a/drivers/net/ethernet/raeth/ra_ethtool.c b/drivers/net/ethernet/raeth/ra_ethtool.c
5585 new file mode 100644
5586 index 0000000..ff13e59
5587 --- /dev/null
5588 +++ b/drivers/net/ethernet/raeth/ra_ethtool.c
5589 @@ -0,0 +1,515 @@
5590 +#include <linux/module.h>
5591 +#include <linux/version.h>
5592 +
5593 +#include <linux/kernel.h>
5594 +#include <linux/sched.h>
5595 +
5596 +#include <linux/netdevice.h>
5597 +#include <linux/etherdevice.h>
5598 +#include <linux/skbuff.h>
5599 +#include <linux/if_ether.h>
5600 +#include <linux/ethtool.h>
5601 +
5602 +#include "ra2882ethreg.h"
5603 +#include "raether.h"
5604 +#include "ra_mac.h"
5605 +#include "ra_ethtool.h"
5606 +
5607 +#define RAETHER_DRIVER_NAME            "raether"
5608 +#define RA_NUM_STATS                   4
5609 +
5610 +
5611 +static struct {
5612 +    const char str[ETH_GSTRING_LEN];
5613 +} ethtool_stats_keys[] = {
5614 +    { "statistic1" },
5615 +    { "statistic2" },
5616 +    { "statistic3" },
5617 +    { "statistic4" },
5618 +};
5619 +
5620 +unsigned char get_current_phy_address(void)
5621 +{
5622 +       struct net_device *cur_dev_p;
5623 +       END_DEVICE *ei_local;
5624 +#if 0
5625 +       for(cur_dev_p=dev_base; cur_dev_p!=NULL; cur_dev_p=cur_dev_p->next){
5626 +               if (strncmp(cur_dev_p->name, DEV_NAME /* "eth2" usually */, 4) == 0)
5627 +                       break;
5628 +       }
5629 +#else
5630 +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,35)
5631 +       cur_dev_p = dev_get_by_name(&init_net, DEV_NAME);
5632 +#else
5633 +       cur_dev_p = dev_get_by_name(DEV_NAME);
5634 +#endif
5635 +#endif
5636 +       if(!cur_dev_p)
5637 +               return 0;
5638 +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,35)
5639 +       ei_local = netdev_priv(cur_dev_p);
5640 +#else
5641 +       ei_local = cur_dev_p->priv;
5642 +#endif
5643 +       return ei_local->mii_info.phy_id;
5644 +}
5645 +#if 0
5646 +static u32 et_get_tx_csum(struct net_device *dev)
5647 +{
5648 +       return (sysRegRead(GDMA1_FWD_CFG) & GDM1_DISCRC) ? 0 : 1;       // a pitfall here, "0" means to enable.
5649 +}
5650 +
5651 +static u32 et_get_rx_csum(struct net_device *dev)
5652 +{
5653 +       return (sysRegRead(GDMA1_FWD_CFG) & GDM1_STRPCRC) ? 1 : 0;
5654 +}
5655 +
5656 +static int et_set_tx_csum(struct net_device *dev, u32 data)
5657 +{
5658 +       int value;
5659 +       //printk("et_set_tx_csum(): data = %d\n", data);
5660 +
5661 +       value = sysRegRead(GDMA1_FWD_CFG);
5662 +       if(data)
5663 +               value |= GDM1_DISCRC;
5664 +       else
5665 +               value &= ~GDM1_DISCRC;
5666 +
5667 +       sysRegWrite(GDMA1_FWD_CFG, value);
5668 +    return 0;
5669 +}
5670 +
5671 +static int et_set_rx_csum(struct net_device *dev, u32 data)
5672 +{
5673 +       int value;
5674 +       //printk("et_set_rx_csum(): data = %d\n", data);
5675 +
5676 +       value = sysRegRead(GDMA1_FWD_CFG);
5677 +       if(data)
5678 +               value |= GDM1_STRPCRC;
5679 +       else
5680 +               value &= ~GDM1_STRPCRC;
5681 +
5682 +       sysRegWrite(GDMA1_FWD_CFG, value);
5683 +    return 0;
5684 +}
5685 +#endif
5686 +
5687 +#define MII_CR_ADDR                    0x00
5688 +#define MII_CR_MR_AUTONEG_ENABLE       (1 << 12)
5689 +#define MII_CR_MR_RESTART_NEGOTIATION  (1 << 9)
5690 +
5691 +#define AUTO_NEGOTIATION_ADVERTISEMENT 0x04
5692 +#define AN_PAUSE                       (1 << 10)
5693 +
5694 +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,35)
5695 +static void et_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
5696 +{
5697 +       int mii_an_reg;
5698 +       int mdio_cfg_reg;
5699 +       END_DEVICE *ei_local = dev->priv;
5700 +
5701 +       // get mii auto-negotiation register
5702 +       mii_mgr_read(ei_local->mii_info.phy_id, AUTO_NEGOTIATION_ADVERTISEMENT, &mii_an_reg);
5703 +       epause->autoneg = (mii_an_reg & AN_PAUSE) ? 1 : 0; //get autonet_enable flag bit
5704 +
5705 +       mdio_cfg_reg = sysRegRead(MDIO_CFG);
5706 +       epause->tx_pause = (mdio_cfg_reg & MDIO_CFG_GP1_FC_TX) ? 1 : 0;
5707 +       epause->rx_pause = (mdio_cfg_reg & MDIO_CFG_GP1_FC_RX) ? 1 : 0;
5708 +
5709 +       //printk("et_get_pauseparam(): autoneg=%d, tx_pause=%d, rx_pause=%d\n", epause->autoneg, epause->tx_pause, epause->rx_pause);
5710 +}
5711 +
5712 +static int et_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
5713 +{
5714 +       int mdio_cfg_reg;
5715 +       int mii_an_reg;
5716 +       END_DEVICE *ei_local = dev->priv;
5717 +
5718 +       //printk("et_set_pauseparam(): autoneg=%d, tx_pause=%d, rx_pause=%d\n", epause->autoneg, epause->tx_pause, epause->rx_pause);
5719 +
5720 +       // auto-neg pause
5721 +       mii_mgr_read(ei_local->mii_info.phy_id, AUTO_NEGOTIATION_ADVERTISEMENT, &mii_an_reg);
5722 +       if(epause->autoneg)
5723 +               mii_an_reg |= AN_PAUSE;
5724 +       else
5725 +               mii_an_reg &= ~AN_PAUSE;
5726 +       mii_mgr_write(ei_local->mii_info.phy_id, AUTO_NEGOTIATION_ADVERTISEMENT, mii_an_reg);
5727 +
5728 +       // tx/rx pause
5729 +       mdio_cfg_reg = sysRegRead(MDIO_CFG);
5730 +       if(epause->tx_pause)
5731 +               mdio_cfg_reg |= MDIO_CFG_GP1_FC_TX;
5732 +       else
5733 +               mdio_cfg_reg &= ~MDIO_CFG_GP1_FC_TX;
5734 +       if(epause->rx_pause)
5735 +               mdio_cfg_reg |= MDIO_CFG_GP1_FC_RX;
5736 +       else
5737 +               mdio_cfg_reg &= ~MDIO_CFG_GP1_FC_RX;
5738 +       sysRegWrite(MDIO_CFG, mdio_cfg_reg);
5739 +
5740 +       return 0;
5741 +}
5742 +
5743 +static int et_nway_reset(struct net_device *dev)
5744 +{
5745 +       END_DEVICE *ei_local = dev->priv;
5746 +       return mii_nway_restart(&ei_local->mii_info);
5747 +}
5748 +#endif
5749 +
5750 +static u32 et_get_link(struct net_device *dev)
5751 +{
5752 +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,35)
5753 +        END_DEVICE *ei_local = netdev_priv(dev);
5754 +#else
5755 +       END_DEVICE *ei_local = dev->priv;
5756 +#endif
5757 +       return mii_link_ok(&ei_local->mii_info);
5758 +}
5759 +
5760 +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,35)
5761 +static int et_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
5762 +{
5763 +       END_DEVICE *ei_local = dev->priv;
5764 +       int rc;
5765 +       rc = mii_ethtool_sset(&ei_local->mii_info, cmd);
5766 +       return rc;
5767 +}
5768 +#endif
5769 +
5770 +static int et_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
5771 +{
5772 +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,35)
5773 +        END_DEVICE *ei_local = netdev_priv(dev);
5774 +#else
5775 +        END_DEVICE *ei_local = dev->priv;
5776 +#endif
5777 +       mii_ethtool_gset(&ei_local->mii_info, cmd);
5778 +       return 0;
5779 +}
5780 +
5781 +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,35)
5782 +static u32 et_get_msglevel(struct net_device *dev)
5783 +{
5784 +       return 0;
5785 +}
5786 +
5787 +static void et_set_msglevel(struct net_device *dev, u32 datum)
5788 +{
5789 +       return;
5790 +}
5791 +
5792 +static void et_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
5793 +{
5794 +       //END_DEVICE *ei_local = dev->priv;
5795 +       strcpy(info->driver, RAETHER_DRIVER_NAME);
5796 +       strcpy(info->version, RAETH_VERSION);
5797 +       strcpy(info->bus_info, "n/a");
5798 +       info->n_stats = RA_NUM_STATS;
5799 +       info->eedump_len = 0;
5800 +       info->regdump_len = 0;
5801 +}
5802 +
5803 +static int et_get_stats_count(struct net_device *dev)
5804 +{
5805 +       return RA_NUM_STATS;
5806 +}
5807 +
5808 +static void et_get_ethtool_stats(struct net_device *dev, struct ethtool_stats *stats, u64 *data)
5809 +{
5810 +//     END_DEVICE *ei_local = dev->priv;
5811 +       data[0] = 0;//np->xstats.early_rx;
5812 +       data[1] = 0;//np->xstats.tx_buf_mapped;
5813 +       data[2] = 0;//np->xstats.tx_timeouts;
5814 +       data[3] = 0;//np->xstats.rx_lost_in_ring;
5815 +}
5816 +
5817 +static void et_get_strings(struct net_device *dev, u32 stringset, u8 *data)
5818 +{
5819 +       memcpy(data, ethtool_stats_keys, sizeof(ethtool_stats_keys));
5820 +}
5821 +#endif
5822 +
5823 +/*
5824 + *     mii_mgr_read wrapper for mii.o ethtool
5825 + */
5826 +int mdio_read(struct net_device *dev, int phy_id, int location)
5827 +{
5828 +       unsigned int result;
5829 +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,35)
5830 +        END_DEVICE *ei_local = netdev_priv(dev);
5831 +#else
5832 +        END_DEVICE *ei_local = dev->priv;
5833 +#endif
5834 +       mii_mgr_read( (unsigned int) ei_local->mii_info.phy_id, (unsigned int)location, &result);
5835 +       //printk("\n%s mii.o query= phy_id:%d, address:%d retval:%x\n", dev->name, phy_id, location, result);
5836 +       return (int)result;
5837 +}
5838 +
5839 +/*
5840 + *     mii_mgr_write wrapper for mii.o ethtool
5841 + */
5842 +void mdio_write(struct net_device *dev, int phy_id, int location, int value)
5843 +{
5844 +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,35)
5845 +               END_DEVICE *ei_local = netdev_priv(dev);
5846 +#else
5847 +               END_DEVICE *ei_local = dev->priv;
5848 +#endif
5849 +       //printk("mii.o write= phy_id:%d, address:%d value:%x\n", phy_id, location, value);
5850 +       mii_mgr_write( (unsigned int) ei_local->mii_info.phy_id, (unsigned int)location, (unsigned int)value);
5851 +       return;
5852 +}
5853 +
5854 +struct ethtool_ops ra_ethtool_ops = {
5855 +
5856 +       .get_settings           = et_get_settings,
5857 +        .get_link               = et_get_link,
5858 +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,35)
5859 +       .get_drvinfo            = et_get_drvinfo,
5860 +       .set_settings           = et_set_settings,
5861 +       .get_pauseparam         = et_get_pauseparam,
5862 +       .set_pauseparam         = et_set_pauseparam,
5863 +//     .get_rx_csum            = et_get_rx_csum,
5864 +//     .set_rx_csum            = et_set_rx_csum,
5865 +//     .get_tx_csum            = et_get_tx_csum,
5866 +//     .set_tx_csum            = et_set_tx_csum,
5867 +       .nway_reset             = et_nway_reset,
5868 +       .get_msglevel           = et_get_msglevel,
5869 +       .set_msglevel           = et_set_msglevel,
5870 +       .get_strings            = et_get_strings,
5871 +       .get_stats_count        = et_get_stats_count,
5872 +       .get_ethtool_stats      = et_get_ethtool_stats,
5873 +/*     .get_regs_len           = et_get_regs_len,
5874 +       .get_regs               = et_get_regs,
5875 +*/
5876 +#endif
5877 +};
5878 +
5879 +#ifdef CONFIG_PSEUDO_SUPPORT
5880 +/*
5881 + * We unable to re-use the Raether functions because it is hard to tell
5882 + * where the calling from is. From eth2 or eth3?
5883 + *
5884 + * These code size is around 950 bytes.
5885 + */
5886 +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,35)
5887 +static void et_virt_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
5888 +{
5889 +       // PSEUDO_ADAPTER *pseudo = dev->priv;
5890 +       return et_get_drvinfo(dev, info);
5891 +}
5892 +
5893 +static void et_virt_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
5894 +{
5895 +       int mii_an_reg, mdio_cfg_reg;
5896 +       PSEUDO_ADAPTER *pseudo = dev->priv;
5897 +
5898 +       // get mii auto-negotiation register
5899 +       mii_mgr_read(pseudo->mii_info.phy_id, AUTO_NEGOTIATION_ADVERTISEMENT, &mii_an_reg);
5900 +       epause->autoneg = (mii_an_reg & AN_PAUSE) ? 1 : 0; //get autonet_enable flag bit
5901 +
5902 +       mdio_cfg_reg = sysRegRead(MDIO_CFG);
5903 +       epause->tx_pause = (mdio_cfg_reg & MDIO_CFG_GP1_FC_TX) ? 1 : 0;
5904 +       epause->rx_pause = (mdio_cfg_reg & MDIO_CFG_GP1_FC_RX) ? 1 : 0;
5905 +
5906 +       //printk("et_get_pauseparam(): autoneg=%d, tx_pause=%d, rx_pause=%d\n", epause->autoneg, epause->tx_pause, epause->rx_pause);
5907 +}
5908 +
5909 +static int et_virt_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
5910 +{
5911 +       int mdio_cfg_reg;
5912 +       int mii_an_reg;
5913 +       PSEUDO_ADAPTER *pseudo = dev->priv;
5914 +
5915 +       //printk("et_set_pauseparam(): autoneg=%d, tx_pause=%d, rx_pause=%d\n", epause->autoneg, epause->tx_pause, epause->rx_pause);
5916 +       // auto-neg pause
5917 +       mii_mgr_read(pseudo->mii_info.phy_id, AUTO_NEGOTIATION_ADVERTISEMENT, &mii_an_reg);
5918 +       if(epause->autoneg)
5919 +               mii_an_reg |= AN_PAUSE;
5920 +       else
5921 +               mii_an_reg &= ~AN_PAUSE;
5922 +       mii_mgr_write(pseudo->mii_info.phy_id, AUTO_NEGOTIATION_ADVERTISEMENT, mii_an_reg);
5923 +
5924 +       // tx/rx pause
5925 +       mdio_cfg_reg = sysRegRead(MDIO_CFG);
5926 +       if(epause->tx_pause)
5927 +               mdio_cfg_reg |= MDIO_CFG_GP1_FC_TX;
5928 +       else
5929 +               mdio_cfg_reg &= ~MDIO_CFG_GP1_FC_TX;
5930 +       if(epause->rx_pause)
5931 +               mdio_cfg_reg |= MDIO_CFG_GP1_FC_RX;
5932 +       else
5933 +               mdio_cfg_reg &= ~MDIO_CFG_GP1_FC_RX;
5934 +       sysRegWrite(MDIO_CFG, mdio_cfg_reg);
5935 +
5936 +       return 0;
5937 +}
5938 +
5939 +static u32 et_virt_get_tx_csum(struct net_device *dev)
5940 +{
5941 +       return (sysRegRead(GDMA2_FWD_CFG) & GDM1_DISCRC) ? 0 : 1;       // a pitfall here, "0" means to enable.
5942 +}
5943 +
5944 +static u32 et_virt_get_rx_csum(struct net_device *dev)
5945 +{
5946 +       return (sysRegRead(GDMA2_FWD_CFG) & GDM1_STRPCRC) ? 1 : 0;
5947 +}
5948 +
5949 +static int et_virt_set_tx_csum(struct net_device *dev, u32 data)
5950 +{
5951 +       int value;
5952 +       //printk("et_set_tx_csum(): data = %d\n", data);
5953 +       value = sysRegRead(GDMA2_FWD_CFG);
5954 +       if(data)
5955 +               value |= GDM1_DISCRC;
5956 +       else
5957 +               value &= ~GDM1_DISCRC;
5958 +       sysRegWrite(GDMA1_FWD_CFG, value);
5959 +       return 0;
5960 +}
5961 +
5962 +static int et_virt_set_rx_csum(struct net_device *dev, u32 data)
5963 +{
5964 +       int value;
5965 +       //printk("et_set_rx_csum(): data = %d\n", data);
5966 +       value = sysRegRead(GDMA2_FWD_CFG);
5967 +       if(data)
5968 +               value |= GDM1_STRPCRC;
5969 +       else
5970 +               value &= ~GDM1_STRPCRC;
5971 +       sysRegWrite(GDMA1_FWD_CFG, value);
5972 +       return 0;
5973 +}
5974 +
5975 +static int et_virt_nway_reset(struct net_device *dev)
5976 +{
5977 +       PSEUDO_ADAPTER *pseudo  = dev->priv;
5978 +       return mii_nway_restart(&pseudo->mii_info);
5979 +}
5980 +#endif
5981 +
5982 +static u32 et_virt_get_link(struct net_device *dev)
5983 +{
5984 +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,35)
5985 +        PSEUDO_ADAPTER *pseudo  = netdev_priv(dev);
5986 +#else
5987 +        PSEUDO_ADAPTER *pseudo  = dev->priv;
5988 +#endif
5989 +       return mii_link_ok(&pseudo->mii_info);
5990 +}
5991 +
5992 +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,35)
5993 +static int et_virt_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
5994 +{
5995 +       PSEUDO_ADAPTER *pseudo = dev->priv;
5996 +       int rc = mii_ethtool_sset(&pseudo->mii_info, cmd);
5997 +       return rc;
5998 +}
5999 +#endif
6000 +
6001 +static int et_virt_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
6002 +{
6003 +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,35)
6004 +        PSEUDO_ADAPTER *pseudo  = netdev_priv(dev);
6005 +#else
6006 +        PSEUDO_ADAPTER *pseudo  = dev->priv;
6007 +#endif
6008 +       mii_ethtool_gset(&pseudo->mii_info, cmd);
6009 +       return 0;
6010 +}
6011 +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,35)
6012 +static u32 et_virt_get_msglevel(struct net_device *dev)
6013 +{
6014 +       return 0;
6015 +}
6016 +
6017 +static void et_virt_set_msglevel(struct net_device *dev, u32 datum)
6018 +{
6019 +       return;
6020 +}
6021 +
6022 +static void et_virt_get_ethtool_stats(struct net_device *dev, struct ethtool_stats *stats, u64 *data)
6023 +{
6024 +//     PSEUDO_ADAPTER *pseudo = dev->priv;
6025 +       data[0] = 0;//np->xstats.early_rx;
6026 +       data[1] = 0;//np->xstats.tx_buf_mapped;
6027 +       data[2] = 0;//np->xstats.tx_timeouts;
6028 +       data[3] = 0;//np->xstats.rx_lost_in_ring;
6029 +}
6030 +
6031 +/* for virtual interface dedicated */
6032 +#define RA_VIRT_NUM_STATS                      4
6033 +static struct {
6034 +    const char str[ETH_GSTRING_LEN];
6035 +} ethtool_stats_keys_2[] = {
6036 +    { "statistic1" },
6037 +    { "statistic2" },
6038 +    { "statistic3" },
6039 +    { "statistic4" },
6040 +};
6041 +
6042 +static int et_virt_get_stats_count(struct net_device *dev)
6043 +{
6044 +       return RA_VIRT_NUM_STATS;
6045 +}
6046 +
6047 +static void et_virt_get_strings(struct net_device *dev, u32 stringset, u8 *data)
6048 +{
6049 +       memcpy(data, ethtool_stats_keys_2, sizeof(ethtool_stats_keys_2));
6050 +}
6051 +#endif
6052 +
6053 +struct ethtool_ops ra_virt_ethtool_ops = {
6054 +       .get_settings           = et_virt_get_settings,
6055 +       .get_link               = et_virt_get_link,
6056 +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,35)
6057 +       .get_drvinfo            = et_virt_get_drvinfo,
6058 +       .set_settings           = et_virt_set_settings,
6059 +       .get_pauseparam         = et_virt_get_pauseparam,
6060 +       .set_pauseparam         = et_virt_set_pauseparam,
6061 +       .get_rx_csum            = et_virt_get_rx_csum,
6062 +       .set_rx_csum            = et_virt_set_rx_csum,
6063 +       .get_tx_csum            = et_virt_get_tx_csum,
6064 +       .set_tx_csum            = et_virt_set_tx_csum,
6065 +       .nway_reset             = et_virt_nway_reset,
6066 +       .get_msglevel           = et_virt_get_msglevel,
6067 +       .set_msglevel           = et_virt_set_msglevel,
6068 +       .get_strings            = et_virt_get_strings,
6069 +       .get_stats_count        = et_virt_get_stats_count,
6070 +       .get_ethtool_stats      = et_virt_get_ethtool_stats,
6071 +/*     .get_regs_len           = et_virt_get_regs_len,
6072 +       .get_regs               = et_virt_get_regs,
6073 +*/
6074 +#endif
6075 +};
6076 +
6077 +int mdio_virt_read(struct net_device *dev, int phy_id, int location)
6078 +{
6079 +       unsigned int result;
6080 +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,35)
6081 +        PSEUDO_ADAPTER *pseudo  = netdev_priv(dev);
6082 +#else
6083 +        PSEUDO_ADAPTER *pseudo  = dev->priv;
6084 +#endif
6085 +       mii_mgr_read( (unsigned int) pseudo->mii_info.phy_id, (unsigned int)location, &result);
6086 +//     printk("%s mii.o query= phy_id:%d, address:%d retval:%d\n", dev->name, phy_id, location, result);
6087 +       return (int)result;
6088 +}
6089 +
6090 +void mdio_virt_write(struct net_device *dev, int phy_id, int location, int value)
6091 +{
6092 +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,35)
6093 +        PSEUDO_ADAPTER *pseudo  = netdev_priv(dev);
6094 +#else
6095 +        PSEUDO_ADAPTER *pseudo  = dev->priv;
6096 +#endif
6097 +//     printk("mii.o write= phy_id:%d, address:%d value:%d\n", phy_id, location, value);
6098 +       mii_mgr_write( (unsigned int) pseudo->mii_info.phy_id, (unsigned int)location, (unsigned int)value);
6099 +       return;
6100 +}
6101 +
6102 +#endif /* CONFIG_PSEUDO_SUPPORT */
6103 +
6104 +
6105 diff --git a/drivers/net/ethernet/raeth/ra_ethtool.h b/drivers/net/ethernet/raeth/ra_ethtool.h
6106 new file mode 100644
6107 index 0000000..d64a1ab
6108 --- /dev/null
6109 +++ b/drivers/net/ethernet/raeth/ra_ethtool.h
6110 @@ -0,0 +1,13 @@
6111 +#ifndef RA_ETHTOOL_H
6112 +#define RA_ETHTOOL_H
6113 +
6114 +/* ethtool related */
6115 +unsigned char get_current_phy_address(void);
6116 +int mdio_read(struct net_device *dev, int phy_id, int location);
6117 +void mdio_write(struct net_device *dev, int phy_id, int location, int value);
6118 +
6119 +/* for pseudo interface */
6120 +int mdio_virt_read(struct net_device *dev, int phy_id, int location);
6121 +void mdio_virt_write(struct net_device *dev, int phy_id, int location, int value);
6122 +
6123 +#endif
6124 diff --git a/drivers/net/ethernet/raeth/ra_ioctl.h b/drivers/net/ethernet/raeth/ra_ioctl.h
6125 new file mode 100644
6126 index 0000000..83b806a
6127 --- /dev/null
6128 +++ b/drivers/net/ethernet/raeth/ra_ioctl.h
6129 @@ -0,0 +1,102 @@
6130 +#ifndef _RAETH_IOCTL_H
6131 +#define _RAETH_IOCTL_H
6132 +
6133 +/* ioctl commands */
6134 +#define RAETH_ESW_REG_READ             0x89F1
6135 +#define RAETH_ESW_REG_WRITE            0x89F2
6136 +#define RAETH_MII_READ                 0x89F3
6137 +#define RAETH_MII_WRITE                        0x89F4
6138 +#define RAETH_ESW_INGRESS_RATE         0x89F5
6139 +#define RAETH_ESW_EGRESS_RATE          0x89F6
6140 +#define RAETH_ESW_PHY_DUMP             0x89F7
6141 +#define RAETH_QDMA_REG_READ            0x89F8
6142 +#define RAETH_QDMA_REG_WRITE           0x89F9
6143 +#define RAETH_QDMA_QUEUE_MAPPING        0x89FA
6144 +#define RAETH_QDMA_READ_CPU_CLK         0x89FB
6145 +#define RAETH_MII_READ_CL45             0x89FC
6146 +#define RAETH_MII_WRITE_CL45            0x89FD
6147 +#if defined(CONFIG_HW_SFQ)
6148 +#define RAETH_QDMA_SFQ_WEB_ENABLE       0x89FE
6149 +#endif
6150 +
6151 +#if defined (CONFIG_RALINK_RT6855) || defined(CONFIG_RALINK_RT6855A) || \
6152 +    defined (CONFIG_RALINK_MT7620) || defined(CONFIG_RALINK_MT7621) || \
6153 +    defined (CONFIG_ARCH_MT7623)
6154 +
6155 +#define REG_ESW_WT_MAC_MFC              0x10
6156 +#define REG_ESW_ISC                     0x18
6157 +#define REG_ESW_WT_MAC_ATA1             0x74
6158 +#define REG_ESW_WT_MAC_ATA2             0x78
6159 +#define REG_ESW_WT_MAC_ATWD             0x7C
6160 +#define REG_ESW_WT_MAC_ATC              0x80
6161 +
6162 +#define REG_ESW_TABLE_TSRA1            0x84
6163 +#define REG_ESW_TABLE_TSRA2            0x88
6164 +#define REG_ESW_TABLE_ATRD             0x8C
6165 +
6166 +
6167 +#define REG_ESW_VLAN_VTCR              0x90
6168 +#define REG_ESW_VLAN_VAWD1             0x94
6169 +#define REG_ESW_VLAN_VAWD2             0x98
6170 +
6171 +
6172 +#define REG_ESW_VLAN_ID_BASE           0x100
6173 +
6174 +//#define REG_ESW_VLAN_ID_BASE         0x50
6175 +#define REG_ESW_VLAN_MEMB_BASE         0x70
6176 +#define REG_ESW_TABLE_SEARCH           0x24
6177 +#define REG_ESW_TABLE_STATUS0          0x28
6178 +#define REG_ESW_TABLE_STATUS1          0x2C
6179 +#define REG_ESW_TABLE_STATUS2          0x30
6180 +#define REG_ESW_WT_MAC_AD0             0x34
6181 +#define REG_ESW_WT_MAC_AD1             0x38
6182 +#define REG_ESW_WT_MAC_AD2             0x3C
6183 +
6184 +#else
6185 +/* rt3052 embedded ethernet switch registers */
6186 +#define REG_ESW_VLAN_ID_BASE           0x50
6187 +#define REG_ESW_VLAN_MEMB_BASE         0x70
6188 +#define REG_ESW_TABLE_SEARCH           0x24
6189 +#define REG_ESW_TABLE_STATUS0          0x28
6190 +#define REG_ESW_TABLE_STATUS1          0x2C
6191 +#define REG_ESW_TABLE_STATUS2          0x30
6192 +#define REG_ESW_WT_MAC_AD0             0x34
6193 +#define REG_ESW_WT_MAC_AD1             0x38
6194 +#define REG_ESW_WT_MAC_AD2             0x3C
6195 +#endif
6196 +
6197 +
6198 +#if defined(CONFIG_RALINK_RT3352) || defined (CONFIG_RALINK_RT5350) || defined (CONFIG_RALINK_MT7628)
6199 +#define REG_ESW_MAX                    0x16C
6200 +#elif defined (CONFIG_RALINK_RT6855) || defined(CONFIG_RALINK_RT6855A) || \
6201 +      defined (CONFIG_RALINK_MT7620)
6202 +#define REG_ESW_MAX                    0x7FFFF
6203 +#else //RT305x, RT3350
6204 +#define REG_ESW_MAX                    0xFC
6205 +#endif
6206 +#define REG_HQOS_MAX                   0x3FFF
6207 +
6208 +
6209 +typedef struct rt3052_esw_reg {
6210 +       unsigned int off;
6211 +       unsigned int val;
6212 +} esw_reg;
6213 +
6214 +typedef struct ralink_mii_ioctl_data {
6215 +       __u32   phy_id;
6216 +       __u32   reg_num;
6217 +       __u32   val_in;
6218 +       __u32   val_out;
6219 +       __u32   port_num;
6220 +       __u32   dev_addr;
6221 +       __u32   reg_addr;
6222 +} ra_mii_ioctl_data;
6223 +
6224 +typedef struct rt335x_esw_reg {
6225 +       unsigned int on_off;
6226 +       unsigned int port;
6227 +       unsigned int bw;/*Mbps*/
6228 +} esw_rate;
6229 +
6230 +
6231 +#endif
6232 diff --git a/drivers/net/ethernet/raeth/ra_mac.c b/drivers/net/ethernet/raeth/ra_mac.c
6233 new file mode 100644
6234 index 0000000..e8e978d
6235 --- /dev/null
6236 +++ b/drivers/net/ethernet/raeth/ra_mac.c
6237 @@ -0,0 +1,2645 @@
6238 +#include <linux/module.h>
6239 +#include <linux/version.h>
6240 +#include <linux/kernel.h>
6241 +#include <linux/sched.h>
6242 +#include <linux/types.h>
6243 +#include <linux/fcntl.h>
6244 +#include <linux/interrupt.h>
6245 +#include <linux/ptrace.h>
6246 +#include <linux/ioport.h>
6247 +#include <linux/in.h>
6248 +#include <linux/slab.h>
6249 +#include <linux/string.h>
6250 +#include <linux/signal.h>
6251 +#include <linux/irq.h>
6252 +#include <linux/ctype.h>
6253 +#if LINUX_VERSION_CODE < KERNEL_VERSION(3,10,4)
6254 +#include <asm/system.h>
6255 +#include <linux/mca.h>
6256 +#endif
6257 +#include <asm/io.h>
6258 +#include <asm/bitops.h>
6259 +#include <asm/io.h>
6260 +#include <asm/dma.h>
6261 +
6262 +#include <asm/rt2880/surfboardint.h>   /* for cp0 reg access, added by bobtseng */
6263 +
6264 +#include <linux/errno.h>
6265 +#include <linux/init.h>
6266 +
6267 +#include <linux/netdevice.h>
6268 +#include <linux/etherdevice.h>
6269 +#include <linux/skbuff.h>
6270 +
6271 +#include <linux/init.h>
6272 +#include <linux/module.h>
6273 +#include <linux/proc_fs.h>
6274 +#include <asm/uaccess.h>
6275 +
6276 +#include <linux/seq_file.h>
6277 +
6278 +
6279 +#if defined(CONFIG_RAETH_LRO)
6280 +#include <linux/inet_lro.h>
6281 +#endif
6282 +
6283 +#include "ra2882ethreg.h"
6284 +#include "raether.h"
6285 +#include "ra_mac.h"
6286 +#include "ra_ethtool.h"
6287 +#if defined(CONFIG_RAETH_PDMA_DVT)
6288 +#include "dvt/raether_pdma_dvt.h"
6289 +#endif  //#if defined(CONFIG_RAETH_PDMA_DVT)
6290 +
6291 +extern struct net_device *dev_raether;
6292 +
6293 +#if defined (CONFIG_RALINK_RT6855) || defined(CONFIG_RALINK_RT6855A) || \
6294 +    defined (CONFIG_RALINK_MT7620)
6295 +extern unsigned short p0_rx_good_cnt;
6296 +extern unsigned short p0_tx_good_cnt;
6297 +extern unsigned short p1_rx_good_cnt;
6298 +extern unsigned short p1_tx_good_cnt;
6299 +extern unsigned short p2_rx_good_cnt;
6300 +extern unsigned short p2_tx_good_cnt;
6301 +extern unsigned short p3_rx_good_cnt;
6302 +extern unsigned short p3_tx_good_cnt;
6303 +extern unsigned short p4_rx_good_cnt;
6304 +extern unsigned short p4_tx_good_cnt;
6305 +extern unsigned short p5_rx_good_cnt;
6306 +extern unsigned short p5_tx_good_cnt;
6307 +extern unsigned short p6_rx_good_cnt;
6308 +extern unsigned short p6_tx_good_cnt;
6309 +
6310 +extern unsigned short p0_rx_byte_cnt;
6311 +extern unsigned short p1_rx_byte_cnt;
6312 +extern unsigned short p2_rx_byte_cnt;
6313 +extern unsigned short p3_rx_byte_cnt;
6314 +extern unsigned short p4_rx_byte_cnt;
6315 +extern unsigned short p5_rx_byte_cnt;
6316 +extern unsigned short p6_rx_byte_cnt;
6317 +extern unsigned short p0_tx_byte_cnt;
6318 +extern unsigned short p1_tx_byte_cnt;
6319 +extern unsigned short p2_tx_byte_cnt;
6320 +extern unsigned short p3_tx_byte_cnt;
6321 +extern unsigned short p4_tx_byte_cnt;
6322 +extern unsigned short p5_tx_byte_cnt;
6323 +extern unsigned short p6_tx_byte_cnt;
6324 +
6325 +#if defined(CONFIG_RALINK_MT7620)
6326 +extern unsigned short p7_rx_good_cnt;
6327 +extern unsigned short p7_tx_good_cnt;
6328 +extern unsigned short p7_rx_byte_cnt;
6329 +extern unsigned short p7_tx_byte_cnt;
6330 +#endif
6331 +#endif
6332 +
6333 +
6334 +
6335 +#if defined(CONFIG_RAETH_TSO)
6336 +int txd_cnt[MAX_SKB_FRAGS/2 + 1];
6337 +int tso_cnt[16];
6338 +#endif
6339 +
6340 +#if defined(CONFIG_RAETH_LRO)
6341 +#define MAX_AGGR 64
6342 +#define MAX_DESC  8
6343 +int lro_stats_cnt[MAX_AGGR + 1];
6344 +int lro_flush_cnt[MAX_AGGR + 1];
6345 +int lro_len_cnt1[16];
6346 +//int lro_len_cnt2[16];
6347 +int aggregated[MAX_DESC];
6348 +int lro_aggregated;
6349 +int lro_flushed;
6350 +int lro_nodesc;
6351 +int force_flush;
6352 +int tot_called1;
6353 +int tot_called2;
6354 +#endif
6355 +
6356 +#if defined(CONFIG_RAETH_HW_LRO)
6357 +#define HW_LRO_RING_NUM 3
6358 +#define MAX_HW_LRO_AGGR 64
6359 +unsigned int hw_lro_agg_num_cnt[HW_LRO_RING_NUM][MAX_HW_LRO_AGGR + 1];
6360 +unsigned int hw_lro_agg_size_cnt[HW_LRO_RING_NUM][16];
6361 +unsigned int hw_lro_tot_agg_cnt[HW_LRO_RING_NUM];
6362 +unsigned int hw_lro_tot_flush_cnt[HW_LRO_RING_NUM];
6363 +#if defined(CONFIG_RAETH_HW_LRO_REASON_DBG)
6364 +unsigned int hw_lro_agg_flush_cnt[HW_LRO_RING_NUM];
6365 +unsigned int hw_lro_age_flush_cnt[HW_LRO_RING_NUM];
6366 +unsigned int hw_lro_seq_flush_cnt[HW_LRO_RING_NUM];
6367 +unsigned int hw_lro_timestamp_flush_cnt[HW_LRO_RING_NUM];
6368 +unsigned int hw_lro_norule_flush_cnt[HW_LRO_RING_NUM];
6369 +#endif  /* CONFIG_RAETH_HW_LRO_REASON_DBG */
6370 +#endif  /* CONFIG_RAETH_HW_LRO */
6371 +
6372 +#if defined(CONFIG_RAETH_QDMA)
6373 +extern unsigned int M2Q_table[64];
6374 +extern struct QDMA_txdesc *free_head;
6375 +#endif
6376 +#if defined (CONFIG_ARCH_MT7623)
6377 +extern struct SFQ_table *sfq0;
6378 +extern struct SFQ_table *sfq1;
6379 +extern struct SFQ_table *sfq2;
6380 +extern struct SFQ_table *sfq3;
6381 +#endif
6382 +
6383 +#if defined(CONFIG_USER_SNMPD)
6384 +
6385 +static int ra_snmp_seq_show(struct seq_file *seq, void *v)
6386 +{
6387 +#if !defined(CONFIG_RALINK_RT5350) && !defined(CONFIG_RALINK_MT7620) && !defined (CONFIG_RALINK_MT7628)
6388 +
6389 +       seq_printf(seq, "rx counters: %x %x %x %x %x %x %x\n", sysRegRead(GDMA_RX_GBCNT0), sysRegRead(GDMA_RX_GPCNT0),sysRegRead(GDMA_RX_OERCNT0), sysRegRead(GDMA_RX_FERCNT0), sysRegRead(GDMA_RX_SERCNT0), sysRegRead(GDMA_RX_LERCNT0), sysRegRead(GDMA_RX_CERCNT0));
6390 +
6391 +       seq_printf(seq, "fc config: %x %x %x %x\n", sysRegRead(CDMA_FC_CFG), sysRegRead(GDMA1_FC_CFG), PDMA_FC_CFG, sysRegRead(PDMA_FC_CFG));
6392 +
6393 +       seq_printf(seq, "scheduler: %x %x %x\n", sysRegRead(GDMA1_SCH_CFG), sysRegRead(GDMA2_SCH_CFG), sysRegRead(PDMA_SCH_CFG));
6394 +
6395 +#endif
6396 +       seq_printf(seq, "ports: %x %x %x %x %x %x\n", sysRegRead(PORT0_PKCOUNT), sysRegRead(PORT1_PKCOUNT), sysRegRead(PORT2_PKCOUNT), sysRegRead(PORT3_PKCOUNT), sysRegRead(PORT4_PKCOUNT), sysRegRead(PORT5_PKCOUNT));
6397 +
6398 +       return 0;
6399 +}
6400 +
6401 +static int ra_snmp_seq_open(struct inode *inode, struct file *file)
6402 +{
6403 +       return single_open(file, ra_snmp_seq_show, NULL);
6404 +}
6405 +
6406 +static const struct file_operations ra_snmp_seq_fops = {
6407 +       .owner   = THIS_MODULE,
6408 +       .open    = ra_snmp_seq_open,
6409 +       .read    = seq_read,
6410 +       .llseek  = seq_lseek,
6411 +       .release = single_release
6412 +};
6413 +#endif
6414 +
6415 +
6416 +#if defined (CONFIG_GIGAPHY) || defined (CONFIG_100PHY) || \
6417 +    defined (CONFIG_P5_MAC_TO_PHY_MODE) || defined (CONFIG_RAETH_GMAC2)
6418 +#if defined (CONFIG_RALINK_RT6855) || defined(CONFIG_RALINK_RT6855A) || \
6419 +    defined (CONFIG_RALINK_MT7620) || defined(CONFIG_RALINK_MT7621)  || \
6420 +    defined (CONFIG_ARCH_MT7623)
6421 +void enable_auto_negotiate(int unused)
6422 +{
6423 +       u32 regValue;
6424 +#if !defined (CONFIG_RALINK_MT7621) && !defined (CONFIG_ARCH_MT7623)
6425 +       u32 addr = CONFIG_MAC_TO_GIGAPHY_MODE_ADDR;
6426 +#endif
6427 +
6428 +#if defined (CONFIG_RALINK_MT7621)
6429 +       //enable MDIO mode all the time
6430 +       regValue = le32_to_cpu(*(volatile u_long *)(RALINK_SYSCTL_BASE + 0x60));
6431 +       regValue &= ~(0x3 << 12);
6432 +       *(volatile u_long *)(RALINK_SYSCTL_BASE + 0x60) = regValue;
6433 +#endif
6434 +
6435 +       /* FIXME: we don't know how to deal with PHY end addr */
6436 +       regValue = sysRegRead(ESW_PHY_POLLING);
6437 +       regValue |= (1<<31);
6438 +       regValue &= ~(0x1f);
6439 +       regValue &= ~(0x1f<<8);
6440 +#if defined (CONFIG_RALINK_MT7620)
6441 +       regValue |= ((addr-1) << 0);//setup PHY address for auto polling (Start Addr).
6442 +       regValue |= (addr << 8);// setup PHY address for auto polling (End Addr).
6443 +#elif defined (CONFIG_RALINK_MT7621) || defined (CONFIG_ARCH_MT7623)
6444 +#if defined (CONFIG_GE_RGMII_INTERNAL_P0_AN)|| defined (CONFIG_GE_RGMII_INTERNAL_P4_AN) || defined (CONFIG_GE2_RGMII_AN)
6445 +       regValue |= ((CONFIG_MAC_TO_GIGAPHY_MODE_ADDR2-1)&0x1f << 0);//setup PHY address for auto polling (Start Addr).
6446 +       regValue |= (CONFIG_MAC_TO_GIGAPHY_MODE_ADDR2 << 8);// setup PHY address for auto polling (End Addr).
6447 +#else
6448 +       regValue |= (CONFIG_MAC_TO_GIGAPHY_MODE_ADDR << 0);//setup PHY address for auto polling (Start Addr).
6449 +       regValue |= (CONFIG_MAC_TO_GIGAPHY_MODE_ADDR2 << 8);// setup PHY address for auto polling (End Addr).
6450 +#endif
6451 +#else
6452 +       regValue |= (addr << 0);// setup PHY address for auto polling (start Addr).
6453 +       regValue |= (addr << 8);// setup PHY address for auto polling (End Addr).
6454 +#endif
6455 +
6456 +       /*kurtis: AN is strange*/
6457 +       sysRegWrite(ESW_PHY_POLLING, regValue);
6458 +
6459 +#if defined (CONFIG_P4_MAC_TO_PHY_MODE)
6460 +       *(unsigned long *)(RALINK_ETH_SW_BASE+0x3400) = 0x56330;
6461 +#endif
6462 +#if defined (CONFIG_P5_MAC_TO_PHY_MODE)
6463 +       *(unsigned long *)(RALINK_ETH_SW_BASE+0x3500) = 0x56330;
6464 +#endif
6465 +}
6466 +#elif defined (CONFIG_RALINK_RT2880) || defined(CONFIG_RALINK_RT3883) || \
6467 +      defined (CONFIG_RALINK_RT3052) || defined(CONFIG_RALINK_RT3352)
6468 +
6469 +void enable_auto_negotiate(int ge)
6470 +{
6471 +#if defined (CONFIG_RALINK_RT3052) || defined (CONFIG_RALINK_RT3352)
6472 +        u32 regValue = sysRegRead(0xb01100C8);
6473 +#else
6474 +       u32 regValue;
6475 +       regValue = (ge == 2)? sysRegRead(MDIO_CFG2) : sysRegRead(MDIO_CFG);
6476 +#endif
6477 +
6478 +        regValue &= 0xe0ff7fff;                 // clear auto polling related field:
6479 +                                                // (MD_PHY1ADDR & GP1_FRC_EN).
6480 +        regValue |= 0x20000000;                 // force to enable MDC/MDIO auto polling.
6481 +
6482 +#if defined (CONFIG_GE2_RGMII_AN) || defined (CONFIG_GE2_MII_AN)
6483 +       if(ge==2) {
6484 +           regValue |= (CONFIG_MAC_TO_GIGAPHY_MODE_ADDR2 << 24);               // setup PHY address for auto polling.
6485 +       }
6486 +#endif
6487 +#if defined (CONFIG_GE1_RGMII_AN) || defined (CONFIG_GE1_MII_AN) || defined (CONFIG_P5_MAC_TO_PHY_MODE)
6488 +       if(ge==1) {
6489 +           regValue |= (CONFIG_MAC_TO_GIGAPHY_MODE_ADDR << 24);               // setup PHY address for auto polling.
6490 +       }
6491 +#endif
6492 +
6493 +#if defined (CONFIG_RALINK_RT3052) || defined (CONFIG_RALINK_RT3352)
6494 +       sysRegWrite(0xb01100C8, regValue);
6495 +#else
6496 +       if (ge == 2)
6497 +               sysRegWrite(MDIO_CFG2, regValue);
6498 +       else
6499 +               sysRegWrite(MDIO_CFG, regValue);
6500 +#endif
6501 +}
6502 +#endif
6503 +#endif
6504 +void ra2880stop(END_DEVICE *ei_local)
6505 +{
6506 +       unsigned int regValue;
6507 +       printk("ra2880stop()...");
6508 +
6509 +       regValue = sysRegRead(DMA_GLO_CFG);
6510 +       regValue &= ~(TX_WB_DDONE | RX_DMA_EN | TX_DMA_EN);
6511 +       sysRegWrite(DMA_GLO_CFG, regValue);
6512 +
6513 +       printk("Done\n");
6514 +       // printk("Done0x%x...\n", readreg(DMA_GLO_CFG));
6515 +}
6516 +
6517 +void ei_irq_clear(void)
6518 +{
6519 +        sysRegWrite(FE_INT_STATUS, 0xFFFFFFFF);
6520 +}
6521 +
6522 +void rt2880_gmac_hard_reset(void)
6523 +{
6524 +#if !defined (CONFIG_RALINK_RT6855A)
6525 +       //FIXME
6526 +       sysRegWrite(RSTCTRL, RALINK_FE_RST);
6527 +       sysRegWrite(RSTCTRL, 0);
6528 +#endif
6529 +}
6530 +
6531 +void ra2880EnableInterrupt()
6532 +{
6533 +       unsigned int regValue = sysRegRead(FE_INT_ENABLE);
6534 +       RAETH_PRINT("FE_INT_ENABLE -- : 0x%08x\n", regValue);
6535 +//     regValue |= (RX_DONE_INT0 | TX_DONE_INT0);
6536 +
6537 +       sysRegWrite(FE_INT_ENABLE, regValue);
6538 +}
6539 +
6540 +void ra2880MacAddressSet(unsigned char p[6])
6541 +{
6542 +        unsigned long regValue;
6543 +
6544 +       regValue = (p[0] << 8) | (p[1]);
6545 +#if defined (CONFIG_RALINK_RT5350) || defined (CONFIG_RALINK_MT7628)
6546 +        sysRegWrite(SDM_MAC_ADRH, regValue);
6547 +       printk("GMAC1_MAC_ADRH -- : 0x%08x\n", sysRegRead(SDM_MAC_ADRH));
6548 +#elif defined (CONFIG_RALINK_RT6855) || defined(CONFIG_RALINK_RT6855A)
6549 +        sysRegWrite(GDMA1_MAC_ADRH, regValue);
6550 +       printk("GMAC1_MAC_ADRH -- : 0x%08x\n", sysRegRead(GDMA1_MAC_ADRH));
6551 +
6552 +       /* To keep the consistence between RT6855 and RT62806, GSW should keep the register. */
6553 +        sysRegWrite(SMACCR1, regValue);
6554 +       printk("SMACCR1 -- : 0x%08x\n", sysRegRead(SMACCR1));
6555 +#elif defined (CONFIG_RALINK_MT7620)
6556 +        sysRegWrite(SMACCR1, regValue);
6557 +       printk("SMACCR1 -- : 0x%08x\n", sysRegRead(SMACCR1));
6558 +#else
6559 +        sysRegWrite(GDMA1_MAC_ADRH, regValue);
6560 +       printk("GMAC1_MAC_ADRH -- : 0x%08x\n", sysRegRead(GDMA1_MAC_ADRH));
6561 +#endif
6562 +
6563 +        regValue = (p[2] << 24) | (p[3] <<16) | (p[4] << 8) | p[5];
6564 +#if defined (CONFIG_RALINK_RT5350) || defined (CONFIG_RALINK_MT7628)
6565 +        sysRegWrite(SDM_MAC_ADRL, regValue);
6566 +       printk("GMAC1_MAC_ADRL -- : 0x%08x\n", sysRegRead(SDM_MAC_ADRL));
6567 +#elif defined (CONFIG_RALINK_RT6855) || defined(CONFIG_RALINK_RT6855A)
6568 +        sysRegWrite(GDMA1_MAC_ADRL, regValue);
6569 +       printk("GMAC1_MAC_ADRL -- : 0x%08x\n", sysRegRead(GDMA1_MAC_ADRL));
6570 +
6571 +       /* To keep the consistence between RT6855 and RT62806, GSW should keep the register. */
6572 +        sysRegWrite(SMACCR0, regValue);
6573 +       printk("SMACCR0 -- : 0x%08x\n", sysRegRead(SMACCR0));
6574 +#elif defined (CONFIG_RALINK_MT7620)
6575 +        sysRegWrite(SMACCR0, regValue);
6576 +       printk("SMACCR0 -- : 0x%08x\n", sysRegRead(SMACCR0));
6577 +#else
6578 +        sysRegWrite(GDMA1_MAC_ADRL, regValue);
6579 +       printk("GMAC1_MAC_ADRL -- : 0x%08x\n", sysRegRead(GDMA1_MAC_ADRL));
6580 +#endif
6581 +
6582 +        return;
6583 +}
6584 +
6585 +#ifdef CONFIG_PSEUDO_SUPPORT
6586 +void ra2880Mac2AddressSet(unsigned char p[6])
6587 +{
6588 +        unsigned long regValue;
6589 +
6590 +       regValue = (p[0] << 8) | (p[1]);
6591 +        sysRegWrite(GDMA2_MAC_ADRH, regValue);
6592 +
6593 +        regValue = (p[2] << 24) | (p[3] <<16) | (p[4] << 8) | p[5];
6594 +        sysRegWrite(GDMA2_MAC_ADRL, regValue);
6595 +
6596 +       printk("GDMA2_MAC_ADRH -- : 0x%08x\n", sysRegRead(GDMA2_MAC_ADRH));
6597 +       printk("GDMA2_MAC_ADRL -- : 0x%08x\n", sysRegRead(GDMA2_MAC_ADRL));
6598 +        return;
6599 +}
6600 +#endif
6601 +
6602 +/**
6603 + * hard_init - Called by raeth_probe to inititialize network device
6604 + * @dev: device pointer
6605 + *
6606 + * ethdev_init initilize dev->priv and set to END_DEVICE structure
6607 + *
6608 + */
6609 +void ethtool_init(struct net_device *dev)
6610 +{
6611 +#if defined (CONFIG_ETHTOOL) /*&& defined (CONFIG_RAETH_ROUTER)*/
6612 +       END_DEVICE *ei_local = netdev_priv(dev);
6613 +
6614 +       // init mii structure
6615 +       ei_local->mii_info.dev = dev;
6616 +       ei_local->mii_info.mdio_read = mdio_read;
6617 +       ei_local->mii_info.mdio_write = mdio_write;
6618 +       ei_local->mii_info.phy_id_mask = 0x1f;
6619 +       ei_local->mii_info.reg_num_mask = 0x1f;
6620 +       ei_local->mii_info.supports_gmii = mii_check_gmii_support(&ei_local->mii_info);
6621 +       // TODO:   phy_id: 0~4
6622 +       ei_local->mii_info.phy_id = 1;
6623 +#endif
6624 +       return;
6625 +}
6626 +
6627 +/*
6628 + *     Routine Name : get_idx(mode, index)
6629 + *     Description: calculate ring usage for tx/rx rings
6630 + *     Mode 1 : Tx Ring
6631 + *     Mode 2 : Rx Ring
6632 + */
6633 +int get_ring_usage(int mode, int i)
6634 +{
6635 +       unsigned long tx_ctx_idx, tx_dtx_idx, tx_usage;
6636 +       unsigned long rx_calc_idx, rx_drx_idx, rx_usage;
6637 +
6638 +       struct PDMA_rxdesc* rxring;
6639 +       struct PDMA_txdesc* txring;
6640 +
6641 +       END_DEVICE *ei_local = netdev_priv(dev_raether);
6642 +
6643 +
6644 +       if (mode == 2 ) {
6645 +               /* cpu point to the next descriptor of rx dma ring */
6646 +               rx_calc_idx = *(unsigned long*)RX_CALC_IDX0;
6647 +               rx_drx_idx = *(unsigned long*)RX_DRX_IDX0;
6648 +               rxring = (struct PDMA_rxdesc*)RX_BASE_PTR0;
6649 +
6650 +               rx_usage = (rx_drx_idx - rx_calc_idx -1 + NUM_RX_DESC) % NUM_RX_DESC;
6651 +               if ( rx_calc_idx == rx_drx_idx ) {
6652 +                   if ( rxring[rx_drx_idx].rxd_info2.DDONE_bit == 1)
6653 +                       tx_usage = NUM_RX_DESC;
6654 +                   else
6655 +                       tx_usage = 0;
6656 +               }
6657 +               return rx_usage;
6658 +       }
6659 +
6660 +
6661 +       switch (i) {
6662 +               case 0:
6663 +                               tx_ctx_idx = *(unsigned long*)TX_CTX_IDX0;
6664 +                               tx_dtx_idx = *(unsigned long*)TX_DTX_IDX0;
6665 +                               txring = ei_local->tx_ring0;
6666 +                               break;
6667 +#if defined(CONFIG_RAETH_QOS)
6668 +               case 1:
6669 +                               tx_ctx_idx = *(unsigned long*)TX_CTX_IDX1;
6670 +                               tx_dtx_idx = *(unsigned long*)TX_DTX_IDX1;
6671 +                               txring = ei_local->tx_ring1;
6672 +                               break;
6673 +               case 2:
6674 +                               tx_ctx_idx = *(unsigned long*)TX_CTX_IDX2;
6675 +                               tx_dtx_idx = *(unsigned long*)TX_DTX_IDX2;
6676 +                               txring = ei_local->tx_ring2;
6677 +                               break;
6678 +               case 3:
6679 +                               tx_ctx_idx = *(unsigned long*)TX_CTX_IDX3;
6680 +                               tx_dtx_idx = *(unsigned long*)TX_DTX_IDX3;
6681 +                               txring = ei_local->tx_ring3;
6682 +                               break;
6683 +#endif
6684 +               default:
6685 +                       printk("get_tx_idx failed %d %d\n", mode, i);
6686 +                       return 0;
6687 +       };
6688 +
6689 +       tx_usage = (tx_ctx_idx - tx_dtx_idx + NUM_TX_DESC) % NUM_TX_DESC;
6690 +       if ( tx_ctx_idx == tx_dtx_idx ) {
6691 +               if ( txring[tx_ctx_idx].txd_info2.DDONE_bit == 1)
6692 +                       tx_usage = 0;
6693 +               else
6694 +                       tx_usage = NUM_TX_DESC;
6695 +       }
6696 +       return tx_usage;
6697 +
6698 +}
6699 +
6700 +#if defined(CONFIG_RAETH_QOS)
6701 +void dump_qos(struct seq_file *s)
6702 +{
6703 +       int usage;
6704 +       int i;
6705 +
6706 +       seq_printf(s, "\n-----Raeth QOS -----\n\n");
6707 +
6708 +       for ( i = 0; i < 4; i++)  {
6709 +               usage = get_ring_usage(1,i);
6710 +               seq_printf(s, "Tx Ring%d Usage : %d/%d\n", i, usage, NUM_TX_DESC);
6711 +       }
6712 +
6713 +       usage = get_ring_usage(2,0);
6714 +       seq_printf(s, "RX Usage : %d/%d\n\n", usage, NUM_RX_DESC);
6715 +#if defined  (CONFIG_RALINK_MT7620)
6716 +       seq_printf(s, "PSE_FQFC_CFG(0x%08x)  : 0x%08x\n", PSE_FQFC_CFG, sysRegRead(PSE_FQFC_CFG));
6717 +       seq_printf(s, "PSE_IQ_CFG(0x%08x)  : 0x%08x\n", PSE_IQ_CFG, sysRegRead(PSE_IQ_CFG));
6718 +       seq_printf(s, "PSE_QUE_STA(0x%08x)  : 0x%08x\n", PSE_QUE_STA, sysRegRead(PSE_QUE_STA));
6719 +#elif defined (CONFIG_RALINK_RT5350) || defined (CONFIG_RALINK_MT7628)
6720 +
6721 +#else
6722 +       seq_printf(s, "GDMA1_FC_CFG(0x%08x)  : 0x%08x\n", GDMA1_FC_CFG, sysRegRead(GDMA1_FC_CFG));
6723 +       seq_printf(s, "GDMA2_FC_CFG(0x%08x)  : 0x%08x\n", GDMA2_FC_CFG, sysRegRead(GDMA2_FC_CFG));
6724 +       seq_printf(s, "PDMA_FC_CFG(0x%08x)  : 0x%08x\n", PDMA_FC_CFG, sysRegRead(PDMA_FC_CFG));
6725 +       seq_printf(s, "PSE_FQ_CFG(0x%08x)  : 0x%08x\n", PSE_FQ_CFG, sysRegRead(PSE_FQ_CFG));
6726 +#endif
6727 +       seq_printf(s, "\n\nTX_CTX_IDX0    : 0x%08x\n", sysRegRead(TX_CTX_IDX0));
6728 +       seq_printf(s, "TX_DTX_IDX0    : 0x%08x\n", sysRegRead(TX_DTX_IDX0));
6729 +       seq_printf(s, "TX_CTX_IDX1    : 0x%08x\n", sysRegRead(TX_CTX_IDX1));
6730 +       seq_printf(s, "TX_DTX_IDX1    : 0x%08x\n", sysRegRead(TX_DTX_IDX1));
6731 +       seq_printf(s, "TX_CTX_IDX2    : 0x%08x\n", sysRegRead(TX_CTX_IDX2));
6732 +       seq_printf(s, "TX_DTX_IDX2    : 0x%08x\n", sysRegRead(TX_DTX_IDX2));
6733 +       seq_printf(s, "TX_CTX_IDX3    : 0x%08x\n", sysRegRead(TX_CTX_IDX3));
6734 +       seq_printf(s, "TX_DTX_IDX3    : 0x%08x\n", sysRegRead(TX_DTX_IDX3));
6735 +       seq_printf(s, "RX_CALC_IDX0   : 0x%08x\n", sysRegRead(RX_CALC_IDX0));
6736 +       seq_printf(s, "RX_DRX_IDX0    : 0x%08x\n", sysRegRead(RX_DRX_IDX0));
6737 +
6738 +       seq_printf(s, "\n------------------------------\n\n");
6739 +}
6740 +#endif
6741 +
6742 +void dump_reg(struct seq_file *s)
6743 +{
6744 +       int fe_int_enable;
6745 +       int rx_usage;
6746 +       int dly_int_cfg;
6747 +       int rx_base_ptr0;
6748 +       int rx_max_cnt0;
6749 +       int rx_calc_idx0;
6750 +       int rx_drx_idx0;
6751 +#if !defined (CONFIG_RAETH_QDMA)
6752 +       int tx_usage;
6753 +       int tx_base_ptr[4];
6754 +       int tx_max_cnt[4];
6755 +       int tx_ctx_idx[4];
6756 +       int tx_dtx_idx[4];
6757 +       int i;
6758 +#endif
6759 +
6760 +       fe_int_enable = sysRegRead(FE_INT_ENABLE);
6761 +        rx_usage = get_ring_usage(2,0);
6762 +
6763 +       dly_int_cfg = sysRegRead(DLY_INT_CFG);
6764 +
6765 +#if !defined (CONFIG_RAETH_QDMA)
6766 +       tx_usage = get_ring_usage(1,0);
6767 +
6768 +       tx_base_ptr[0] = sysRegRead(TX_BASE_PTR0);
6769 +       tx_max_cnt[0] = sysRegRead(TX_MAX_CNT0);
6770 +       tx_ctx_idx[0] = sysRegRead(TX_CTX_IDX0);
6771 +       tx_dtx_idx[0] = sysRegRead(TX_DTX_IDX0);
6772 +
6773 +       tx_base_ptr[1] = sysRegRead(TX_BASE_PTR1);
6774 +       tx_max_cnt[1] = sysRegRead(TX_MAX_CNT1);
6775 +       tx_ctx_idx[1] = sysRegRead(TX_CTX_IDX1);
6776 +       tx_dtx_idx[1] = sysRegRead(TX_DTX_IDX1);
6777 +
6778 +       tx_base_ptr[2] = sysRegRead(TX_BASE_PTR2);
6779 +       tx_max_cnt[2] = sysRegRead(TX_MAX_CNT2);
6780 +       tx_ctx_idx[2] = sysRegRead(TX_CTX_IDX2);
6781 +       tx_dtx_idx[2] = sysRegRead(TX_DTX_IDX2);
6782 +
6783 +       tx_base_ptr[3] = sysRegRead(TX_BASE_PTR3);
6784 +       tx_max_cnt[3] = sysRegRead(TX_MAX_CNT3);
6785 +       tx_ctx_idx[3] = sysRegRead(TX_CTX_IDX3);
6786 +       tx_dtx_idx[3] = sysRegRead(TX_DTX_IDX3);
6787 +#endif
6788 +
6789 +       rx_base_ptr0 = sysRegRead(RX_BASE_PTR0);
6790 +       rx_max_cnt0 = sysRegRead(RX_MAX_CNT0);
6791 +       rx_calc_idx0 = sysRegRead(RX_CALC_IDX0);
6792 +       rx_drx_idx0 = sysRegRead(RX_DRX_IDX0);
6793 +
6794 +       seq_printf(s, "\n\nFE_INT_ENABLE  : 0x%08x\n", fe_int_enable);
6795 +#if !defined (CONFIG_RAETH_QDMA)
6796 +       seq_printf(s, "TxRing PktCnt: %d/%d\n", tx_usage, NUM_TX_DESC);
6797 +#endif
6798 +       seq_printf(s, "RxRing PktCnt: %d/%d\n\n", rx_usage, NUM_RX_DESC);
6799 +       seq_printf(s, "DLY_INT_CFG    : 0x%08x\n", dly_int_cfg);
6800 +
6801 +#if !defined (CONFIG_RAETH_QDMA)
6802 +       for(i=0;i<4;i++) {
6803 +               seq_printf(s, "TX_BASE_PTR%d   : 0x%08x\n", i, tx_base_ptr[i]);
6804 +               seq_printf(s, "TX_MAX_CNT%d    : 0x%08x\n", i, tx_max_cnt[i]);
6805 +               seq_printf(s, "TX_CTX_IDX%d     : 0x%08x\n", i, tx_ctx_idx[i]);
6806 +               seq_printf(s, "TX_DTX_IDX%d     : 0x%08x\n", i, tx_dtx_idx[i]);
6807 +       }
6808 +#endif
6809 +
6810 +       seq_printf(s, "RX_BASE_PTR0   : 0x%08x\n", rx_base_ptr0);
6811 +       seq_printf(s, "RX_MAX_CNT0    : 0x%08x\n", rx_max_cnt0);
6812 +       seq_printf(s, "RX_CALC_IDX0   : 0x%08x\n", rx_calc_idx0);
6813 +       seq_printf(s, "RX_DRX_IDX0    : 0x%08x\n", rx_drx_idx0);
6814 +
6815 +#if defined (CONFIG_ETHTOOL) && defined (CONFIG_RAETH_ROUTER)
6816 +       seq_printf(s, "The current PHY address selected by ethtool is %d\n", get_current_phy_address());
6817 +#endif
6818 +
6819 +#if defined (CONFIG_RALINK_RT2883) || defined(CONFIG_RALINK_RT3883)
6820 +       seq_printf(s, "GDMA_RX_FCCNT1(0x%08x)     : 0x%08x\n\n", GDMA_RX_FCCNT1, sysRegRead(GDMA_RX_FCCNT1));
6821 +#endif
6822 +}
6823 +
6824 +#if 0
6825 +void dump_cp0(void)
6826 +{
6827 +       printk("CP0 Register dump --\n");
6828 +       printk("CP0_INDEX\t: 0x%08x\n", read_32bit_cp0_register(CP0_INDEX));
6829 +       printk("CP0_RANDOM\t: 0x%08x\n", read_32bit_cp0_register(CP0_RANDOM));
6830 +       printk("CP0_ENTRYLO0\t: 0x%08x\n", read_32bit_cp0_register(CP0_ENTRYLO0));
6831 +       printk("CP0_ENTRYLO1\t: 0x%08x\n", read_32bit_cp0_register(CP0_ENTRYLO1));
6832 +       printk("CP0_CONF\t: 0x%08x\n", read_32bit_cp0_register(CP0_CONF));
6833 +       printk("CP0_CONTEXT\t: 0x%08x\n", read_32bit_cp0_register(CP0_CONTEXT));
6834 +       printk("CP0_PAGEMASK\t: 0x%08x\n", read_32bit_cp0_register(CP0_PAGEMASK));
6835 +       printk("CP0_WIRED\t: 0x%08x\n", read_32bit_cp0_register(CP0_WIRED));
6836 +       printk("CP0_INFO\t: 0x%08x\n", read_32bit_cp0_register(CP0_INFO));
6837 +       printk("CP0_BADVADDR\t: 0x%08x\n", read_32bit_cp0_register(CP0_BADVADDR));
6838 +       printk("CP0_COUNT\t: 0x%08x\n", read_32bit_cp0_register(CP0_COUNT));
6839 +       printk("CP0_ENTRYHI\t: 0x%08x\n", read_32bit_cp0_register(CP0_ENTRYHI));
6840 +       printk("CP0_COMPARE\t: 0x%08x\n", read_32bit_cp0_register(CP0_COMPARE));
6841 +       printk("CP0_STATUS\t: 0x%08x\n", read_32bit_cp0_register(CP0_STATUS));
6842 +       printk("CP0_CAUSE\t: 0x%08x\n", read_32bit_cp0_register(CP0_CAUSE));
6843 +       printk("CP0_EPC\t: 0x%08x\n", read_32bit_cp0_register(CP0_EPC));
6844 +       printk("CP0_PRID\t: 0x%08x\n", read_32bit_cp0_register(CP0_PRID));
6845 +       printk("CP0_CONFIG\t: 0x%08x\n", read_32bit_cp0_register(CP0_CONFIG));
6846 +       printk("CP0_LLADDR\t: 0x%08x\n", read_32bit_cp0_register(CP0_LLADDR));
6847 +       printk("CP0_WATCHLO\t: 0x%08x\n", read_32bit_cp0_register(CP0_WATCHLO));
6848 +       printk("CP0_WATCHHI\t: 0x%08x\n", read_32bit_cp0_register(CP0_WATCHHI));
6849 +       printk("CP0_XCONTEXT\t: 0x%08x\n", read_32bit_cp0_register(CP0_XCONTEXT));
6850 +       printk("CP0_FRAMEMASK\t: 0x%08x\n", read_32bit_cp0_register(CP0_FRAMEMASK));
6851 +       printk("CP0_DIAGNOSTIC\t: 0x%08x\n", read_32bit_cp0_register(CP0_DIAGNOSTIC));
6852 +       printk("CP0_DEBUG\t: 0x%08x\n", read_32bit_cp0_register(CP0_DEBUG));
6853 +       printk("CP0_DEPC\t: 0x%08x\n", read_32bit_cp0_register(CP0_DEPC));
6854 +       printk("CP0_PERFORMANCE\t: 0x%08x\n", read_32bit_cp0_register(CP0_PERFORMANCE));
6855 +       printk("CP0_ECC\t: 0x%08x\n", read_32bit_cp0_register(CP0_ECC));
6856 +       printk("CP0_CACHEERR\t: 0x%08x\n", read_32bit_cp0_register(CP0_CACHEERR));
6857 +       printk("CP0_TAGLO\t: 0x%08x\n", read_32bit_cp0_register(CP0_TAGLO));
6858 +       printk("CP0_TAGHI\t: 0x%08x\n", read_32bit_cp0_register(CP0_TAGHI));
6859 +       printk("CP0_ERROREPC\t: 0x%08x\n", read_32bit_cp0_register(CP0_ERROREPC));
6860 +       printk("CP0_DESAVE\t: 0x%08x\n\n", read_32bit_cp0_register(CP0_DESAVE));
6861 +}
6862 +#endif
6863 +
6864 +struct proc_dir_entry *procRegDir;
6865 +static struct proc_dir_entry *procGmac, *procSysCP0, *procTxRing, *procRxRing, *procSkbFree;
6866 +#if defined(CONFIG_PSEUDO_SUPPORT) && defined(CONFIG_ETHTOOL)
6867 +static struct proc_dir_entry *procGmac2;
6868 +#endif
6869 +#if defined(CONFIG_USER_SNMPD)
6870 +static struct proc_dir_entry *procRaSnmp;
6871 +#endif
6872 +#if defined(CONFIG_RAETH_TSO)
6873 +static struct proc_dir_entry *procNumOfTxd, *procTsoLen;
6874 +#endif
6875 +
6876 +#if defined(CONFIG_RAETH_LRO)
6877 +static struct proc_dir_entry *procLroStats;
6878 +#endif
6879 +#if defined(CONFIG_RAETH_HW_LRO) || defined (CONFIG_RAETH_MULTIPLE_RX_RING)
6880 +static struct proc_dir_entry *procRxRing1, *procRxRing2, *procRxRing3;
6881 +static struct proc_dir_entry *procHwLroStats, *procHwLroAutoTlb;
6882 +const static HWLRO_DBG_FUNC hw_lro_dbg_func[] =
6883 +{
6884 +    [0] = hwlro_agg_cnt_ctrl,
6885 +    [1] = hwlro_agg_time_ctrl,
6886 +    [2] = hwlro_age_time_ctrl,
6887 +    [3] = hwlro_pkt_int_alpha_ctrl,
6888 +    [4] = hwlro_threshold_ctrl,
6889 +    [5] = hwlro_fix_setting_switch_ctrl,
6890 +};
6891 +#endif  /* CONFIG_RAETH_HW_LRO */
6892 +#if defined (TASKLET_WORKQUEUE_SW)
6893 +static struct proc_dir_entry *procSCHE;
6894 +#endif
6895 +
6896 +#if defined(CONFIG_RAETH_PDMA_DVT)
6897 +static struct proc_dir_entry *procPdmaDvt;
6898 +
6899 +const static PDMA_DBG_FUNC pdma_dvt_dbg_func[] =
6900 +{
6901 +    [0] = pdma_dvt_show_ctrl,
6902 +    [1] = pdma_dvt_test_rx_ctrl,
6903 +    [2] = pdma_dvt_test_tx_ctrl,
6904 +    [3] = pdma_dvt_test_debug_ctrl,
6905 +    [4] = pdma_dvt_test_lro_ctrl,
6906 +};
6907 +#endif  //#if defined(CONFIG_RAETH_PDMA_DVT)
6908 +
6909 +int RegReadMain(struct seq_file *seq, void *v)
6910 +{
6911 +       dump_reg(seq);
6912 +       return 0;
6913 +}
6914 +
6915 +static void *seq_SkbFree_start(struct seq_file *seq, loff_t *pos)
6916 +{
6917 +       if (*pos < NUM_TX_DESC)
6918 +               return pos;
6919 +       return NULL;
6920 +}
6921 +
6922 +static void *seq_SkbFree_next(struct seq_file *seq, void *v, loff_t *pos)
6923 +{
6924 +       (*pos)++;
6925 +       if (*pos >= NUM_TX_DESC)
6926 +               return NULL;
6927 +       return pos;
6928 +}
6929 +
6930 +static void seq_SkbFree_stop(struct seq_file *seq, void *v)
6931 +{
6932 +       /* Nothing to do */
6933 +}
6934 +
6935 +static int seq_SkbFree_show(struct seq_file *seq, void *v)
6936 +{
6937 +       int i = *(loff_t *) v;
6938 +       END_DEVICE *ei_local = netdev_priv(dev_raether);
6939 +
6940 +       seq_printf(seq, "%d: %08x\n",i,  *(int *)&ei_local->skb_free[i]);
6941 +
6942 +       return 0;
6943 +}
6944 +
6945 +static const struct seq_operations seq_skb_free_ops = {
6946 +       .start = seq_SkbFree_start,
6947 +       .next  = seq_SkbFree_next,
6948 +       .stop  = seq_SkbFree_stop,
6949 +       .show  = seq_SkbFree_show
6950 +};
6951 +
6952 +static int skb_free_open(struct inode *inode, struct file *file)
6953 +{
6954 +       return seq_open(file, &seq_skb_free_ops);
6955 +}
6956 +
6957 +static const struct file_operations skb_free_fops = {
6958 +       .owner          = THIS_MODULE,
6959 +       .open           = skb_free_open,
6960 +       .read           = seq_read,
6961 +       .llseek         = seq_lseek,
6962 +       .release        = seq_release
6963 +};
6964 +
6965 +#if defined (CONFIG_RAETH_QDMA)
6966 +int QDMARead(struct seq_file *seq, void *v)
6967 +{
6968 +       unsigned int temp,i;
6969 +       unsigned int sw_fq, hw_fq;
6970 +       unsigned int min_en, min_rate, max_en, max_rate, sch, weight;
6971 +       unsigned int queue, tx_des_cnt, hw_resv, sw_resv, queue_head, queue_tail;
6972 +       struct net_device *dev = dev_raether;
6973 +        END_DEVICE *ei_local = netdev_priv(dev);
6974 +
6975 +       seq_printf(seq, "==== General Information ====\n");
6976 +       temp = sysRegRead(QDMA_FQ_CNT);
6977 +       sw_fq = (temp&0xFFFF0000)>>16;
6978 +       hw_fq = (temp&0x0000FFFF);
6979 +       seq_printf(seq, "SW TXD: %d/%d; HW TXD: %d/%d\n", sw_fq, NUM_TX_DESC, hw_fq,NUM_QDMA_PAGE);
6980 +       seq_printf(seq, "SW TXD virtual start address: 0x%08x\n", ei_local->txd_pool);
6981 +       seq_printf(seq, "HW TXD virtual start address: 0x%08x\n\n", free_head);
6982 +
6983 +       seq_printf(seq, "==== Scheduler Information ====\n");
6984 +       temp = sysRegRead(QDMA_TX_SCH);
6985 +       max_en = (temp&0x00000800)>>11;
6986 +       max_rate = (temp&0x000007F0)>>4;
6987 +       for(i=0;i<(temp&0x0000000F);i++)
6988 +               max_rate *= 10;
6989 +       seq_printf(seq, "SCH1 rate control:%d. Rate is %dKbps.\n", max_en, max_rate);
6990 +       max_en = (temp&0x08000000)>>27;
6991 +       max_rate = (temp&0x07F00000)>>20;
6992 +       for(i=0;i<(temp&0x000F0000);i++)
6993 +               max_rate *= 10;
6994 +       seq_printf(seq, "SCH2 rate control:%d. Rate is %dKbps.\n\n", max_en, max_rate);
6995 +
6996 +       seq_printf(seq, "==== Physical Queue Information ====\n");
6997 +       for (queue = 0; queue < 16; queue++){
6998 +               temp = sysRegRead(QTX_CFG_0 + 0x10 * queue);
6999 +               tx_des_cnt = (temp & 0xffff0000) >> 16;
7000 +               hw_resv = (temp & 0xff00) >> 8;
7001 +               sw_resv = (temp & 0xff);
7002 +               temp = sysRegRead(QTX_CFG_0 +(0x10 * queue) + 0x4);
7003 +               sch = (temp >> 31) + 1 ;
7004 +               min_en = (temp & 0x8000000) >> 27;
7005 +               min_rate = (temp & 0x7f00000) >> 20;
7006 +               for (i = 0; i< (temp & 0xf0000) >> 16; i++)
7007 +                       min_rate *= 10;
7008 +               max_en = (temp & 0x800) >> 11;
7009 +               max_rate = (temp & 0x7f0) >> 4;
7010 +               for (i = 0; i< (temp & 0xf); i++)
7011 +                       max_rate *= 10;
7012 +               weight = (temp & 0xf000) >> 12;
7013 +               queue_head = sysRegRead(QTX_HEAD_0 + 0x10 * queue);
7014 +               queue_tail = sysRegRead(QTX_TAIL_0 + 0x10 * queue);
7015 +
7016 +               seq_printf(seq, "Queue#%d Information:\n", queue);
7017 +               seq_printf(seq, "%d packets in the queue; head address is 0x%08x, tail address is 0x%08x.\n", tx_des_cnt, queue_head, queue_tail);
7018 +               seq_printf(seq, "HW_RESV: %d; SW_RESV: %d; SCH: %d; Weighting: %d\n", hw_resv, sw_resv, sch, weight);
7019 +               seq_printf(seq, "Min_Rate_En is %d, Min_Rate is %dKbps; Max_Rate_En is %d, Max_Rate is %dKbps.\n\n", min_en, min_rate, max_en, max_rate);
7020 +       }
7021 +#if defined (CONFIG_ARCH_MT7623) && defined(CONFIG_HW_SFQ)
7022 +       seq_printf(seq, "==== Virtual Queue Information ====\n");
7023 +       seq_printf(seq, "VQTX_TB_BASE_0:0x%08x;VQTX_TB_BASE_1:0x%08x;VQTX_TB_BASE_2:0x%08x;VQTX_TB_BASE_3:0x%08x\n", \
7024 +                       sfq0, sfq1, sfq2, sfq3);
7025 +       temp = sysRegRead(VQTX_NUM);
7026 +       seq_printf(seq, "VQTX_NUM_0:0x%01x;VQTX_NUM_1:0x%01x;VQTX_NUM_2:0x%01x;VQTX_NUM_3:0x%01x\n\n", \
7027 +                       temp&0xF, (temp&0xF0)>>4, (temp&0xF00)>>8, (temp&0xF000)>>12);
7028 +
7029 +#endif
7030 +
7031 +       seq_printf(seq, "==== Flow Control Information ====\n");
7032 +       temp = sysRegRead(QDMA_FC_THRES);
7033 +       seq_printf(seq, "SW_DROP_EN:%x; SW_DROP_FFA:%d; SW_DROP_MODE:%d\n", \
7034 +                       (temp&0x1000000)>>24, (temp&0x200000)>>25, (temp&0x30000000)>>28);
7035 +       seq_printf(seq, "WH_DROP_EN:%x; HW_DROP_FFA:%d; HW_DROP_MODE:%d\n", \
7036 +                       (temp&0x10000)>>16, (temp&0x2000)>>17, (temp&0x300000)>>20);
7037 +#if defined (CONFIG_ARCH_MT7623)
7038 +       seq_printf(seq, "SW_DROP_FSTVQ_MODE:%d;SW_DROP_FSTVQ:%d\n", \
7039 +                       (temp&0xC0000000)>>30, (temp&0x08000000)>>27);
7040 +       seq_printf(seq, "HW_DROP_FSTVQ_MODE:%d;HW_DROP_FSTVQ:%d\n", \
7041 +                       (temp&0xC00000)>>22, (temp&0x080000)>>19);
7042 +#endif
7043 +
7044 +       seq_printf(seq, "\n==== FSM Information\n");
7045 +       temp = sysRegRead(QDMA_DMA);
7046 +#if defined (CONFIG_ARCH_MT7623)
7047 +       seq_printf(seq, "VQTB_FSM:0x%01x\n", (temp&0x0F000000)>>24);
7048 +#endif
7049 +       seq_printf(seq, "FQ_FSM:0x%01x\n", (temp&0x000F0000)>>16);
7050 +       seq_printf(seq, "TX_FSM:0x%01x\n", (temp&0x00000F00)>>12);
7051 +       seq_printf(seq, "RX_FSM:0x%01x\n\n", (temp&0x0000000f));
7052 +
7053 +       seq_printf(seq, "==== M2Q Information ====\n");
7054 +       for (i = 0; i < 64; i+=8){
7055 +               seq_printf(seq, " (%d,%d)(%d,%d)(%d,%d)(%d,%d)(%d,%d)(%d,%d)(%d,%d)(%d,%d)\n",
7056 +                               i, M2Q_table[i], i+1, M2Q_table[i+1], i+2, M2Q_table[i+2], i+3, M2Q_table[i+3],
7057 +                               i+4, M2Q_table[i+4], i+5, M2Q_table[i+5], i+6, M2Q_table[i+6], i+7, M2Q_table[i+7]);
7058 +       }
7059 +
7060 +       return 0;
7061 +
7062 +}
7063 +
7064 +static int qdma_open(struct inode *inode, struct file *file)
7065 +{
7066 +       return single_open(file, QDMARead, NULL);
7067 +}
7068 +
7069 +static const struct file_operations qdma_fops = {
7070 +       .owner          = THIS_MODULE,
7071 +       .open           = qdma_open,
7072 +       .read           = seq_read,
7073 +       .llseek         = seq_lseek,
7074 +       .release        = single_release
7075 +};
7076 +#endif
7077 +
7078 +int TxRingRead(struct seq_file *seq, void *v)
7079 +{
7080 +       END_DEVICE *ei_local = netdev_priv(dev_raether);
7081 +       struct PDMA_txdesc *tx_ring;
7082 +       int i = 0;
7083 +
7084 +       tx_ring = kmalloc(sizeof(struct PDMA_txdesc) * NUM_TX_DESC, GFP_KERNEL);
7085 +        if(tx_ring==NULL){
7086 +               seq_printf(seq, " allocate temp tx_ring fail.\n");
7087 +               return 0;
7088 +       }
7089 +
7090 +       for (i=0; i < NUM_TX_DESC; i++) {
7091 +               tx_ring[i] = ei_local->tx_ring0[i];
7092 +        }
7093 +
7094 +       for (i=0; i < NUM_TX_DESC; i++) {
7095 +#ifdef CONFIG_32B_DESC
7096 +               seq_printf(seq, "%d: %08x %08x %08x %08x %08x %08x %08x %08x\n",i,  *(int *)&tx_ring[i].txd_info1,
7097 +                               *(int *)&tx_ring[i].txd_info2, *(int *)&tx_ring[i].txd_info3,
7098 +                               *(int *)&tx_ring[i].txd_info4, *(int *)&tx_ring[i].txd_info5,
7099 +                               *(int *)&tx_ring[i].txd_info6, *(int *)&tx_ring[i].txd_info7,
7100 +                               *(int *)&tx_ring[i].txd_info8);
7101 +#else
7102 +               seq_printf(seq, "%d: %08x %08x %08x %08x\n",i,  *(int *)&tx_ring[i].txd_info1, *(int *)&tx_ring[i].txd_info2,
7103 +                               *(int *)&tx_ring[i].txd_info3, *(int *)&tx_ring[i].txd_info4);
7104 +#endif
7105 +       }
7106 +
7107 +       kfree(tx_ring);
7108 +       return 0;
7109 +}
7110 +
7111 +static int tx_ring_open(struct inode *inode, struct file *file)
7112 +{
7113 +#if !defined (CONFIG_RAETH_QDMA)
7114 +       return single_open(file, TxRingRead, NULL);
7115 +#else
7116 +       return single_open(file, QDMARead, NULL);
7117 +#endif
7118 +}
7119 +
7120 +static const struct file_operations tx_ring_fops = {
7121 +       .owner          = THIS_MODULE,
7122 +       .open           = tx_ring_open,
7123 +       .read           = seq_read,
7124 +       .llseek         = seq_lseek,
7125 +       .release        = single_release
7126 +};
7127 +
7128 +int RxRingRead(struct seq_file *seq, void *v)
7129 +{
7130 +       END_DEVICE *ei_local = netdev_priv(dev_raether);
7131 +       struct PDMA_rxdesc *rx_ring;
7132 +       int i = 0;
7133 +
7134 +       rx_ring = kmalloc(sizeof(struct PDMA_rxdesc) * NUM_RX_DESC, GFP_KERNEL);
7135 +       if(rx_ring==NULL){
7136 +               seq_printf(seq, " allocate temp rx_ring fail.\n");
7137 +               return 0;
7138 +       }
7139 +
7140 +       for (i=0; i < NUM_RX_DESC; i++) {
7141 +               memcpy(&rx_ring[i], &ei_local->rx_ring0[i], sizeof(struct PDMA_rxdesc));
7142 +       }
7143 +
7144 +       for (i=0; i < NUM_RX_DESC; i++) {
7145 +#ifdef CONFIG_32B_DESC
7146 +               seq_printf(seq, "%d: %08x %08x %08x %08x %08x %08x %08x %08x\n",i,  *(int *)&rx_ring[i].rxd_info1,
7147 +                               *(int *)&rx_ring[i].rxd_info2, *(int *)&rx_ring[i].rxd_info3,
7148 +                               *(int *)&rx_ring[i].rxd_info4, *(int *)&rx_ring[i].rxd_info5,
7149 +                               *(int *)&rx_ring[i].rxd_info6, *(int *)&rx_ring[i].rxd_info7,
7150 +                               *(int *)&rx_ring[i].rxd_info8);
7151 +#else
7152 +               seq_printf(seq, "%d: %08x %08x %08x %08x\n",i,  *(int *)&rx_ring[i].rxd_info1, *(int *)&rx_ring[i].rxd_info2,
7153 +                               *(int *)&rx_ring[i].rxd_info3, *(int *)&rx_ring[i].rxd_info4);
7154 +#endif
7155 +        }
7156 +
7157 +       kfree(rx_ring);
7158 +       return 0;
7159 +}
7160 +
7161 +static int rx_ring_open(struct inode *inode, struct file *file)
7162 +{
7163 +       return single_open(file, RxRingRead, NULL);
7164 +}
7165 +
7166 +static const struct file_operations rx_ring_fops = {
7167 +       .owner          = THIS_MODULE,
7168 +       .open           = rx_ring_open,
7169 +       .read           = seq_read,
7170 +       .llseek         = seq_lseek,
7171 +       .release        = single_release
7172 +};
7173 +
7174 +#if defined(CONFIG_RAETH_HW_LRO) || defined (CONFIG_RAETH_MULTIPLE_RX_RING)
7175 +int RxLRORingRead(struct seq_file *seq, void *v, struct PDMA_rxdesc *rx_ring_p)
7176 +{
7177 +       struct PDMA_rxdesc *rx_ring;
7178 +       int i = 0;
7179 +
7180 +       rx_ring = kmalloc(sizeof(struct PDMA_rxdesc) * NUM_LRO_RX_DESC, GFP_KERNEL);
7181 +       if(rx_ring==NULL){
7182 +               seq_printf(seq, " allocate temp rx_ring fail.\n");
7183 +               return 0;
7184 +       }
7185 +
7186 +       for (i=0; i < NUM_LRO_RX_DESC; i++) {
7187 +               memcpy(&rx_ring[i], &rx_ring_p[i], sizeof(struct PDMA_rxdesc));
7188 +       }
7189 +
7190 +       for (i=0; i < NUM_LRO_RX_DESC; i++) {
7191 +#ifdef CONFIG_32B_DESC
7192 +               seq_printf(seq, "%d: %08x %08x %08x %08x %08x %08x %08x %08x\n",i,  *(int *)&rx_ring[i].rxd_info1,
7193 +                               *(int *)&rx_ring[i].rxd_info2, *(int *)&rx_ring[i].rxd_info3,
7194 +                               *(int *)&rx_ring[i].rxd_info4, *(int *)&rx_ring[i].rxd_info5,
7195 +                               *(int *)&rx_ring[i].rxd_info6, *(int *)&rx_ring[i].rxd_info7,
7196 +                               *(int *)&rx_ring[i].rxd_info8);
7197 +#else
7198 +               seq_printf(seq, "%d: %08x %08x %08x %08x\n",i,  *(int *)&rx_ring[i].rxd_info1, *(int *)&rx_ring[i].rxd_info2,
7199 +                               *(int *)&rx_ring[i].rxd_info3, *(int *)&rx_ring[i].rxd_info4);
7200 +#endif
7201 +    }
7202 +
7203 +       kfree(rx_ring);
7204 +       return 0;
7205 +}
7206 +
7207 +int RxRing1Read(struct seq_file *seq, void *v)
7208 +{
7209 +       END_DEVICE *ei_local = netdev_priv(dev_raether);
7210 +    RxLRORingRead(seq, v, ei_local->rx_ring1);
7211 +
7212 +    return 0;
7213 +}
7214 +
7215 +int RxRing2Read(struct seq_file *seq, void *v)
7216 +{
7217 +       END_DEVICE *ei_local = netdev_priv(dev_raether);
7218 +    RxLRORingRead(seq, v, ei_local->rx_ring2);
7219 +
7220 +    return 0;
7221 +}
7222 +
7223 +int RxRing3Read(struct seq_file *seq, void *v)
7224 +{
7225 +       END_DEVICE *ei_local = netdev_priv(dev_raether);
7226 +    RxLRORingRead(seq, v, ei_local->rx_ring3);
7227 +
7228 +    return 0;
7229 +}
7230 +
7231 +static int rx_ring1_open(struct inode *inode, struct file *file)
7232 +{
7233 +       return single_open(file, RxRing1Read, NULL);
7234 +}
7235 +
7236 +static int rx_ring2_open(struct inode *inode, struct file *file)
7237 +{
7238 +       return single_open(file, RxRing2Read, NULL);
7239 +}
7240 +
7241 +static int rx_ring3_open(struct inode *inode, struct file *file)
7242 +{
7243 +       return single_open(file, RxRing3Read, NULL);
7244 +}
7245 +
7246 +static const struct file_operations rx_ring1_fops = {
7247 +       .owner          = THIS_MODULE,
7248 +       .open           = rx_ring1_open,
7249 +       .read           = seq_read,
7250 +       .llseek         = seq_lseek,
7251 +       .release        = single_release
7252 +};
7253 +
7254 +static const struct file_operations rx_ring2_fops = {
7255 +       .owner          = THIS_MODULE,
7256 +       .open           = rx_ring2_open,
7257 +       .read           = seq_read,
7258 +       .llseek         = seq_lseek,
7259 +       .release        = single_release
7260 +};
7261 +
7262 +static const struct file_operations rx_ring3_fops = {
7263 +       .owner          = THIS_MODULE,
7264 +       .open           = rx_ring3_open,
7265 +       .read           = seq_read,
7266 +       .llseek         = seq_lseek,
7267 +       .release        = single_release
7268 +};
7269 +#endif  /* CONFIG_RAETH_HW_LRO */
7270 +
7271 +#if defined(CONFIG_RAETH_TSO)
7272 +
7273 +int NumOfTxdUpdate(int num_of_txd)
7274 +{
7275 +
7276 +       txd_cnt[num_of_txd]++;
7277 +
7278 +       return 0;
7279 +}
7280 +
7281 +static void *seq_TsoTxdNum_start(struct seq_file *seq, loff_t *pos)
7282 +{
7283 +       seq_printf(seq, "TXD | Count\n");
7284 +       if (*pos < (MAX_SKB_FRAGS/2 + 1))
7285 +               return pos;
7286 +       return NULL;
7287 +}
7288 +
7289 +static void *seq_TsoTxdNum_next(struct seq_file *seq, void *v, loff_t *pos)
7290 +{
7291 +       (*pos)++;
7292 +       if (*pos >= (MAX_SKB_FRAGS/2 + 1))
7293 +               return NULL;
7294 +       return pos;
7295 +}
7296 +
7297 +static void seq_TsoTxdNum_stop(struct seq_file *seq, void *v)
7298 +{
7299 +       /* Nothing to do */
7300 +}
7301 +
7302 +static int seq_TsoTxdNum_show(struct seq_file *seq, void *v)
7303 +{
7304 +       int i = *(loff_t *) v;
7305 +       seq_printf(seq, "%d: %d\n",i , txd_cnt[i]);
7306 +
7307 +       return 0;
7308 +}
7309 +
7310 +ssize_t NumOfTxdWrite(struct file *file, const char __user *buffer,
7311 +                     size_t count, loff_t *data)
7312 +{
7313 +       memset(txd_cnt, 0, sizeof(txd_cnt));
7314 +        printk("clear txd cnt table\n");
7315 +
7316 +       return count;
7317 +}
7318 +
7319 +int TsoLenUpdate(int tso_len)
7320 +{
7321 +
7322 +       if(tso_len > 70000) {
7323 +               tso_cnt[14]++;
7324 +       }else if(tso_len >  65000) {
7325 +               tso_cnt[13]++;
7326 +       }else if(tso_len >  60000) {
7327 +               tso_cnt[12]++;
7328 +       }else if(tso_len >  55000) {
7329 +               tso_cnt[11]++;
7330 +       }else if(tso_len >  50000) {
7331 +               tso_cnt[10]++;
7332 +       }else if(tso_len >  45000) {
7333 +               tso_cnt[9]++;
7334 +       }else if(tso_len > 40000) {
7335 +               tso_cnt[8]++;
7336 +       }else if(tso_len > 35000) {
7337 +               tso_cnt[7]++;
7338 +       }else if(tso_len > 30000) {
7339 +               tso_cnt[6]++;
7340 +       }else if(tso_len > 25000) {
7341 +               tso_cnt[5]++;
7342 +       }else if(tso_len > 20000) {
7343 +               tso_cnt[4]++;
7344 +       }else if(tso_len > 15000) {
7345 +               tso_cnt[3]++;
7346 +       }else if(tso_len > 10000) {
7347 +               tso_cnt[2]++;
7348 +       }else if(tso_len > 5000) {
7349 +               tso_cnt[1]++;
7350 +       }else {
7351 +               tso_cnt[0]++;
7352 +       }
7353 +
7354 +       return 0;
7355 +}
7356 +
7357 +ssize_t TsoLenWrite(struct file *file, const char __user *buffer,
7358 +                   size_t count, loff_t *data)
7359 +{
7360 +       memset(tso_cnt, 0, sizeof(tso_cnt));
7361 +        printk("clear tso cnt table\n");
7362 +
7363 +       return count;
7364 +}
7365 +
7366 +static void *seq_TsoLen_start(struct seq_file *seq, loff_t *pos)
7367 +{
7368 +       seq_printf(seq, " Length  | Count\n");
7369 +       if (*pos < 15)
7370 +               return pos;
7371 +       return NULL;
7372 +}
7373 +
7374 +static void *seq_TsoLen_next(struct seq_file *seq, void *v, loff_t *pos)
7375 +{
7376 +       (*pos)++;
7377 +       if (*pos >= 15)
7378 +               return NULL;
7379 +       return pos;
7380 +}
7381 +
7382 +static void seq_TsoLen_stop(struct seq_file *seq, void *v)
7383 +{
7384 +       /* Nothing to do */
7385 +}
7386 +
7387 +static int seq_TsoLen_show(struct seq_file *seq, void *v)
7388 +{
7389 +       int i = *(loff_t *) v;
7390 +
7391 +       seq_printf(seq, "%d~%d: %d\n", i*5000, (i+1)*5000, tso_cnt[i]);
7392 +
7393 +       return 0;
7394 +}
7395 +
7396 +static const struct seq_operations seq_tso_txd_num_ops = {
7397 +       .start = seq_TsoTxdNum_start,
7398 +       .next  = seq_TsoTxdNum_next,
7399 +       .stop  = seq_TsoTxdNum_stop,
7400 +       .show  = seq_TsoTxdNum_show
7401 +};
7402 +
7403 +static int tso_txd_num_open(struct inode *inode, struct file *file)
7404 +{
7405 +       return seq_open(file, &seq_tso_txd_num_ops);
7406 +}
7407 +
7408 +static struct file_operations tso_txd_num_fops = {
7409 +       .owner          = THIS_MODULE,
7410 +       .open           = tso_txd_num_open,
7411 +       .read           = seq_read,
7412 +       .llseek         = seq_lseek,
7413 +       .write          = NumOfTxdWrite,
7414 +       .release        = seq_release
7415 +};
7416 +
7417 +static const struct seq_operations seq_tso_len_ops = {
7418 +       .start = seq_TsoLen_start,
7419 +       .next  = seq_TsoLen_next,
7420 +       .stop  = seq_TsoLen_stop,
7421 +       .show  = seq_TsoLen_show
7422 +};
7423 +
7424 +static int tso_len_open(struct inode *inode, struct file *file)
7425 +{
7426 +       return seq_open(file, &seq_tso_len_ops);
7427 +}
7428 +
7429 +static struct file_operations tso_len_fops = {
7430 +       .owner          = THIS_MODULE,
7431 +       .open           = tso_len_open,
7432 +       .read           = seq_read,
7433 +       .llseek         = seq_lseek,
7434 +       .write          = TsoLenWrite,
7435 +       .release        = seq_release
7436 +};
7437 +#endif
7438 +
7439 +#if defined(CONFIG_RAETH_LRO)
7440 +static int LroLenUpdate(struct net_lro_desc *lro_desc)
7441 +{
7442 +       int len_idx;
7443 +
7444 +       if(lro_desc->ip_tot_len > 65000) {
7445 +               len_idx = 13;
7446 +       }else if(lro_desc->ip_tot_len > 60000) {
7447 +               len_idx = 12;
7448 +       }else if(lro_desc->ip_tot_len > 55000) {
7449 +               len_idx = 11;
7450 +       }else if(lro_desc->ip_tot_len > 50000) {
7451 +               len_idx = 10;
7452 +       }else if(lro_desc->ip_tot_len > 45000) {
7453 +               len_idx = 9;
7454 +       }else if(lro_desc->ip_tot_len > 40000) {
7455 +               len_idx = 8;
7456 +       }else if(lro_desc->ip_tot_len > 35000) {
7457 +               len_idx = 7;
7458 +       }else if(lro_desc->ip_tot_len > 30000) {
7459 +               len_idx = 6;
7460 +       }else if(lro_desc->ip_tot_len > 25000) {
7461 +               len_idx = 5;
7462 +       }else if(lro_desc->ip_tot_len > 20000) {
7463 +               len_idx = 4;
7464 +       }else if(lro_desc->ip_tot_len > 15000) {
7465 +               len_idx = 3;
7466 +       }else if(lro_desc->ip_tot_len > 10000) {
7467 +               len_idx = 2;
7468 +       }else if(lro_desc->ip_tot_len > 5000) {
7469 +               len_idx = 1;
7470 +       }else {
7471 +               len_idx = 0;
7472 +       }
7473 +
7474 +       return len_idx;
7475 +}
7476 +int LroStatsUpdate(struct net_lro_mgr *lro_mgr, bool all_flushed)
7477 +{
7478 +       struct net_lro_desc *tmp;
7479 +       int len_idx;
7480 +       int i, j;
7481 +
7482 +       if (all_flushed) {
7483 +               for (i=0; i< MAX_DESC; i++) {
7484 +                       tmp = & lro_mgr->lro_arr[i];
7485 +                       if (tmp->pkt_aggr_cnt !=0) {
7486 +                               for(j=0; j<=MAX_AGGR; j++) {
7487 +                                       if(tmp->pkt_aggr_cnt == j) {
7488 +                                               lro_flush_cnt[j]++;
7489 +                                       }
7490 +                               }
7491 +                               len_idx = LroLenUpdate(tmp);
7492 +                               lro_len_cnt1[len_idx]++;
7493 +                               tot_called1++;
7494 +                       }
7495 +                       aggregated[i] = 0;
7496 +               }
7497 +       } else {
7498 +               if (lro_flushed != lro_mgr->stats.flushed) {
7499 +                       if (lro_aggregated != lro_mgr->stats.aggregated) {
7500 +                               for (i=0; i<MAX_DESC; i++) {
7501 +                                       tmp = &lro_mgr->lro_arr[i];
7502 +                                       if ((aggregated[i]!= tmp->pkt_aggr_cnt)
7503 +                                                       && (tmp->pkt_aggr_cnt == 0)) {
7504 +                                               aggregated[i] ++;
7505 +                                               for (j=0; j<=MAX_AGGR; j++) {
7506 +                                                       if (aggregated[i] == j) {
7507 +                                                               lro_stats_cnt[j] ++;
7508 +                                                       }
7509 +                                               }
7510 +                                               aggregated[i] = 0;
7511 +                                               //len_idx = LroLenUpdate(tmp);
7512 +                                               //lro_len_cnt2[len_idx]++;
7513 +                                               tot_called2++;
7514 +                                       }
7515 +                               }
7516 +                       } else {
7517 +                               for (i=0; i<MAX_DESC; i++) {
7518 +                                       tmp = &lro_mgr->lro_arr[i];
7519 +                                       if ((aggregated[i] != 0) && (tmp->pkt_aggr_cnt==0)) {
7520 +                                               for (j=0; j<=MAX_AGGR; j++) {
7521 +                                                       if (aggregated[i] == j) {
7522 +                                                               lro_stats_cnt[j] ++;
7523 +                                                       }
7524 +                                               }
7525 +                                               aggregated[i] = 0;
7526 +                                               //len_idx = LroLenUpdate(tmp);
7527 +                                               //lro_len_cnt2[len_idx]++;
7528 +                                               force_flush ++;
7529 +                                               tot_called2++;
7530 +                                       }
7531 +                               }
7532 +                       }
7533 +               } else {
7534 +                       if (lro_aggregated != lro_mgr->stats.aggregated) {
7535 +                               for (i=0; i<MAX_DESC; i++) {
7536 +                                       tmp = &lro_mgr->lro_arr[i];
7537 +                                       if (tmp->active) {
7538 +                                               if (aggregated[i] != tmp->pkt_aggr_cnt)
7539 +                                                       aggregated[i] = tmp->pkt_aggr_cnt;
7540 +                                       } else
7541 +                                               aggregated[i] = 0;
7542 +                               }
7543 +                       }
7544 +               }
7545 +
7546 +       }
7547 +
7548 +       lro_aggregated = lro_mgr->stats.aggregated;
7549 +       lro_flushed = lro_mgr->stats.flushed;
7550 +       lro_nodesc = lro_mgr->stats.no_desc;
7551 +
7552 +       return 0;
7553 +
7554 +}
7555 +
7556 +
7557 +ssize_t LroStatsWrite(struct file *file, const char __user *buffer,
7558 +                     size_t count, loff_t *data)
7559 +{
7560 +       memset(lro_stats_cnt, 0, sizeof(lro_stats_cnt));
7561 +       memset(lro_flush_cnt, 0, sizeof(lro_flush_cnt));
7562 +       memset(lro_len_cnt1, 0, sizeof(lro_len_cnt1));
7563 +       //memset(lro_len_cnt2, 0, sizeof(lro_len_cnt2));
7564 +       memset(aggregated, 0, sizeof(aggregated));
7565 +       lro_aggregated = 0;
7566 +       lro_flushed = 0;
7567 +       lro_nodesc = 0;
7568 +       force_flush = 0;
7569 +       tot_called1 = 0;
7570 +       tot_called2 = 0;
7571 +        printk("clear lro  cnt table\n");
7572 +
7573 +       return count;
7574 +}
7575 +
7576 +int LroStatsRead(struct seq_file *seq, void *v)
7577 +{
7578 +       int i;
7579 +       int tot_cnt=0;
7580 +       int tot_aggr=0;
7581 +       int ave_aggr=0;
7582 +
7583 +       seq_printf(seq, "LRO statistic dump:\n");
7584 +       seq_printf(seq, "Cnt:   Kernel | Driver\n");
7585 +       for(i=0; i<=MAX_AGGR; i++) {
7586 +               tot_cnt = tot_cnt + lro_stats_cnt[i] + lro_flush_cnt[i];
7587 +               seq_printf(seq, " %d :      %d        %d\n", i, lro_stats_cnt[i], lro_flush_cnt[i]);
7588 +               tot_aggr = tot_aggr + i * (lro_stats_cnt[i] + lro_flush_cnt[i]);
7589 +       }
7590 +       ave_aggr = lro_aggregated/lro_flushed;
7591 +       seq_printf(seq, "Total aggregated pkt: %d\n", lro_aggregated);
7592 +       seq_printf(seq, "Flushed pkt: %d  %d\n", lro_flushed, force_flush);
7593 +       seq_printf(seq, "Average flush cnt:  %d\n", ave_aggr);
7594 +       seq_printf(seq, "No descriptor pkt: %d\n\n\n", lro_nodesc);
7595 +
7596 +       seq_printf(seq, "Driver flush pkt len:\n");
7597 +       seq_printf(seq, " Length  | Count\n");
7598 +       for(i=0; i<15; i++) {
7599 +               seq_printf(seq, "%d~%d: %d\n", i*5000, (i+1)*5000, lro_len_cnt1[i]);
7600 +       }
7601 +       seq_printf(seq, "Kernel flush: %d;  Driver flush: %d\n", tot_called2, tot_called1);
7602 +       return 0;
7603 +}
7604 +
7605 +static int lro_stats_open(struct inode *inode, struct file *file)
7606 +{
7607 +       return single_open(file, LroStatsRead, NULL);
7608 +}
7609 +
7610 +static struct file_operations lro_stats_fops = {
7611 +       .owner          = THIS_MODULE,
7612 +       .open           = lro_stats_open,
7613 +       .read           = seq_read,
7614 +       .llseek         = seq_lseek,
7615 +       .write          = LroStatsWrite,
7616 +       .release        = single_release
7617 +};
7618 +#endif
7619 +
7620 +int getnext(const char *src, int separator, char *dest)
7621 +{
7622 +    char *c;
7623 +    int len;
7624 +
7625 +    if ( (src == NULL) || (dest == NULL) ) {
7626 +        return -1;
7627 +    }
7628 +
7629 +    c = strchr(src, separator);
7630 +    if (c == NULL) {
7631 +        strcpy(dest, src);
7632 +        return -1;
7633 +    }
7634 +    len = c - src;
7635 +    strncpy(dest, src, len);
7636 +    dest[len] = '\0';
7637 +    return len + 1;
7638 +}
7639 +
7640 +int str_to_ip(unsigned int *ip, const char *str)
7641 +{
7642 +    int len;
7643 +    const char *ptr = str;
7644 +    char buf[128];
7645 +    unsigned char c[4];
7646 +    int i;
7647 +
7648 +    for (i = 0; i < 3; ++i) {
7649 +        if ((len = getnext(ptr, '.', buf)) == -1) {
7650 +            return 1; /* parse error */
7651 +        }
7652 +        c[i] = simple_strtoul(buf, NULL, 10);
7653 +        ptr += len;
7654 +    }
7655 +    c[3] = simple_strtoul(ptr, NULL, 0);
7656 +    *ip = (c[0]<<24) + (c[1]<<16) + (c[2]<<8) + c[3];
7657 +    return 0;
7658 +}
7659 +
7660 +#if defined(CONFIG_RAETH_HW_LRO)
7661 +static int HwLroLenUpdate(unsigned int agg_size)
7662 +{
7663 +       int len_idx;
7664 +
7665 +       if(agg_size > 65000) {
7666 +               len_idx = 13;
7667 +       }else if(agg_size > 60000) {
7668 +               len_idx = 12;
7669 +       }else if(agg_size > 55000) {
7670 +               len_idx = 11;
7671 +       }else if(agg_size > 50000) {
7672 +               len_idx = 10;
7673 +       }else if(agg_size > 45000) {
7674 +               len_idx = 9;
7675 +       }else if(agg_size > 40000) {
7676 +               len_idx = 8;
7677 +       }else if(agg_size > 35000) {
7678 +               len_idx = 7;
7679 +       }else if(agg_size > 30000) {
7680 +               len_idx = 6;
7681 +       }else if(agg_size > 25000) {
7682 +               len_idx = 5;
7683 +       }else if(agg_size > 20000) {
7684 +               len_idx = 4;
7685 +       }else if(agg_size > 15000) {
7686 +               len_idx = 3;
7687 +       }else if(agg_size > 10000) {
7688 +               len_idx = 2;
7689 +       }else if(agg_size > 5000) {
7690 +               len_idx = 1;
7691 +       }else {
7692 +               len_idx = 0;
7693 +       }
7694 +
7695 +       return len_idx;
7696 +}
7697 +
7698 +int HwLroStatsUpdate(unsigned int ring_num, unsigned int agg_cnt, unsigned int agg_size)
7699 +{
7700 +    if( (ring_num > 0) && (ring_num < 4) )
7701 +    {
7702 +        hw_lro_agg_size_cnt[ring_num-1][HwLroLenUpdate(agg_size)]++;
7703 +        hw_lro_agg_num_cnt[ring_num-1][agg_cnt]++;
7704 +        hw_lro_tot_flush_cnt[ring_num-1]++;
7705 +        hw_lro_tot_agg_cnt[ring_num-1] += agg_cnt;
7706 +    }
7707 +
7708 +    return 0;
7709 +}
7710 +
7711 +#if defined(CONFIG_RAETH_HW_LRO_REASON_DBG)
7712 +int HwLroFlushStatsUpdate(unsigned int ring_num, unsigned int flush_reason)
7713 +{
7714 +    if( (ring_num > 0) && (ring_num < 4) )
7715 +    {
7716 +#if 1
7717 +        if ( (flush_reason & 0x7) == HW_LRO_AGG_FLUSH )
7718 +            hw_lro_agg_flush_cnt[ring_num-1]++;
7719 +        else if ( (flush_reason & 0x7) == HW_LRO_AGE_FLUSH )
7720 +            hw_lro_age_flush_cnt[ring_num-1]++;
7721 +        else if ( (flush_reason & 0x7) == HW_LRO_NOT_IN_SEQ_FLUSH )
7722 +            hw_lro_seq_flush_cnt[ring_num-1]++;
7723 +        else if ( (flush_reason & 0x7) == HW_LRO_TIMESTAMP_FLUSH )
7724 +            hw_lro_timestamp_flush_cnt[ring_num-1]++;
7725 +        else if ( (flush_reason & 0x7) == HW_LRO_NON_RULE_FLUSH )
7726 +            hw_lro_norule_flush_cnt[ring_num-1]++;
7727 +#else
7728 +        if ( flush_reason & BIT(4) )
7729 +            hw_lro_agg_flush_cnt[ring_num-1]++;
7730 +        else if ( flush_reason & BIT(3) )
7731 +            hw_lro_age_flush_cnt[ring_num-1]++;
7732 +        else if ( flush_reason & BIT(2) )
7733 +            hw_lro_seq_flush_cnt[ring_num-1]++;
7734 +        else if ( flush_reason & BIT(1) )
7735 +            hw_lro_timestamp_flush_cnt[ring_num-1]++;
7736 +        else if ( flush_reason & BIT(0) )
7737 +            hw_lro_norule_flush_cnt[ring_num-1]++;
7738 +#endif
7739 +    }
7740 +
7741 +    return 0;
7742 +}
7743 +#endif  /* CONFIG_RAETH_HW_LRO_REASON_DBG */
7744 +
7745 +ssize_t HwLroStatsWrite(struct file *file, const char __user *buffer,
7746 +                     size_t count, loff_t *data)
7747 +{
7748 +    memset(hw_lro_agg_num_cnt, 0, sizeof(hw_lro_agg_num_cnt));
7749 +    memset(hw_lro_agg_size_cnt, 0, sizeof(hw_lro_agg_size_cnt));
7750 +    memset(hw_lro_tot_agg_cnt, 0, sizeof(hw_lro_tot_agg_cnt));
7751 +    memset(hw_lro_tot_flush_cnt, 0, sizeof(hw_lro_tot_flush_cnt));
7752 +#if defined(CONFIG_RAETH_HW_LRO_REASON_DBG)
7753 +    memset(hw_lro_agg_flush_cnt, 0, sizeof(hw_lro_agg_flush_cnt));
7754 +    memset(hw_lro_age_flush_cnt, 0, sizeof(hw_lro_age_flush_cnt));
7755 +    memset(hw_lro_seq_flush_cnt, 0, sizeof(hw_lro_seq_flush_cnt));
7756 +    memset(hw_lro_timestamp_flush_cnt, 0, sizeof(hw_lro_timestamp_flush_cnt));
7757 +    memset(hw_lro_norule_flush_cnt, 0, sizeof(hw_lro_norule_flush_cnt));
7758 +#endif  /* CONFIG_RAETH_HW_LRO_REASON_DBG */
7759 +
7760 +    printk("clear hw lro cnt table\n");
7761 +
7762 +       return count;
7763 +}
7764 +
7765 +int HwLroStatsRead(struct seq_file *seq, void *v)
7766 +{
7767 +       int i;
7768 +
7769 +       seq_printf(seq, "HW LRO statistic dump:\n");
7770 +
7771 +    /* Agg number count */
7772 +       seq_printf(seq, "Cnt:   RING1 | RING2 | RING3 | Total\n");
7773 +       for(i=0; i<=MAX_HW_LRO_AGGR; i++) {
7774 +               seq_printf(seq, " %d :      %d        %d        %d        %d\n",
7775 +            i, hw_lro_agg_num_cnt[0][i], hw_lro_agg_num_cnt[1][i], hw_lro_agg_num_cnt[2][i],
7776 +            hw_lro_agg_num_cnt[0][i]+hw_lro_agg_num_cnt[1][i]+hw_lro_agg_num_cnt[2][i]);
7777 +       }
7778 +
7779 +    /* Total agg count */
7780 +    seq_printf(seq, "Total agg:   RING1 | RING2 | RING3 | Total\n");
7781 +    seq_printf(seq, "                %d      %d      %d      %d\n",
7782 +        hw_lro_tot_agg_cnt[0], hw_lro_tot_agg_cnt[1], hw_lro_tot_agg_cnt[2],
7783 +        hw_lro_tot_agg_cnt[0]+hw_lro_tot_agg_cnt[1]+hw_lro_tot_agg_cnt[2]);
7784 +
7785 +    /* Total flush count */
7786 +    seq_printf(seq, "Total flush:   RING1 | RING2 | RING3 | Total\n");
7787 +    seq_printf(seq, "                %d      %d      %d      %d\n",
7788 +        hw_lro_tot_flush_cnt[0], hw_lro_tot_flush_cnt[1], hw_lro_tot_flush_cnt[2],
7789 +        hw_lro_tot_flush_cnt[0]+hw_lro_tot_flush_cnt[1]+hw_lro_tot_flush_cnt[2]);
7790 +
7791 +    /* Avg agg count */
7792 +    seq_printf(seq, "Avg agg:   RING1 | RING2 | RING3 | Total\n");
7793 +    seq_printf(seq, "                %d      %d      %d      %d\n",
7794 +        (hw_lro_tot_flush_cnt[0]) ? hw_lro_tot_agg_cnt[0]/hw_lro_tot_flush_cnt[0] : 0,
7795 +        (hw_lro_tot_flush_cnt[1]) ? hw_lro_tot_agg_cnt[1]/hw_lro_tot_flush_cnt[1] : 0,
7796 +        (hw_lro_tot_flush_cnt[2]) ? hw_lro_tot_agg_cnt[2]/hw_lro_tot_flush_cnt[2] : 0,
7797 +        (hw_lro_tot_flush_cnt[0]+hw_lro_tot_flush_cnt[1]+hw_lro_tot_flush_cnt[2]) ? \
7798 +        ((hw_lro_tot_agg_cnt[0]+hw_lro_tot_agg_cnt[1]+hw_lro_tot_agg_cnt[2])/(hw_lro_tot_flush_cnt[0]+hw_lro_tot_flush_cnt[1]+hw_lro_tot_flush_cnt[2])) : 0
7799 +    );
7800 +
7801 +    /*  Statistics of aggregation size counts */
7802 +       seq_printf(seq, "HW LRO flush pkt len:\n");
7803 +       seq_printf(seq, " Length  | RING1  | RING2  | RING3  | Total\n");
7804 +       for(i=0; i<15; i++) {
7805 +               seq_printf(seq, "%d~%d: %d      %d      %d      %d\n", i*5000, (i+1)*5000,
7806 +            hw_lro_agg_size_cnt[0][i], hw_lro_agg_size_cnt[1][i], hw_lro_agg_size_cnt[2][i],
7807 +            hw_lro_agg_size_cnt[0][i]+hw_lro_agg_size_cnt[1][i]+hw_lro_agg_size_cnt[2][i]);
7808 +       }
7809 +#if defined(CONFIG_RAETH_HW_LRO_REASON_DBG)
7810 +    seq_printf(seq, "Flush reason:   RING1 | RING2 | RING3 | Total\n");
7811 +    seq_printf(seq, "AGG timeout:      %d      %d      %d      %d\n",
7812 +        hw_lro_agg_flush_cnt[0], hw_lro_agg_flush_cnt[1], hw_lro_agg_flush_cnt[2],
7813 +        (hw_lro_agg_flush_cnt[0]+hw_lro_agg_flush_cnt[1]+hw_lro_agg_flush_cnt[2])
7814 +    );
7815 +    seq_printf(seq, "AGE timeout:      %d      %d      %d      %d\n",
7816 +        hw_lro_age_flush_cnt[0], hw_lro_age_flush_cnt[1], hw_lro_age_flush_cnt[2],
7817 +        (hw_lro_age_flush_cnt[0]+hw_lro_age_flush_cnt[1]+hw_lro_age_flush_cnt[2])
7818 +    );
7819 +    seq_printf(seq, "Not in-sequence:  %d      %d      %d      %d\n",
7820 +        hw_lro_seq_flush_cnt[0], hw_lro_seq_flush_cnt[1], hw_lro_seq_flush_cnt[2],
7821 +        (hw_lro_seq_flush_cnt[0]+hw_lro_seq_flush_cnt[1]+hw_lro_seq_flush_cnt[2])
7822 +    );
7823 +    seq_printf(seq, "Timestamp:        %d      %d      %d      %d\n",
7824 +        hw_lro_timestamp_flush_cnt[0], hw_lro_timestamp_flush_cnt[1], hw_lro_timestamp_flush_cnt[2],
7825 +        (hw_lro_timestamp_flush_cnt[0]+hw_lro_timestamp_flush_cnt[1]+hw_lro_timestamp_flush_cnt[2])
7826 +    );
7827 +    seq_printf(seq, "No LRO rule:      %d      %d      %d      %d\n",
7828 +        hw_lro_norule_flush_cnt[0], hw_lro_norule_flush_cnt[1], hw_lro_norule_flush_cnt[2],
7829 +        (hw_lro_norule_flush_cnt[0]+hw_lro_norule_flush_cnt[1]+hw_lro_norule_flush_cnt[2])
7830 +    );
7831 +#endif  /* CONFIG_RAETH_HW_LRO_REASON_DBG */
7832 +
7833 +       return 0;
7834 +}
7835 +
7836 +static int hw_lro_stats_open(struct inode *inode, struct file *file)
7837 +{
7838 +       return single_open(file, HwLroStatsRead, NULL);
7839 +}
7840 +
7841 +static struct file_operations hw_lro_stats_fops = {
7842 +       .owner          = THIS_MODULE,
7843 +       .open           = hw_lro_stats_open,
7844 +       .read           = seq_read,
7845 +       .llseek         = seq_lseek,
7846 +       .write          = HwLroStatsWrite,
7847 +       .release        = single_release
7848 +};
7849 +
7850 +int hwlro_agg_cnt_ctrl(int par1, int par2)
7851 +{
7852 +    SET_PDMA_RXRING_MAX_AGG_CNT(ADMA_RX_RING1, par2);
7853 +    SET_PDMA_RXRING_MAX_AGG_CNT(ADMA_RX_RING2, par2);
7854 +    SET_PDMA_RXRING_MAX_AGG_CNT(ADMA_RX_RING3, par2);
7855 +    return 0;
7856 +}
7857 +
7858 +int hwlro_agg_time_ctrl(int par1, int par2)
7859 +{
7860 +    SET_PDMA_RXRING_AGG_TIME(ADMA_RX_RING1, par2);
7861 +    SET_PDMA_RXRING_AGG_TIME(ADMA_RX_RING2, par2);
7862 +    SET_PDMA_RXRING_AGG_TIME(ADMA_RX_RING3, par2);
7863 +    return 0;
7864 +}
7865 +
7866 +int hwlro_age_time_ctrl(int par1, int par2)
7867 +{
7868 +    SET_PDMA_RXRING_AGE_TIME(ADMA_RX_RING1, par2);
7869 +    SET_PDMA_RXRING_AGE_TIME(ADMA_RX_RING2, par2);
7870 +    SET_PDMA_RXRING_AGE_TIME(ADMA_RX_RING3, par2);
7871 +    return 0;
7872 +}
7873 +
7874 +int hwlro_pkt_int_alpha_ctrl(int par1, int par2)
7875 +{
7876 +    END_DEVICE *ei_local = netdev_priv(dev_raether);
7877 +
7878 +    ei_local->hw_lro_alpha = par2;
7879 +    printk("[hwlro_pkt_int_alpha_ctrl]ei_local->hw_lro_alpha = %d\n", ei_local->hw_lro_alpha);
7880 +
7881 +    return 0;
7882 +}
7883 +
7884 +int hwlro_threshold_ctrl(int par1, int par2)
7885 +{
7886 +    /* bandwidth threshold setting */
7887 +    SET_PDMA_LRO_BW_THRESHOLD(par2);
7888 +    return 0;
7889 +}
7890 +
7891 +int hwlro_fix_setting_switch_ctrl(int par1, int par2)
7892 +{
7893 +#if defined (CONFIG_RAETH_HW_LRO_AUTO_ADJ_DBG)
7894 +    END_DEVICE *ei_local = netdev_priv(dev_raether);
7895 +
7896 +    ei_local->hw_lro_fix_setting = par2;
7897 +    printk("[hwlro_pkt_int_alpha_ctrl]ei_local->hw_lro_fix_setting = %d\n", ei_local->hw_lro_fix_setting);
7898 +#endif  /* CONFIG_RAETH_HW_LRO_AUTO_ADJ_DBG */
7899 +
7900 +    return 0;
7901 +}
7902 +
7903 +ssize_t HwLroAutoTlbWrite(struct file *file, const char __user *buffer,
7904 +                     size_t count, loff_t *data)
7905 +{
7906 +    char buf[32];
7907 +    char *pBuf;
7908 +    int len = count;
7909 +    int x = 0,y = 0;
7910 +    char *pToken = NULL;
7911 +    char *pDelimiter = " \t";
7912 +
7913 +    printk("[HwLroAutoTlbWrite]write parameter len = %d\n\r", (int)len);
7914 +    if(len >= sizeof(buf)){
7915 +        printk("input handling fail!\n");
7916 +        len = sizeof(buf) - 1;
7917 +        return -1;
7918 +    }
7919 +
7920 +    if(copy_from_user(buf, buffer, len)){
7921 +        return -EFAULT;
7922 +    }
7923 +    buf[len] = '\0';
7924 +    printk("[HwLroAutoTlbWrite]write parameter data = %s\n\r", buf);
7925 +
7926 +    pBuf = buf;
7927 +    pToken = strsep(&pBuf, pDelimiter);
7928 +    x = NULL != pToken ? simple_strtol(pToken, NULL, 16) : 0;
7929 +
7930 +    pToken = strsep(&pBuf, "\t\n ");
7931 +    if(pToken != NULL){
7932 +        y = NULL != pToken ? simple_strtol(pToken, NULL, 16) : 0;
7933 +        printk("y = 0x%08x \n\r", y);
7934 +    }
7935 +
7936 +    if ( (sizeof(hw_lro_dbg_func)/sizeof(hw_lro_dbg_func[0]) > x) && NULL != hw_lro_dbg_func[x])
7937 +    {
7938 +        (*hw_lro_dbg_func[x])(x, y);
7939 +    }
7940 +
7941 +       return count;
7942 +}
7943 +
7944 +void HwLroAutoTlbDump(struct seq_file *seq, unsigned int index)
7945 +{
7946 +    int i;
7947 +    struct PDMA_LRO_AUTO_TLB_INFO   pdma_lro_auto_tlb;
7948 +    unsigned int tlb_info[9];
7949 +    unsigned int dw_len, cnt, priority;
7950 +    unsigned int entry;
7951 +
7952 +    if( index > 4 )
7953 +        index = index - 1;
7954 +    entry = (index * 9) + 1;
7955 +
7956 +    /* read valid entries of the auto-learn table */
7957 +    sysRegWrite( PDMA_FE_ALT_CF8, entry );
7958 +
7959 +    //seq_printf(seq, "\nEntry = %d\n", entry);
7960 +    for(i=0; i<9; i++){
7961 +        tlb_info[i] = sysRegRead(PDMA_FE_ALT_SEQ_CFC);
7962 +        //seq_printf(seq, "tlb_info[%d] = 0x%x\n", i, tlb_info[i]);
7963 +    }
7964 +    memcpy(&pdma_lro_auto_tlb, tlb_info, sizeof(struct PDMA_LRO_AUTO_TLB_INFO));
7965 +
7966 +    dw_len = pdma_lro_auto_tlb.auto_tlb_info7.DW_LEN;
7967 +    cnt = pdma_lro_auto_tlb.auto_tlb_info6.CNT;
7968 +
7969 +    if ( sysRegRead(ADMA_LRO_CTRL_DW0) & PDMA_LRO_ALT_SCORE_MODE )  /* packet count */
7970 +        priority = cnt;
7971 +    else    /* byte count */
7972 +        priority = dw_len;
7973 +
7974 +    /* dump valid entries of the auto-learn table */
7975 +    if( index >= 4 )
7976 +        seq_printf(seq, "\n===== TABLE Entry: %d (Act) =====\n", index);
7977 +    else
7978 +        seq_printf(seq, "\n===== TABLE Entry: %d (LRU) =====\n", index);
7979 +    if( pdma_lro_auto_tlb.auto_tlb_info8.IPV4 ){
7980 +        seq_printf(seq, "SIP = 0x%x:0x%x:0x%x:0x%x (IPv4)\n",
7981 +            pdma_lro_auto_tlb.auto_tlb_info4.SIP3,
7982 +            pdma_lro_auto_tlb.auto_tlb_info3.SIP2,
7983 +            pdma_lro_auto_tlb.auto_tlb_info2.SIP1,
7984 +            pdma_lro_auto_tlb.auto_tlb_info1.SIP0);
7985 +    }
7986 +    else{
7987 +        seq_printf(seq, "SIP = 0x%x:0x%x:0x%x:0x%x (IPv6)\n",
7988 +            pdma_lro_auto_tlb.auto_tlb_info4.SIP3,
7989 +            pdma_lro_auto_tlb.auto_tlb_info3.SIP2,
7990 +            pdma_lro_auto_tlb.auto_tlb_info2.SIP1,
7991 +            pdma_lro_auto_tlb.auto_tlb_info1.SIP0);
7992 +    }
7993 +    seq_printf(seq, "DIP_ID = %d\n", pdma_lro_auto_tlb.auto_tlb_info8.DIP_ID);
7994 +    seq_printf(seq, "TCP SPORT = %d | TCP DPORT = %d\n",
7995 +        pdma_lro_auto_tlb.auto_tlb_info0.STP,
7996 +        pdma_lro_auto_tlb.auto_tlb_info0.DTP);
7997 +    seq_printf(seq, "VLAN1 = %d | VLAN2 = %d | VLAN3 = %d | VLAN4 =%d \n",
7998 +        pdma_lro_auto_tlb.auto_tlb_info5.VLAN_VID0,
7999 +        (pdma_lro_auto_tlb.auto_tlb_info5.VLAN_VID0 << 12),
8000 +        (pdma_lro_auto_tlb.auto_tlb_info5.VLAN_VID0 << 24),
8001 +        pdma_lro_auto_tlb.auto_tlb_info6.VLAN_VID1);
8002 +    seq_printf(seq, "TPUT = %d | FREQ = %d\n", dw_len, cnt);
8003 +    seq_printf(seq, "PRIORITY = %d\n", priority);
8004 +}
8005 +
8006 +int HwLroAutoTlbRead(struct seq_file *seq, void *v)
8007 +{
8008 +       int i;
8009 +    unsigned int regVal;
8010 +    unsigned int regOp1, regOp2, regOp3, regOp4;
8011 +    unsigned int agg_cnt, agg_time, age_time;
8012 +
8013 +    /* Read valid entries of the auto-learn table */
8014 +    sysRegWrite(PDMA_FE_ALT_CF8, 0);
8015 +    regVal = sysRegRead(PDMA_FE_ALT_SEQ_CFC);
8016 +
8017 +    seq_printf(seq, "HW LRO Auto-learn Table: (PDMA_LRO_ALT_CFC_RSEQ_DBG=0x%x)\n", regVal);
8018 +
8019 +    for(i = 7; i >= 0; i--)
8020 +    {
8021 +        if( regVal & (1 << i) )
8022 +            HwLroAutoTlbDump(seq, i);
8023 +    }
8024 +
8025 +    /* Read the agg_time/age_time/agg_cnt of LRO rings */
8026 +    seq_printf(seq, "\nHW LRO Ring Settings\n");
8027 +    for(i = 1; i <= 3; i++)
8028 +    {
8029 +        regOp1 = sysRegRead( LRO_RX_RING0_CTRL_DW1 + (i * 0x40) );
8030 +        regOp2 = sysRegRead( LRO_RX_RING0_CTRL_DW2 + (i * 0x40) );
8031 +        regOp3 = sysRegRead( LRO_RX_RING0_CTRL_DW3 + (i * 0x40) );
8032 +        regOp4 = sysRegRead( ADMA_LRO_CTRL_DW2 );
8033 +        agg_cnt = ((regOp3 & 0x03) << PDMA_LRO_AGG_CNT_H_OFFSET) | ((regOp2 >> PDMA_LRO_RING_AGG_CNT1_OFFSET) & 0x3f);
8034 +        agg_time = (regOp2 >> PDMA_LRO_RING_AGG_OFFSET) & 0xffff;
8035 +        age_time = ((regOp2 & 0x03f) << PDMA_LRO_AGE_H_OFFSET) | ((regOp1 >> PDMA_LRO_RING_AGE1_OFFSET) & 0x3ff);
8036 +        seq_printf(seq, "Ring[%d]: MAX_AGG_CNT=%d, AGG_TIME=%d, AGE_TIME=%d, Threshold=%d\n",
8037 +            i, agg_cnt, agg_time, age_time, regOp4);
8038 +    }
8039 +
8040 +       return 0;
8041 +}
8042 +
8043 +static int hw_lro_auto_tlb_open(struct inode *inode, struct file *file)
8044 +{
8045 +       return single_open(file, HwLroAutoTlbRead, NULL);
8046 +}
8047 +
8048 +static struct file_operations hw_lro_auto_tlb_fops = {
8049 +       .owner          = THIS_MODULE,
8050 +       .open           = hw_lro_auto_tlb_open,
8051 +       .read           = seq_read,
8052 +       .llseek         = seq_lseek,
8053 +       .write          = HwLroAutoTlbWrite,
8054 +       .release        = single_release
8055 +};
8056 +#endif  /* CONFIG_RAETH_HW_LRO */
8057 +
8058 +#if defined (CONFIG_MIPS)
8059 +int CP0RegRead(struct seq_file *seq, void *v)
8060 +{
8061 +       seq_printf(seq, "CP0 Register dump --\n");
8062 +       seq_printf(seq, "CP0_INDEX\t: 0x%08x\n", read_32bit_cp0_register(CP0_INDEX));
8063 +       seq_printf(seq, "CP0_RANDOM\t: 0x%08x\n", read_32bit_cp0_register(CP0_RANDOM));
8064 +       seq_printf(seq, "CP0_ENTRYLO0\t: 0x%08x\n", read_32bit_cp0_register(CP0_ENTRYLO0));
8065 +       seq_printf(seq, "CP0_ENTRYLO1\t: 0x%08x\n", read_32bit_cp0_register(CP0_ENTRYLO1));
8066 +       seq_printf(seq, "CP0_CONF\t: 0x%08x\n", read_32bit_cp0_register(CP0_CONF));
8067 +       seq_printf(seq, "CP0_CONTEXT\t: 0x%08x\n", read_32bit_cp0_register(CP0_CONTEXT));
8068 +       seq_printf(seq, "CP0_PAGEMASK\t: 0x%08x\n", read_32bit_cp0_register(CP0_PAGEMASK));
8069 +       seq_printf(seq, "CP0_WIRED\t: 0x%08x\n", read_32bit_cp0_register(CP0_WIRED));
8070 +       seq_printf(seq, "CP0_INFO\t: 0x%08x\n", read_32bit_cp0_register(CP0_INFO));
8071 +       seq_printf(seq, "CP0_BADVADDR\t: 0x%08x\n", read_32bit_cp0_register(CP0_BADVADDR));
8072 +       seq_printf(seq, "CP0_COUNT\t: 0x%08x\n", read_32bit_cp0_register(CP0_COUNT));
8073 +       seq_printf(seq, "CP0_ENTRYHI\t: 0x%08x\n", read_32bit_cp0_register(CP0_ENTRYHI));
8074 +       seq_printf(seq, "CP0_COMPARE\t: 0x%08x\n", read_32bit_cp0_register(CP0_COMPARE));
8075 +       seq_printf(seq, "CP0_STATUS\t: 0x%08x\n", read_32bit_cp0_register(CP0_STATUS));
8076 +       seq_printf(seq, "CP0_CAUSE\t: 0x%08x\n", read_32bit_cp0_register(CP0_CAUSE));
8077 +       seq_printf(seq, "CP0_EPC\t: 0x%08x\n", read_32bit_cp0_register(CP0_EPC));
8078 +       seq_printf(seq, "CP0_PRID\t: 0x%08x\n", read_32bit_cp0_register(CP0_PRID));
8079 +       seq_printf(seq, "CP0_CONFIG\t: 0x%08x\n", read_32bit_cp0_register(CP0_CONFIG));
8080 +       seq_printf(seq, "CP0_LLADDR\t: 0x%08x\n", read_32bit_cp0_register(CP0_LLADDR));
8081 +       seq_printf(seq, "CP0_WATCHLO\t: 0x%08x\n", read_32bit_cp0_register(CP0_WATCHLO));
8082 +       seq_printf(seq, "CP0_WATCHHI\t: 0x%08x\n", read_32bit_cp0_register(CP0_WATCHHI));
8083 +       seq_printf(seq, "CP0_XCONTEXT\t: 0x%08x\n", read_32bit_cp0_register(CP0_XCONTEXT));
8084 +       seq_printf(seq, "CP0_FRAMEMASK\t: 0x%08x\n", read_32bit_cp0_register(CP0_FRAMEMASK));
8085 +       seq_printf(seq, "CP0_DIAGNOSTIC\t: 0x%08x\n", read_32bit_cp0_register(CP0_DIAGNOSTIC));
8086 +       seq_printf(seq, "CP0_DEBUG\t: 0x%08x\n", read_32bit_cp0_register(CP0_DEBUG));
8087 +       seq_printf(seq, "CP0_DEPC\t: 0x%08x\n", read_32bit_cp0_register(CP0_DEPC));
8088 +       seq_printf(seq, "CP0_PERFORMANCE\t: 0x%08x\n", read_32bit_cp0_register(CP0_PERFORMANCE));
8089 +       seq_printf(seq, "CP0_ECC\t: 0x%08x\n", read_32bit_cp0_register(CP0_ECC));
8090 +       seq_printf(seq, "CP0_CACHEERR\t: 0x%08x\n", read_32bit_cp0_register(CP0_CACHEERR));
8091 +       seq_printf(seq, "CP0_TAGLO\t: 0x%08x\n", read_32bit_cp0_register(CP0_TAGLO));
8092 +       seq_printf(seq, "CP0_TAGHI\t: 0x%08x\n", read_32bit_cp0_register(CP0_TAGHI));
8093 +       seq_printf(seq, "CP0_ERROREPC\t: 0x%08x\n", read_32bit_cp0_register(CP0_ERROREPC));
8094 +       seq_printf(seq, "CP0_DESAVE\t: 0x%08x\n\n", read_32bit_cp0_register(CP0_DESAVE));
8095 +
8096 +       return 0;
8097 +}
8098 +
8099 +static int cp0_reg_open(struct inode *inode, struct file *file)
8100 +{
8101 +       return single_open(file, CP0RegRead, NULL);
8102 +}
8103 +
8104 +static const struct file_operations cp0_reg_fops = {
8105 +       .owner          = THIS_MODULE,
8106 +       .open           = cp0_reg_open,
8107 +       .read           = seq_read,
8108 +       .llseek         = seq_lseek,
8109 +       .release        = single_release
8110 +};
8111 +#endif
8112 +
8113 +#if defined(CONFIG_RAETH_QOS)
8114 +static struct proc_dir_entry *procRaQOS, *procRaFeIntr, *procRaEswIntr;
8115 +extern uint32_t num_of_rxdone_intr;
8116 +extern uint32_t num_of_esw_intr;
8117 +
8118 +int RaQOSRegRead(struct seq_file *seq, void *v)
8119 +{
8120 +       dump_qos(seq);
8121 +       return 0;
8122 +}
8123 +
8124 +static int raeth_qos_open(struct inode *inode, struct file *file)
8125 +{
8126 +       return single_open(file, RaQOSRegRead, NULL);
8127 +}
8128 +
8129 +static const struct file_operations raeth_qos_fops = {
8130 +       .owner          = THIS_MODULE,
8131 +       .open           = raeth_qos_open,
8132 +       .read           = seq_read,
8133 +       .llseek         = seq_lseek,
8134 +       .release        = single_release
8135 +};
8136 +#endif
8137 +
8138 +static struct proc_dir_entry *procEswCnt;
8139 +
8140 +int EswCntRead(struct seq_file *seq, void *v)
8141 +{
8142 +#if defined (CONFIG_RALINK_MT7621) || defined (CONFIG_P5_RGMII_TO_MT7530_MODE) || defined (CONFIG_ARCH_MT7623)
8143 +       unsigned int pkt_cnt = 0;
8144 +       int i = 0;
8145 +#endif
8146 +       seq_printf(seq, "\n               <<CPU>>                        \n");
8147 +       seq_printf(seq, "                   |                            \n");
8148 +#if defined (CONFIG_RALINK_RT5350) || defined (CONFIG_RALINK_MT7628)
8149 +       seq_printf(seq, "+-----------------------------------------------+\n");
8150 +       seq_printf(seq, "|                <<PDMA>>                      |\n");
8151 +       seq_printf(seq, "+-----------------------------------------------+\n");
8152 +#else
8153 +       seq_printf(seq, "+-----------------------------------------------+\n");
8154 +       seq_printf(seq, "|                <<PSE>>                       |\n");
8155 +       seq_printf(seq, "+-----------------------------------------------+\n");
8156 +       seq_printf(seq, "                  |                             \n");
8157 +       seq_printf(seq, "+-----------------------------------------------+\n");
8158 +       seq_printf(seq, "|                <<GDMA>>                      |\n");
8159 +#if defined (CONFIG_RALINK_MT7620)
8160 +       seq_printf(seq, "| GDMA1_TX_GPCNT  : %010u (Tx Good Pkts)       |\n", sysRegRead(RALINK_FRAME_ENGINE_BASE+0x1304));
8161 +       seq_printf(seq, "| GDMA1_RX_GPCNT  : %010u (Rx Good Pkts)       |\n", sysRegRead(RALINK_FRAME_ENGINE_BASE+0x1324));
8162 +       seq_printf(seq, "|                                              |\n");
8163 +       seq_printf(seq, "| GDMA1_TX_SKIPCNT: %010u (skip)               |\n", sysRegRead(RALINK_FRAME_ENGINE_BASE+0x1308));
8164 +       seq_printf(seq, "| GDMA1_TX_COLCNT : %010u (collision)  |\n", sysRegRead(RALINK_FRAME_ENGINE_BASE+0x130c));
8165 +       seq_printf(seq, "| GDMA1_RX_OERCNT : %010u (overflow)   |\n", sysRegRead(RALINK_FRAME_ENGINE_BASE+0x1328));
8166 +       seq_printf(seq, "| GDMA1_RX_FERCNT : %010u (FCS error)  |\n", sysRegRead(RALINK_FRAME_ENGINE_BASE+0x132c));
8167 +       seq_printf(seq, "| GDMA1_RX_SERCNT : %010u (too short)  |\n", sysRegRead(RALINK_FRAME_ENGINE_BASE+0x1330));
8168 +       seq_printf(seq, "| GDMA1_RX_LERCNT : %010u (too long)   |\n", sysRegRead(RALINK_FRAME_ENGINE_BASE+0x1334));
8169 +       seq_printf(seq, "| GDMA1_RX_CERCNT : %010u (l3/l4 checksum) |\n", sysRegRead(RALINK_FRAME_ENGINE_BASE+0x1338));
8170 +       seq_printf(seq, "| GDMA1_RX_FCCNT  : %010u (flow control)       |\n", sysRegRead(RALINK_FRAME_ENGINE_BASE+0x133c));
8171 +
8172 +       seq_printf(seq, "|                                              |\n");
8173 +       seq_printf(seq, "| GDMA2_TX_GPCNT  : %010u (Tx Good Pkts)       |\n", sysRegRead(RALINK_FRAME_ENGINE_BASE+0x1344));
8174 +       seq_printf(seq, "| GDMA2_RX_GPCNT  : %010u (Rx Good Pkts)       |\n", sysRegRead(RALINK_FRAME_ENGINE_BASE+0x1364));
8175 +       seq_printf(seq, "|                                              |\n");
8176 +       seq_printf(seq, "| GDMA2_TX_SKIPCNT: %010u (skip)               |\n", sysRegRead(RALINK_FRAME_ENGINE_BASE+0x1348));
8177 +       seq_printf(seq, "| GDMA2_TX_COLCNT : %010u (collision)  |\n", sysRegRead(RALINK_FRAME_ENGINE_BASE+0x134c));
8178 +       seq_printf(seq, "| GDMA2_RX_OERCNT : %010u (overflow)   |\n", sysRegRead(RALINK_FRAME_ENGINE_BASE+0x1368));
8179 +       seq_printf(seq, "| GDMA2_RX_FERCNT : %010u (FCS error)  |\n", sysRegRead(RALINK_FRAME_ENGINE_BASE+0x136c));
8180 +       seq_printf(seq, "| GDMA2_RX_SERCNT : %010u (too short)  |\n", sysRegRead(RALINK_FRAME_ENGINE_BASE+0x1370));
8181 +       seq_printf(seq, "| GDMA2_RX_LERCNT : %010u (too long)   |\n", sysRegRead(RALINK_FRAME_ENGINE_BASE+0x1374));
8182 +       seq_printf(seq, "| GDMA2_RX_CERCNT : %010u (l3/l4 checksum) |\n", sysRegRead(RALINK_FRAME_ENGINE_BASE+0x1378));
8183 +       seq_printf(seq, "| GDMA2_RX_FCCNT  : %010u (flow control)       |\n", sysRegRead(RALINK_FRAME_ENGINE_BASE+0x137c));
8184 +#elif defined (CONFIG_RALINK_MT7621) || defined (CONFIG_ARCH_MT7623)
8185 +       seq_printf(seq, "| GDMA1_RX_GBCNT  : %010u (Rx Good Bytes)      |\n", sysRegRead(RALINK_FRAME_ENGINE_BASE+0x2400));
8186 +       seq_printf(seq, "| GDMA1_RX_GPCNT  : %010u (Rx Good Pkts)       |\n", sysRegRead(RALINK_FRAME_ENGINE_BASE+0x2408));
8187 +       seq_printf(seq, "| GDMA1_RX_OERCNT : %010u (overflow error)     |\n", sysRegRead(RALINK_FRAME_ENGINE_BASE+0x2410));
8188 +       seq_printf(seq, "| GDMA1_RX_FERCNT : %010u (FCS error)  |\n", sysRegRead(RALINK_FRAME_ENGINE_BASE+0x2414));
8189 +       seq_printf(seq, "| GDMA1_RX_SERCNT : %010u (too short)  |\n", sysRegRead(RALINK_FRAME_ENGINE_BASE+0x2418));
8190 +       seq_printf(seq, "| GDMA1_RX_LERCNT : %010u (too long)   |\n", sysRegRead(RALINK_FRAME_ENGINE_BASE+0x241C));
8191 +       seq_printf(seq, "| GDMA1_RX_CERCNT : %010u (checksum error)     |\n", sysRegRead(RALINK_FRAME_ENGINE_BASE+0x2420));
8192 +       seq_printf(seq, "| GDMA1_RX_FCCNT  : %010u (flow control)       |\n", sysRegRead(RALINK_FRAME_ENGINE_BASE+0x2424));
8193 +       seq_printf(seq, "| GDMA1_TX_SKIPCNT: %010u (about count)        |\n", sysRegRead(RALINK_FRAME_ENGINE_BASE+0x2428));
8194 +       seq_printf(seq, "| GDMA1_TX_COLCNT : %010u (collision count)    |\n", sysRegRead(RALINK_FRAME_ENGINE_BASE+0x242C));
8195 +       seq_printf(seq, "| GDMA1_TX_GBCNT  : %010u (Tx Good Bytes)      |\n", sysRegRead(RALINK_FRAME_ENGINE_BASE+0x2430));
8196 +       seq_printf(seq, "| GDMA1_TX_GPCNT  : %010u (Tx Good Pkts)       |\n", sysRegRead(RALINK_FRAME_ENGINE_BASE+0x2438));
8197 +       seq_printf(seq, "|                                              |\n");
8198 +       seq_printf(seq, "| GDMA2_RX_GBCNT  : %010u (Rx Good Bytes)      |\n", sysRegRead(RALINK_FRAME_ENGINE_BASE+0x2440));
8199 +       seq_printf(seq, "| GDMA2_RX_GPCNT  : %010u (Rx Good Pkts)       |\n", sysRegRead(RALINK_FRAME_ENGINE_BASE+0x2448));
8200 +       seq_printf(seq, "| GDMA2_RX_OERCNT : %010u (overflow error)     |\n", sysRegRead(RALINK_FRAME_ENGINE_BASE+0x2450));
8201 +       seq_printf(seq, "| GDMA2_RX_FERCNT : %010u (FCS error)  |\n", sysRegRead(RALINK_FRAME_ENGINE_BASE+0x2454));
8202 +       seq_printf(seq, "| GDMA2_RX_SERCNT : %010u (too short)  |\n", sysRegRead(RALINK_FRAME_ENGINE_BASE+0x2458));
8203 +       seq_printf(seq, "| GDMA2_RX_LERCNT : %010u (too long)   |\n", sysRegRead(RALINK_FRAME_ENGINE_BASE+0x245C));
8204 +       seq_printf(seq, "| GDMA2_RX_CERCNT : %010u (checksum error)     |\n", sysRegRead(RALINK_FRAME_ENGINE_BASE+0x2460));
8205 +       seq_printf(seq, "| GDMA2_RX_FCCNT  : %010u (flow control)       |\n", sysRegRead(RALINK_FRAME_ENGINE_BASE+0x2464));
8206 +       seq_printf(seq, "| GDMA2_TX_SKIPCNT: %010u (skip)               |\n", sysRegRead(RALINK_FRAME_ENGINE_BASE+0x2468));
8207 +       seq_printf(seq, "| GDMA2_TX_COLCNT : %010u (collision)  |\n", sysRegRead(RALINK_FRAME_ENGINE_BASE+0x246C));
8208 +       seq_printf(seq, "| GDMA2_TX_GBCNT  : %010u (Tx Good Bytes)      |\n", sysRegRead(RALINK_FRAME_ENGINE_BASE+0x2470));
8209 +       seq_printf(seq, "| GDMA2_TX_GPCNT  : %010u (Tx Good Pkts)       |\n", sysRegRead(RALINK_FRAME_ENGINE_BASE+0x2478));
8210 +#else
8211 +       seq_printf(seq, "| GDMA_TX_GPCNT1  : %010u (Tx Good Pkts)       |\n", sysRegRead(RALINK_FRAME_ENGINE_BASE+0x704));
8212 +       seq_printf(seq, "| GDMA_RX_GPCNT1  : %010u (Rx Good Pkts)       |\n", sysRegRead(RALINK_FRAME_ENGINE_BASE+0x724));
8213 +       seq_printf(seq, "|                                              |\n");
8214 +       seq_printf(seq, "| GDMA_TX_SKIPCNT1: %010u (skip)               |\n", sysRegRead(RALINK_FRAME_ENGINE_BASE+0x708));
8215 +       seq_printf(seq, "| GDMA_TX_COLCNT1 : %010u (collision)  |\n", sysRegRead(RALINK_FRAME_ENGINE_BASE+0x70c));
8216 +       seq_printf(seq, "| GDMA_RX_OERCNT1 : %010u (overflow)   |\n", sysRegRead(RALINK_FRAME_ENGINE_BASE+0x728));
8217 +       seq_printf(seq, "| GDMA_RX_FERCNT1 : %010u (FCS error)  |\n", sysRegRead(RALINK_FRAME_ENGINE_BASE+0x72c));
8218 +       seq_printf(seq, "| GDMA_RX_SERCNT1 : %010u (too short)  |\n", sysRegRead(RALINK_FRAME_ENGINE_BASE+0x730));
8219 +       seq_printf(seq, "| GDMA_RX_LERCNT1 : %010u (too long)   |\n", sysRegRead(RALINK_FRAME_ENGINE_BASE+0x734));
8220 +       seq_printf(seq, "| GDMA_RX_CERCNT1 : %010u (l3/l4 checksum)     |\n", sysRegRead(RALINK_FRAME_ENGINE_BASE+0x738));
8221 +       seq_printf(seq, "| GDMA_RX_FCCNT1  : %010u (flow control)       |\n", sysRegRead(RALINK_FRAME_ENGINE_BASE+0x73c));
8222 +
8223 +#endif
8224 +       seq_printf(seq, "+-----------------------------------------------+\n");
8225 +#endif
8226 +
8227 +#if defined (CONFIG_RALINK_RT6855) || defined(CONFIG_RALINK_RT6855A) || \
8228 +    defined (CONFIG_RALINK_MT7620)
8229 +
8230 +       seq_printf(seq, "                      ^                          \n");
8231 +       seq_printf(seq, "                      | Port6 Rx:%010u Good Pkt   \n", ((p6_rx_good_cnt << 16) | (sysRegRead(RALINK_ETH_SW_BASE+0x4620)&0xFFFF)));
8232 +       seq_printf(seq, "                      | Port6 Rx:%010u Bad Pkt    \n", sysRegRead(RALINK_ETH_SW_BASE+0x4620)>>16);
8233 +       seq_printf(seq, "                      | Port6 Tx:%010u Good Pkt   \n", ((p6_tx_good_cnt << 16) | (sysRegRead(RALINK_ETH_SW_BASE+0x4610)&0xFFFF)));
8234 +       seq_printf(seq, "                      | Port6 Tx:%010u Bad Pkt    \n", sysRegRead(RALINK_ETH_SW_BASE+0x4610)>>16);
8235 +#if defined (CONFIG_RALINK_MT7620)
8236 +
8237 +       seq_printf(seq, "                      | Port7 Rx:%010u Good Pkt   \n", ((p7_rx_good_cnt << 16) | (sysRegRead(RALINK_ETH_SW_BASE+0x4720)&0xFFFF)));
8238 +       seq_printf(seq, "                      | Port7 Rx:%010u Bad Pkt    \n", sysRegRead(RALINK_ETH_SW_BASE+0x4720)>>16);
8239 +       seq_printf(seq, "                      | Port7 Tx:%010u Good Pkt   \n", ((p7_tx_good_cnt << 16) | (sysRegRead(RALINK_ETH_SW_BASE+0x4710)&0xFFFF)));
8240 +       seq_printf(seq, "                      | Port7 Tx:%010u Bad Pkt    \n", sysRegRead(RALINK_ETH_SW_BASE+0x4710)>>16);
8241 +#endif
8242 +       seq_printf(seq, "+---------------------v-------------------------+\n");
8243 +       seq_printf(seq, "|                    P6                        |\n");
8244 +       seq_printf(seq, "|        <<10/100/1000 Embedded Switch>>        |\n");
8245 +       seq_printf(seq, "|     P0    P1    P2     P3     P4     P5       |\n");
8246 +       seq_printf(seq, "+-----------------------------------------------+\n");
8247 +       seq_printf(seq, "       |     |     |     |       |      |        \n");
8248 +#elif defined (CONFIG_RALINK_RT3883) || defined (CONFIG_RALINK_MT7621) || defined (CONFIG_ARCH_MT7623)
8249 +       /* no built-in switch */
8250 +#else
8251 +       seq_printf(seq, "                      ^                          \n");
8252 +       seq_printf(seq, "                      | Port6 Rx:%08u Good Pkt   \n", sysRegRead(RALINK_ETH_SW_BASE+0xE0)&0xFFFF);
8253 +       seq_printf(seq, "                      | Port6 Tx:%08u Good Pkt   \n", sysRegRead(RALINK_ETH_SW_BASE+0xE0)>>16);
8254 +       seq_printf(seq, "+---------------------v-------------------------+\n");
8255 +       seq_printf(seq, "|                    P6                        |\n");
8256 +       seq_printf(seq, "|           <<10/100 Embedded Switch>>         |\n");
8257 +       seq_printf(seq, "|     P0    P1    P2     P3     P4     P5       |\n");
8258 +       seq_printf(seq, "+-----------------------------------------------+\n");
8259 +       seq_printf(seq, "       |     |     |     |       |      |        \n");
8260 +#endif
8261 +
8262 +#if defined (CONFIG_RALINK_RT6855) || defined(CONFIG_RALINK_RT6855A) || \
8263 +    defined (CONFIG_RALINK_MT7620)
8264 +
8265 +       seq_printf(seq, "Port0 Good RX=%010u Tx=%010u (Bad Rx=%010u Tx=%010u)\n", ((p0_rx_good_cnt << 16) | (sysRegRead(RALINK_ETH_SW_BASE+0x4020)&0xFFFF)), ((p0_tx_good_cnt << 16)| (sysRegRead(RALINK_ETH_SW_BASE+0x4010)&0xFFFF)), sysRegRead(RALINK_ETH_SW_BASE+0x4020)>>16, sysRegRead(RALINK_ETH_SW_BASE+0x4010)>>16);
8266 +
8267 +       seq_printf(seq, "Port1 Good RX=%010u Tx=%010u (Bad Rx=%010u Tx=%010u)\n", ((p1_rx_good_cnt << 16) | (sysRegRead(RALINK_ETH_SW_BASE+0x4120)&0xFFFF)), ((p1_tx_good_cnt << 16)| (sysRegRead(RALINK_ETH_SW_BASE+0x4110)&0xFFFF)), sysRegRead(RALINK_ETH_SW_BASE+0x4120)>>16, sysRegRead(RALINK_ETH_SW_BASE+0x4110)>>16);
8268 +
8269 +       seq_printf(seq, "Port2 Good RX=%010u Tx=%010u (Bad Rx=%010u Tx=%010u)\n", ((p2_rx_good_cnt << 16) | (sysRegRead(RALINK_ETH_SW_BASE+0x4220)&0xFFFF)), ((p2_tx_good_cnt << 16)| (sysRegRead(RALINK_ETH_SW_BASE+0x4210)&0xFFFF)), sysRegRead(RALINK_ETH_SW_BASE+0x4220)>>16, sysRegRead(RALINK_ETH_SW_BASE+0x4210)>>16);
8270 +
8271 +       seq_printf(seq, "Port3 Good RX=%010u Tx=%010u (Bad Rx=%010u Tx=%010u)\n", ((p3_rx_good_cnt << 16) | (sysRegRead(RALINK_ETH_SW_BASE+0x4320)&0xFFFF)), ((p3_tx_good_cnt << 16)| (sysRegRead(RALINK_ETH_SW_BASE+0x4310)&0xFFFF)), sysRegRead(RALINK_ETH_SW_BASE+0x4320)>>16, sysRegRead(RALINK_ETH_SW_BASE+0x4310)>>16);
8272 +
8273 +       seq_printf(seq, "Port4 Good RX=%010u Tx=%010u (Bad Rx=%010u Tx=%010u)\n", ((p4_rx_good_cnt << 16) | (sysRegRead(RALINK_ETH_SW_BASE+0x4420)&0xFFFF)), ((p4_tx_good_cnt << 16)| (sysRegRead(RALINK_ETH_SW_BASE+0x4410)&0xFFFF)), sysRegRead(RALINK_ETH_SW_BASE+0x4420)>>16, sysRegRead(RALINK_ETH_SW_BASE+0x4410)>>16);
8274 +
8275 +       seq_printf(seq, "Port5 Good RX=%010u Tx=%010u (Bad Rx=%010u Tx=%010u)\n", ((p5_rx_good_cnt << 16) | (sysRegRead(RALINK_ETH_SW_BASE+0x4520)&0xFFFF)), ((p5_tx_good_cnt << 16)| (sysRegRead(RALINK_ETH_SW_BASE+0x4510)&0xFFFF)), sysRegRead(RALINK_ETH_SW_BASE+0x4520)>>16, sysRegRead(RALINK_ETH_SW_BASE+0x4510)>>16);
8276 +
8277 +       seq_printf(seq, "Port0 KBytes RX=%010u Tx=%010u \n", ((p0_rx_byte_cnt << 22) + (sysRegRead(RALINK_ETH_SW_BASE+0x4028) >> 10)), ((p0_tx_byte_cnt << 22) + (sysRegRead(RALINK_ETH_SW_BASE+0x4018) >> 10)));
8278 +
8279 +       seq_printf(seq, "Port1 KBytes RX=%010u Tx=%010u \n", ((p1_rx_byte_cnt << 22) + (sysRegRead(RALINK_ETH_SW_BASE+0x4128) >> 10)), ((p1_tx_byte_cnt << 22) + (sysRegRead(RALINK_ETH_SW_BASE+0x4118) >> 10)));
8280 +
8281 +       seq_printf(seq, "Port2 KBytes RX=%010u Tx=%010u \n", ((p2_rx_byte_cnt << 22) + (sysRegRead(RALINK_ETH_SW_BASE+0x4228) >> 10)), ((p2_tx_byte_cnt << 22) + (sysRegRead(RALINK_ETH_SW_BASE+0x4218) >> 10)));
8282 +
8283 +       seq_printf(seq, "Port3 KBytes RX=%010u Tx=%010u \n", ((p3_rx_byte_cnt << 22) + (sysRegRead(RALINK_ETH_SW_BASE+0x4328) >> 10)), ((p3_tx_byte_cnt << 22) + (sysRegRead(RALINK_ETH_SW_BASE+0x4318) >> 10)));
8284 +
8285 +       seq_printf(seq, "Port4 KBytes RX=%010u Tx=%010u \n", ((p4_rx_byte_cnt << 22) + (sysRegRead(RALINK_ETH_SW_BASE+0x4428) >> 10)), ((p4_tx_byte_cnt << 22) + (sysRegRead(RALINK_ETH_SW_BASE+0x4418) >> 10)));
8286 +
8287 +       seq_printf(seq, "Port5 KBytes RX=%010u Tx=%010u \n", ((p5_rx_byte_cnt << 22) + (sysRegRead(RALINK_ETH_SW_BASE+0x4528) >> 10)), ((p5_tx_byte_cnt << 22) + (sysRegRead(RALINK_ETH_SW_BASE+0x4518) >> 10)));
8288 +
8289 +#if defined (CONFIG_P5_RGMII_TO_MT7530_MODE)
8290 +#define DUMP_EACH_PORT(base)                                   \
8291 +       for(i=0; i < 7;i++) {                                   \
8292 +               mii_mgr_read(31, (base) + (i*0x100), &pkt_cnt); \
8293 +               seq_printf(seq, "%8u ", pkt_cnt);                       \
8294 +       }                                                       \
8295 +       seq_printf(seq, "\n");
8296 +       seq_printf(seq, "========================================[MT7530] READ CLEAR========================\n");
8297 +
8298 +               seq_printf(seq, "===================== %8s %8s %8s %8s %8s %8s %8s\n","Port0", "Port1", "Port2", "Port3", "Port4", "Port5", "Port6");
8299 +               seq_printf(seq, "Tx Drop Packet      :"); DUMP_EACH_PORT(0x4000);
8300 +               //seq_printf(seq, "Tx CRC Error        :"); DUMP_EACH_PORT(0x4004);
8301 +               seq_printf(seq, "Tx Unicast Packet   :"); DUMP_EACH_PORT(0x4008);
8302 +               seq_printf(seq, "Tx Multicast Packet :"); DUMP_EACH_PORT(0x400C);
8303 +               seq_printf(seq, "Tx Broadcast Packet :"); DUMP_EACH_PORT(0x4010);
8304 +               //seq_printf(seq, "Tx Collision Event  :"); DUMP_EACH_PORT(0x4014);
8305 +               seq_printf(seq, "Tx Pause Packet     :"); DUMP_EACH_PORT(0x402C);
8306 +               seq_printf(seq, "Rx Drop Packet      :"); DUMP_EACH_PORT(0x4060);
8307 +               seq_printf(seq, "Rx Filtering Packet :"); DUMP_EACH_PORT(0x4064);
8308 +               seq_printf(seq, "Rx Unicast Packet   :"); DUMP_EACH_PORT(0x4068);
8309 +               seq_printf(seq, "Rx Multicast Packet :"); DUMP_EACH_PORT(0x406C);
8310 +               seq_printf(seq, "Rx Broadcast Packet :"); DUMP_EACH_PORT(0x4070);
8311 +               seq_printf(seq, "Rx Alignment Error  :"); DUMP_EACH_PORT(0x4074);
8312 +               seq_printf(seq, "Rx CRC Error       :"); DUMP_EACH_PORT(0x4078);
8313 +               seq_printf(seq, "Rx Undersize Error  :"); DUMP_EACH_PORT(0x407C);
8314 +               //seq_printf(seq, "Rx Fragment Error   :"); DUMP_EACH_PORT(0x4080);
8315 +               //seq_printf(seq, "Rx Oversize Error   :"); DUMP_EACH_PORT(0x4084);
8316 +               //seq_printf(seq, "Rx Jabber Error     :"); DUMP_EACH_PORT(0x4088);
8317 +               seq_printf(seq, "Rx Pause Packet     :"); DUMP_EACH_PORT(0x408C);
8318 +               mii_mgr_write(31, 0x4fe0, 0xf0);
8319 +               mii_mgr_write(31, 0x4fe0, 0x800000f0);
8320 +#endif
8321 +
8322 +
8323 +#elif defined (CONFIG_RALINK_RT5350) || defined (CONFIG_RALINK_MT7628)
8324 +       seq_printf(seq, "Port0 Good Pkt Cnt: RX=%08u Tx=%08u (Bad Pkt Cnt: Rx=%08u Tx=%08u)\n", sysRegRead(RALINK_ETH_SW_BASE+0xE8)&0xFFFF,sysRegRead(RALINK_ETH_SW_BASE+0x150)&0xFFFF,sysRegRead(RALINK_ETH_SW_BASE+0xE8)>>16, sysRegRead(RALINK_ETH_SW_BASE+0x150)>>16);
8325 +
8326 +       seq_printf(seq, "Port1 Good Pkt Cnt: RX=%08u Tx=%08u (Bad Pkt Cnt: Rx=%08u Tx=%08u)\n", sysRegRead(RALINK_ETH_SW_BASE+0xEC)&0xFFFF,sysRegRead(RALINK_ETH_SW_BASE+0x154)&0xFFFF,sysRegRead(RALINK_ETH_SW_BASE+0xEC)>>16, sysRegRead(RALINK_ETH_SW_BASE+0x154)>>16);
8327 +
8328 +       seq_printf(seq, "Port2 Good Pkt Cnt: RX=%08u Tx=%08u (Bad Pkt Cnt: Rx=%08u Tx=%08u)\n", sysRegRead(RALINK_ETH_SW_BASE+0xF0)&0xFFFF,sysRegRead(RALINK_ETH_SW_BASE+0x158)&0xFFFF,sysRegRead(RALINK_ETH_SW_BASE+0xF0)>>16, sysRegRead(RALINK_ETH_SW_BASE+0x158)>>16);
8329 +
8330 +       seq_printf(seq, "Port3 Good Pkt Cnt: RX=%08u Tx=%08u (Bad Pkt Cnt: Rx=%08u Tx=%08u)\n", sysRegRead(RALINK_ETH_SW_BASE+0xF4)&0xFFFF,sysRegRead(RALINK_ETH_SW_BASE+0x15C)&0xFFFF,sysRegRead(RALINK_ETH_SW_BASE+0xF4)>>16, sysRegRead(RALINK_ETH_SW_BASE+0x15c)>>16);
8331 +
8332 +       seq_printf(seq, "Port4 Good Pkt Cnt: RX=%08u Tx=%08u (Bad Pkt Cnt: Rx=%08u Tx=%08u)\n", sysRegRead(RALINK_ETH_SW_BASE+0xF8)&0xFFFF,sysRegRead(RALINK_ETH_SW_BASE+0x160)&0xFFFF,sysRegRead(RALINK_ETH_SW_BASE+0xF8)>>16, sysRegRead(RALINK_ETH_SW_BASE+0x160)>>16);
8333 +
8334 +       seq_printf(seq, "Port5 Good Pkt Cnt: RX=%08u Tx=%08u (Bad Pkt Cnt: Rx=%08u Tx=%08u)\n", sysRegRead(RALINK_ETH_SW_BASE+0xFC)&0xFFFF,sysRegRead(RALINK_ETH_SW_BASE+0x164)&0xFFFF,sysRegRead(RALINK_ETH_SW_BASE+0xFC)>>16, sysRegRead(RALINK_ETH_SW_BASE+0x164)>>16);
8335 +#elif defined (CONFIG_RALINK_RT3883)
8336 +       /* no built-in switch */
8337 +#elif defined (CONFIG_RALINK_MT7621) || defined (CONFIG_ARCH_MT7623)
8338 +
8339 +#define DUMP_EACH_PORT(base)                                   \
8340 +       for(i=0; i < 7;i++) {                                   \
8341 +               mii_mgr_read(31, (base) + (i*0x100), &pkt_cnt); \
8342 +               seq_printf(seq, "%8u ", pkt_cnt);                       \
8343 +       }                                                       \
8344 +       seq_printf(seq, "\n");
8345 +
8346 +#if defined (CONFIG_RALINK_MT7621) /* TODO: need to update to use MT7530 compiler flag */
8347 +       if(sysRegRead(0xbe00000c & (1<<16)))//MCM
8348 +#endif
8349 +       {
8350 +               seq_printf(seq, "===================== %8s %8s %8s %8s %8s %8s %8s\n","Port0", "Port1", "Port2", "Port3", "Port4", "Port5", "Port6");
8351 +               seq_printf(seq, "Tx Drop Packet      :"); DUMP_EACH_PORT(0x4000);
8352 +               seq_printf(seq, "Tx CRC Error        :"); DUMP_EACH_PORT(0x4004);
8353 +               seq_printf(seq, "Tx Unicast Packet   :"); DUMP_EACH_PORT(0x4008);
8354 +               seq_printf(seq, "Tx Multicast Packet :"); DUMP_EACH_PORT(0x400C);
8355 +               seq_printf(seq, "Tx Broadcast Packet :"); DUMP_EACH_PORT(0x4010);
8356 +               seq_printf(seq, "Tx Collision Event  :"); DUMP_EACH_PORT(0x4014);
8357 +               seq_printf(seq, "Tx Pause Packet     :"); DUMP_EACH_PORT(0x402C);
8358 +               seq_printf(seq, "Rx Drop Packet      :"); DUMP_EACH_PORT(0x4060);
8359 +               seq_printf(seq, "Rx Filtering Packet :"); DUMP_EACH_PORT(0x4064);
8360 +               seq_printf(seq, "Rx Unicast Packet   :"); DUMP_EACH_PORT(0x4068);
8361 +               seq_printf(seq, "Rx Multicast Packet :"); DUMP_EACH_PORT(0x406C);
8362 +               seq_printf(seq, "Rx Broadcast Packet :"); DUMP_EACH_PORT(0x4070);
8363 +               seq_printf(seq, "Rx Alignment Error  :"); DUMP_EACH_PORT(0x4074);
8364 +               seq_printf(seq, "Rx CRC Error       :"); DUMP_EACH_PORT(0x4078);
8365 +               seq_printf(seq, "Rx Undersize Error  :"); DUMP_EACH_PORT(0x407C);
8366 +               seq_printf(seq, "Rx Fragment Error   :"); DUMP_EACH_PORT(0x4080);
8367 +               seq_printf(seq, "Rx Oversize Error   :"); DUMP_EACH_PORT(0x4084);
8368 +               seq_printf(seq, "Rx Jabber Error     :"); DUMP_EACH_PORT(0x4088);
8369 +               seq_printf(seq, "Rx Pause Packet     :"); DUMP_EACH_PORT(0x408C);
8370 +               mii_mgr_write(31, 0x4fe0, 0xf0);
8371 +               mii_mgr_write(31, 0x4fe0, 0x800000f0);
8372 +       }
8373 +#if defined (CONFIG_RALINK_MT7621)     /* TODO: need to update to use MT7530 compiler flag */
8374 +       else {
8375 +               seq_printf(seq, "no built-in switch\n");
8376 +       }
8377 +#endif
8378 +
8379 +#else /* RT305x, RT3352 */
8380 +       seq_printf(seq, "Port0: Good Pkt Cnt: RX=%08u (Bad Pkt Cnt: Rx=%08u)\n", sysRegRead(RALINK_ETH_SW_BASE+0xE8)&0xFFFF,sysRegRead(RALINK_ETH_SW_BASE+0xE8)>>16);
8381 +       seq_printf(seq, "Port1: Good Pkt Cnt: RX=%08u (Bad Pkt Cnt: Rx=%08u)\n", sysRegRead(RALINK_ETH_SW_BASE+0xEC)&0xFFFF,sysRegRead(RALINK_ETH_SW_BASE+0xEC)>>16);
8382 +       seq_printf(seq, "Port2: Good Pkt Cnt: RX=%08u (Bad Pkt Cnt: Rx=%08u)\n", sysRegRead(RALINK_ETH_SW_BASE+0xF0)&0xFFFF,sysRegRead(RALINK_ETH_SW_BASE+0xF0)>>16);
8383 +       seq_printf(seq, "Port3: Good Pkt Cnt: RX=%08u (Bad Pkt Cnt: Rx=%08u)\n", sysRegRead(RALINK_ETH_SW_BASE+0xF4)&0xFFFF,sysRegRead(RALINK_ETH_SW_BASE+0xF4)>>16);
8384 +       seq_printf(seq, "Port4: Good Pkt Cnt: RX=%08u (Bad Pkt Cnt: Rx=%08u)\n", sysRegRead(RALINK_ETH_SW_BASE+0xF8)&0xFFFF,sysRegRead(RALINK_ETH_SW_BASE+0xF8)>>16);
8385 +       seq_printf(seq, "Port5: Good Pkt Cnt: RX=%08u (Bad Pkt Cnt: Rx=%08u)\n", sysRegRead(RALINK_ETH_SW_BASE+0xFC)&0xFFFF,sysRegRead(RALINK_ETH_SW_BASE+0xFC)>>16);
8386 +#endif
8387 +       seq_printf(seq, "\n");
8388 +
8389 +       return 0;
8390 +}
8391 +
8392 +static int switch_count_open(struct inode *inode, struct file *file)
8393 +{
8394 +       return single_open(file, EswCntRead, NULL);
8395 +}
8396 +
8397 +static const struct file_operations switch_count_fops = {
8398 +       .owner          = THIS_MODULE,
8399 +       .open           = switch_count_open,
8400 +       .read           = seq_read,
8401 +       .llseek         = seq_lseek,
8402 +       .release        = single_release
8403 +};
8404 +
8405 +#if defined (CONFIG_ETHTOOL) /*&& defined (CONFIG_RAETH_ROUTER)*/
8406 +/*
8407 + * proc write procedure
8408 + */
8409 +static ssize_t change_phyid(struct file *file, const char __user *buffer,
8410 +                           size_t count, loff_t *data)
8411 +{
8412 +       char buf[32];
8413 +       struct net_device *cur_dev_p;
8414 +       END_DEVICE *ei_local;
8415 +       char if_name[64];
8416 +       unsigned int phy_id;
8417 +
8418 +       if (count > 32)
8419 +               count = 32;
8420 +       memset(buf, 0, 32);
8421 +       if (copy_from_user(buf, buffer, count))
8422 +               return -EFAULT;
8423 +
8424 +       /* determine interface name */
8425 +    strcpy(if_name, DEV_NAME); /* "eth2" by default */
8426 +    if(isalpha(buf[0]))
8427 +               sscanf(buf, "%s %d", if_name, &phy_id);
8428 +       else
8429 +               phy_id = simple_strtol(buf, 0, 10);
8430 +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,35)
8431 +       cur_dev_p = dev_get_by_name(&init_net, DEV_NAME);
8432 +#else
8433 +       cur_dev_p = dev_get_by_name(DEV_NAME);
8434 +#endif
8435 +       if (cur_dev_p == NULL)
8436 +               return -EFAULT;
8437 +
8438 +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,35)
8439 +       ei_local = netdev_priv(cur_dev_p);
8440 +#else
8441 +       ei_local = cur_dev_p->priv;
8442 +#endif
8443 +       ei_local->mii_info.phy_id = (unsigned char)phy_id;
8444 +       return count;
8445 +}
8446 +
8447 +#if defined(CONFIG_PSEUDO_SUPPORT)
8448 +static ssize_t change_gmac2_phyid(struct file *file, const char __user *buffer,
8449 +                                 size_t count, loff_t *data)
8450 +{
8451 +       char buf[32];
8452 +       struct net_device *cur_dev_p;
8453 +       PSEUDO_ADAPTER *pPseudoAd;
8454 +       char if_name[64];
8455 +       unsigned int phy_id;
8456 +
8457 +       if (count > 32)
8458 +               count = 32;
8459 +       memset(buf, 0, 32);
8460 +       if (copy_from_user(buf, buffer, count))
8461 +               return -EFAULT;
8462 +       /* determine interface name */
8463 +       strcpy(if_name, DEV2_NAME);  /* "eth3" by default */
8464 +       if(isalpha(buf[0]))
8465 +               sscanf(buf, "%s %d", if_name, &phy_id);
8466 +       else
8467 +               phy_id = simple_strtol(buf, 0, 10);
8468 +
8469 +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,35)
8470 +       cur_dev_p = dev_get_by_name(&init_net, DEV2_NAME);
8471 +#else
8472 +       cur_dev_p = dev_get_by_name(DEV2_NAMEj);
8473 +#endif
8474 +       if (cur_dev_p == NULL)
8475 +               return -EFAULT;
8476 +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,35)
8477 +        pPseudoAd = netdev_priv(cur_dev_p);
8478 +#else
8479 +       pPseudoAd = cur_dev_p->priv;
8480 +#endif
8481 +       pPseudoAd->mii_info.phy_id = (unsigned char)phy_id;
8482 +       return count;
8483 +}
8484 +
8485 +static struct file_operations gmac2_fops = {
8486 +       .owner          = THIS_MODULE,
8487 +       .write          = change_gmac2_phyid
8488 +};
8489 +#endif
8490 +#endif
8491 +
8492 +static int gmac_open(struct inode *inode, struct file *file)
8493 +{
8494 +       return single_open(file, RegReadMain, NULL);
8495 +}
8496 +
8497 +static struct file_operations gmac_fops = {
8498 +       .owner          = THIS_MODULE,
8499 +       .open           = gmac_open,
8500 +       .read           = seq_read,
8501 +       .llseek         = seq_lseek,
8502 +#if defined (CONFIG_ETHTOOL)
8503 +       .write          = change_phyid,
8504 +#endif
8505 +       .release        = single_release
8506 +};
8507 +
8508 +#if defined (TASKLET_WORKQUEUE_SW)
8509 +extern int init_schedule;
8510 +extern int working_schedule;
8511 +static int ScheduleRead(struct seq_file *seq, void *v)
8512 +{
8513 +       if (init_schedule == 1)
8514 +               seq_printf(seq, "Initialize Raeth with workqueque<%d>\n", init_schedule);
8515 +       else
8516 +               seq_printf(seq, "Initialize Raeth with tasklet<%d>\n", init_schedule);
8517 +       if (working_schedule == 1)
8518 +               seq_printf(seq, "Raeth is running at workqueque<%d>\n", working_schedule);
8519 +       else
8520 +               seq_printf(seq, "Raeth is running at tasklet<%d>\n", working_schedule);
8521 +
8522 +       return 0;
8523 +}
8524 +
8525 +static ssize_t ScheduleWrite(struct file *file, const char __user *buffer,
8526 +                     size_t count, loff_t *data)
8527 +{
8528 +       char buf[2];
8529 +       int old;
8530 +
8531 +       if (copy_from_user(buf, buffer, count))
8532 +               return -EFAULT;
8533 +       old = init_schedule;
8534 +       init_schedule = simple_strtol(buf, 0, 10);
8535 +       printk("Change Raeth initial schedule from <%d> to <%d>\n! Not running schedule at present !\n",
8536 +               old, init_schedule);
8537 +
8538 +       return count;
8539 +}
8540 +
8541 +static int schedule_switch_open(struct inode *inode, struct file *file)
8542 +{
8543 +       return single_open(file, ScheduleRead, NULL);
8544 +}
8545 +
8546 +static const struct file_operations schedule_sw_fops = {
8547 +       .owner          = THIS_MODULE,
8548 +       .open           = schedule_switch_open,
8549 +       .read           = seq_read,
8550 +       .write          = ScheduleWrite,
8551 +       .llseek         = seq_lseek,
8552 +       .release        = single_release
8553 +};
8554 +#endif
8555 +
8556 +#if defined(CONFIG_RAETH_PDMA_DVT)
8557 +static int PdmaDvtRead(struct seq_file *seq, void *v)
8558 +{
8559 +    seq_printf(seq, "g_pdma_dvt_show_config = 0x%x\n", pdma_dvt_get_show_config());
8560 +    seq_printf(seq, "g_pdma_dvt_rx_test_config = 0x%x\n", pdma_dvt_get_rx_test_config());
8561 +    seq_printf(seq, "g_pdma_dvt_tx_test_config = 0x%x\n", pdma_dvt_get_tx_test_config());
8562 +
8563 +       return 0;
8564 +}
8565 +
8566 +static int PdmaDvtOpen(struct inode *inode, struct file *file)
8567 +{
8568 +       return single_open(file, PdmaDvtRead, NULL);
8569 +}
8570 +
8571 +static ssize_t PdmaDvtWrite(struct file *file, const char __user *buffer,
8572 +                     size_t count, loff_t *data)
8573 +{
8574 +       char buf[32];
8575 +    char *pBuf;
8576 +    int len = count;
8577 +    int x = 0,y = 0;
8578 +    char *pToken = NULL;
8579 +    char *pDelimiter = " \t";
8580 +
8581 +    printk("write parameter len = %d\n\r", (int)len);
8582 +    if(len >= sizeof(buf)){
8583 +        printk("input handling fail!\n");
8584 +        len = sizeof(buf) - 1;
8585 +        return -1;
8586 +    }
8587 +
8588 +    if(copy_from_user(buf, buffer, len)){
8589 +        return -EFAULT;
8590 +    }
8591 +    buf[len] = '\0';
8592 +    printk("write parameter data = %s\n\r", buf);
8593 +
8594 +    pBuf = buf;
8595 +    pToken = strsep(&pBuf, pDelimiter);
8596 +    x = NULL != pToken ? simple_strtol(pToken, NULL, 16) : 0;
8597 +
8598 +    pToken = strsep(&pBuf, "\t\n ");
8599 +    if(pToken != NULL){
8600 +        y = NULL != pToken ? simple_strtol(pToken, NULL, 16) : 0;
8601 +        printk("y = 0x%08x \n\r", y);
8602 +    }
8603 +
8604 +    if ( (sizeof(pdma_dvt_dbg_func)/sizeof(pdma_dvt_dbg_func[0]) > x) && NULL != pdma_dvt_dbg_func[x])
8605 +    {
8606 +        (*pdma_dvt_dbg_func[x])(x, y);
8607 +    }
8608 +    else
8609 +    {
8610 +        printk("no handler defined for command id(0x%08x)\n\r", x);
8611 +    }
8612 +
8613 +    printk("x(0x%08x), y(0x%08x)\n", x, y);
8614 +
8615 +    return len;
8616 +}
8617 +
8618 +static const struct file_operations pdma_dev_sw_fops = {
8619 +       .owner          = THIS_MODULE,
8620 +       .open       = PdmaDvtOpen,
8621 +       .read           = seq_read,
8622 +       .write          = PdmaDvtWrite
8623 +};
8624 +#endif  //#if defined(CONFIG_RAETH_PDMA_DVT)
8625 +
8626 +int debug_proc_init(void)
8627 +{
8628 +    if (procRegDir == NULL)
8629 +       procRegDir = proc_mkdir(PROCREG_DIR, NULL);
8630 +
8631 +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,36)
8632 +    if ((procGmac = create_proc_entry(PROCREG_GMAC, 0, procRegDir)))
8633 +           procGmac->proc_fops = &gmac_fops;
8634 +    else
8635 +#else
8636 +    if (!(procGmac = proc_create(PROCREG_GMAC, 0, procRegDir, &gmac_fops)))
8637 +#endif
8638 +           printk("!! FAIL to create %s PROC !!\n", PROCREG_GMAC);
8639 +#if defined (CONFIG_ETHTOOL) /*&& defined (CONFIG_RAETH_ROUTER)*/
8640 +#if defined(CONFIG_PSEUDO_SUPPORT)
8641 +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,36)
8642 +    if ((procGmac2 = create_proc_entry(PROCREG_GMAC2, 0, procRegDir)))
8643 +           procGmac2->proc_fops = &gmac2_fops;
8644 +    else
8645 +#else
8646 +    if (!(procGmac2 = proc_create(PROCREG_GMAC2, 0, procRegDir, &gmac2_fops)))
8647 +#endif
8648 +           printk("!! FAIL to create %s PROC !!\n", PROCREG_GMAC2);
8649 +#endif
8650 +#endif
8651 +
8652 +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,36)
8653 +    if ((procSkbFree = create_proc_entry(PROCREG_SKBFREE, 0, procRegDir)))
8654 +           procSkbFree->proc_fops = &skb_free_fops;
8655 +    else
8656 +#else
8657 +    if (!(procSkbFree = proc_create(PROCREG_SKBFREE, 0, procRegDir, &skb_free_fops)))
8658 +#endif
8659 +           printk("!! FAIL to create %s PROC !!\n", PROCREG_SKBFREE);
8660 +
8661 +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,36)
8662 +    if ((procTxRing = create_proc_entry(PROCREG_TXRING, 0, procRegDir)))
8663 +           procTxRing->proc_fops = &tx_ring_fops;
8664 +    else
8665 +#else
8666 +    if (!(procTxRing = proc_create(PROCREG_TXRING, 0, procRegDir, &tx_ring_fops)))
8667 +#endif
8668 +           printk("!! FAIL to create %s PROC !!\n", PROCREG_TXRING);
8669 +
8670 +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,36)
8671 +    if ((procRxRing = create_proc_entry(PROCREG_RXRING, 0, procRegDir)))
8672 +           procRxRing->proc_fops = &rx_ring_fops;
8673 +    else
8674 +#else
8675 +    if (!(procRxRing = proc_create(PROCREG_RXRING, 0, procRegDir, &rx_ring_fops)))
8676 +#endif
8677 +           printk("!! FAIL to create %s PROC !!\n", PROCREG_RXRING);
8678 +
8679 +#if defined (CONFIG_RAETH_HW_LRO) || defined (CONFIG_RAETH_MULTIPLE_RX_RING)
8680 +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,36)
8681 +    if ((procRxRing1 = create_proc_entry(PROCREG_RXRING1, 0, procRegDir)))
8682 +           procRxRing1->proc_fops = &rx_ring1_fops;
8683 +    else
8684 +#else
8685 +    if (!(procRxRing1 = proc_create(PROCREG_RXRING1, 0, procRegDir, &rx_ring1_fops)))
8686 +#endif
8687 +           printk("!! FAIL to create %s PROC !!\n", PROCREG_RXRING1);
8688 +
8689 +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,36)
8690 +    if ((procRxRing2 = create_proc_entry(PROCREG_RXRING2, 0, procRegDir)))
8691 +           procRxRing2->proc_fops = &rx_ring2_fops;
8692 +    else
8693 +#else
8694 +    if (!(procRxRing2 = proc_create(PROCREG_RXRING2, 0, procRegDir, &rx_ring2_fops)))
8695 +#endif
8696 +           printk("!! FAIL to create %s PROC !!\n", PROCREG_RXRING2);
8697 +
8698 +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,36)
8699 +    if ((procRxRing3 = create_proc_entry(PROCREG_RXRING3, 0, procRegDir)))
8700 +           procRxRing3->proc_fops = &rx_ring3_fops;
8701 +    else
8702 +#else
8703 +    if (!(procRxRing3 = proc_create(PROCREG_RXRING3, 0, procRegDir, &rx_ring3_fops)))
8704 +#endif
8705 +           printk("!! FAIL to create %s PROC !!\n", PROCREG_RXRING3);
8706 +#endif  /* CONFIG_RAETH_HW_LRO */
8707 +
8708 +#if defined (CONFIG_MIPS)
8709 +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,36)
8710 +    if ((procSysCP0 = create_proc_entry(PROCREG_CP0, 0, procRegDir)))
8711 +           procSysCP0->proc_fops = &cp0_reg_fops;
8712 +    else
8713 +#else
8714 +    if (!(procSysCP0 = proc_create(PROCREG_CP0, 0, procRegDir, &cp0_reg_fops)))
8715 +#endif
8716 +           printk("!! FAIL to create %s PROC !!\n", PROCREG_CP0);
8717 +#endif
8718 +
8719 +#if defined(CONFIG_RAETH_TSO)
8720 +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,36)
8721 +    if ((procNumOfTxd = create_proc_entry(PROCREG_NUM_OF_TXD, 0, procRegDir)))
8722 +           procNumOfTxd->proc_fops = &tso_txd_num_fops;
8723 +    else
8724 +#else
8725 +    if (!(procNumOfTxd = proc_create(PROCREG_NUM_OF_TXD, 0, procRegDir, &tso_txd_num_fops)))
8726 +#endif
8727 +           printk("!! FAIL to create %s PROC !!\n", PROCREG_NUM_OF_TXD);
8728 +
8729 +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,36)
8730 +    if ((procTsoLen = create_proc_entry(PROCREG_TSO_LEN, 0, procRegDir)))
8731 +           procTsoLen->proc_fops = &tso_len_fops;
8732 +    else
8733 +#else
8734 +    if (!(procTsoLen = proc_create(PROCREG_TSO_LEN, 0, procRegDir, &tso_len_fops)))
8735 +#endif
8736 +           printk("!! FAIL to create %s PROC !!\n", PROCREG_TSO_LEN);
8737 +#endif
8738 +
8739 +#if defined(CONFIG_RAETH_LRO)
8740 +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,36)
8741 +    if ((procLroStats = create_proc_entry(PROCREG_LRO_STATS, 0, procRegDir)))
8742 +           procLroStats->proc_fops = &lro_stats_fops;
8743 +    else
8744 +#else
8745 +    if (!(procLroStats = proc_create(PROCREG_LRO_STATS, 0, procRegDir, &lro_stats_fops)))
8746 +#endif
8747 +           printk("!! FAIL to create %s PROC !!\n", PROCREG_LRO_STATS);
8748 +#endif
8749 +
8750 +#if defined(CONFIG_RAETH_HW_LRO)
8751 +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,36)
8752 +    if ((procHwLroStats = create_proc_entry(PROCREG_HW_LRO_STATS, 0, procRegDir)))
8753 +           procHwLroStats->proc_fops = &hw_lro_stats_fops;
8754 +    else
8755 +#else
8756 +    if (!(procHwLroStats = proc_create(PROCREG_HW_LRO_STATS, 0, procRegDir, &hw_lro_stats_fops)))
8757 +#endif
8758 +           printk("!! FAIL to create %s PROC !!\n", PROCREG_HW_LRO_STATS);
8759 +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,36)
8760 +    if ((procHwLroAutoTlb = create_proc_entry(PROCREG_HW_LRO_AUTO_TLB, 0, procRegDir)))
8761 +           procHwLroAutoTlb->proc_fops = &hw_lro_auto_tlb_fops;
8762 +    else
8763 +#else
8764 +    if (!(procHwLroAutoTlb = proc_create(PROCREG_HW_LRO_AUTO_TLB, 0, procRegDir, &hw_lro_auto_tlb_fops)))
8765 +#endif
8766 +           printk("!! FAIL to create %s PROC !!\n", PROCREG_HW_LRO_AUTO_TLB);
8767 +#endif  /* CONFIG_RAETH_HW_LRO */
8768 +
8769 +#if defined(CONFIG_RAETH_QOS)
8770 +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,36)
8771 +    if ((procRaQOS = create_proc_entry(PROCREG_RAQOS, 0, procRegDir)))
8772 +           procRaQOS->proc_fops = &raeth_qos_fops;
8773 +    else
8774 +#else
8775 +    if (!(procRaQOS = proc_create(PROCREG_RAQOS, 0, procRegDir, &raeth_qos_fops)))
8776 +#endif
8777 +           printk("!! FAIL to create %s PROC !!\n", PROCREG_RAQOS);
8778 +#endif
8779 +
8780 +#if defined(CONFIG_USER_SNMPD)
8781 +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,36)
8782 +    if ((procRaSnmp = create_proc_entry(PROCREG_SNMP, S_IRUGO, procRegDir)))
8783 +           procRaSnmp->proc_fops = &ra_snmp_seq_fops;
8784 +    else
8785 +#else
8786 +    if (!(procRaSnmp = proc_create(PROCREG_SNMP, S_IRUGO, procRegDir, &ra_snmp_seq_fops)))
8787 +#endif
8788 +           printk("!! FAIL to create %s PROC !!\n", PROCREG_SNMP);
8789 +#endif
8790 +
8791 +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,36)
8792 +    if ((procEswCnt = create_proc_entry(PROCREG_ESW_CNT, 0, procRegDir)))
8793 +           procEswCnt->proc_fops = &switch_count_fops;
8794 +    else
8795 +#else
8796 +    if (!(procEswCnt = proc_create(PROCREG_ESW_CNT, 0, procRegDir, &switch_count_fops)))
8797 +#endif
8798 +           printk("!! FAIL to create %s PROC !!\n", PROCREG_ESW_CNT);
8799 +
8800 +#if defined (TASKLET_WORKQUEUE_SW)
8801 +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,36)
8802 +    if ((procSCHE = create_proc_entry(PROCREG_SCHE, 0, procRegDir)))
8803 +           procSCHE->proc_fops = &schedule_sw_fops;
8804 +    else
8805 +#else
8806 +    if (!(procSCHE = proc_create(PROCREG_SCHE, 0, procRegDir, &schedule_sw_fops)))
8807 +#endif
8808 +           printk("!! FAIL to create %s PROC !!\n", PROCREG_SCHE);
8809 +#endif
8810 +
8811 +#if defined(CONFIG_RAETH_PDMA_DVT)
8812 +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,36)
8813 +    if ((procPdmaDvt = create_proc_entry(PROCREG_PDMA_DVT, 0, procRegDir)))
8814 +        procPdmaDvt->proc_fops = &pdma_dev_sw_fops;
8815 +    else
8816 +#else
8817 +    if (!(procPdmaDvt = proc_create(PROCREG_PDMA_DVT, 0, procRegDir, &pdma_dev_sw_fops )))
8818 +#endif
8819 +        printk("!! FAIL to create %s PROC !!\n", PROCREG_PDMA_DVT);
8820 +#endif  //#if defined(CONFIG_RAETH_PDMA_DVT)
8821 +
8822 +    printk(KERN_ALERT "PROC INIT OK!\n");
8823 +    return 0;
8824 +}
8825 +
8826 +void debug_proc_exit(void)
8827 +{
8828 +
8829 +    if (procSysCP0)
8830 +       remove_proc_entry(PROCREG_CP0, procRegDir);
8831 +
8832 +    if (procGmac)
8833 +       remove_proc_entry(PROCREG_GMAC, procRegDir);
8834 +#if defined(CONFIG_PSEUDO_SUPPORT) && defined(CONFIG_ETHTOOL)
8835 +    if (procGmac)
8836 +        remove_proc_entry(PROCREG_GMAC, procRegDir);
8837 +#endif
8838 +    if (procSkbFree)
8839 +       remove_proc_entry(PROCREG_SKBFREE, procRegDir);
8840 +
8841 +    if (procTxRing)
8842 +       remove_proc_entry(PROCREG_TXRING, procRegDir);
8843 +
8844 +    if (procRxRing)
8845 +       remove_proc_entry(PROCREG_RXRING, procRegDir);
8846 +
8847 +#if defined(CONFIG_RAETH_TSO)
8848 +    if (procNumOfTxd)
8849 +       remove_proc_entry(PROCREG_NUM_OF_TXD, procRegDir);
8850 +
8851 +    if (procTsoLen)
8852 +       remove_proc_entry(PROCREG_TSO_LEN, procRegDir);
8853 +#endif
8854 +
8855 +#if defined(CONFIG_RAETH_LRO)
8856 +    if (procLroStats)
8857 +       remove_proc_entry(PROCREG_LRO_STATS, procRegDir);
8858 +#endif
8859 +
8860 +#if defined(CONFIG_RAETH_QOS)
8861 +    if (procRaQOS)
8862 +       remove_proc_entry(PROCREG_RAQOS, procRegDir);
8863 +    if (procRaFeIntr)
8864 +       remove_proc_entry(PROCREG_RXDONE_INTR, procRegDir);
8865 +    if (procRaEswIntr)
8866 +       remove_proc_entry(PROCREG_ESW_INTR, procRegDir);
8867 +#endif
8868 +
8869 +#if defined(CONFIG_USER_SNMPD)
8870 +    if (procRaSnmp)
8871 +       remove_proc_entry(PROCREG_SNMP, procRegDir);
8872 +#endif
8873 +
8874 +    if (procEswCnt)
8875 +       remove_proc_entry(PROCREG_ESW_CNT, procRegDir);
8876 +
8877 +    //if (procRegDir)
8878 +       //remove_proc_entry(PROCREG_DIR, 0);
8879 +
8880 +    printk(KERN_ALERT "proc exit\n");
8881 +}
8882 +EXPORT_SYMBOL(procRegDir);
8883 diff --git a/drivers/net/ethernet/raeth/ra_mac.h b/drivers/net/ethernet/raeth/ra_mac.h
8884 new file mode 100644
8885 index 0000000..66b32d3
8886 --- /dev/null
8887 +++ b/drivers/net/ethernet/raeth/ra_mac.h
8888 @@ -0,0 +1,57 @@
8889 +#ifndef RA_MAC_H
8890 +#define RA_MAC_H
8891 +
8892 +void ra2880stop(END_DEVICE *ei_local);
8893 +void ra2880MacAddressSet(unsigned char p[6]);
8894 +void ra2880Mac2AddressSet(unsigned char p[6]);
8895 +void ethtool_init(struct net_device *dev);
8896 +
8897 +void ra2880EnableInterrupt(void);
8898 +
8899 +void dump_qos(void);
8900 +void dump_reg(struct seq_file *s);
8901 +void dump_cp0(void);
8902 +
8903 +int debug_proc_init(void);
8904 +void debug_proc_exit(void);
8905 +
8906 +#if defined (CONFIG_RALINK_RT6855) || defined(CONFIG_RALINK_RT6855A) || \
8907 +           defined (CONFIG_RALINK_MT7620) || defined(CONFIG_RALINK_MT7621)
8908 +void enable_auto_negotiate(int unused);
8909 +#else
8910 +void enable_auto_negotiate(int ge);
8911 +#endif
8912 +
8913 +void rt2880_gmac_hard_reset(void);
8914 +
8915 +int TsoLenUpdate(int tso_len);
8916 +int NumOfTxdUpdate(int num_of_txd);
8917 +
8918 +#ifdef CONFIG_RAETH_LRO
8919 +int LroStatsUpdate(struct net_lro_mgr *lro_mgr, bool all_flushed);
8920 +#endif
8921 +#ifdef CONFIG_RAETH_HW_LRO
8922 +int HwLroStatsUpdate(unsigned int ring_num, unsigned int agg_cnt, unsigned int agg_size);
8923 +#if defined(CONFIG_RAETH_HW_LRO_REASON_DBG)
8924 +#define HW_LRO_AGG_FLUSH        (1)
8925 +#define HW_LRO_AGE_FLUSH        (2)
8926 +#define HW_LRO_NOT_IN_SEQ_FLUSH (3)
8927 +#define HW_LRO_TIMESTAMP_FLUSH  (4)
8928 +#define HW_LRO_NON_RULE_FLUSH   (5)
8929 +int HwLroFlushStatsUpdate(unsigned int ring_num, unsigned int flush_reason);
8930 +#endif  /* CONFIG_RAETH_HW_LRO_REASON_DBG */
8931 +typedef int (*HWLRO_DBG_FUNC)(int par1, int par2);
8932 +int hwlro_agg_cnt_ctrl(int par1, int par2);
8933 +int hwlro_agg_time_ctrl(int par1, int par2);
8934 +int hwlro_age_time_ctrl(int par1, int par2);
8935 +int hwlro_pkt_int_alpha_ctrl(int par1, int par2);
8936 +int hwlro_threshold_ctrl(int par1, int par2);
8937 +int hwlro_fix_setting_switch_ctrl(int par1, int par2);
8938 +#endif  /* CONFIG_RAETH_HW_LRO */
8939 +int getnext(const char *src, int separator, char *dest);
8940 +int str_to_ip(unsigned int *ip, const char *str);
8941 +
8942 +#if defined(CONFIG_RAETH_PDMA_DVT)
8943 +typedef int (*PDMA_DBG_FUNC)(int par1, int par2);
8944 +#endif  //#if defined(CONFIG_RAETH_PDMA_DVT)
8945 +#endif
8946 diff --git a/drivers/net/ethernet/raeth/ra_netlink.c b/drivers/net/ethernet/raeth/ra_netlink.c
8947 new file mode 100644
8948 index 0000000..f7c3650
8949 --- /dev/null
8950 +++ b/drivers/net/ethernet/raeth/ra_netlink.c
8951 @@ -0,0 +1,142 @@
8952 +// for netlink header
8953 +#include <asm/types.h>
8954 +#include <net/sock.h>
8955 +#include <linux/socket.h>
8956 +#include <linux/netlink.h>
8957 +#include <linux/skbuff.h>
8958 +#include <linux/net.h>
8959 +#include <linux/version.h>
8960 +
8961 +#include "csr_netlink.h"
8962 +#include "ra2882ethreg.h"
8963 +#include "ra_netlink.h"
8964 +
8965 +static struct sock *csr_msg_socket = NULL; // synchronize socket for netlink use
8966 +unsigned int flags;
8967 +
8968 +void rt2880_csr_receiver(struct sock *sk, int len)
8969 +{
8970 +       struct sk_buff *skb;
8971 +       int err;
8972 +       struct nlmsghdr *nlh;
8973 +       unsigned int reg_value = 0;
8974 +       CSR_MSG *csrmsg;
8975 +       RAETH_PRINT("csr netlink receiver!\n");
8976 +       skb = skb_recv_datagram(sk, 0, 1, &err);
8977 +
8978 +       RAETH_PRINT("error no : %d\n", err);
8979 +
8980 +       if (skb == NULL) {
8981 +               printk("rt2880_csr_receiver(): No data received, error!\n");
8982 +               return;
8983 +       }
8984 +
8985 +       nlh = (struct nlmsghdr*)skb->data;
8986 +
8987 +       csrmsg = NLMSG_DATA(nlh);
8988 +
8989 +       if (csrmsg->enable == CSR_READ ) {
8990 +               reg_value = sysRegRead(csrmsg->address);
8991 +#if 0
8992 +               printk("raeth -- 0x%08x: 0x%08x\n", csrmsg->address, reg_value);
8993 +#endif
8994 +       } else if ( csrmsg->enable == CSR_WRITE ) {
8995 +               sysRegWrite(csrmsg->address, csrmsg->default_value);
8996 +               reg_value = sysRegRead(csrmsg->address);
8997 +       } else if ( csrmsg->enable == CSR_TEST ) {
8998 +               reg_value = sysRegRead(csrmsg->address);
8999 +               printk("0x%08x: 0x%08x\n", (unsigned int)csrmsg->address, reg_value);
9000 +       }
9001 +       else
9002 +               printk("drv: Command format error!\n");
9003 +
9004 +       csrmsg->default_value = reg_value;
9005 +
9006 +       RAETH_PRINT("drv: rt2880_csr_msgsend() - msg to send!\n");
9007 +
9008 +       err = rt2880_csr_msgsend(csrmsg);
9009 +
9010 +       if ( err == -2 )
9011 +               printk("drv: msg send error!\n");
9012 +
9013 +       skb_free_datagram(sk, skb);
9014 +}
9015 +
9016 +int rt2880_csr_msgsend(CSR_MSG* csrmsg)
9017 +{
9018 +       struct sk_buff *skb;
9019 +       struct nlmsghdr *nlh = NULL;
9020 +       size_t size = 0;
9021 +       struct sock *send_syncnl = csr_msg_socket;
9022 +
9023 +       CSR_MSG* csr_reg;
9024 +       if (send_syncnl == NULL) {
9025 +               printk("drv: netlink_kernel_create() failed!\n");
9026 +               return -1;
9027 +       }
9028 +
9029 +       size = NLMSG_SPACE(sizeof(CSR_MSG));
9030 +       skb = alloc_skb(size, GFP_ATOMIC);
9031 +
9032 +       if(!skb)
9033 +       {
9034 +               printk("rt2880_csr_msgsend() : error! msg structure not available\n");
9035 +               return -1;
9036 +       }
9037 +
9038 +       nlh = NLMSG_PUT(skb, 0, 0, RALINK_CSR_GROUP, size - sizeof(struct nlmsghdr));
9039 +
9040 +       if (!nlh)
9041 +       {
9042 +               printk("rt2880_csr_msgsend() : error! nlh structure not available\n");
9043 +               return -1;
9044 +       }
9045 +
9046 +       csr_reg = NLMSG_DATA(nlh);
9047 +       if (!csr_reg)
9048 +       {
9049 +               printk("rt2880_csr_msgsend() : error! nlh structure not available\n");
9050 +               return -1;
9051 +       }
9052 +
9053 +       csr_reg->address        = csrmsg->address;
9054 +       csr_reg->default_value  = csrmsg->default_value;
9055 +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,21)
9056 +       NETLINK_CB(skb).dst_group = RALINK_CSR_GROUP;
9057 +#else
9058 +       NETLINK_CB(skb).dst_groups = RALINK_CSR_GROUP;
9059 +#endif
9060 +       netlink_broadcast(send_syncnl, skb, 0, RALINK_CSR_GROUP, GFP_ATOMIC);
9061 +       return 0;
9062 +
9063 +nlmsg_failure:
9064 +       return -2;
9065 +}
9066 +
9067 +int csr_netlink_init()
9068 +{
9069 +
9070 +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,21)
9071 +       csr_msg_socket = netlink_kernel_create(NETLINK_CSR, RALINK_CSR_GROUP, rt2880_csr_receiver, THIS_MODULE);
9072 +#else
9073 +       csr_msg_socket = netlink_kernel_create(NETLINK_CSR, rt2880_csr_receiver);
9074 +#endif
9075 +
9076 +       if ( csr_msg_socket == NULL )
9077 +               printk("unable to create netlink socket!\n");
9078 +       else
9079 +               printk("Netlink init ok!\n");
9080 +       return 0;
9081 +}
9082 +
9083 +void csr_netlink_end()
9084 +{
9085 +       if (csr_msg_socket != NULL){
9086 +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,21)
9087 +               sock_release(csr_msg_socket->sk_socket);
9088 +#else
9089 +               sock_release(csr_msg_socket->socket);
9090 +#endif
9091 +               printk("Netlink end...\n");
9092 +       }
9093 +}
9094 diff --git a/drivers/net/ethernet/raeth/ra_netlink.h b/drivers/net/ethernet/raeth/ra_netlink.h
9095 new file mode 100644
9096 index 0000000..19ca71f
9097 --- /dev/null
9098 +++ b/drivers/net/ethernet/raeth/ra_netlink.h
9099 @@ -0,0 +1,10 @@
9100 +#ifndef RA_NETLINK
9101 +#define RA_NETLINK
9102 +
9103 +#include "csr_netlink.h"
9104 +int rt2880_csr_msgsend(CSR_MSG* csrmsg);
9105 +void rt2880_csr_receiver(struct sock *sk, int len);
9106 +int csr_netlink_init(void);
9107 +void csr_netlink_end(void);
9108 +
9109 +#endif
9110 diff --git a/drivers/net/ethernet/raeth/ra_qos.c b/drivers/net/ethernet/raeth/ra_qos.c
9111 new file mode 100644
9112 index 0000000..0a7d9c5
9113 --- /dev/null
9114 +++ b/drivers/net/ethernet/raeth/ra_qos.c
9115 @@ -0,0 +1,655 @@
9116 +#include <asm/io.h>
9117 +#include <linux/pci.h>
9118 +#include <linux/netdevice.h>
9119 +#include <linux/etherdevice.h>
9120 +#include <linux/net.h>
9121 +#include <linux/in.h>
9122 +#include "ra_qos.h"
9123 +#include "raether.h"
9124 +#include "ra2882ethreg.h"
9125 +
9126 +#include <asm/types.h>
9127 +#include <net/sock.h>
9128 +#include <linux/socket.h>
9129 +#include <linux/skbuff.h>
9130 +#include <linux/net.h>
9131 +#include <linux/if_vlan.h>
9132 +#include <linux/ip.h>
9133 +
9134 +
9135 +#if defined (CONFIG_RA_HW_NAT) || defined (CONFIG_RA_HW_NAT_MODULE)
9136 +#include "../../../net/nat/hw_nat/ra_nat.h"
9137 +#endif
9138 +
9139 +#define CONTI_TX_SEND_MAX_SIZE 1440
9140 +
9141 +/*
9142 + * set tx queue # to descriptor
9143 + */
9144 +void rt3052_tx_queue_init(unsigned long data)
9145 +{
9146 +       /* define qos p */
9147 +
9148 +}
9149 +
9150 +void rt3052_pse_port0_fc_clear(unsigned long data)
9151 +{
9152 +       /* clear FE_INT_STATUS.PSE_P0_FC */
9153 +
9154 +}
9155 +
9156 +inline int get_tx_ctx_idx(unsigned int ring_no, unsigned long *idx)
9157 +{
9158 +       switch (ring_no) {
9159 +               case RING0:
9160 +                       *idx = *(unsigned long*)TX_CTX_IDX0;
9161 +                       break;
9162 +               case RING1:
9163 +                       *idx = *(unsigned long*)TX_CTX_IDX1;
9164 +                       break;
9165 +               case RING2:
9166 +                       *idx = *(unsigned long*)TX_CTX_IDX2;
9167 +                       break;
9168 +               case RING3:
9169 +                       *idx = *(unsigned long*)TX_CTX_IDX3;
9170 +                       break;
9171 +               default:
9172 +                       printk("set_tx_ctx_idex error\n");
9173 +                       return -1;
9174 +       };
9175 +       return 0;
9176 +}
9177 +
9178 +inline int set_tx_ctx_idx(unsigned int ring_no, unsigned int idx)
9179 +{
9180 +       switch (ring_no ) {
9181 +               case RING0:
9182 +                       *(unsigned long*)TX_CTX_IDX0 = cpu_to_le32((u32)idx);
9183 +                       break;
9184 +               case RING1:
9185 +                       *(unsigned long*)TX_CTX_IDX1 = cpu_to_le32((u32)idx);
9186 +                       break;
9187 +               case RING2:
9188 +                       *(unsigned long*)TX_CTX_IDX2 = cpu_to_le32((u32)idx);
9189 +                       break;
9190 +               case RING3:
9191 +                       *(unsigned long*)TX_CTX_IDX3 = cpu_to_le32((u32)idx);
9192 +                       break;
9193 +               default:
9194 +                       printk("set_tx_ctx_idex error\n");
9195 +                       return -1;
9196 +       };
9197 +
9198 +       return 1;
9199 +}
9200 +
9201 +void get_tx_desc_and_dtx_idx(END_DEVICE* ei_local, int ring_no, unsigned long *tx_dtx_idx, struct PDMA_txdesc **tx_desc)
9202 +{
9203 +       switch (ring_no) {
9204 +               case RING0:
9205 +                       *tx_desc = ei_local->tx_ring0;
9206 +                       *tx_dtx_idx      = *(unsigned long*)TX_DTX_IDX0;
9207 +                       break;
9208 +               case RING1:
9209 +                       *tx_desc = ei_local->tx_ring1;
9210 +                       *tx_dtx_idx      = *(unsigned long*)TX_DTX_IDX1;
9211 +                       break;
9212 +               case RING2:
9213 +                       *tx_desc = ei_local->tx_ring2;
9214 +                       *tx_dtx_idx      = *(unsigned long*)TX_DTX_IDX2;
9215 +                       break;
9216 +               case RING3:
9217 +                       *tx_desc = ei_local->tx_ring3;
9218 +                       *tx_dtx_idx      = *(unsigned long*)TX_DTX_IDX3;
9219 +                       break;
9220 +               default:
9221 +                       printk("ring_no input error... %d\n", ring_no);
9222 +       };
9223 +}
9224 +
9225 +int fe_qos_packet_send(struct net_device *dev, struct sk_buff* skb, unsigned int ring_no, unsigned int qn, unsigned pn)
9226 +{
9227 +       END_DEVICE* ei_local = netdev_priv(dev);
9228 +       struct PDMA_txdesc* tx_desc;
9229 +       unsigned int tx_cpu_owner_idx, tx_dtx_idx;
9230 +
9231 +       unsigned int    length=skb->len;
9232 +       int ret;
9233 +       unsigned long flags;
9234 +
9235 +       //printk("fe_qos_packet_send: ring_no=%d qn=%d pn=%d\n", ring_no, qn, pn);
9236 +
9237 +       switch ( ring_no ) {
9238 +               case 0:
9239 +                       tx_desc = ei_local->tx_ring0;
9240 +                       tx_cpu_owner_idx = *(unsigned long*)TX_CTX_IDX0;
9241 +                       tx_dtx_idx       = *(unsigned long*)TX_DTX_IDX0;
9242 +                       break;
9243 +               case 1:
9244 +                       tx_desc = ei_local->tx_ring1;
9245 +                       tx_cpu_owner_idx = *(unsigned long*)TX_CTX_IDX1;
9246 +                       tx_dtx_idx       = *(unsigned long*)TX_DTX_IDX1;
9247 +                       break;
9248 +               case 2:
9249 +                       tx_desc = ei_local->tx_ring2;
9250 +                       tx_cpu_owner_idx = *(unsigned long*)TX_CTX_IDX2;
9251 +                       tx_dtx_idx       = *(unsigned long*)TX_DTX_IDX2;
9252 +                       break;
9253 +               case 3:
9254 +                       tx_desc = ei_local->tx_ring3;
9255 +                       tx_cpu_owner_idx = *(unsigned long*)TX_CTX_IDX3;
9256 +                       tx_dtx_idx       = *(unsigned long*)TX_DTX_IDX3;
9257 +                       break;
9258 +               default:
9259 +                       printk("ring_no input error... %d\n", ring_no);
9260 +                       return -1;
9261 +       };
9262 +
9263 +       //printk("tx_cpu_owner_idx=%d tx_dtx_idx=%d\n", tx_cpu_owner_idx, tx_dtx_idx);
9264 +
9265 +       if(tx_desc == NULL) {
9266 +               printk("%s : txdesc is NULL\n", dev->name);
9267 +               return -1;
9268 +       }
9269 +
9270 +       tx_desc[tx_cpu_owner_idx].txd_info1.SDP0 = virt_to_phys(skb->data);
9271 +       tx_desc[tx_cpu_owner_idx].txd_info2.SDL0 = length;
9272 +       tx_desc[tx_cpu_owner_idx].txd_info2.DDONE_bit = 0;
9273 +       tx_desc[tx_cpu_owner_idx].txd_info4.PN = pn;
9274 +       tx_desc[tx_cpu_owner_idx].txd_info4.QN = qn;
9275 +
9276 +#ifdef CONFIG_RAETH_CHECKSUM_OFFLOAD
9277 +       ei_local->tx_ring0[tx_cpu_owner_idx].txd_info4.TCO = 1;
9278 +       ei_local->tx_ring0[tx_cpu_owner_idx].txd_info4.UCO = 1;
9279 +       ei_local->tx_ring0[tx_cpu_owner_idx].txd_info4.ICO = 1;
9280 +#endif
9281 +
9282 +#if defined (CONFIG_RA_HW_NAT) || defined (CONFIG_RA_HW_NAT_MODULE)
9283 +       if(FOE_MAGIC_TAG(skb) == FOE_MAGIC_PPE) {
9284 +           tx_desc[tx_cpu_owner_idx].txd_info4.PN = 6; /* PPE */
9285 +       } else {
9286 +           tx_desc[tx_cpu_owner_idx].txd_info4.PN = pn;
9287 +       }
9288 +
9289 +#endif
9290 +
9291 +       spin_lock_irqsave(&ei_local->page_lock, flags);
9292 +       ei_local->skb_free[ring_no][tx_cpu_owner_idx] = skb;
9293 +       tx_cpu_owner_idx = (tx_cpu_owner_idx +1) % NUM_TX_DESC;
9294 +       ret = set_tx_ctx_idx(ring_no, tx_cpu_owner_idx);
9295 +       spin_unlock_irqrestore(&ei_local->page_lock, flags);
9296 +
9297 +       ei_local->stat.tx_packets++;
9298 +       ei_local->stat.tx_bytes += length;
9299 +
9300 +#ifdef CONFIG_RAETH_NAPI
9301 +       switch ( ring_no ) {
9302 +               case 0:
9303 +                       if ( ei_local->tx0_full == 1) {
9304 +                               ei_local->tx0_full = 0;
9305 +                               netif_wake_queue(dev);
9306 +                       }
9307 +                       break;
9308 +               case 1:
9309 +                       if ( ei_local->tx1_full == 1) {
9310 +                               ei_local->tx1_full = 0;
9311 +                               netif_wake_queue(dev);
9312 +                       }
9313 +                       break;
9314 +               case 2:
9315 +                       if ( ei_local->tx2_full == 1) {
9316 +                               ei_local->tx2_full = 0;
9317 +                               netif_wake_queue(dev);
9318 +                       }
9319 +                       break;
9320 +               case 3:
9321 +                       if ( ei_local->tx3_full == 1) {
9322 +                               ei_local->tx3_full = 0;
9323 +                               netif_wake_queue(dev);
9324 +                       }
9325 +                       break;
9326 +               default :
9327 +                       printk("ring_no input error %d\n", ring_no);
9328 +       };
9329 +#endif
9330 +       return length;
9331 +}
9332 +
9333 +int fe_tx_desc_init(struct net_device *dev, unsigned int ring_no, unsigned int qn, unsigned int pn)
9334 +{
9335 +       END_DEVICE* ei_local = netdev_priv(dev);
9336 +       struct PDMA_txdesc *tx_desc;
9337 +       unsigned int tx_cpu_owner_idx = 0;
9338 +       int i;
9339 +       unsigned int phy_tx_ring;
9340 +
9341 +       // sanity check
9342 +       if ( ring_no > 3 ){
9343 +               printk("%s : ring_no - %d, please under 4...\n", dev->name, ring_no);
9344 +               return 0;
9345 +       }
9346 +
9347 +       if ( pn > 2 ){
9348 +               printk("%s : pn - %d, please under 2...\n", dev->name, pn);
9349 +               return 0;
9350 +       }
9351 +
9352 +       tx_desc = pci_alloc_consistent(NULL, NUM_TX_DESC*sizeof(struct PDMA_txdesc), &phy_tx_ring);
9353 +       ei_local->tx_cpu_owner_idx0 = tx_cpu_owner_idx;
9354 +
9355 +       switch (ring_no) {
9356 +               case 0:
9357 +                       ei_local->tx_ring0 = tx_desc;
9358 +                       ei_local->phy_tx_ring0 = phy_tx_ring;
9359 +                       break;
9360 +               case 1:
9361 +                       ei_local->phy_tx_ring1 = phy_tx_ring;
9362 +                       ei_local->tx_ring1 = tx_desc;
9363 +                       break;
9364 +               case 2:
9365 +                       ei_local->phy_tx_ring2 = phy_tx_ring;
9366 +                       ei_local->tx_ring2 = tx_desc;
9367 +                       break;
9368 +               case 3:
9369 +                       ei_local->phy_tx_ring3 = phy_tx_ring;
9370 +                       ei_local->tx_ring3 = tx_desc;
9371 +                       break;
9372 +               default:
9373 +                       printk("ring_no input error! %d\n", ring_no);
9374 +                       pci_free_consistent(NULL, NUM_TX_DESC*sizeof(struct PDMA_txdesc), tx_desc, phy_tx_ring);
9375 +                       return 0;
9376 +       };
9377 +
9378 +       if ( tx_desc == NULL)
9379 +       {
9380 +               printk("tx desc allocation failed!\n");
9381 +               return 0;
9382 +       }
9383 +
9384 +       for( i = 0; i < NUM_TX_DESC; i++) {
9385 +               memset( &tx_desc[i], 0, sizeof(struct PDMA_txdesc));
9386 +               tx_desc[i].txd_info2.LS0_bit = 1;
9387 +               tx_desc[i].txd_info2.DDONE_bit = 1;
9388 +               tx_desc[i].txd_info4.PN = pn;
9389 +               tx_desc[i].txd_info4.QN = qn;
9390 +       }
9391 +
9392 +       switch ( ring_no ) {
9393 +               case 0 :
9394 +                       *(unsigned long*)TX_BASE_PTR0 = phys_to_bus((u32) phy_tx_ring);
9395 +                       *(unsigned long*)TX_MAX_CNT0  = cpu_to_le32((u32)NUM_TX_DESC);
9396 +                       *(unsigned long*)TX_CTX_IDX0  = cpu_to_le32((u32) tx_cpu_owner_idx);
9397 +                       sysRegWrite(PDMA_RST_CFG, PST_DTX_IDX0);
9398 +                       break;
9399 +               case 1 :
9400 +                       *(unsigned long*)TX_BASE_PTR1 = phys_to_bus((u32) phy_tx_ring);
9401 +                       *(unsigned long*)TX_MAX_CNT1  = cpu_to_le32((u32)NUM_TX_DESC);
9402 +                       *(unsigned long*)TX_CTX_IDX1  = cpu_to_le32((u32) tx_cpu_owner_idx);
9403 +                       sysRegWrite(PDMA_RST_CFG, PST_DTX_IDX1);
9404 +                       break;
9405 +               case 2 :
9406 +                       *(unsigned long*)TX_BASE_PTR2 = phys_to_bus((u32) phy_tx_ring);
9407 +                       *(unsigned long*)TX_MAX_CNT2  = cpu_to_le32((u32)NUM_TX_DESC);
9408 +                       *(unsigned long*)TX_CTX_IDX2  = cpu_to_le32((u32) tx_cpu_owner_idx);
9409 +                       sysRegWrite(PDMA_RST_CFG, PST_DTX_IDX2);
9410 +                       break;
9411 +               case 3 :
9412 +                       *(unsigned long*)TX_BASE_PTR3 = phys_to_bus((u32) phy_tx_ring);
9413 +                       *(unsigned long*)TX_MAX_CNT3  = cpu_to_le32((u32)NUM_TX_DESC);
9414 +                       *(unsigned long*)TX_CTX_IDX3  = cpu_to_le32((u32) tx_cpu_owner_idx);
9415 +                       sysRegWrite(PDMA_RST_CFG, PST_DTX_IDX3);
9416 +                       break;
9417 +               default :
9418 +                       printk("tx descriptor init failed %d\n", ring_no);
9419 +                       return 0;
9420 +       };
9421 +       return 1;
9422 +}
9423 +
9424 +/*
9425 +   DSCP | AC | WMM_AC (Access Category)
9426 +   ------+----+--------
9427 +   00-07|  1 |  BE
9428 +   24-31|  1 |  BE
9429 +   08-15|  0 |  BG
9430 +   16-23|  0 |  BG
9431 +   32-39|  2 |  VI
9432 +   40-47|  2 |  VI
9433 +   48-55|  3 |  VO
9434 +   56-63|  3 |  VO
9435 +
9436 +          |    TOS    |
9437 +     DSCP |(bit5~bit7)|  WMM
9438 +   -------+-----------+-------
9439 +    0x00  |    000    |   BE
9440 +    0x18  |    011    |   BE
9441 +    0x08  |    001    |   BG
9442 +    0x10  |    010    |   BG
9443 +    0x20  |    100    |   VI
9444 +    0x28  |    101    |   VI
9445 +    0x30  |    110    |   VO
9446 +    0x38  |    111    |   VO
9447 +
9448 +    Notes: BE should be mapped to AC1, but mapped to AC0 in linux kernel.
9449 +
9450 + */
9451 +
9452 +int  pkt_classifier(struct sk_buff *skb,int gmac_no, int *ring_no, int *queue_no, int *port_no)
9453 +{
9454 +#if defined(CONFIG_RALINK_RT2880)
9455 +    /* RT2880 -- Assume using 1 Ring (Ring0), Queue 0, and Port 0 */
9456 +    *port_no   = 0;
9457 +    *ring_no   = 0;
9458 +    *queue_no  = 0;
9459 +#else
9460 +    unsigned int ac=0;
9461 +    unsigned int bridge_traffic=0, lan_traffic=0;
9462 +    struct iphdr *iph=NULL;
9463 +    struct vlan_ethhdr *veth=NULL;
9464 +    unsigned int vlan_id=0;
9465 +#if defined (CONFIG_RAETH_QOS_DSCP_BASED)
9466 +    static char DscpToAcMap[8]={1,0,0,1,2,2,3,3};
9467 +#elif defined (CONFIG_RAETH_QOS_VPRI_BASED)
9468 +    static char VlanPriToAcMap[8]={1,0,0,1,2,2,3,3};
9469 +#endif
9470 +
9471 +    /* Bridge:: {BG,BE,VI,VO} */
9472 +    /* GateWay:: WAN: {BG,BE,VI,VO}, LAN: {BG,BE,VI,VO} */
9473 +#if defined (CONFIG_RALINK_RT3883) && defined (CONFIG_RAETH_GMAC2)
9474 +    /*
9475 +     * 1) Bridge:
9476 +     *    1.1) GMAC1 ONLY:
9477 +     *                 VO/VI->Ring3, BG/BE->Ring2
9478 +     *    1.2) GMAC1+GMAC2:
9479 +     *                 GMAC1:: VO/VI->Ring3, BG/BE->Ring2
9480 +     *                 GMAC2:: VO/VI->Ring1, BG/BE->Ring0
9481 +     * 2) GateWay:
9482 +     *    2.1) GMAC1 ONLY:
9483 +     *        GMAC1:: LAN:VI/VO->Ring2, BE/BK->Ring2
9484 +     *                WAN:VI/VO->Ring3, BE/BK->Ring3
9485 +     *    2.2)GMAC1+GMAC2:
9486 +     *        GMAC1:: LAN:VI/VO/BE/BK->Ring2, WAN:VI/VO/BE/BK->Ring3
9487 +     *        GMAC2:: VI/VO->Ring1, BE/BK->Ring0
9488 +     */
9489 +    static unsigned char AcToRing_BridgeMap[4] = {2, 2, 3, 3};
9490 +    static unsigned char AcToRing_GE1Map[2][4] = {{3, 3, 3, 3},{2, 2, 2, 2}};
9491 +    static unsigned char AcToRing_GE2Map[4] = {0, 0, 1, 1};
9492 +#elif defined (CONFIG_RALINK_RT3052) || defined (CONFIG_RALINK_RT2883) || \
9493 +      defined (CONFIG_RALINK_RT3352) || defined (CONFIG_RALINK_RT5350) || \
9494 +      defined (CONFIG_RALINK_RT6855) || defined(CONFIG_RALINK_RT6855A) || \
9495 +      defined (CONFIG_RALINK_MT7620) || defined(CONFIG_RALINK_MT7621) || \
9496 +      defined (CONFIG_RALINK_MT7628) || \
9497 +     (defined (CONFIG_RALINK_RT3883) && !defined(CONFIG_RAETH_GMAC2))
9498 +    /*
9499 +     * 1) Bridge: VO->Ring3, VI->Ring2, BG->Ring1, BE->Ring0
9500 +     * 2) GateWay:
9501 +     *    2.1) GMAC1:: LAN:VI/VO->Ring1, BE/BK->Ring0
9502 +     *                WAN:VI/VO->Ring3, BE/BK->Ring2
9503 +     */
9504 +    static unsigned char AcToRing_BridgeMap[4] = {0, 1, 2, 3};
9505 +    static unsigned char AcToRing_GE1Map[2][4] = {{2, 2, 3, 3},{0, 0, 1, 1}};
9506 +#endif  // CONFIG_RALINK_RT2883
9507 +
9508 +    /*
9509 +     * Set queue no - QN field in TX Descriptor
9510 +     * always use queue 3 for the packet from CPU to GMAC
9511 +     */
9512 +    *queue_no = 3;
9513 +
9514 +    /* Get access category */
9515 +    veth = (struct vlan_ethhdr *)(skb->data);
9516 +    if(veth->h_vlan_proto == htons(ETH_P_8021Q)) { // VLAN traffic
9517 +       iph= (struct iphdr *)(skb->data + VLAN_ETH_HLEN);
9518 +
9519 +       vlan_id = ntohs(veth->h_vlan_TCI & VLAN_VID_MASK);
9520 +       if(vlan_id==1) { //LAN
9521 +           lan_traffic = 1;
9522 +       } else { //WAN
9523 +           lan_traffic = 0;
9524 +       }
9525 +
9526 +       if (veth->h_vlan_encapsulated_proto == htons(ETH_P_IP)) { //IPv4
9527 +#if defined (CONFIG_RAETH_QOS_DSCP_BASED)
9528 +           ac = DscpToAcMap[(iph->tos & 0xe0) >> 5];
9529 +#elif defined (CONFIG_RAETH_QOS_VPRI_BASED)
9530 +           ac = VlanPriToAcMap[skb->priority];
9531 +#endif
9532 +       }else { //Ipv6, ARP ...etc
9533 +           ac = 0;
9534 +       }
9535 +    }else { // non-VLAN traffic
9536 +       if (veth->h_vlan_proto == htons(ETH_P_IP)) { //IPv4
9537 +#if defined (CONFIG_RAETH_QOS_DSCP_BASED)
9538 +           iph= (struct iphdr *)(skb->data + ETH_HLEN);
9539 +           ac = DscpToAcMap[(iph->tos & 0xe0) >> 5];
9540 +#elif defined (CONFIG_RAETH_QOS_VPRI_BASED)
9541 +           ac= VlanPriToAcMap[skb->priority];
9542 +#endif
9543 +       }else { // IPv6, ARP ...etc
9544 +           ac = 0;
9545 +       }
9546 +
9547 +       bridge_traffic=1;
9548 +    }
9549 +
9550 +
9551 +    /* Set Tx Ring no */
9552 +    if(gmac_no==1) { //GMAC1
9553 +       if(bridge_traffic) { //Bridge Mode
9554 +           *ring_no = AcToRing_BridgeMap[ac];
9555 +       }else { //GateWay Mode
9556 +           *ring_no = AcToRing_GE1Map[lan_traffic][ac];
9557 +       }
9558 +    }else { //GMAC2
9559 +#if defined (CONFIG_RALINK_RT3883) && defined (CONFIG_RAETH_GMAC2)
9560 +       *ring_no = AcToRing_GE2Map[ac];
9561 +#endif
9562 +    }
9563 +
9564 +
9565 +    /* Set Port No - PN field in Tx Descriptor*/
9566 +#if defined(CONFIG_RAETH_GMAC2)
9567 +    *port_no = gmac_no;
9568 +#else
9569 +    if(bridge_traffic) {
9570 +       *port_no = 1;
9571 +    }else {
9572 +       if(lan_traffic==1) { //LAN use VP1
9573 +           *port_no = 1;
9574 +       }else { //WAN use VP2
9575 +           *port_no = 2;
9576 +       }
9577 +    }
9578 +#endif // CONFIG_RAETH_GMAC2 //
9579 +
9580 +#endif
9581 +
9582 +    return 1;
9583 +
9584 +}
9585 +
9586 +
9587 +/*
9588 + *  Routine Description :
9589 + *  Hi/Li Rings and Queues definition for QoS Purpose
9590 + *
9591 + *  Related registers: (Detail information refer to pp106 of RT3052_DS_20080226.doc)
9592 + *  Priority High/Low Definition - PDMA_FC_CFG, GDMA1_FC_CFG, GDMA2_FC_CFG
9593 + *  Bit 28 -  Allows high priority Q to share low priority Q's reserved pages
9594 + *  Bit 27:24 -  Px high priority definition bitmap
9595 + *  Weight Configuration - GDMA1_SCH_CFG, GDMA2_SCH_CFG, PDMA_SCH_CFG -> default 3210
9596 + *
9597 + * Parameter:
9598 + *     NONE
9599 + *
9600 +*/
9601 +#define PSE_P1_LQ_FULL (1<<2)
9602 +#define PSE_P1_HQ_FULL (1<<3)
9603 +#define PSE_P2_LQ_FULL (1<<4)
9604 +#define PSE_P2_HQ_FULL (1<<5)
9605 +
9606 +#define HIGH_QUEUE(queue)   (1<<(queue))
9607 +#define LOW_QUEUE(queue)    (0<<(queue))
9608 +#define PAGES_SHARING      (1<<28)
9609 +#define RSEV_PAGE_COUNT_HQ  0x10 /* Reserved page count for high priority Q */
9610 +#define RSEV_PAGE_COUNT_LQ  0x10 /* Reserved page count for low priority Q */
9611 +#define VIQ_FC_ASRT        0x10 /* Virtual input Q FC assertion threshold */
9612 +
9613 +#define QUEUE_WEIGHT_1     0
9614 +#define QUEUE_WEIGHT_2     1
9615 +#define QUEUE_WEIGHT_4     2
9616 +#define QUEUE_WEIGHT_8     3
9617 +#define QUEUE_WEIGHT_16     4
9618 +
9619 +#define WRR_SCH                    0 /*WRR */
9620 +#define STRICT_PRI_SCH     1 /* Strict Priority */
9621 +#define MIX_SCH                    2 /* Mixed : Q3>WRR(Q2,Q1,Q0) */
9622 +
9623 +/*
9624 + *           Ring3  Ring2  Ring1  Ring0
9625 + *            |  |   |  |  |  |   |  |
9626 + *            |  |   |  |  |  |   |  |
9627 + *        --------------------------------
9628 + *        |         WRR Scheduler        |
9629 + *        --------------------------------
9630 + *                       |
9631 + *    ---------------------------------------
9632 + *    |                 PDMA                |
9633 + *    ---------------------------------------
9634 + *     |Q3||Q2||Q1||Q0|    |Q3||Q2||Q1||Q0|
9635 + *     |  ||  ||  ||  |    |  ||  ||  ||  |
9636 + *    ------------------- -------------------
9637 + *    |      GDMA2      | |     GDMA1       |
9638 + *    ------------------- -------------------
9639 + *              |                      |
9640 + *      ------------------------------------
9641 + *      |              GMAC                |
9642 + *      ------------------------------------
9643 + *                       |
9644 + *
9645 + */
9646 +void set_scheduler_weight(void)
9647 +{
9648 +#if !defined (CONFIG_RALINK_RT5350) && !defined (CONFIG_RALINK_MT7628)
9649 +    /*
9650 +     * STEP1: Queue scheduling configuration
9651 +     */
9652 +    *(unsigned long *)GDMA1_SCH_CFG = (WRR_SCH << 24) |
9653 +       (QUEUE_WEIGHT_16 << 12) | /* queue 3 weight */
9654 +       (QUEUE_WEIGHT_8 << 8) |  /* queue 2 weight */
9655 +       (QUEUE_WEIGHT_4  << 4) |  /* queue 1 weight */
9656 +       (QUEUE_WEIGHT_2  << 0);   /* queue 0 weight */
9657 +
9658 +    *(unsigned long *)GDMA2_SCH_CFG = (WRR_SCH << 24) |
9659 +       (QUEUE_WEIGHT_16 << 12) | /* queue 3 weight */
9660 +       (QUEUE_WEIGHT_8 << 8) |  /* queue 2 weight */
9661 +       (QUEUE_WEIGHT_4  << 4) |  /* queue 1 weight */
9662 +       (QUEUE_WEIGHT_2  << 0);   /* queue 0 weight */
9663 +
9664 +#endif
9665 +    /*
9666 +     * STEP2: Ring scheduling configuration
9667 +     */
9668 +#if defined (CONFIG_RALINK_RT6855) || defined(CONFIG_RALINK_RT6855A) || \
9669 +    defined (CONFIG_RALINK_MT7620) || defined(CONFIG_RALINK_MT7621)
9670 +    /* MIN_RATE_RATIO0=0, MAX_RATE_ULMT0=1, Weight0=1 */
9671 +    *(unsigned long *)SCH_Q01_CFG =  (0 << 10) | (1<<14) | (0 << 12);
9672 +    /* MIN_RATE_RATIO1=0, MAX_RATE_ULMT1=1, Weight1=4 */
9673 +    *(unsigned long *)SCH_Q01_CFG |= (0 << 26) | (1<<30) | (2 << 28);
9674 +
9675 +    /* MIN_RATE_RATIO2=0, MAX_RATE_ULMT2=1, Weight0=1 */
9676 +    *(unsigned long *)SCH_Q23_CFG =  (0 << 10) | (1<<14) | (0 << 12);
9677 +    /* MIN_RATE_RATIO3=0, MAX_RATE_ULMT3=1, Weight1=4 */
9678 +    *(unsigned long *)SCH_Q23_CFG |= (0 << 26) | (1<<30) | (2 << 28);
9679 +#else
9680 +    *(unsigned long *)PDMA_SCH_CFG = (WRR_SCH << 24) |
9681 +       (QUEUE_WEIGHT_16 << 12) | /* ring 3 weight */
9682 +       (QUEUE_WEIGHT_4 << 8) |  /* ring 2 weight */
9683 +       (QUEUE_WEIGHT_16 << 4) |  /* ring 1 weight */
9684 +       (QUEUE_WEIGHT_4 << 0);   /* ring 0 weight */
9685 +#endif
9686 +}
9687 +
9688 +/*
9689 + * Routine Description :
9690 + *     Bucket size and related information from ASIC Designer,
9691 + *     please check Max Lee to update these values
9692 + *
9693 + *     Related Registers
9694 + *       FE_GLO_CFG - initialize clock rate for rate limiting
9695 + *       PDMA_FC_CFG - Pause mechanism for Rings (Ref to pp116 in datasheet)
9696 + *       :
9697 + * Parameter:
9698 + *     NONE
9699 + */
9700 +/*
9701 + *     Bit 29:24 - Q3 flow control pause condition
9702 + *     Bit 21:16 - Q2 flow control pause condition
9703 + *     Bit 13:8  - Q1 flow control pause condition
9704 + *     Bit 5:0   - Q0 flow control pause condition
9705 + *
9706 + *     detail bitmap -
9707 + *       Bit[5] - Pause Qx when PSE p2 HQ full
9708 + *       Bit[4] - Pause Qx when PSE p2 LQ full
9709 + *       Bit[3] - Pause Qx when PSE p1 HQ full
9710 + *       Bit[2] - Pause Qx when PSE p1 LQ full
9711 + *       Bit[1] - Pause Qx when PSE p0 HQ full
9712 + *       Bit[0] - Pause Qx when PSE p0 LQ full
9713 + */
9714 +void set_schedule_pause_condition(void)
9715 +{
9716 +#if defined (CONFIG_RALINK_MT7620)
9717 +
9718 +#elif defined (CONFIG_RALINK_RT5350) || defined (CONFIG_RALINK_MT7628)
9719 +    *(unsigned long *)SDM_TRING = (0xC << 28) | (0x3 << 24) | (0xC << 4) | 0x3;
9720 +#else
9721 +    /*
9722 +     * STEP1: Set queue priority is high or low
9723 +     *
9724 +     * Set queue 3 as high queue in GMAC1/GMAC2
9725 +     */
9726 +    *(unsigned long *)GDMA1_FC_CFG = ((HIGH_QUEUE(3)|LOW_QUEUE(2) |
9727 +                                     LOW_QUEUE(1)|LOW_QUEUE(0))<<24) |
9728 +                                     (RSEV_PAGE_COUNT_HQ << 16) |
9729 +                                     (RSEV_PAGE_COUNT_LQ <<8) |
9730 +                                     VIQ_FC_ASRT | PAGES_SHARING;
9731 +
9732 +    *(unsigned long *)GDMA2_FC_CFG = ((HIGH_QUEUE(3)|LOW_QUEUE(2) |
9733 +                                     LOW_QUEUE(1)|LOW_QUEUE(0))<<24) |
9734 +                                     (RSEV_PAGE_COUNT_HQ << 16) |
9735 +                                     (RSEV_PAGE_COUNT_LQ <<8) |
9736 +                                     VIQ_FC_ASRT | PAGES_SHARING;
9737 +
9738 +    /*
9739 +     * STEP2: Set flow control pause condition
9740 +     *
9741 +     * CPU always use queue 3, and queue3 is high queue.
9742 +     * If P2(GMAC2) high queue is full, pause ring3/ring2
9743 +     * If P1(GMAC1) high queue is full, pause ring1/ring0
9744 +     */
9745 +    *(unsigned long *)PDMA_FC_CFG =  ( PSE_P2_HQ_FULL << 24 ) | /* queue 3 */
9746 +       ( PSE_P2_HQ_FULL << 16 ) | /* queue 2 */
9747 +       ( PSE_P1_HQ_FULL << 8 ) |  /* queue 1 */
9748 +       ( PSE_P1_HQ_FULL << 0 );  /* queue 0 */
9749 +#endif
9750 +
9751 +}
9752 +
9753 +
9754 +void set_output_shaper(void)
9755 +{
9756 +#define GDMA1_TOKEN_RATE       16  /* unit=64bits/ms */
9757 +#define GDMA2_TOKEN_RATE       16  /* unit=64bits/ms */
9758 +
9759 +#if 0
9760 +    *(unsigned long *)GDMA1_SHPR_CFG =  (1 << 24) | /* output shaper enable */
9761 +                                       (128 << 16) | /* bucket size (unit=1KB) */
9762 +                                       (GDMA1_TOKEN_RATE << 0); /* token rate (unit=8B/ms) */
9763 +#endif
9764 +
9765 +#if 0
9766 +    *(unsigned long *)GDMA2_SHPR_CFG =  (1 << 24) | /* output shaper enable */
9767 +                                       (128 << 16) | /* bucket size (unit=1KB) */
9768 +                                       (GDMA2_TOKEN_RATE << 0); /* token rate (unit=8B/ms) */
9769 +#endif
9770 +}
9771 diff --git a/drivers/net/ethernet/raeth/ra_qos.h b/drivers/net/ethernet/raeth/ra_qos.h
9772 new file mode 100644
9773 index 0000000..7f2a8a1
9774 --- /dev/null
9775 +++ b/drivers/net/ethernet/raeth/ra_qos.h
9776 @@ -0,0 +1,18 @@
9777 +#ifndef RA_QOS_H
9778 +#define        RA_QOS_H
9779 +
9780 +#include "ra2882ethreg.h"
9781 +#define RING0  0
9782 +#define RING1  1
9783 +#define RING2  2
9784 +#define RING3  3
9785 +void get_tx_desc_and_dtx_idx(END_DEVICE* ei_local, int ring_no, unsigned long *tx_dtx_idx, struct PDMA_txdesc **tx_desc);
9786 +int get_tx_ctx_idx(unsigned int ring_no, unsigned long *idx);
9787 +int fe_tx_desc_init(struct net_device *dev, unsigned int ring_no, unsigned int qn, unsigned int pn);
9788 +int fe_qos_packet_send(struct net_device *dev, struct sk_buff* skb, unsigned int ring_no, unsigned int qn, unsigned int pn);
9789 +
9790 +int  pkt_classifier(struct sk_buff *skb,int gmac_no, int *ring_no, int *queue_no, int *port_no);
9791 +void set_schedule_pause_condition(void);
9792 +void set_scheduler_weight(void);
9793 +void set_output_shaper(void);
9794 +#endif
9795 diff --git a/drivers/net/ethernet/raeth/ra_rfrw.c b/drivers/net/ethernet/raeth/ra_rfrw.c
9796 new file mode 100644
9797 index 0000000..d73db01
9798 --- /dev/null
9799 +++ b/drivers/net/ethernet/raeth/ra_rfrw.c
9800 @@ -0,0 +1,66 @@
9801 +#include <linux/module.h>
9802 +#include <linux/version.h>
9803 +#include <linux/kernel.h>
9804 +#include <linux/sched.h>
9805 +#include <linux/types.h>
9806 +#include <linux/fcntl.h>
9807 +#include <linux/interrupt.h>
9808 +#include <linux/ptrace.h>
9809 +#include <linux/ioport.h>
9810 +#include <linux/in.h>
9811 +#include <linux/slab.h>
9812 +#include <linux/string.h>
9813 +#include <linux/signal.h>
9814 +#include <linux/irq.h>
9815 +#include <linux/netdevice.h>
9816 +#include <linux/etherdevice.h>
9817 +#include <linux/skbuff.h>
9818 +
9819 +#include "ra2882ethreg.h"
9820 +#include "raether.h"
9821 +#include "ra_mac.h"
9822 +
9823 +#define RF_CSR_CFG      0xb0180500
9824 +#define RF_CSR_KICK     (1<<17)
9825 +int rw_rf_reg(int write, int reg, int *data)
9826 +{
9827 +        unsigned long    rfcsr, i = 0;
9828 +
9829 +        while (1) {
9830 +                rfcsr =  sysRegRead(RF_CSR_CFG);
9831 +                if (! (rfcsr & (u32)RF_CSR_KICK) )
9832 +                        break;
9833 +                if (++i > 10000) {
9834 +                        printk("Warning: Abort rw rf register: too busy\n");
9835 +                        return -1;
9836 +                }
9837 +        }
9838 +
9839 +        rfcsr = (u32)(RF_CSR_KICK | ((reg&0x3f) << 8) | (*data & 0xff));
9840 +        if (write)
9841 +                rfcsr |= 0x10000;
9842 +
9843 +         sysRegRead(RF_CSR_CFG) = cpu_to_le32(rfcsr);
9844 +
9845 +        i = 0;
9846 +        while (1) {
9847 +                rfcsr =  sysRegRead(RF_CSR_CFG);
9848 +                if (! (rfcsr & (u32)RF_CSR_KICK) )
9849 +                        break;
9850 +                if (++i > 10000) {
9851 +                        printk("Warning: still busy\n");
9852 +                        return -1;
9853 +                }
9854 +        }
9855 +
9856 +        rfcsr =  sysRegRead(RF_CSR_CFG);
9857 +
9858 +        if (((rfcsr&0x1f00) >> 8) != (reg & 0x1f)) {
9859 +                printk("Error: rw register failed\n");
9860 +                return -1;
9861 +        }
9862 +        *data = (int)(rfcsr & 0xff);
9863 +
9864 +        return 0;
9865 +}
9866 +
9867 diff --git a/drivers/net/ethernet/raeth/ra_rfrw.h b/drivers/net/ethernet/raeth/ra_rfrw.h
9868 new file mode 100644
9869 index 0000000..da5a371
9870 --- /dev/null
9871 +++ b/drivers/net/ethernet/raeth/ra_rfrw.h
9872 @@ -0,0 +1,6 @@
9873 +#ifndef RA_RFRW_H
9874 +#define RA_RFRW_H
9875 +
9876 +int rw_rf_reg(int write, int reg, int *data);
9877 +
9878 +#endif
9879 diff --git a/drivers/net/ethernet/raeth/raether.c b/drivers/net/ethernet/raeth/raether.c
9880 new file mode 100644
9881 index 0000000..328285a
9882 --- /dev/null
9883 +++ b/drivers/net/ethernet/raeth/raether.c
9884 @@ -0,0 +1,6401 @@
9885 +#include <linux/module.h>
9886 +#include <linux/version.h>
9887 +#include <linux/kernel.h>
9888 +#include <linux/types.h>
9889 +#include <linux/pci.h>
9890 +#include <linux/init.h>
9891 +#include <linux/skbuff.h>
9892 +#include <linux/if_vlan.h>
9893 +#include <linux/if_ether.h>
9894 +#include <linux/fs.h>
9895 +#include <asm/uaccess.h>
9896 +#include <asm/rt2880/surfboardint.h>
9897 +#include <linux/platform_device.h>
9898 +#if defined (CONFIG_RAETH_TSO)
9899 +#include <linux/tcp.h>
9900 +#include <net/ipv6.h>
9901 +#include <linux/ip.h>
9902 +#include <net/ip.h>
9903 +#include <net/tcp.h>
9904 +#include <linux/in.h>
9905 +#include <linux/ppp_defs.h>
9906 +#include <linux/if_pppox.h>
9907 +#endif
9908 +#if defined (CONFIG_RAETH_LRO)
9909 +#include <linux/inet_lro.h>
9910 +#endif
9911 +#include <linux/delay.h>
9912 +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,35)
9913 +#include <linux/sched.h>
9914 +#endif
9915 +
9916 +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,0)
9917 +#include <asm/rt2880/rt_mmap.h>
9918 +#else
9919 +#include <linux/libata-compat.h>
9920 +#endif
9921 +
9922 +#include "ra2882ethreg.h"
9923 +#include "raether.h"
9924 +#include "ra_mac.h"
9925 +#include "ra_ioctl.h"
9926 +#include "ra_rfrw.h"
9927 +#ifdef CONFIG_RAETH_NETLINK
9928 +#include "ra_netlink.h"
9929 +#endif
9930 +#if defined (CONFIG_RAETH_QOS)
9931 +#include "ra_qos.h"
9932 +#endif
9933 +
9934 +#if defined (CONFIG_RA_HW_NAT) || defined (CONFIG_RA_HW_NAT_MODULE)
9935 +#include "../../../net/nat/hw_nat/ra_nat.h"
9936 +#endif
9937 +#if defined(CONFIG_RAETH_PDMA_DVT)
9938 +#include "dvt/raether_pdma_dvt.h"
9939 +#endif  /* CONFIG_RAETH_PDMA_DVT */
9940 +
9941 +static int fe_irq = 0;
9942 +
9943 +#if defined (TASKLET_WORKQUEUE_SW)
9944 +int init_schedule;
9945 +int working_schedule;
9946 +#endif
9947 +
9948 +#ifdef CONFIG_RAETH_NAPI
9949 +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,35)
9950 +static int raeth_clean(struct napi_struct *napi, int budget);
9951 +#else
9952 +static int raeth_clean(struct net_device *dev, int *budget);
9953 +#endif
9954 +
9955 +static int rt2880_eth_recv(struct net_device* dev, int *work_done, int work_to_do);
9956 +#else
9957 +static int rt2880_eth_recv(struct net_device* dev);
9958 +#endif
9959 +
9960 +#if !defined(CONFIG_RA_NAT_NONE)
9961 +/* bruce+
9962 + */
9963 +extern int (*ra_sw_nat_hook_rx)(struct sk_buff *skb);
9964 +extern int (*ra_sw_nat_hook_tx)(struct sk_buff *skb, int gmac_no);
9965 +#endif
9966 +
9967 +#if defined(CONFIG_RA_CLASSIFIER)||defined(CONFIG_RA_CLASSIFIER_MODULE)
9968 +/* Qwert+
9969 + */
9970 +#include <asm/mipsregs.h>
9971 +extern int (*ra_classifier_hook_tx)(struct sk_buff *skb, unsigned long cur_cycle);
9972 +extern int (*ra_classifier_hook_rx)(struct sk_buff *skb, unsigned long cur_cycle);
9973 +#endif /* CONFIG_RA_CLASSIFIER */
9974 +
9975 +#if defined (CONFIG_RALINK_RT3052_MP2)
9976 +int32_t mcast_rx(struct sk_buff * skb);
9977 +int32_t mcast_tx(struct sk_buff * skb);
9978 +#endif
9979 +
9980 +int ra_mtd_read_nm(char *name, loff_t from, size_t len, u_char *buf)
9981 +{
9982 +       /* TODO */
9983 +       return 0;
9984 +}
9985 +
9986 +#if defined (CONFIG_RALINK_MT7621) || defined (CONFIG_P5_RGMII_TO_MT7530_MODE) || defined (CONFIG_ARCH_MT7623)
9987 +void setup_internal_gsw(void);
9988 +#if defined (CONFIG_GE1_TRGMII_FORCE_1200)
9989 +void apll_xtal_enable(void);
9990 +#define REGBIT(x, n)              (x << n)
9991 +#endif
9992 +#endif
9993 +
9994 +#if defined (CONFIG_MT7623_FPGA)
9995 +void setup_fpga_gsw(void);
9996 +#endif
9997 +
9998 +/* gmac driver feature set config */
9999 +#if defined (CONFIG_RAETH_NAPI) || defined (CONFIG_RAETH_QOS)
10000 +#undef DELAY_INT
10001 +#else
10002 +#if defined     (CONFIG_ARCH_MT7623)
10003 +#undef DELAY_INT
10004 +#else
10005 +#define DELAY_INT       1
10006 +#endif
10007 +#endif
10008 +
10009 +//#define CONFIG_UNH_TEST
10010 +/* end of config */
10011 +
10012 +#if defined (CONFIG_RAETH_JUMBOFRAME)
10013 +#define        MAX_RX_LENGTH   4096
10014 +#else
10015 +#define        MAX_RX_LENGTH   1536
10016 +#endif
10017 +
10018 +struct net_device              *dev_raether;
10019 +
10020 +static int rx_dma_owner_idx;
10021 +static int rx_dma_owner_idx0;
10022 +#if defined (CONFIG_RAETH_HW_LRO)
10023 +static int rx_dma_owner_lro1;
10024 +static int rx_dma_owner_lro2;
10025 +static int rx_dma_owner_lro3;
10026 +#elif defined (CONFIG_RAETH_MULTIPLE_RX_RING)
10027 +static int rx_dma_owner_idx1;
10028 +#if defined(CONFIG_ARCH_MT7623)
10029 +static int rx_dma_owner_idx2;
10030 +static int rx_dma_owner_idx3;
10031 +#endif  /* CONFIG_ARCH_MT7623 */
10032 +#ifdef CONFIG_RAETH_RW_PDMAPTR_FROM_VAR
10033 +int rx_calc_idx1;
10034 +#endif
10035 +#endif
10036 +#ifdef CONFIG_RAETH_RW_PDMAPTR_FROM_VAR
10037 +int rx_calc_idx0;
10038 +#endif
10039 +static int pending_recv;
10040 +static struct PDMA_rxdesc      *rx_ring;
10041 +unsigned long tx_ring_full=0;
10042 +
10043 +#if defined(CONFIG_RALINK_RT6855) || defined(CONFIG_RALINK_RT6855A) || \
10044 +    defined(CONFIG_RALINK_MT7620)
10045 +unsigned short p0_rx_good_cnt = 0;
10046 +unsigned short p1_rx_good_cnt = 0;
10047 +unsigned short p2_rx_good_cnt = 0;
10048 +unsigned short p3_rx_good_cnt = 0;
10049 +unsigned short p4_rx_good_cnt = 0;
10050 +unsigned short p5_rx_good_cnt = 0;
10051 +unsigned short p6_rx_good_cnt = 0;
10052 +unsigned short p0_tx_good_cnt = 0;
10053 +unsigned short p1_tx_good_cnt = 0;
10054 +unsigned short p2_tx_good_cnt = 0;
10055 +unsigned short p3_tx_good_cnt = 0;
10056 +unsigned short p4_tx_good_cnt = 0;
10057 +unsigned short p5_tx_good_cnt = 0;
10058 +unsigned short p6_tx_good_cnt = 0;
10059 +
10060 +unsigned short p0_rx_byte_cnt = 0;
10061 +unsigned short p1_rx_byte_cnt = 0;
10062 +unsigned short p2_rx_byte_cnt = 0;
10063 +unsigned short p3_rx_byte_cnt = 0;
10064 +unsigned short p4_rx_byte_cnt = 0;
10065 +unsigned short p5_rx_byte_cnt = 0;
10066 +unsigned short p6_rx_byte_cnt = 0;
10067 +unsigned short p0_tx_byte_cnt = 0;
10068 +unsigned short p1_tx_byte_cnt = 0;
10069 +unsigned short p2_tx_byte_cnt = 0;
10070 +unsigned short p3_tx_byte_cnt = 0;
10071 +unsigned short p4_tx_byte_cnt = 0;
10072 +unsigned short p5_tx_byte_cnt = 0;
10073 +unsigned short p6_tx_byte_cnt = 0;
10074 +
10075 +#if defined(CONFIG_RALINK_MT7620)
10076 +unsigned short p7_rx_good_cnt = 0;
10077 +unsigned short p7_tx_good_cnt = 0;
10078 +
10079 +unsigned short p7_rx_byte_cnt = 0;
10080 +unsigned short p7_tx_byte_cnt = 0;
10081 +#endif
10082 +#endif
10083 +
10084 +
10085 +
10086 +
10087 +#if defined (CONFIG_ETHTOOL) /*&& defined (CONFIG_RAETH_ROUTER)*/
10088 +#include "ra_ethtool.h"
10089 +extern struct ethtool_ops      ra_ethtool_ops;
10090 +#ifdef CONFIG_PSEUDO_SUPPORT
10091 +extern struct ethtool_ops      ra_virt_ethtool_ops;
10092 +#endif // CONFIG_PSEUDO_SUPPORT //
10093 +#endif // (CONFIG_ETHTOOL //
10094 +
10095 +#ifdef CONFIG_RALINK_VISTA_BASIC
10096 +int is_switch_175c = 1;
10097 +#endif
10098 +
10099 +unsigned int M2Q_table[64] = {0};
10100 +unsigned int lan_wan_separate = 0;
10101 +
10102 +#if defined(CONFIG_HW_SFQ)
10103 +unsigned int web_sfq_enable = 0;
10104 +EXPORT_SYMBOL(web_sfq_enable);
10105 +#endif
10106 +
10107 +EXPORT_SYMBOL(M2Q_table);
10108 +EXPORT_SYMBOL(lan_wan_separate);
10109 +#if defined (CONFIG_RAETH_LRO)
10110 +unsigned int lan_ip;
10111 +struct lro_para_struct lro_para;
10112 +int lro_flush_needed;
10113 +extern char const *nvram_get(int index, char *name);
10114 +#endif
10115 +
10116 +#define KSEG1                   0xa0000000
10117 +#if defined (CONFIG_MIPS)
10118 +#define PHYS_TO_VIRT(x)         ((void *)((x) | KSEG1))
10119 +#define VIRT_TO_PHYS(x)         ((unsigned long)(x) & ~KSEG1)
10120 +#else
10121 +#define PHYS_TO_VIRT(x)         phys_to_virt(x)
10122 +#define VIRT_TO_PHYS(x)         virt_to_phys(x)
10123 +#endif
10124 +
10125 +extern int fe_dma_init(struct net_device *dev);
10126 +extern int ei_start_xmit(struct sk_buff* skb, struct net_device *dev, int gmac_no);
10127 +extern void ei_xmit_housekeeping(unsigned long unused);
10128 +extern inline int rt2880_eth_send(struct net_device* dev, struct sk_buff *skb, int gmac_no);
10129 +#if defined (CONFIG_RAETH_HW_LRO)
10130 +extern int fe_hw_lro_init(struct net_device *dev);
10131 +#endif  /* CONFIG_RAETH_HW_LRO */
10132 +
10133 +#if 0
10134 +void skb_dump(struct sk_buff* sk) {
10135 +        unsigned int i;
10136 +
10137 +        printk("skb_dump: from %s with len %d (%d) headroom=%d tailroom=%d\n",
10138 +                sk->dev?sk->dev->name:"ip stack",sk->len,sk->truesize,
10139 +                skb_headroom(sk),skb_tailroom(sk));
10140 +
10141 +        //for(i=(unsigned int)sk->head;i<=(unsigned int)sk->tail;i++) {
10142 +        for(i=(unsigned int)sk->head;i<=(unsigned int)sk->data+20;i++) {
10143 +                if((i % 20) == 0)
10144 +                        printk("\n");
10145 +                if(i==(unsigned int)sk->data) printk("{");
10146 +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,21)
10147 +                if(i==(unsigned int)sk->transport_header) printk("#");
10148 +                if(i==(unsigned int)sk->network_header) printk("|");
10149 +                if(i==(unsigned int)sk->mac_header) printk("*");
10150 +#else
10151 +                if(i==(unsigned int)sk->h.raw) printk("#");
10152 +                if(i==(unsigned int)sk->nh.raw) printk("|");
10153 +                if(i==(unsigned int)sk->mac.raw) printk("*");
10154 +#endif
10155 +                printk("%02X-",*((unsigned char*)i));
10156 +                if(i==(unsigned int)sk->tail) printk("}");
10157 +        }
10158 +        printk("\n");
10159 +}
10160 +#endif
10161 +
10162 +
10163 +
10164 +#if defined (CONFIG_GIGAPHY) || defined (CONFIG_P5_MAC_TO_PHY_MODE)
10165 +int isICPlusGigaPHY(int ge)
10166 +{
10167 +       u32 phy_id0 = 0, phy_id1 = 0;
10168 +
10169 +#ifdef CONFIG_GE2_RGMII_AN
10170 +       if (ge == 2) {
10171 +               if (!mii_mgr_read(CONFIG_MAC_TO_GIGAPHY_MODE_ADDR2, 2, &phy_id0)) {
10172 +                       printk("\n Read PhyID 1 is Fail!!\n");
10173 +                       phy_id0 =0;
10174 +               }
10175 +               if (!mii_mgr_read(CONFIG_MAC_TO_GIGAPHY_MODE_ADDR2, 3, &phy_id1)) {
10176 +                       printk("\n Read PhyID 1 is Fail!!\n");
10177 +                       phy_id1 = 0;
10178 +               }
10179 +       }
10180 +       else
10181 +#endif
10182 +#if defined (CONFIG_GE1_RGMII_AN) || defined (CONFIG_P5_MAC_TO_PHY_MODE)
10183 +       {
10184 +               if (!mii_mgr_read(CONFIG_MAC_TO_GIGAPHY_MODE_ADDR, 2, &phy_id0)) {
10185 +                       printk("\n Read PhyID 0 is Fail!!\n");
10186 +                       phy_id0 =0;
10187 +               }
10188 +               if (!mii_mgr_read(CONFIG_MAC_TO_GIGAPHY_MODE_ADDR, 3, &phy_id1)) {
10189 +                       printk("\n Read PhyID 0 is Fail!!\n");
10190 +                       phy_id1 = 0;
10191 +               }
10192 +       }
10193 +#endif
10194 +
10195 +       if ((phy_id0 == EV_ICPLUS_PHY_ID0) && ((phy_id1 & 0xfff0) == EV_ICPLUS_PHY_ID1))
10196 +               return 1;
10197 +       return 0;
10198 +}
10199 +
10200 +
10201 +int isMarvellGigaPHY(int ge)
10202 +{
10203 +       u32 phy_id0 = 0, phy_id1 = 0;
10204 +
10205 +#if defined (CONFIG_GE2_RGMII_AN) || defined (CONFIG_P4_MAC_TO_PHY_MODE)
10206 +       if (ge == 2) {
10207 +               if (!mii_mgr_read(CONFIG_MAC_TO_GIGAPHY_MODE_ADDR2, 2, &phy_id0)) {
10208 +                       printk("\n Read PhyID 1 is Fail!!\n");
10209 +                       phy_id0 =0;
10210 +               }
10211 +               if (!mii_mgr_read(CONFIG_MAC_TO_GIGAPHY_MODE_ADDR2, 3, &phy_id1)) {
10212 +                       printk("\n Read PhyID 1 is Fail!!\n");
10213 +                       phy_id1 = 0;
10214 +               }
10215 +       }
10216 +       else
10217 +#endif
10218 +#if defined (CONFIG_GE1_RGMII_AN) || defined (CONFIG_P5_MAC_TO_PHY_MODE)
10219 +       {
10220 +               if (!mii_mgr_read(CONFIG_MAC_TO_GIGAPHY_MODE_ADDR, 2, &phy_id0)) {
10221 +                       printk("\n Read PhyID 0 is Fail!!\n");
10222 +                       phy_id0 =0;
10223 +               }
10224 +               if (!mii_mgr_read(CONFIG_MAC_TO_GIGAPHY_MODE_ADDR, 3, &phy_id1)) {
10225 +                       printk("\n Read PhyID 0 is Fail!!\n");
10226 +                       phy_id1 = 0;
10227 +               }
10228 +       }
10229 +#endif
10230 +               ;
10231 +       if ((phy_id0 == EV_MARVELL_PHY_ID0) && (phy_id1 == EV_MARVELL_PHY_ID1))
10232 +               return 1;
10233 +       return 0;
10234 +}
10235 +
10236 +int isVtssGigaPHY(int ge)
10237 +{
10238 +       u32 phy_id0 = 0, phy_id1 = 0;
10239 +
10240 +#if defined (CONFIG_GE2_RGMII_AN) || defined (CONFIG_P4_MAC_TO_PHY_MODE)
10241 +       if (ge == 2) {
10242 +               if (!mii_mgr_read(CONFIG_MAC_TO_GIGAPHY_MODE_ADDR2, 2, &phy_id0)) {
10243 +                       printk("\n Read PhyID 1 is Fail!!\n");
10244 +                       phy_id0 =0;
10245 +               }
10246 +               if (!mii_mgr_read(CONFIG_MAC_TO_GIGAPHY_MODE_ADDR2, 3, &phy_id1)) {
10247 +                       printk("\n Read PhyID 1 is Fail!!\n");
10248 +                       phy_id1 = 0;
10249 +               }
10250 +       }
10251 +       else
10252 +#endif
10253 +#if defined (CONFIG_GE1_RGMII_AN) || defined (CONFIG_P5_MAC_TO_PHY_MODE)
10254 +       {
10255 +               if (!mii_mgr_read(CONFIG_MAC_TO_GIGAPHY_MODE_ADDR, 2, &phy_id0)) {
10256 +                       printk("\n Read PhyID 0 is Fail!!\n");
10257 +                       phy_id0 =0;
10258 +               }
10259 +               if (!mii_mgr_read(CONFIG_MAC_TO_GIGAPHY_MODE_ADDR, 3, &phy_id1)) {
10260 +                       printk("\n Read PhyID 0 is Fail!!\n");
10261 +                       phy_id1 = 0;
10262 +               }
10263 +       }
10264 +#endif
10265 +               ;
10266 +       if ((phy_id0 == EV_VTSS_PHY_ID0) && (phy_id1 == EV_VTSS_PHY_ID1))
10267 +               return 1;
10268 +       return 0;
10269 +}
10270 +#endif
10271 +
10272 +/*
10273 + * Set the hardware MAC address.
10274 + */
10275 +static int ei_set_mac_addr(struct net_device *dev, void *p)
10276 +{
10277 +       struct sockaddr *addr = p;
10278 +
10279 +       memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
10280 +
10281 +       if(netif_running(dev))
10282 +               return -EBUSY;
10283 +
10284 +        ra2880MacAddressSet(addr->sa_data);
10285 +       return 0;
10286 +}
10287 +
10288 +#ifdef CONFIG_PSEUDO_SUPPORT
10289 +static int ei_set_mac2_addr(struct net_device *dev, void *p)
10290 +{
10291 +       struct sockaddr *addr = p;
10292 +
10293 +       memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
10294 +
10295 +       if(netif_running(dev))
10296 +               return -EBUSY;
10297 +
10298 +        ra2880Mac2AddressSet(addr->sa_data);
10299 +       return 0;
10300 +}
10301 +#endif
10302 +
10303 +void set_fe_dma_glo_cfg(void)
10304 +{
10305 +        int dma_glo_cfg=0;
10306 +#if defined (CONFIG_RALINK_RT2880) || defined(CONFIG_RALINK_RT2883) || \
10307 +    defined (CONFIG_RALINK_RT3052) || defined (CONFIG_RALINK_RT3883)
10308 +        int fe_glo_cfg=0;
10309 +#endif
10310 +
10311 +#if defined (CONFIG_RALINK_RT6855) || defined(CONFIG_RALINK_RT6855A)
10312 +       dma_glo_cfg = (TX_WB_DDONE | RX_DMA_EN | TX_DMA_EN | PDMA_BT_SIZE_32DWORDS);
10313 +#elif defined (CONFIG_RALINK_MT7620) || defined (CONFIG_RALINK_MT7621)
10314 +       dma_glo_cfg = (TX_WB_DDONE | RX_DMA_EN | TX_DMA_EN | PDMA_BT_SIZE_16DWORDS);
10315 +#elif defined (CONFIG_ARCH_MT7623)
10316 +       dma_glo_cfg = (TX_WB_DDONE | RX_DMA_EN | TX_DMA_EN | PDMA_BT_SIZE_16DWORDS | ADMA_RX_BT_SIZE_32DWORDS);
10317 +#else
10318 +       dma_glo_cfg = (TX_WB_DDONE | RX_DMA_EN | TX_DMA_EN | PDMA_BT_SIZE_4DWORDS);
10319 +#endif
10320 +
10321 +#if defined (CONFIG_RAETH_SCATTER_GATHER_RX_DMA)
10322 +       dma_glo_cfg |= (RX_2B_OFFSET);
10323 +#endif
10324 +
10325 +#if defined (CONFIG_32B_DESC)
10326 +       dma_glo_cfg |= (DESC_32B_EN);
10327 +#endif
10328 +       sysRegWrite(DMA_GLO_CFG, dma_glo_cfg);
10329 +#ifdef CONFIG_RAETH_QDMA
10330 +       sysRegWrite(QDMA_GLO_CFG, dma_glo_cfg);
10331 +#endif
10332 +
10333 +       /* only the following chipset need to set it */
10334 +#if defined (CONFIG_RALINK_RT2880) || defined(CONFIG_RALINK_RT2883) || \
10335 +    defined (CONFIG_RALINK_RT3052) || defined (CONFIG_RALINK_RT3883)
10336 +       //set 1us timer count in unit of clock cycle
10337 +       fe_glo_cfg = sysRegRead(FE_GLO_CFG);
10338 +       fe_glo_cfg &= ~(0xff << 8); //clear bit8-bit15
10339 +       fe_glo_cfg |= (((get_surfboard_sysclk()/1000000)) << 8);
10340 +       sysRegWrite(FE_GLO_CFG, fe_glo_cfg);
10341 +#endif
10342 +}
10343 +
10344 +int forward_config(struct net_device *dev)
10345 +{
10346 +
10347 +#if defined (CONFIG_RALINK_RT5350) || defined (CONFIG_RALINK_MT7628)
10348 +
10349 +       /* RT5350: No GDMA, PSE, CDMA, PPE */
10350 +       unsigned int sdmVal;
10351 +       sdmVal = sysRegRead(SDM_CON);
10352 +
10353 +#ifdef CONFIG_RAETH_CHECKSUM_OFFLOAD
10354 +       sdmVal |= 0x7<<16; // UDPCS, TCPCS, IPCS=1
10355 +#endif // CONFIG_RAETH_CHECKSUM_OFFLOAD //
10356 +
10357 +#if defined (CONFIG_RAETH_SPECIAL_TAG)
10358 +       sdmVal |= 0x1<<20; // TCI_81XX
10359 +#endif // CONFIG_RAETH_SPECIAL_TAG //
10360 +
10361 +       sysRegWrite(SDM_CON, sdmVal);
10362 +
10363 +#else //Non RT5350 chipset
10364 +
10365 +       unsigned int    regVal, regCsg;
10366 +
10367 +#ifdef CONFIG_PSEUDO_SUPPORT
10368 +       unsigned int    regVal2;
10369 +#endif
10370 +
10371 +#ifdef CONFIG_RAETH_HW_VLAN_TX
10372 +#if defined(CONFIG_RALINK_MT7620)
10373 +       /* frame engine will push VLAN tag regarding to VIDX feild in Tx desc. */
10374 +       *(unsigned long *)(RALINK_FRAME_ENGINE_BASE + 0x430) = 0x00010000;
10375 +       *(unsigned long *)(RALINK_FRAME_ENGINE_BASE + 0x434) = 0x00030002;
10376 +       *(unsigned long *)(RALINK_FRAME_ENGINE_BASE + 0x438) = 0x00050004;
10377 +       *(unsigned long *)(RALINK_FRAME_ENGINE_BASE + 0x43C) = 0x00070006;
10378 +       *(unsigned long *)(RALINK_FRAME_ENGINE_BASE + 0x440) = 0x00090008;
10379 +       *(unsigned long *)(RALINK_FRAME_ENGINE_BASE + 0x444) = 0x000b000a;
10380 +       *(unsigned long *)(RALINK_FRAME_ENGINE_BASE + 0x448) = 0x000d000c;
10381 +       *(unsigned long *)(RALINK_FRAME_ENGINE_BASE + 0x44C) = 0x000f000e;
10382 +#else
10383 +       /*
10384 +        * VLAN_IDX 0 = VLAN_ID 0
10385 +        * .........
10386 +        * VLAN_IDX 15 = VLAN ID 15
10387 +        *
10388 +        */
10389 +       /* frame engine will push VLAN tag regarding to VIDX feild in Tx desc. */
10390 +       *(unsigned long *)(RALINK_FRAME_ENGINE_BASE + 0xa8) = 0x00010000;
10391 +       *(unsigned long *)(RALINK_FRAME_ENGINE_BASE + 0xac) = 0x00030002;
10392 +       *(unsigned long *)(RALINK_FRAME_ENGINE_BASE + 0xb0) = 0x00050004;
10393 +       *(unsigned long *)(RALINK_FRAME_ENGINE_BASE + 0xb4) = 0x00070006;
10394 +       *(unsigned long *)(RALINK_FRAME_ENGINE_BASE + 0xb8) = 0x00090008;
10395 +       *(unsigned long *)(RALINK_FRAME_ENGINE_BASE + 0xbc) = 0x000b000a;
10396 +       *(unsigned long *)(RALINK_FRAME_ENGINE_BASE + 0xc0) = 0x000d000c;
10397 +       *(unsigned long *)(RALINK_FRAME_ENGINE_BASE + 0xc4) = 0x000f000e;
10398 +#endif
10399 +#endif
10400 +
10401 +       regVal = sysRegRead(GDMA1_FWD_CFG);
10402 +       regCsg = sysRegRead(CDMA_CSG_CFG);
10403 +
10404 +#ifdef CONFIG_PSEUDO_SUPPORT
10405 +       regVal2 = sysRegRead(GDMA2_FWD_CFG);
10406 +#endif
10407 +
10408 +       //set unicast/multicast/broadcast frame to cpu
10409 +#if defined (CONFIG_RALINK_MT7620)
10410 +       /* GDMA1 frames destination port is port0 CPU*/
10411 +       regVal &= ~0x7;
10412 +#else
10413 +       regVal &= ~0xFFFF;
10414 +       regVal |= GDMA1_FWD_PORT;
10415 +#endif
10416 +       regCsg &= ~0x7;
10417 +
10418 +#if defined (CONFIG_RAETH_SPECIAL_TAG)
10419 +       regVal |= (1 << 24); //GDM1_TCI_81xx
10420 +#endif
10421 +
10422 +
10423 +#ifdef CONFIG_RAETH_HW_VLAN_TX
10424 +#if LINUX_VERSION_CODE < KERNEL_VERSION(3,10,0)
10425 +       dev->features |= NETIF_F_HW_VLAN_TX;
10426 +#else
10427 +       dev->features |= NETIF_F_HW_VLAN_CTAG_TX;
10428 +#endif
10429 +#endif
10430 +#ifdef CONFIG_RAETH_HW_VLAN_RX
10431 +#if LINUX_VERSION_CODE < KERNEL_VERSION(3,10,0)
10432 +       dev->features |= NETIF_F_HW_VLAN_RX;
10433 +#else
10434 +       dev->features |= NETIF_F_HW_VLAN_CTAG_RX;
10435 +#endif
10436 +#endif
10437 +
10438 +#ifdef CONFIG_RAETH_CHECKSUM_OFFLOAD
10439 +       //enable ipv4 header checksum check
10440 +       regVal |= GDM1_ICS_EN;
10441 +       regCsg |= ICS_GEN_EN;
10442 +
10443 +       //enable tcp checksum check
10444 +       regVal |= GDM1_TCS_EN;
10445 +       regCsg |= TCS_GEN_EN;
10446 +
10447 +       //enable udp checksum check
10448 +       regVal |= GDM1_UCS_EN;
10449 +       regCsg |= UCS_GEN_EN;
10450 +
10451 +#ifdef CONFIG_PSEUDO_SUPPORT
10452 +       regVal2 &= ~0xFFFF;
10453 +       regVal2 |= GDMA2_FWD_PORT;
10454 +
10455 +       regVal2 |= GDM1_ICS_EN;
10456 +       regVal2 |= GDM1_TCS_EN;
10457 +       regVal2 |= GDM1_UCS_EN;
10458 +#endif
10459 +
10460 +#if defined (CONFIG_RAETH_HW_LRO)
10461 +    dev->features |= NETIF_F_HW_CSUM;
10462 +#else
10463 +       dev->features |= NETIF_F_IP_CSUM; /* Can checksum TCP/UDP over IPv4 */
10464 +#endif  /* CONFIG_RAETH_HW_LRO */
10465 +//#if LINUX_VERSION_CODE > KERNEL_VERSION(3,10,0)
10466 +//     dev->vlan_features |= NETIF_F_IP_CSUM;
10467 +//#endif
10468 +
10469 +#if defined(CONFIG_RALINK_MT7620)
10470 +#if defined (CONFIG_RAETH_TSO)
10471 +       if ((sysRegRead(0xB000000C) & 0xf) >= 0x5) {
10472 +               dev->features |= NETIF_F_SG;
10473 +               dev->features |= NETIF_F_TSO;
10474 +       }
10475 +#endif // CONFIG_RAETH_TSO //
10476 +
10477 +#if defined (CONFIG_RAETH_TSOV6)
10478 +       if ((sysRegRead(0xB000000C) & 0xf) >= 0x5) {
10479 +               dev->features |= NETIF_F_TSO6;
10480 +               dev->features |= NETIF_F_IPV6_CSUM; /* Can checksum TCP/UDP over IPv6 */
10481 +       }
10482 +#endif // CONFIG_RAETH_TSOV6 //
10483 +#else
10484 +#if defined (CONFIG_RAETH_TSO)
10485 +       dev->features |= NETIF_F_SG;
10486 +       dev->features |= NETIF_F_TSO;
10487 +#endif // CONFIG_RAETH_TSO //
10488 +
10489 +#if defined (CONFIG_RAETH_TSOV6)
10490 +       dev->features |= NETIF_F_TSO6;
10491 +       dev->features |= NETIF_F_IPV6_CSUM; /* Can checksum TCP/UDP over IPv6 */
10492 +#endif // CONFIG_RAETH_TSOV6 //
10493 +#endif // CONFIG_RALINK_MT7620 //
10494 +#else // Checksum offload disabled
10495 +
10496 +       //disable ipv4 header checksum check
10497 +       regVal &= ~GDM1_ICS_EN;
10498 +       regCsg &= ~ICS_GEN_EN;
10499 +
10500 +       //disable tcp checksum check
10501 +       regVal &= ~GDM1_TCS_EN;
10502 +       regCsg &= ~TCS_GEN_EN;
10503 +
10504 +       //disable udp checksum check
10505 +       regVal &= ~GDM1_UCS_EN;
10506 +       regCsg &= ~UCS_GEN_EN;
10507 +
10508 +#ifdef CONFIG_PSEUDO_SUPPORT
10509 +       regVal2 &= ~GDM1_ICS_EN;
10510 +       regVal2 &= ~GDM1_TCS_EN;
10511 +       regVal2 &= ~GDM1_UCS_EN;
10512 +#endif
10513 +
10514 +       dev->features &= ~NETIF_F_IP_CSUM; /* disable checksum TCP/UDP over IPv4 */
10515 +#endif // CONFIG_RAETH_CHECKSUM_OFFLOAD //
10516 +
10517 +#ifdef CONFIG_RAETH_JUMBOFRAME
10518 +       regVal |= GDM1_JMB_EN;
10519 +#ifdef CONFIG_PSEUDO_SUPPORT
10520 +       regVal2 |= GDM1_JMB_EN;
10521 +#endif
10522 +#endif
10523 +
10524 +       sysRegWrite(GDMA1_FWD_CFG, regVal);
10525 +       sysRegWrite(CDMA_CSG_CFG, regCsg);
10526 +#ifdef CONFIG_PSEUDO_SUPPORT
10527 +       sysRegWrite(GDMA2_FWD_CFG, regVal2);
10528 +#endif
10529 +
10530 +#if LINUX_VERSION_CODE > KERNEL_VERSION(3,10,0)
10531 +        dev->vlan_features = dev->features;
10532 +#endif
10533 +
10534 +/*
10535 + *     PSE_FQ_CFG register definition -
10536 + *
10537 + *     Define max free queue page count in PSE. (31:24)
10538 + *     RT2883/RT3883 - 0xff908000 (255 pages)
10539 + *     RT3052 - 0x80504000 (128 pages)
10540 + *     RT2880 - 0x80504000 (128 pages)
10541 + *
10542 + *     In each page, there are 128 bytes in each page.
10543 + *
10544 + *     23:16 - free queue flow control release threshold
10545 + *     15:8  - free queue flow control assertion threshold
10546 + *     7:0   - free queue empty threshold
10547 + *
10548 + *     The register affects QOS correctness in frame engine!
10549 + */
10550 +
10551 +#if defined(CONFIG_RALINK_RT2883) || defined(CONFIG_RALINK_RT3883)
10552 +       sysRegWrite(PSE_FQ_CFG, cpu_to_le32(INIT_VALUE_OF_RT2883_PSE_FQ_CFG));
10553 +#elif defined(CONFIG_RALINK_RT3352) || defined(CONFIG_RALINK_RT5350) ||  \
10554 +      defined(CONFIG_RALINK_RT6855) || defined(CONFIG_RALINK_RT6855A) || \
10555 +      defined(CONFIG_RALINK_MT7620) || defined(CONFIG_RALINK_MT7621) || \
10556 +      defined (CONFIG_RALINK_MT7628) || defined(CONFIG_ARCH_MT7623)
10557 +        /*use default value*/
10558 +#else
10559 +       sysRegWrite(PSE_FQ_CFG, cpu_to_le32(INIT_VALUE_OF_PSE_FQFC_CFG));
10560 +#endif
10561 +
10562 +       /*
10563 +        *FE_RST_GLO register definition -
10564 +        *Bit 0: PSE Rest
10565 +        *Reset PSE after re-programming PSE_FQ_CFG.
10566 +        */
10567 +       regVal = 0x1;
10568 +       sysRegWrite(FE_RST_GL, regVal);
10569 +       sysRegWrite(FE_RST_GL, 0);      // update for RSTCTL issue
10570 +
10571 +       regCsg = sysRegRead(CDMA_CSG_CFG);
10572 +       printk("CDMA_CSG_CFG = %0X\n",regCsg);
10573 +       regVal = sysRegRead(GDMA1_FWD_CFG);
10574 +       printk("GDMA1_FWD_CFG = %0X\n",regVal);
10575 +
10576 +#ifdef CONFIG_PSEUDO_SUPPORT
10577 +       regVal = sysRegRead(GDMA2_FWD_CFG);
10578 +       printk("GDMA2_FWD_CFG = %0X\n",regVal);
10579 +#endif
10580 +#endif
10581 +       return 1;
10582 +}
10583 +
10584 +#ifdef CONFIG_RAETH_LRO
10585 +static int
10586 +rt_get_skb_header(struct sk_buff *skb, void **iphdr, void **tcph,
10587 +                       u64 *hdr_flags, void *priv)
10588 +{
10589 +        struct iphdr *iph = NULL;
10590 +       int    vhdr_len = 0;
10591 +
10592 +        /*
10593 +         * Make sure that this packet is Ethernet II, is not VLAN
10594 +         * tagged, is IPv4, has a valid IP header, and is TCP.
10595 +         */
10596 +       if (skb->protocol == 0x0081) {
10597 +               vhdr_len = VLAN_HLEN;
10598 +       }
10599 +
10600 +       iph = (struct iphdr *)(skb->data + vhdr_len);
10601 +       if (iph->daddr != lro_para.lan_ip1) {
10602 +               return -1;
10603 +       }
10604 +
10605 +       if(iph->protocol != IPPROTO_TCP) {
10606 +               return -1;
10607 +       } else {
10608 +               *iphdr = iph;
10609 +               *tcph = skb->data + (iph->ihl << 2) + vhdr_len;
10610 +               *hdr_flags = LRO_IPV4 | LRO_TCP;
10611 +
10612 +               lro_flush_needed = 1;
10613 +               return 0;
10614 +       }
10615 +}
10616 +#endif // CONFIG_RAETH_LRO //
10617 +
10618 +#ifdef CONFIG_RAETH_NAPI
10619 +static int rt2880_eth_recv(struct net_device* dev, int *work_done, int work_to_do)
10620 +#else
10621 +static int rt2880_eth_recv(struct net_device* dev)
10622 +#endif
10623 +{
10624 +       struct sk_buff  *skb, *rx_skb;
10625 +       unsigned int    length = 0;
10626 +       unsigned long   RxProcessed;
10627 +
10628 +       int bReschedule = 0;
10629 +       END_DEVICE*     ei_local = netdev_priv(dev);
10630 +#if defined (CONFIG_RAETH_MULTIPLE_RX_RING) || defined (CONFIG_RAETH_HW_LRO)
10631 +       int rx_ring_no=0;
10632 +#endif
10633 +
10634 +#if defined (CONFIG_RAETH_SPECIAL_TAG)
10635 +       struct vlan_ethhdr *veth=NULL;
10636 +#endif
10637 +
10638 +#ifdef CONFIG_PSEUDO_SUPPORT
10639 +       PSEUDO_ADAPTER *pAd;
10640 +#endif
10641 +
10642 +       RxProcessed = 0;
10643 +#ifdef CONFIG_RAETH_RW_PDMAPTR_FROM_VAR
10644 +       rx_dma_owner_idx0 = (rx_calc_idx0 + 1) % NUM_RX_DESC;
10645 +#else
10646 +       rx_dma_owner_idx0 = (sysRegRead(RAETH_RX_CALC_IDX0) + 1) % NUM_RX_DESC;
10647 +#endif
10648 +
10649 +#if defined (CONFIG_32B_DESC)
10650 +       dma_cache_sync(NULL, &ei_local->rx_ring0[rx_dma_owner_idx0], sizeof(struct PDMA_rxdesc), DMA_FROM_DEVICE);
10651 +#endif
10652 +#if defined (CONFIG_RAETH_HW_LRO)
10653 +       rx_dma_owner_lro1 = (sysRegRead(RX_CALC_IDX1) + 1) % NUM_LRO_RX_DESC;
10654 +       rx_dma_owner_lro2 = (sysRegRead(RX_CALC_IDX2) + 1) % NUM_LRO_RX_DESC;
10655 +       rx_dma_owner_lro3 = (sysRegRead(RX_CALC_IDX3) + 1) % NUM_LRO_RX_DESC;
10656 +#elif defined (CONFIG_RAETH_MULTIPLE_RX_RING)
10657 +#ifdef CONFIG_RAETH_RW_PDMAPTR_FROM_VAR
10658 +       rx_dma_owner_idx1 = (rx_calc_idx1 + 1) % NUM_RX_DESC;
10659 +#else
10660 +       rx_dma_owner_idx1 = (sysRegRead(RX_CALC_IDX1) + 1) % NUM_RX_DESC;
10661 +#endif  /* CONFIG_RAETH_RW_PDMAPTR_FROM_VAR */
10662 +#if defined(CONFIG_ARCH_MT7623)
10663 +    rx_dma_owner_idx2 = (sysRegRead(RX_CALC_IDX2) + 1) % NUM_RX_DESC;
10664 +    rx_dma_owner_idx3 = (sysRegRead(RX_CALC_IDX3) + 1) % NUM_RX_DESC;
10665 +#endif
10666 +#if defined (CONFIG_32B_DESC)
10667 +       dma_cache_sync(NULL, &ei_local->rx_ring1[rx_dma_owner_idx1], sizeof(struct PDMA_rxdesc), DMA_FROM_DEVICE);
10668 +#endif
10669 +#endif
10670 +       for ( ; ; ) {
10671 +
10672 +
10673 +#ifdef CONFIG_RAETH_NAPI
10674 +                if(*work_done >= work_to_do)
10675 +                        break;
10676 +                (*work_done)++;
10677 +#else
10678 +               if (RxProcessed++ > NUM_RX_MAX_PROCESS)
10679 +                {
10680 +                        // need to reschedule rx handle
10681 +                        bReschedule = 1;
10682 +                        break;
10683 +                }
10684 +#endif
10685 +
10686 +
10687 +#if defined (CONFIG_RAETH_HW_LRO)
10688 +               if (ei_local->rx_ring3[rx_dma_owner_lro3].rxd_info2.DDONE_bit == 1)  {
10689 +                   rx_ring = ei_local->rx_ring3;
10690 +                   rx_dma_owner_idx = rx_dma_owner_lro3;
10691 +               //    printk("rx_dma_owner_lro3=%x\n",rx_dma_owner_lro3);
10692 +                   rx_ring_no=3;
10693 +               }
10694 +               else if (ei_local->rx_ring2[rx_dma_owner_lro2].rxd_info2.DDONE_bit == 1)  {
10695 +                   rx_ring = ei_local->rx_ring2;
10696 +                   rx_dma_owner_idx = rx_dma_owner_lro2;
10697 +               //    printk("rx_dma_owner_lro2=%x\n",rx_dma_owner_lro2);
10698 +                   rx_ring_no=2;
10699 +               }
10700 +               else if (ei_local->rx_ring1[rx_dma_owner_lro1].rxd_info2.DDONE_bit == 1)  {
10701 +                   rx_ring = ei_local->rx_ring1;
10702 +                   rx_dma_owner_idx = rx_dma_owner_lro1;
10703 +               //    printk("rx_dma_owner_lro1=%x\n",rx_dma_owner_lro1);
10704 +                   rx_ring_no=1;
10705 +               }
10706 +               else if (ei_local->rx_ring0[rx_dma_owner_idx0].rxd_info2.DDONE_bit == 1)  {
10707 +                   rx_ring = ei_local->rx_ring0;
10708 +                   rx_dma_owner_idx = rx_dma_owner_idx0;
10709 +                //   printk("rx_dma_owner_idx0=%x\n",rx_dma_owner_idx0);
10710 +                   rx_ring_no=0;
10711 +               } else {
10712 +                   break;
10713 +               }
10714 +    #if defined (CONFIG_RAETH_HW_LRO_DBG)
10715 +        HwLroStatsUpdate(rx_ring_no, rx_ring[rx_dma_owner_idx].rxd_info2.LRO_AGG_CNT, \
10716 +            (rx_ring[rx_dma_owner_idx].rxd_info2.PLEN1 << 14) | rx_ring[rx_dma_owner_idx].rxd_info2.PLEN0);
10717 +    #endif
10718 +    #if defined(CONFIG_RAETH_HW_LRO_REASON_DBG)
10719 +        HwLroFlushStatsUpdate(rx_ring_no, rx_ring[rx_dma_owner_idx].rxd_info2.REV);
10720 +    #endif
10721 +#elif defined (CONFIG_RAETH_MULTIPLE_RX_RING)
10722 +               if (ei_local->rx_ring1[rx_dma_owner_idx1].rxd_info2.DDONE_bit == 1)  {
10723 +                   rx_ring = ei_local->rx_ring1;
10724 +                   rx_dma_owner_idx = rx_dma_owner_idx1;
10725 +               //    printk("rx_dma_owner_idx1=%x\n",rx_dma_owner_idx1);
10726 +                   rx_ring_no=1;
10727 +               }
10728 +#if defined(CONFIG_ARCH_MT7623)
10729 +        else if (ei_local->rx_ring2[rx_dma_owner_idx2].rxd_info2.DDONE_bit == 1)  {
10730 +            rx_ring = ei_local->rx_ring2;
10731 +            rx_dma_owner_idx = rx_dma_owner_idx2;
10732 +        //    printk("rx_dma_owner_idx2=%x\n",rx_dma_owner_idx2);
10733 +            rx_ring_no=2;
10734 +        }
10735 +        else if (ei_local->rx_ring3[rx_dma_owner_idx3].rxd_info2.DDONE_bit == 1)  {
10736 +                   rx_ring = ei_local->rx_ring3;
10737 +                   rx_dma_owner_idx = rx_dma_owner_idx3;
10738 +               //    printk("rx_dma_owner_idx3=%x\n",rx_dma_owner_idx3);
10739 +                   rx_ring_no=3;
10740 +               }
10741 +#endif  /* CONFIG_ARCH_MT7623 */
10742 +        else if (ei_local->rx_ring0[rx_dma_owner_idx0].rxd_info2.DDONE_bit == 1)  {
10743 +                   rx_ring = ei_local->rx_ring0;
10744 +                   rx_dma_owner_idx = rx_dma_owner_idx0;
10745 +                //   printk("rx_dma_owner_idx0=%x\n",rx_dma_owner_idx0);
10746 +                   rx_ring_no=0;
10747 +               } else {
10748 +                   break;
10749 +               }
10750 +#else
10751 +
10752 +               if (ei_local->rx_ring0[rx_dma_owner_idx0].rxd_info2.DDONE_bit == 1)  {
10753 +                   rx_ring = ei_local->rx_ring0;
10754 +                   rx_dma_owner_idx = rx_dma_owner_idx0;
10755 +               } else {
10756 +                   break;
10757 +               }
10758 +#endif
10759 +
10760 +#if defined (CONFIG_32B_DESC)
10761 +               prefetch(&rx_ring[(rx_dma_owner_idx + 1) % NUM_RX_DESC]);
10762 +#endif
10763 +               /* skb processing */
10764 +#if defined (CONFIG_RAETH_HW_LRO)
10765 +        length = (rx_ring[rx_dma_owner_idx].rxd_info2.PLEN1 << 14) | rx_ring[rx_dma_owner_idx].rxd_info2.PLEN0;
10766 +#else
10767 +               length = rx_ring[rx_dma_owner_idx].rxd_info2.PLEN0;
10768 +#endif  /* CONFIG_RAETH_HW_LRO */
10769 +
10770 +#if defined (CONFIG_ARCH_MT7623)
10771 +               dma_unmap_single(NULL, rx_ring[rx_dma_owner_idx].rxd_info1.PDP0, length, DMA_FROM_DEVICE);
10772 +#endif
10773 +
10774 +#if defined (CONFIG_RAETH_HW_LRO)
10775 +               if(rx_ring_no==3) {
10776 +                   rx_skb = ei_local->netrx3_skbuf[rx_dma_owner_idx];
10777 +                   rx_skb->data = ei_local->netrx3_skbuf[rx_dma_owner_idx]->data;
10778 +               }
10779 +               else if(rx_ring_no==2) {
10780 +                   rx_skb = ei_local->netrx2_skbuf[rx_dma_owner_idx];
10781 +                   rx_skb->data = ei_local->netrx2_skbuf[rx_dma_owner_idx]->data;
10782 +               }
10783 +               else if(rx_ring_no==1) {
10784 +                   rx_skb = ei_local->netrx1_skbuf[rx_dma_owner_idx];
10785 +                   rx_skb->data = ei_local->netrx1_skbuf[rx_dma_owner_idx]->data;
10786 +               }
10787 +               else {
10788 +                   rx_skb = ei_local->netrx0_skbuf[rx_dma_owner_idx];
10789 +                   rx_skb->data = ei_local->netrx0_skbuf[rx_dma_owner_idx]->data;
10790 +               }
10791 +    #if defined(CONFIG_RAETH_PDMA_DVT)
10792 +        raeth_pdma_lro_dvt( rx_ring_no, ei_local, rx_dma_owner_idx );
10793 +    #endif  /* CONFIG_RAETH_PDMA_DVT */
10794 +#elif defined (CONFIG_RAETH_MULTIPLE_RX_RING)
10795 +               if(rx_ring_no==1) {
10796 +                   rx_skb = ei_local->netrx1_skbuf[rx_dma_owner_idx];
10797 +                   rx_skb->data = ei_local->netrx1_skbuf[rx_dma_owner_idx]->data;
10798 +               }
10799 +#if defined(CONFIG_ARCH_MT7623)
10800 +               else if(rx_ring_no==2) {
10801 +                   rx_skb = ei_local->netrx2_skbuf[rx_dma_owner_idx];
10802 +                   rx_skb->data = ei_local->netrx2_skbuf[rx_dma_owner_idx]->data;
10803 +               }
10804 +        else if(rx_ring_no==3) {
10805 +                   rx_skb = ei_local->netrx3_skbuf[rx_dma_owner_idx];
10806 +                   rx_skb->data = ei_local->netrx3_skbuf[rx_dma_owner_idx]->data;
10807 +               }
10808 +#endif  /* CONFIG_ARCH_MT7623 */
10809 +        else {
10810 +                   rx_skb = ei_local->netrx0_skbuf[rx_dma_owner_idx];
10811 +                   rx_skb->data = ei_local->netrx0_skbuf[rx_dma_owner_idx]->data;
10812 +               }
10813 +    #if defined(CONFIG_RAETH_PDMA_DVT)
10814 +        raeth_pdma_lro_dvt( rx_ring_no, ei_local, rx_dma_owner_idx );
10815 +    #endif  /* CONFIG_RAETH_PDMA_DVT */
10816 +#else
10817 +               rx_skb = ei_local->netrx0_skbuf[rx_dma_owner_idx];
10818 +               rx_skb->data = ei_local->netrx0_skbuf[rx_dma_owner_idx]->data;
10819 +    #if defined(CONFIG_RAETH_PDMA_DVT)
10820 +        raeth_pdma_rx_desc_dvt( ei_local, rx_dma_owner_idx0 );
10821 +    #endif  /* CONFIG_RAETH_PDMA_DVT */
10822 +#endif
10823 +               rx_skb->len     = length;
10824 +/*TODO*/
10825 +#if defined (CONFIG_RAETH_SCATTER_GATHER_RX_DMA)
10826 +               rx_skb->data += NET_IP_ALIGN;
10827 +#endif
10828 +               rx_skb->tail    = rx_skb->data + length;
10829 +
10830 +#ifdef CONFIG_PSEUDO_SUPPORT
10831 +               if(rx_ring[rx_dma_owner_idx].rxd_info4.SP == 2) {
10832 +                   if(ei_local->PseudoDev!=NULL) {
10833 +                       rx_skb->dev       = ei_local->PseudoDev;
10834 +                       rx_skb->protocol  = eth_type_trans(rx_skb,ei_local->PseudoDev);
10835 +                   }else {
10836 +                       printk("ERROR: PseudoDev is still not initialize but receive packet from GMAC2\n");
10837 +                   }
10838 +               }else{
10839 +                   rx_skb->dev           = dev;
10840 +                   rx_skb->protocol      = eth_type_trans(rx_skb,dev);
10841 +               }
10842 +#else
10843 +               rx_skb->dev       = dev;
10844 +               rx_skb->protocol  = eth_type_trans(rx_skb,dev);
10845 +#endif
10846 +
10847 +#ifdef CONFIG_RAETH_CHECKSUM_OFFLOAD
10848 +#if defined (CONFIG_PDMA_NEW)
10849 +               if(rx_ring[rx_dma_owner_idx].rxd_info4.L4VLD) {
10850 +                       rx_skb->ip_summed = CHECKSUM_UNNECESSARY;
10851 +               }else {
10852 +                   rx_skb->ip_summed = CHECKSUM_NONE;
10853 +               }
10854 +#else
10855 +               if(rx_ring[rx_dma_owner_idx].rxd_info4.IPFVLD_bit) {
10856 +                       rx_skb->ip_summed = CHECKSUM_UNNECESSARY;
10857 +               }else {
10858 +                   rx_skb->ip_summed = CHECKSUM_NONE;
10859 +               }
10860 +#endif
10861 +#else
10862 +                   rx_skb->ip_summed = CHECKSUM_NONE;
10863 +#endif
10864 +
10865 +#if defined(CONFIG_RA_CLASSIFIER)||defined(CONFIG_RA_CLASSIFIER_MODULE)
10866 +               /* Qwert+
10867 +                */
10868 +               if(ra_classifier_hook_rx!= NULL)
10869 +               {
10870 +#if defined(CONFIG_RALINK_EXTERNAL_TIMER)
10871 +                       ra_classifier_hook_rx(rx_skb, (*((volatile u32 *)(0xB0000D08))&0x0FFFF));
10872 +#else
10873 +                       ra_classifier_hook_rx(rx_skb, read_c0_count());
10874 +#endif
10875 +               }
10876 +#endif /* CONFIG_RA_CLASSIFIER */
10877 +
10878 +#if defined (CONFIG_RA_HW_NAT)  || defined (CONFIG_RA_HW_NAT_MODULE)
10879 +               if(ra_sw_nat_hook_rx != NULL) {
10880 +                   FOE_MAGIC_TAG(rx_skb)= FOE_MAGIC_GE;
10881 +                   *(uint32_t *)(FOE_INFO_START_ADDR(rx_skb)+2) = *(uint32_t *)&rx_ring[rx_dma_owner_idx].rxd_info4;
10882 +                   FOE_ALG(rx_skb) = 0;
10883 +               }
10884 +#endif
10885 +
10886 +               /* We have to check the free memory size is big enough
10887 +                * before pass the packet to cpu*/
10888 +#if defined (CONFIG_RAETH_SKB_RECYCLE_2K)
10889 +#if defined (CONFIG_RAETH_HW_LRO)
10890 +            if( rx_ring != ei_local->rx_ring0 )
10891 +                skb = __dev_alloc_skb(MAX_LRO_RX_LENGTH + NET_IP_ALIGN, GFP_ATOMIC);
10892 +            else
10893 +#endif  /* CONFIG_RAETH_HW_LRO */
10894 +                skb = skbmgr_dev_alloc_skb2k();
10895 +#else
10896 +#if defined (CONFIG_RAETH_HW_LRO)
10897 +        if( rx_ring != ei_local->rx_ring0 )
10898 +            skb = __dev_alloc_skb(MAX_LRO_RX_LENGTH + NET_IP_ALIGN, GFP_ATOMIC);
10899 +        else
10900 +#endif  /* CONFIG_RAETH_HW_LRO */
10901 +               skb = __dev_alloc_skb(MAX_RX_LENGTH + NET_IP_ALIGN, GFP_ATOMIC);
10902 +#endif
10903 +
10904 +               if (unlikely(skb == NULL))
10905 +               {
10906 +                       printk(KERN_ERR "skb not available...\n");
10907 +#ifdef CONFIG_PSEUDO_SUPPORT
10908 +                       if (rx_ring[rx_dma_owner_idx].rxd_info4.SP == 2) {
10909 +                               if (ei_local->PseudoDev != NULL) {
10910 +                                       pAd = netdev_priv(ei_local->PseudoDev);
10911 +                                       pAd->stat.rx_dropped++;
10912 +                               }
10913 +                       } else
10914 +#endif
10915 +                               ei_local->stat.rx_dropped++;
10916 +                        bReschedule = 1;
10917 +                       break;
10918 +               }
10919 +#if !defined (CONFIG_RAETH_SCATTER_GATHER_RX_DMA)
10920 +               skb_reserve(skb, NET_IP_ALIGN);
10921 +#endif
10922 +
10923 +#if defined (CONFIG_RAETH_SPECIAL_TAG)
10924 +               // port0: 0x8100 => 0x8100 0001
10925 +               // port1: 0x8101 => 0x8100 0002
10926 +               // port2: 0x8102 => 0x8100 0003
10927 +               // port3: 0x8103 => 0x8100 0004
10928 +               // port4: 0x8104 => 0x8100 0005
10929 +               // port5: 0x8105 => 0x8100 0006
10930 +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,21)
10931 +               veth = (struct vlan_ethhdr *)(rx_skb->mac_header);
10932 +#else
10933 +               veth = (struct vlan_ethhdr *)(rx_skb->mac.raw);
10934 +#endif
10935 +               /*donot check 0x81 due to MT7530 SPEC*/
10936 +               //if((veth->h_vlan_proto & 0xFF) == 0x81)
10937 +               {
10938 +                   veth->h_vlan_TCI = htons( (((veth->h_vlan_proto >> 8) & 0xF) + 1) );
10939 +                   rx_skb->protocol = veth->h_vlan_proto = htons(ETH_P_8021Q);
10940 +               }
10941 +#endif
10942 +
10943 +/* ra_sw_nat_hook_rx return 1 --> continue
10944 + * ra_sw_nat_hook_rx return 0 --> FWD & without netif_rx
10945 + */
10946 +#if !defined(CONFIG_RA_NAT_NONE)
10947 +         if((ra_sw_nat_hook_rx == NULL) ||
10948 +           (ra_sw_nat_hook_rx!= NULL && ra_sw_nat_hook_rx(rx_skb)))
10949 +#endif
10950 +         {
10951 +#if defined (CONFIG_RALINK_RT3052_MP2)
10952 +              if(mcast_rx(rx_skb)==0) {
10953 +                  kfree_skb(rx_skb);
10954 +              }else
10955 +#endif
10956 +#if defined (CONFIG_RAETH_LRO)
10957 +              if (rx_skb->ip_summed == CHECKSUM_UNNECESSARY) {
10958 +                      lro_receive_skb(&ei_local->lro_mgr, rx_skb, NULL);
10959 +                      //LroStatsUpdate(&ei_local->lro_mgr,0);
10960 +              } else
10961 +#endif
10962 +#ifdef CONFIG_RAETH_NAPI
10963 +                netif_receive_skb(rx_skb);
10964 +#else
10965 +#ifdef CONFIG_RAETH_HW_VLAN_RX
10966 +               if(ei_local->vlgrp && rx_ring[rx_dma_owner_idx].rxd_info2.TAG) {
10967 +                       vlan_hwaccel_rx(rx_skb, ei_local->vlgrp, rx_ring[rx_dma_owner_idx].rxd_info3.VID);
10968 +               } else {
10969 +                       netif_rx(rx_skb);
10970 +               }
10971 +#else
10972 +#ifdef CONFIG_RAETH_CPU_LOOPBACK
10973 +                skb_push(rx_skb,ETH_HLEN);
10974 +                ei_start_xmit(rx_skb, dev, 1);
10975 +#else
10976 +                netif_rx(rx_skb);
10977 +#endif
10978 +#endif
10979 +#endif
10980 +         }
10981 +
10982 +#ifdef CONFIG_PSEUDO_SUPPORT
10983 +               if (rx_ring[rx_dma_owner_idx].rxd_info4.SP == 2) {
10984 +                       if (ei_local->PseudoDev != NULL) {
10985 +                               pAd = netdev_priv(ei_local->PseudoDev);
10986 +                               pAd->stat.rx_packets++;
10987 +                               pAd->stat.rx_bytes += length;
10988 +                       }
10989 +               } else
10990 +#endif
10991 +               {
10992 +                       ei_local->stat.rx_packets++;
10993 +                       ei_local->stat.rx_bytes += length;
10994 +               }
10995 +
10996 +
10997 +#if defined (CONFIG_RAETH_SCATTER_GATHER_RX_DMA)
10998 +#if defined (CONFIG_RAETH_HW_LRO)
10999 +        if( rx_ring != ei_local->rx_ring0 ){
11000 +            rx_ring[rx_dma_owner_idx].rxd_info2.PLEN0 = SET_ADMA_RX_LEN0(MAX_LRO_RX_LENGTH);
11001 +            rx_ring[rx_dma_owner_idx].rxd_info2.PLEN1 = SET_ADMA_RX_LEN1(MAX_LRO_RX_LENGTH >> 14);
11002 +        }
11003 +        else
11004 +#endif  /* CONFIG_RAETH_HW_LRO */
11005 +               rx_ring[rx_dma_owner_idx].rxd_info2.PLEN0 = MAX_RX_LENGTH;
11006 +               rx_ring[rx_dma_owner_idx].rxd_info2.LS0 = 0;
11007 +#endif
11008 +               rx_ring[rx_dma_owner_idx].rxd_info2.DDONE_bit = 0;
11009 +#if defined (CONFIG_RAETH_HW_LRO)
11010 +        if( rx_ring != ei_local->rx_ring0 )
11011 +            rx_ring[rx_dma_owner_idx].rxd_info1.PDP0 = dma_map_single(NULL, skb->data, MAX_LRO_RX_LENGTH, PCI_DMA_FROMDEVICE);
11012 +        else
11013 +#endif  /* CONFIG_RAETH_HW_LRO */
11014 +               rx_ring[rx_dma_owner_idx].rxd_info1.PDP0 = dma_map_single(NULL, skb->data, MAX_RX_LENGTH, PCI_DMA_FROMDEVICE);
11015 +#ifdef CONFIG_32B_DESC
11016 +               dma_cache_sync(NULL, &rx_ring[rx_dma_owner_idx], sizeof(struct PDMA_rxdesc), DMA_TO_DEVICE);
11017 +#endif
11018 +               /*  Move point to next RXD which wants to alloc*/
11019 +#if defined (CONFIG_RAETH_HW_LRO)
11020 +               if(rx_ring_no==3) {
11021 +                   sysRegWrite(RAETH_RX_CALC_IDX3, rx_dma_owner_idx);
11022 +                   ei_local->netrx3_skbuf[rx_dma_owner_idx] = skb;
11023 +               }
11024 +               else if(rx_ring_no==2) {
11025 +                   sysRegWrite(RAETH_RX_CALC_IDX2, rx_dma_owner_idx);
11026 +                   ei_local->netrx2_skbuf[rx_dma_owner_idx] = skb;
11027 +               }
11028 +               else if(rx_ring_no==1) {
11029 +                   sysRegWrite(RAETH_RX_CALC_IDX1, rx_dma_owner_idx);
11030 +                   ei_local->netrx1_skbuf[rx_dma_owner_idx] = skb;
11031 +               }
11032 +               else if(rx_ring_no==0) {
11033 +                   sysRegWrite(RAETH_RX_CALC_IDX0, rx_dma_owner_idx);
11034 +                   ei_local->netrx0_skbuf[rx_dma_owner_idx] = skb;
11035 +               }
11036 +#elif defined (CONFIG_RAETH_MULTIPLE_RX_RING)
11037 +               if(rx_ring_no==0) {
11038 +                   sysRegWrite(RAETH_RX_CALC_IDX0, rx_dma_owner_idx);
11039 +                   ei_local->netrx0_skbuf[rx_dma_owner_idx] = skb;
11040 +#ifdef CONFIG_RAETH_RW_PDMAPTR_FROM_VAR
11041 +                   rx_calc_idx0 = rx_dma_owner_idx;
11042 +#endif
11043 +               }
11044 +#if defined(CONFIG_ARCH_MT7623)
11045 +        else if(rx_ring_no==3) {
11046 +                   sysRegWrite(RAETH_RX_CALC_IDX3, rx_dma_owner_idx);
11047 +                   ei_local->netrx3_skbuf[rx_dma_owner_idx] = skb;
11048 +               }
11049 +               else if(rx_ring_no==2) {
11050 +                   sysRegWrite(RAETH_RX_CALC_IDX2, rx_dma_owner_idx);
11051 +                   ei_local->netrx2_skbuf[rx_dma_owner_idx] = skb;
11052 +               }
11053 +#endif  /* CONFIG_ARCH_MT7623 */
11054 +        else {
11055 +                   sysRegWrite(RAETH_RX_CALC_IDX1, rx_dma_owner_idx);
11056 +                   ei_local->netrx1_skbuf[rx_dma_owner_idx] = skb;
11057 +#ifdef CONFIG_RAETH_RW_PDMAPTR_FROM_VAR
11058 +                   rx_calc_idx1 = rx_dma_owner_idx;
11059 +#endif
11060 +               }
11061 +#else
11062 +               sysRegWrite(RAETH_RX_CALC_IDX0, rx_dma_owner_idx);
11063 +               ei_local->netrx0_skbuf[rx_dma_owner_idx] = skb;
11064 +#ifdef CONFIG_RAETH_RW_PDMAPTR_FROM_VAR
11065 +               rx_calc_idx0 = rx_dma_owner_idx;
11066 +#endif
11067 +#endif
11068 +
11069 +
11070 +               /* Update to Next packet point that was received.
11071 +                */
11072 +#if defined (CONFIG_RAETH_HW_LRO)
11073 +               if(rx_ring_no==3)
11074 +                       rx_dma_owner_lro3 = (sysRegRead(RAETH_RX_CALC_IDX3) + 1) % NUM_LRO_RX_DESC;
11075 +               else if(rx_ring_no==2)
11076 +                       rx_dma_owner_lro2 = (sysRegRead(RAETH_RX_CALC_IDX2) + 1) % NUM_LRO_RX_DESC;
11077 +               else if(rx_ring_no==1)
11078 +                       rx_dma_owner_lro1 = (sysRegRead(RAETH_RX_CALC_IDX1) + 1) % NUM_LRO_RX_DESC;
11079 +               else if(rx_ring_no==0)
11080 +                       rx_dma_owner_idx0 = (sysRegRead(RAETH_RX_CALC_IDX0) + 1) % NUM_RX_DESC;
11081 +               else {
11082 +               }
11083 +#elif defined (CONFIG_RAETH_MULTIPLE_RX_RING)
11084 +               if(rx_ring_no==0) {
11085 +#ifdef CONFIG_RAETH_RW_PDMAPTR_FROM_VAR
11086 +                       rx_dma_owner_idx0 = (rx_dma_owner_idx + 1) % NUM_RX_DESC;
11087 +#else
11088 +                       rx_dma_owner_idx0 = (sysRegRead(RAETH_RX_CALC_IDX0) + 1) % NUM_RX_DESC;
11089 +#endif
11090 +#if defined(CONFIG_ARCH_MT7623)
11091 +        }else if(rx_ring_no==3) {
11092 +            rx_dma_owner_idx3 = (sysRegRead(RAETH_RX_CALC_IDX3) + 1) % NUM_RX_DESC;
11093 +        }else if(rx_ring_no==2) {
11094 +            rx_dma_owner_idx2 = (sysRegRead(RAETH_RX_CALC_IDX2) + 1) % NUM_RX_DESC;
11095 +#endif  /* CONFIG_ARCH_MT7623 */
11096 +               }else {
11097 +#ifdef CONFIG_RAETH_RW_PDMAPTR_FROM_VAR
11098 +                       rx_dma_owner_idx1 = (rx_dma_owner_idx + 1) % NUM_RX_DESC;
11099 +#else
11100 +                       rx_dma_owner_idx1 = (sysRegRead(RAETH_RX_CALC_IDX1) + 1) % NUM_RX_DESC;
11101 +#endif
11102 +               }
11103 +#else
11104 +#ifdef CONFIG_RAETH_RW_PDMAPTR_FROM_VAR
11105 +               rx_dma_owner_idx0 = (rx_dma_owner_idx + 1) % NUM_RX_DESC;
11106 +#else
11107 +               rx_dma_owner_idx0 = (sysRegRead(RAETH_RX_CALC_IDX0) + 1) % NUM_RX_DESC;
11108 +#endif
11109 +#endif
11110 +       }       /* for */
11111 +
11112 +#if defined (CONFIG_RAETH_LRO)
11113 +       if (lro_flush_needed) {
11114 +               //LroStatsUpdate(&ei_local->lro_mgr,1);
11115 +               lro_flush_all(&ei_local->lro_mgr);
11116 +               lro_flush_needed = 0;
11117 +       }
11118 +#endif
11119 +       return bReschedule;
11120 +}
11121 +
11122 +
11123 +///////////////////////////////////////////////////////////////////
11124 +/////
11125 +///// ra_get_stats - gather packet information for management plane
11126 +/////
11127 +///// Pass net_device_stats to the upper layer.
11128 +/////
11129 +/////
11130 +///// RETURNS: pointer to net_device_stats
11131 +///////////////////////////////////////////////////////////////////
11132 +
11133 +struct net_device_stats *ra_get_stats(struct net_device *dev)
11134 +{
11135 +       END_DEVICE *ei_local = netdev_priv(dev);
11136 +       return &ei_local->stat;
11137 +}
11138 +
11139 +#if defined (CONFIG_RT_3052_ESW)
11140 +void kill_sig_workq(struct work_struct *work)
11141 +{
11142 +       struct file *fp;
11143 +       char pid[8];
11144 +       struct task_struct *p = NULL;
11145 +
11146 +       //read udhcpc pid from file, and send signal USR2,USR1 to get a new IP
11147 +       fp = filp_open("/var/run/udhcpc.pid", O_RDONLY, 0);
11148 +       if (IS_ERR(fp))
11149 +           return;
11150 +
11151 +       if (fp->f_op && fp->f_op->read) {
11152 +           if (fp->f_op->read(fp, pid, 8, &fp->f_pos) > 0) {
11153 +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,35)
11154 +               p = pid_task(find_get_pid(simple_strtoul(pid, NULL, 10)),  PIDTYPE_PID);
11155 +#else
11156 +               p = find_task_by_pid(simple_strtoul(pid, NULL, 10));
11157 +#endif
11158 +
11159 +               if (NULL != p) {
11160 +                   send_sig(SIGUSR2, p, 0);
11161 +                   send_sig(SIGUSR1, p, 0);
11162 +               }
11163 +           }
11164 +       }
11165 +       filp_close(fp, NULL);
11166 +
11167 +}
11168 +#endif
11169 +
11170 +
11171 +///////////////////////////////////////////////////////////////////
11172 +/////
11173 +///// ra2880Recv - process the next incoming packet
11174 +/////
11175 +///// Handle one incoming packet.  The packet is checked for errors and sent
11176 +///// to the upper layer.
11177 +/////
11178 +///// RETURNS: OK on success or ERROR.
11179 +///////////////////////////////////////////////////////////////////
11180 +
11181 +#ifndef CONFIG_RAETH_NAPI
11182 +#if defined WORKQUEUE_BH || defined (TASKLET_WORKQUEUE_SW)
11183 +void ei_receive_workq(struct work_struct *work)
11184 +#else
11185 +void ei_receive(unsigned long unused)  // device structure
11186 +#endif // WORKQUEUE_BH //
11187 +{
11188 +       struct net_device *dev = dev_raether;
11189 +       END_DEVICE *ei_local = netdev_priv(dev);
11190 +       unsigned long reg_int_mask=0;
11191 +       int bReschedule=0;
11192 +
11193 +
11194 +       if(tx_ring_full==0){
11195 +               bReschedule = rt2880_eth_recv(dev);
11196 +               if(bReschedule)
11197 +               {
11198 +#ifdef WORKQUEUE_BH
11199 +                       schedule_work(&ei_local->rx_wq);
11200 +#else
11201 +#if defined (TASKLET_WORKQUEUE_SW)
11202 +                       if (working_schedule == 1)
11203 +                               schedule_work(&ei_local->rx_wq);
11204 +                       else
11205 +#endif
11206 +                       tasklet_hi_schedule(&ei_local->rx_tasklet);
11207 +#endif // WORKQUEUE_BH //
11208 +               }else{
11209 +                       reg_int_mask=sysRegRead(RAETH_FE_INT_ENABLE);
11210 +#if defined(DELAY_INT)
11211 +                       sysRegWrite(RAETH_FE_INT_ENABLE, reg_int_mask| RX_DLY_INT);
11212 +#else
11213 +                       sysRegWrite(RAETH_FE_INT_ENABLE, (reg_int_mask | RX_DONE_INT0 | RX_DONE_INT1 | RX_DONE_INT2 | RX_DONE_INT3));
11214 +#endif
11215 +#ifdef CONFIG_RAETH_QDMA
11216 +                       reg_int_mask=sysRegRead(QFE_INT_ENABLE);
11217 +#if defined(DELAY_INT)
11218 +                       sysRegWrite(QFE_INT_ENABLE, reg_int_mask| RX_DLY_INT);
11219 +#else
11220 +                       sysRegWrite(QFE_INT_ENABLE, (reg_int_mask | RX_DONE_INT0 | RX_DONE_INT1));
11221 +#endif
11222 +
11223 +#endif
11224 +
11225 +               }
11226 +       }else{
11227 +#ifdef WORKQUEUE_BH
11228 +                schedule_work(&ei_local->rx_wq);
11229 +#else
11230 +#if defined (TASKLET_WORKQUEUE_SW)
11231 +               if (working_schedule == 1)
11232 +                       schedule_work(&ei_local->rx_wq);
11233 +               else
11234 +#endif
11235 +                tasklet_schedule(&ei_local->rx_tasklet);
11236 +#endif // WORKQUEUE_BH //
11237 +       }
11238 +}
11239 +#endif
11240 +
11241 +#if defined (CONFIG_RAETH_HW_LRO)
11242 +void ei_hw_lro_auto_adj(unsigned int index, END_DEVICE* ei_local)
11243 +{
11244 +    unsigned int entry;
11245 +    unsigned int pkt_cnt;
11246 +    unsigned int tick_cnt;
11247 +    unsigned int duration_us;
11248 +    unsigned int byte_cnt;
11249 +
11250 +    /* read packet count statitics of the auto-learn table */
11251 +    entry = index  + 68;
11252 +    sysRegWrite( PDMA_FE_ALT_CF8, entry );
11253 +    pkt_cnt = sysRegRead(PDMA_FE_ALT_SGL_CFC) & 0xfff;
11254 +    tick_cnt = (sysRegRead(PDMA_FE_ALT_SGL_CFC) >> 16) & 0xffff;
11255 +#if defined (CONFIG_RAETH_HW_LRO_AUTO_ADJ_DBG)
11256 +    printk("[HW LRO] ei_hw_lro_auto_adj(): pkt_cnt[%d]=%d, tick_cnt[%d]=%d\n", index, pkt_cnt, index, tick_cnt);
11257 +    printk("[HW LRO] ei_hw_lro_auto_adj(): packet_interval[%d]=%d (ticks/pkt)\n", index, tick_cnt/pkt_cnt);
11258 +#endif
11259 +
11260 +    /* read byte count statitics of the auto-learn table */
11261 +    entry = index  + 64;
11262 +    sysRegWrite( PDMA_FE_ALT_CF8, entry );
11263 +    byte_cnt = sysRegRead(PDMA_FE_ALT_SGL_CFC);
11264 +#if defined (CONFIG_RAETH_HW_LRO_AUTO_ADJ_DBG)
11265 +    printk("[HW LRO] ei_hw_lro_auto_adj(): byte_cnt[%d]=%d\n", index, byte_cnt);
11266 +#endif
11267 +
11268 +    /* calculate the packet interval of the rx flow */
11269 +    duration_us = tick_cnt * HW_LRO_TIMER_UNIT;
11270 +    ei_local->hw_lro_pkt_interval[index - 1] = (duration_us/pkt_cnt) * ei_local->hw_lro_alpha / 100;
11271 +#if defined (CONFIG_RAETH_HW_LRO_AUTO_ADJ_DBG)
11272 +    printk("[HW LRO] ei_hw_lro_auto_adj(): packet_interval[%d]=%d (20us)\n", index, duration_us/pkt_cnt);
11273 +#endif
11274 +
11275 +    if ( !ei_local->hw_lro_fix_setting ){
11276 +    /* adjust age_time, agg_time for the lro ring */
11277 +       if(ei_local->hw_lro_pkt_interval[index - 1] > 0){
11278 +               SET_PDMA_RXRING_AGE_TIME(index, (ei_local->hw_lro_pkt_interval[index - 1] * HW_LRO_MAX_AGG_CNT));
11279 +               SET_PDMA_RXRING_AGG_TIME(index, (ei_local->hw_lro_pkt_interval[index - 1] * HW_LRO_AGG_DELTA));
11280 +       }
11281 +       else{
11282 +               SET_PDMA_RXRING_AGE_TIME(index, HW_LRO_MAX_AGG_CNT);
11283 +               SET_PDMA_RXRING_AGG_TIME(index, HW_LRO_AGG_DELTA);
11284 +       }
11285 +    }
11286 +}
11287 +
11288 +void ei_hw_lro_workq(struct work_struct *work)
11289 +{
11290 +    END_DEVICE *ei_local;
11291 +    unsigned int reg_int_val;
11292 +    unsigned int reg_int_mask;
11293 +
11294 +    ei_local = container_of(work, struct end_device, hw_lro_wq);
11295 +
11296 +    reg_int_val = sysRegRead(RAETH_FE_INT_STATUS);
11297 +#if defined (CONFIG_RAETH_HW_LRO_AUTO_ADJ_DBG)
11298 +    printk("[HW LRO] ei_hw_lro_workq(): RAETH_FE_INT_STATUS=0x%x\n", reg_int_val);
11299 +#endif
11300 +    if((reg_int_val & ALT_RPLC_INT3)){
11301 +#if defined (CONFIG_RAETH_HW_LRO_AUTO_ADJ_DBG)
11302 +        printk("[HW LRO] ALT_RPLC_INT3 occurred!\n");
11303 +#endif
11304 +        sysRegWrite(RAETH_FE_INT_STATUS, ALT_RPLC_INT3);
11305 +        ei_hw_lro_auto_adj(3, ei_local);
11306 +    }
11307 +    if((reg_int_val & ALT_RPLC_INT2)){
11308 +#if defined (CONFIG_RAETH_HW_LRO_AUTO_ADJ_DBG)
11309 +        printk("[HW LRO] ALT_RPLC_INT2 occurred!\n");
11310 +#endif
11311 +        sysRegWrite(RAETH_FE_INT_STATUS, ALT_RPLC_INT2);
11312 +        ei_hw_lro_auto_adj(2, ei_local);
11313 +    }
11314 +    if((reg_int_val & ALT_RPLC_INT1)){
11315 +#if defined (CONFIG_RAETH_HW_LRO_AUTO_ADJ_DBG)
11316 +        printk("[HW LRO] ALT_RPLC_INT1 occurred!\n");
11317 +#endif
11318 +        sysRegWrite(RAETH_FE_INT_STATUS, ALT_RPLC_INT1);
11319 +        ei_hw_lro_auto_adj(1, ei_local);
11320 +    }
11321 +
11322 +    /* unmask interrupts of rx flow to hw lor rings */
11323 +    reg_int_mask = sysRegRead(RAETH_FE_INT_ENABLE);
11324 +    sysRegWrite(RAETH_FE_INT_ENABLE, reg_int_mask | ALT_RPLC_INT3 | ALT_RPLC_INT2 | ALT_RPLC_INT1);
11325 +}
11326 +#endif  /* CONFIG_RAETH_HW_LRO */
11327 +
11328 +#ifdef CONFIG_RAETH_NAPI
11329 +static int
11330 +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,35)
11331 +raeth_clean(struct napi_struct *napi, int budget)
11332 +#else
11333 +raeth_clean(struct net_device *netdev, int *budget)
11334 +#endif
11335 +{
11336 +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,35)
11337 +       struct net_device *netdev=dev_raether;
11338 +        int work_to_do = budget;
11339 +#else
11340 +        int work_to_do = min(*budget, netdev->quota);
11341 +#endif
11342 +       END_DEVICE *ei_local =netdev_priv(netdev);
11343 +        int work_done = 0;
11344 +       unsigned long reg_int_mask=0;
11345 +
11346 +       ei_xmit_housekeeping(0);
11347 +
11348 +       rt2880_eth_recv(netdev, &work_done, work_to_do);
11349 +
11350 +        /* this could control when to re-enable interrupt, 0-> mean never enable interrupt*/
11351 +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,35)
11352 +        *budget -= work_done;
11353 +        netdev->quota -= work_done;
11354 +#endif
11355 +        /* if no Tx and not enough Rx work done, exit the polling mode */
11356 +        if(( (work_done < work_to_do)) || !netif_running(netdev)) {
11357 +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,35)
11358 +               napi_complete(&ei_local->napi);
11359 +#else
11360 +                netif_rx_complete(netdev);
11361 +#endif
11362 +               atomic_dec_and_test(&ei_local->irq_sem);
11363 +
11364 +               sysRegWrite(RAETH_FE_INT_STATUS, RAETH_FE_INT_ALL);             // ack all fe interrupts
11365 +               reg_int_mask=sysRegRead(RAETH_FE_INT_ENABLE);
11366 +
11367 +#ifdef DELAY_INT
11368 +               sysRegWrite(RAETH_FE_INT_ENABLE, reg_int_mask |RAETH_FE_INT_DLY_INIT);  // init delay interrupt only
11369 +#else
11370 +               sysRegWrite(RAETH_FE_INT_ENABLE,reg_int_mask | RAETH_FE_INT_SETTING);
11371 +#endif
11372 +
11373 +#ifdef CONFIG_RAETH_QDMA
11374 +               sysRegWrite(QFE_INT_STATUS, QFE_INT_ALL);
11375 +               reg_int_mask=sysRegRead(QFE_INT_ENABLE);
11376 +#ifdef DELAY_INT
11377 +                sysRegWrite(QFE_INT_ENABLE, reg_int_mask |QFE_INT_DLY_INIT);  // init delay interrupt only
11378 +#else
11379 +                sysRegWrite(QFE_INT_ENABLE,reg_int_mask | (RX_DONE_INT0 | RX_DONE_INT1 | RLS_DONE_INT));
11380 +#endif
11381 +#endif // CONFIG_RAETH_QDMA //
11382 +
11383 +                return 0;
11384 +        }
11385 +
11386 +        return 1;
11387 +}
11388 +
11389 +#endif
11390 +
11391 +
11392 +void gsw_delay_setting(void)
11393 +{
11394 +#if defined (CONFIG_GE_RGMII_INTERNAL_P0_AN) || defined (CONFIG_GE_RGMII_INTERNAL_P4_AN)
11395 +       END_DEVICE *ei_local = netdev_priv(dev_raether);
11396 +       int reg_int_val = 0;
11397 +       int link_speed = 0;
11398 +
11399 +       reg_int_val = sysRegRead(FE_INT_STATUS2);
11400 +#if defined (CONFIG_RALINK_MT7621)
11401 +       if( reg_int_val & BIT(25))
11402 +       {
11403 +               if(sysRegRead(RALINK_ETH_SW_BASE+0x0208) & 0x1) // link up
11404 +               {
11405 +                       link_speed = (sysRegRead(RALINK_ETH_SW_BASE+0x0208)>>2 & 0x3);
11406 +                       if(link_speed == 1)
11407 +                       {
11408 +                               // delay setting for 100M
11409 +                               if((sysRegRead(0xbe00000c)&0xFFFF)==0x0101)
11410 +                                       mii_mgr_write(31, 0x7b00, 8);
11411 +                               printk("MT7621 GE2 link rate to 100M\n");
11412 +                       } else
11413 +                       {
11414 +                               //delay setting for 10/1000M
11415 +                               if((sysRegRead(0xbe00000c)&0xFFFF)==0x0101)
11416 +                                       mii_mgr_write(31, 0x7b00, 0x102);
11417 +                               printk("MT7621 GE2 link rate to 10M/1G\n");
11418 +                       }
11419 +                       schedule_work(&ei_local->kill_sig_wq);
11420 +               }
11421 +       }
11422 +#endif
11423 +       sysRegWrite(FE_INT_STATUS2, reg_int_val);
11424 +#endif
11425 +}
11426 +
11427 +/**
11428 + * ei_interrupt - handle controler interrupt
11429 + *
11430 + * This routine is called at interrupt level in response to an interrupt from
11431 + * the controller.
11432 + *
11433 + * RETURNS: N/A.
11434 + */
11435 +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,21)
11436 +static irqreturn_t ei_interrupt(int irq, void *dev_id)
11437 +#else
11438 +static irqreturn_t ei_interrupt(int irq, void *dev_id, struct pt_regs * regs)
11439 +#endif
11440 +{
11441 +#if !defined(CONFIG_RAETH_NAPI)
11442 +       unsigned long reg_int_val;
11443 +       unsigned long reg_int_mask=0;
11444 +       unsigned int recv = 0;
11445 +       unsigned int transmit __maybe_unused = 0;
11446 +       unsigned long flags;
11447 +#endif
11448 +
11449 +       struct net_device *dev = (struct net_device *) dev_id;
11450 +       END_DEVICE *ei_local = netdev_priv(dev);
11451 +
11452 +       //Qwert
11453 +       /*
11454 +       unsigned long old,cur,dcycle;
11455 +       static int cnt = 0;
11456 +       static unsigned long max_dcycle = 0,tcycle = 0;
11457 +       old = read_c0_count();
11458 +       */
11459 +       if (dev == NULL)
11460 +       {
11461 +               printk (KERN_ERR "net_interrupt(): irq %x for unknown device.\n", IRQ_ENET0);
11462 +               return IRQ_NONE;
11463 +       }
11464 +
11465 +#ifdef CONFIG_RAETH_NAPI
11466 +       gsw_delay_setting();
11467 +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,35)
11468 +        if(napi_schedule_prep(&ei_local->napi)) {
11469 +#else
11470 +        if(netif_rx_schedule_prep(dev)) {
11471 +#endif
11472 +                atomic_inc(&ei_local->irq_sem);
11473 +               sysRegWrite(RAETH_FE_INT_ENABLE, 0);
11474 +#ifdef CONFIG_RAETH_QDMA
11475 +               sysRegWrite(QFE_INT_ENABLE, 0);
11476 +#endif
11477 +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,35)
11478 +               __napi_schedule(&ei_local->napi);
11479 +#else
11480 +                __netif_rx_schedule(dev);
11481 +#endif
11482 +        }
11483 +#else
11484 +
11485 +       spin_lock_irqsave(&(ei_local->page_lock), flags);
11486 +       reg_int_val = sysRegRead(RAETH_FE_INT_STATUS);
11487 +#ifdef CONFIG_RAETH_QDMA
11488 +       reg_int_val |= sysRegRead(QFE_INT_STATUS);
11489 +#endif
11490 +#if defined (DELAY_INT)
11491 +       if((reg_int_val & RX_DLY_INT))
11492 +               recv = 1;
11493 +
11494 +       if (reg_int_val & RAETH_TX_DLY_INT)
11495 +               transmit = 1;
11496 +
11497 +#if defined(CONFIG_RAETH_PDMA_DVT)
11498 +    raeth_pdma_lro_dly_int_dvt();
11499 +#endif  /* CONFIG_RAETH_PDMA_DVT */
11500 +
11501 +#else
11502 +       if((reg_int_val & (RX_DONE_INT0 | RX_DONE_INT3 | RX_DONE_INT2 | RX_DONE_INT1)))
11503 +               recv = 1;
11504 +
11505 +#if defined (CONFIG_RAETH_MULTIPLE_RX_RING)
11506 +#if defined(CONFIG_ARCH_MT7623)
11507 +    if((reg_int_val & RX_DONE_INT3))
11508 +        recv = 3;
11509 +    if((reg_int_val & RX_DONE_INT2))
11510 +        recv = 2;
11511 +#endif  /* CONFIG_ARCH_MT7623 */
11512 +       if((reg_int_val & RX_DONE_INT1))
11513 +               recv = 1;
11514 +#endif
11515 +
11516 +       if (reg_int_val & RAETH_TX_DONE_INT0)
11517 +               transmit |= RAETH_TX_DONE_INT0;
11518 +#if defined (CONFIG_RAETH_QOS)
11519 +       if (reg_int_val & TX_DONE_INT1)
11520 +               transmit |= TX_DONE_INT1;
11521 +       if (reg_int_val & TX_DONE_INT2)
11522 +               transmit |= TX_DONE_INT2;
11523 +       if (reg_int_val & TX_DONE_INT3)
11524 +               transmit |= TX_DONE_INT3;
11525 +#endif //CONFIG_RAETH_QOS
11526 +
11527 +#endif //DELAY_INT
11528 +
11529 +#if defined (DELAY_INT)
11530 +       sysRegWrite(RAETH_FE_INT_STATUS, RAETH_FE_INT_DLY_INIT);
11531 +#else
11532 +       sysRegWrite(RAETH_FE_INT_STATUS, RAETH_FE_INT_ALL);
11533 +#endif
11534 +#ifdef CONFIG_RAETH_QDMA
11535 +#if defined (DELAY_INT)
11536 +       sysRegWrite(QFE_INT_STATUS, QFE_INT_DLY_INIT);
11537 +#else
11538 +       sysRegWrite(QFE_INT_STATUS, QFE_INT_ALL);
11539 +#endif
11540 +#endif
11541 +
11542 +#if defined (CONFIG_RAETH_HW_LRO)
11543 +    if( reg_int_val & (ALT_RPLC_INT3 | ALT_RPLC_INT2 | ALT_RPLC_INT1) ){
11544 +        /* mask interrupts of rx flow to hw lor rings */
11545 +        reg_int_mask = sysRegRead(RAETH_FE_INT_ENABLE);
11546 +        sysRegWrite(RAETH_FE_INT_ENABLE, reg_int_mask & ~(ALT_RPLC_INT3 | ALT_RPLC_INT2 | ALT_RPLC_INT1));
11547 +        schedule_work(&ei_local->hw_lro_wq);
11548 +    }
11549 +#endif  /* CONFIG_RAETH_HW_LRO */
11550 +
11551 +#if LINUX_VERSION_CODE > KERNEL_VERSION(3,10,0)
11552 +       if(transmit)
11553 +               ei_xmit_housekeeping(0);
11554 +#else
11555 +               ei_xmit_housekeeping(0);
11556 +#endif
11557 +
11558 +       if (((recv == 1) || (pending_recv ==1)) && (tx_ring_full==0))
11559 +       {
11560 +               reg_int_mask = sysRegRead(RAETH_FE_INT_ENABLE);
11561 +#if defined (DELAY_INT)
11562 +               sysRegWrite(RAETH_FE_INT_ENABLE, reg_int_mask & ~(RX_DLY_INT));
11563 +#else
11564 +               sysRegWrite(RAETH_FE_INT_ENABLE, reg_int_mask & ~(RX_DONE_INT0 | RX_DONE_INT1 | RX_DONE_INT2 | RX_DONE_INT3));
11565 +#endif //DELAY_INT
11566 +#ifdef CONFIG_RAETH_QDMA
11567 +               reg_int_mask = sysRegRead(QFE_INT_ENABLE);
11568 +#if defined (DELAY_INT)
11569 +               sysRegWrite(QFE_INT_ENABLE, reg_int_mask & ~(RX_DLY_INT));
11570 +#else
11571 +               sysRegWrite(QFE_INT_ENABLE, reg_int_mask & ~(RX_DONE_INT0 | RX_DONE_INT1 | RX_DONE_INT2 | RX_DONE_INT3));
11572 +#endif //DELAY_INT
11573 +#endif
11574 +
11575 +               pending_recv=0;
11576 +#ifdef WORKQUEUE_BH
11577 +               schedule_work(&ei_local->rx_wq);
11578 +#else
11579 +#if defined (TASKLET_WORKQUEUE_SW)
11580 +               if (working_schedule == 1)
11581 +                       schedule_work(&ei_local->rx_wq);
11582 +               else
11583 +#endif
11584 +               tasklet_hi_schedule(&ei_local->rx_tasklet);
11585 +#endif // WORKQUEUE_BH //
11586 +       }
11587 +       else if (recv == 1 && tx_ring_full==1)
11588 +       {
11589 +               pending_recv=1;
11590 +       }
11591 +       else if((recv == 0) && (transmit == 0))
11592 +       {
11593 +               gsw_delay_setting();
11594 +       }
11595 +       spin_unlock_irqrestore(&(ei_local->page_lock), flags);
11596 +#endif
11597 +
11598 +       return IRQ_HANDLED;
11599 +}
11600 +
11601 +#if defined (CONFIG_RALINK_RT6855) || defined (CONFIG_RALINK_RT6855A) || \
11602 +    defined (CONFIG_RALINK_MT7620)|| defined (CONFIG_RALINK_MT7621)
11603 +static void esw_link_status_changed(int port_no, void *dev_id)
11604 +{
11605 +    unsigned int reg_val;
11606 +    struct net_device *dev = (struct net_device *) dev_id;
11607 +    END_DEVICE *ei_local = netdev_priv(dev);
11608 +
11609 +#if defined (CONFIG_RALINK_RT6855) || defined(CONFIG_RALINK_RT6855A) || \
11610 +    defined (CONFIG_RALINK_MT7620)
11611 +    reg_val = *((volatile u32 *)(RALINK_ETH_SW_BASE+ 0x3008 + (port_no*0x100)));
11612 +#elif defined (CONFIG_RALINK_MT7621)
11613 +    mii_mgr_read(31, (0x3008 + (port_no*0x100)), &reg_val);
11614 +#endif
11615 +    if(reg_val & 0x1) {
11616 +       printk("ESW: Link Status Changed - Port%d Link UP\n", port_no);
11617 +#if defined (CONFIG_RALINK_MT7621) && defined (CONFIG_RAETH_8023AZ_EEE)
11618 +       mii_mgr_write(port_no, 31, 0x52b5);
11619 +       mii_mgr_write(port_no, 16, 0xb780);
11620 +       mii_mgr_write(port_no, 17, 0x00e0);
11621 +       mii_mgr_write(port_no, 16, 0x9780);
11622 +#endif
11623 +
11624 +#if defined (CONFIG_WAN_AT_P0)
11625 +       if(port_no==0) {
11626 +           schedule_work(&ei_local->kill_sig_wq);
11627 +       }
11628 +#elif defined (CONFIG_WAN_AT_P4)
11629 +       if(port_no==4) {
11630 +           schedule_work(&ei_local->kill_sig_wq);
11631 +       }
11632 +#endif
11633 +    } else {
11634 +       printk("ESW: Link Status Changed - Port%d Link Down\n", port_no);
11635 +#if defined (CONFIG_RALINK_MT7621) && defined (CONFIG_RAETH_8023AZ_EEE)
11636 +        mii_mgr_write(port_no, 31, 0x52b5);
11637 +        mii_mgr_write(port_no, 16, 0xb780);
11638 +        mii_mgr_write(port_no, 17, 0x0000);
11639 +        mii_mgr_write(port_no, 16, 0x9780);
11640 +#endif
11641 +
11642 +    }
11643 +}
11644 +#endif
11645 +
11646 +#if defined (CONFIG_RT_3052_ESW) && ! defined(CONFIG_RALINK_MT7621) && ! defined(CONFIG_ARCH_MT7623)
11647 +static irqreturn_t esw_interrupt(int irq, void *dev_id)
11648 +{
11649 +       unsigned long flags;
11650 +       unsigned long reg_int_val;
11651 +#if defined (CONFIG_RALINK_RT6855) || defined(CONFIG_RALINK_RT6855A) || \
11652 +    defined(CONFIG_RALINK_MT7620)
11653 +       unsigned long acl_int_val;
11654 +       unsigned long mib_int_val;
11655 +#else
11656 +       static unsigned long stat;
11657 +       unsigned long stat_curr;
11658 +#endif
11659 +
11660 +       struct net_device *dev = (struct net_device *) dev_id;
11661 +       END_DEVICE *ei_local = netdev_priv(dev);
11662 +
11663 +
11664 +       spin_lock_irqsave(&(ei_local->page_lock), flags);
11665 +       reg_int_val = (*((volatile u32 *)(ESW_ISR))); //Interrupt Status Register
11666 +
11667 +#if defined (CONFIG_RALINK_RT6855) || defined(CONFIG_RALINK_RT6855A) || \
11668 +    defined(CONFIG_RALINK_MT7620)
11669 +       if (reg_int_val & P5_LINK_CH) {
11670 +           esw_link_status_changed(5, dev_id);
11671 +       }
11672 +       if (reg_int_val & P4_LINK_CH) {
11673 +           esw_link_status_changed(4, dev_id);
11674 +       }
11675 +       if (reg_int_val & P3_LINK_CH) {
11676 +           esw_link_status_changed(3, dev_id);
11677 +       }
11678 +       if (reg_int_val & P2_LINK_CH) {
11679 +           esw_link_status_changed(2, dev_id);
11680 +       }
11681 +       if (reg_int_val & P1_LINK_CH) {
11682 +           esw_link_status_changed(1, dev_id);
11683 +       }
11684 +       if (reg_int_val & P0_LINK_CH) {
11685 +           esw_link_status_changed(0, dev_id);
11686 +       }
11687 +       if (reg_int_val & ACL_INT) {
11688 +           acl_int_val = sysRegRead(ESW_AISR);
11689 +           sysRegWrite(ESW_AISR, acl_int_val);
11690 +       }
11691 +       if (reg_int_val & MIB_INT) {
11692 +
11693 +           mib_int_val = sysRegRead(ESW_P0_IntSn);
11694 +           if(mib_int_val){
11695 +               sysRegWrite(ESW_P0_IntSn, mib_int_val);
11696 +               if(mib_int_val & RX_GOOD_CNT)
11697 +                       p0_rx_good_cnt ++;
11698 +               if(mib_int_val & TX_GOOD_CNT)
11699 +                       p0_tx_good_cnt ++;
11700 +               if(mib_int_val & RX_GOCT_CNT)
11701 +                       p0_rx_byte_cnt ++;
11702 +               if(mib_int_val & TX_GOCT_CNT)
11703 +                       p0_tx_byte_cnt ++;
11704 +           }
11705 +
11706 +           mib_int_val = sysRegRead(ESW_P1_IntSn);
11707 +           if(mib_int_val){
11708 +               sysRegWrite(ESW_P1_IntSn, mib_int_val);
11709 +               if(mib_int_val & RX_GOOD_CNT)
11710 +                       p1_rx_good_cnt ++;
11711 +               if(mib_int_val & TX_GOOD_CNT)
11712 +                       p1_tx_good_cnt ++;
11713 +               if(mib_int_val & RX_GOCT_CNT)
11714 +                       p1_rx_byte_cnt ++;
11715 +               if(mib_int_val & TX_GOCT_CNT)
11716 +                       p1_tx_byte_cnt ++;
11717 +           }
11718 +
11719 +           mib_int_val = sysRegRead(ESW_P2_IntSn);
11720 +           if(mib_int_val){
11721 +               sysRegWrite(ESW_P2_IntSn, mib_int_val);
11722 +               if(mib_int_val & RX_GOOD_CNT)
11723 +                       p2_rx_good_cnt ++;
11724 +               if(mib_int_val & TX_GOOD_CNT)
11725 +                       p2_tx_good_cnt ++;
11726 +               if(mib_int_val & RX_GOCT_CNT)
11727 +                       p2_rx_byte_cnt ++;
11728 +               if(mib_int_val & TX_GOCT_CNT)
11729 +                       p2_tx_byte_cnt ++;
11730 +           }
11731 +
11732 +
11733 +           mib_int_val = sysRegRead(ESW_P3_IntSn);
11734 +           if(mib_int_val){
11735 +               sysRegWrite(ESW_P3_IntSn, mib_int_val);
11736 +               if(mib_int_val & RX_GOOD_CNT)
11737 +                       p3_rx_good_cnt ++;
11738 +               if(mib_int_val & TX_GOOD_CNT)
11739 +                       p3_tx_good_cnt ++;
11740 +               if(mib_int_val & RX_GOCT_CNT)
11741 +                       p3_rx_byte_cnt ++;
11742 +               if(mib_int_val & TX_GOCT_CNT)
11743 +                       p3_tx_byte_cnt ++;
11744 +           }
11745 +
11746 +           mib_int_val = sysRegRead(ESW_P4_IntSn);
11747 +           if(mib_int_val){
11748 +               sysRegWrite(ESW_P4_IntSn, mib_int_val);
11749 +               if(mib_int_val & RX_GOOD_CNT)
11750 +                       p4_rx_good_cnt ++;
11751 +               if(mib_int_val & TX_GOOD_CNT)
11752 +                       p4_tx_good_cnt ++;
11753 +               if(mib_int_val & RX_GOCT_CNT)
11754 +                       p4_rx_byte_cnt ++;
11755 +               if(mib_int_val & TX_GOCT_CNT)
11756 +                       p4_tx_byte_cnt ++;
11757 +           }
11758 +
11759 +           mib_int_val = sysRegRead(ESW_P5_IntSn);
11760 +           if(mib_int_val){
11761 +               sysRegWrite(ESW_P5_IntSn, mib_int_val);
11762 +               if(mib_int_val & RX_GOOD_CNT)
11763 +                       p5_rx_good_cnt ++;
11764 +               if(mib_int_val & TX_GOOD_CNT)
11765 +                       p5_tx_good_cnt ++;
11766 +               if(mib_int_val & RX_GOCT_CNT)
11767 +                       p5_rx_byte_cnt ++;
11768 +               if(mib_int_val & TX_GOCT_CNT)
11769 +                       p5_tx_byte_cnt ++;
11770 +           }
11771 +
11772 +           mib_int_val = sysRegRead(ESW_P6_IntSn);
11773 +           if(mib_int_val){
11774 +               sysRegWrite(ESW_P6_IntSn, mib_int_val);
11775 +               if(mib_int_val & RX_GOOD_CNT)
11776 +                       p6_rx_good_cnt ++;
11777 +               if(mib_int_val & TX_GOOD_CNT)
11778 +                       p6_tx_good_cnt ++;
11779 +               if(mib_int_val & RX_GOCT_CNT)
11780 +                       p6_rx_byte_cnt ++;
11781 +               if(mib_int_val & TX_GOCT_CNT)
11782 +                       p6_tx_byte_cnt ++;
11783 +           }
11784 +#if defined (CONFIG_RALINK_MT7620)
11785 +           mib_int_val = sysRegRead(ESW_P7_IntSn);
11786 +           if(mib_int_val){
11787 +               sysRegWrite(ESW_P7_IntSn, mib_int_val);
11788 +               if(mib_int_val & RX_GOOD_CNT)
11789 +                       p7_rx_good_cnt ++;
11790 +               if(mib_int_val & TX_GOOD_CNT)
11791 +                       p7_tx_good_cnt ++;
11792 +               if(mib_int_val & RX_GOCT_CNT)
11793 +                       p7_rx_byte_cnt ++;
11794 +               if(mib_int_val & TX_GOCT_CNT)
11795 +                       p7_tx_byte_cnt ++;
11796 +
11797 +           }
11798 +#endif
11799 +       }
11800 +
11801 +#else // not RT6855
11802 +       if (reg_int_val & PORT_ST_CHG) {
11803 +               printk("RT305x_ESW: Link Status Changed\n");
11804 +
11805 +               stat_curr = *((volatile u32 *)(RALINK_ETH_SW_BASE+0x80));
11806 +#ifdef CONFIG_WAN_AT_P0
11807 +               //link down --> link up : send signal to user application
11808 +               //link up --> link down : ignore
11809 +               if ((stat & (1<<25)) || !(stat_curr & (1<<25)))
11810 +#else
11811 +               if ((stat & (1<<29)) || !(stat_curr & (1<<29)))
11812 +#endif
11813 +                       goto out;
11814 +
11815 +               schedule_work(&ei_local->kill_sig_wq);
11816 +out:
11817 +               stat = stat_curr;
11818 +       }
11819 +
11820 +#endif // defined(CONFIG_RALINK_RT6855) || defined(CONFIG_RALINK_RT6855A)//
11821 +
11822 +       sysRegWrite(ESW_ISR, reg_int_val);
11823 +
11824 +       spin_unlock_irqrestore(&(ei_local->page_lock), flags);
11825 +       return IRQ_HANDLED;
11826 +}
11827 +
11828 +
11829 +
11830 +#elif defined (CONFIG_RT_3052_ESW) && defined(CONFIG_RALINK_MT7621)
11831 +
11832 +static irqreturn_t esw_interrupt(int irq, void *dev_id)
11833 +{
11834 +       unsigned long flags;
11835 +       unsigned int reg_int_val;
11836 +       struct net_device *dev = (struct net_device *) dev_id;
11837 +       END_DEVICE *ei_local = netdev_priv(dev);
11838 +
11839 +       spin_lock_irqsave(&(ei_local->page_lock), flags);
11840 +        mii_mgr_read(31, 0x700c, &reg_int_val);
11841 +
11842 +       if (reg_int_val & P4_LINK_CH) {
11843 +           esw_link_status_changed(4, dev_id);
11844 +       }
11845 +
11846 +       if (reg_int_val & P3_LINK_CH) {
11847 +           esw_link_status_changed(3, dev_id);
11848 +       }
11849 +       if (reg_int_val & P2_LINK_CH) {
11850 +           esw_link_status_changed(2, dev_id);
11851 +       }
11852 +       if (reg_int_val & P1_LINK_CH) {
11853 +           esw_link_status_changed(1, dev_id);
11854 +       }
11855 +       if (reg_int_val & P0_LINK_CH) {
11856 +           esw_link_status_changed(0, dev_id);
11857 +       }
11858 +
11859 +        mii_mgr_write(31, 0x700c, 0x1f); //ack switch link change
11860 +
11861 +       spin_unlock_irqrestore(&(ei_local->page_lock), flags);
11862 +       return IRQ_HANDLED;
11863 +}
11864 +
11865 +#endif
11866 +
11867 +
11868 +static int ei_start_xmit_fake(struct sk_buff* skb, struct net_device *dev)
11869 +{
11870 +       return ei_start_xmit(skb, dev, 1);
11871 +}
11872 +
11873 +
11874 +#if defined (CONFIG_RALINK_RT3052) || defined (CONFIG_RALINK_RT3352) || defined (CONFIG_RALINK_RT5350)
11875 +void dump_phy_reg(int port_no, int from, int to, int is_local)
11876 +{
11877 +        u32 i=0;
11878 +        u32 temp=0;
11879 +
11880 +        if(is_local==0) {
11881 +            printk("Global Register\n");
11882 +            printk("===============");
11883 +            mii_mgr_write(0, 31, 0); //select global register
11884 +            for(i=from;i<=to;i++) {
11885 +                if(i%8==0) {
11886 +                    printk("\n");
11887 +                }
11888 +                mii_mgr_read(port_no,i, &temp);
11889 +                printk("%02d: %04X ",i, temp);
11890 +            }
11891 +        } else {
11892 +            mii_mgr_write(0, 31, 0x8000); //select local register
11893 +                printk("\n\nLocal Register Port %d\n",port_no);
11894 +                printk("===============");
11895 +                for(i=from;i<=to;i++) {
11896 +                    if(i%8==0) {
11897 +                        printk("\n");
11898 +                    }
11899 +                    mii_mgr_read(port_no,i, &temp);
11900 +                    printk("%02d: %04X ",i, temp);
11901 +                }
11902 +        }
11903 +        printk("\n");
11904 +}
11905 +#else
11906 +void dump_phy_reg(int port_no, int from, int to, int is_local, int page_no)
11907 +{
11908 +
11909 +        u32 i=0;
11910 +        u32 temp=0;
11911 +        u32 r31=0;
11912 +
11913 +
11914 +        if(is_local==0) {
11915 +
11916 +            printk("\n\nGlobal Register Page %d\n",page_no);
11917 +            printk("===============");
11918 +            r31 |= 0 << 15; //global
11919 +            r31 |= ((page_no&0x7) << 12); //page no
11920 +            mii_mgr_write(port_no, 31, r31); //select global page x
11921 +            for(i=16;i<32;i++) {
11922 +                if(i%8==0) {
11923 +                    printk("\n");
11924 +                }
11925 +                mii_mgr_read(port_no,i, &temp);
11926 +                printk("%02d: %04X ",i, temp);
11927 +            }
11928 +        }else {
11929 +            printk("\n\nLocal Register Port %d Page %d\n",port_no, page_no);
11930 +            printk("===============");
11931 +            r31 |= 1 << 15; //local
11932 +            r31 |= ((page_no&0x7) << 12); //page no
11933 +            mii_mgr_write(port_no, 31, r31); //select local page x
11934 +            for(i=16;i<32;i++) {
11935 +                if(i%8==0) {
11936 +                    printk("\n");
11937 +                }
11938 +                mii_mgr_read(port_no,i, &temp);
11939 +                printk("%02d: %04X ",i, temp);
11940 +            }
11941 +        }
11942 +        printk("\n");
11943 +}
11944 +
11945 +#endif
11946 +
11947 +int ei_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
11948 +{
11949 +#if defined(CONFIG_RT_3052_ESW) || defined(CONFIG_RAETH_QDMA)
11950 +               esw_reg reg;
11951 +#endif
11952 +#if defined(CONFIG_RALINK_RT3352) || defined(CONFIG_RALINK_RT5350) || \
11953 +    defined (CONFIG_RALINK_RT6855) || defined(CONFIG_RALINK_RT6855A) || \
11954 +    defined(CONFIG_RALINK_MT7620) || defined(CONFIG_RALINK_MT7621) || \
11955 +    defined (CONFIG_RALINK_MT7628) || defined (CONFIG_ARCH_MT7623)
11956 +        esw_rate ratelimit;
11957 +#endif
11958 +#if defined(CONFIG_RT_3052_ESW)
11959 +       unsigned int offset = 0;
11960 +       unsigned int value = 0;
11961 +#endif
11962 +
11963 +       int ret = 0;
11964 +       END_DEVICE *ei_local = netdev_priv(dev);
11965 +       ra_mii_ioctl_data mii;
11966 +       spin_lock_irq(&ei_local->page_lock);
11967 +
11968 +       switch (cmd) {
11969 +#if defined(CONFIG_RAETH_QDMA)
11970 +#define _HQOS_REG(x)   (*((volatile u32 *)(RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + x)))
11971 +               case RAETH_QDMA_REG_READ:
11972 +                       copy_from_user(&reg, ifr->ifr_data, sizeof(reg));
11973 +                       if (reg.off > REG_HQOS_MAX) {
11974 +                               ret = -EINVAL;
11975 +                               break;
11976 +                       }
11977 +                       reg.val = _HQOS_REG(reg.off);
11978 +                       //printk("read reg off:%x val:%x\n", reg.off, reg.val);
11979 +                       copy_to_user(ifr->ifr_data, &reg, sizeof(reg));
11980 +                       break;
11981 +               case RAETH_QDMA_REG_WRITE:
11982 +                       copy_from_user(&reg, ifr->ifr_data, sizeof(reg));
11983 +                       if (reg.off > REG_HQOS_MAX) {
11984 +                               ret = -EINVAL;
11985 +                               break;
11986 +                       }
11987 +                       _HQOS_REG(reg.off) = reg.val;
11988 +                       //printk("write reg off:%x val:%x\n", reg.off, reg.val);
11989 +                       break;
11990 +#if 0
11991 +                case RAETH_QDMA_READ_CPU_CLK:
11992 +                        copy_from_user(&reg, ifr->ifr_data, sizeof(reg));
11993 +                        reg.val = get_surfboard_sysclk();
11994 +                        //printk("read reg off:%x val:%x\n", reg.off, reg.val);
11995 +                       copy_to_user(ifr->ifr_data, &reg, sizeof(reg));
11996 +                       break;
11997 +#endif
11998 +               case RAETH_QDMA_QUEUE_MAPPING:
11999 +                       copy_from_user(&reg, ifr->ifr_data, sizeof(reg));
12000 +                               if((reg.off&0x100) == 0x100){
12001 +                                       lan_wan_separate = 1;
12002 +                                       reg.off &= 0xff;
12003 +                               }else{
12004 +                                       lan_wan_separate = 0;
12005 +                               }
12006 +                       M2Q_table[reg.off] = reg.val;
12007 +               break;
12008 +#if defined(CONFIG_HW_SFQ)
12009 +      case RAETH_QDMA_SFQ_WEB_ENABLE:
12010 +                       copy_from_user(&reg, ifr->ifr_data, sizeof(reg));
12011 +                       if((reg.val) == 0x1){
12012 +                               web_sfq_enable = 1;
12013 +
12014 +                       }else{
12015 +                               web_sfq_enable = 0;
12016 +                       }
12017 +               break;
12018 +#endif
12019 +
12020 +
12021 +#endif
12022 +               case RAETH_MII_READ:
12023 +                       copy_from_user(&mii, ifr->ifr_data, sizeof(mii));
12024 +                       mii_mgr_read(mii.phy_id, mii.reg_num, &mii.val_out);
12025 +                       //printk("phy %d, reg %d, val 0x%x\n", mii.phy_id, mii.reg_num, mii.val_out);
12026 +                       copy_to_user(ifr->ifr_data, &mii, sizeof(mii));
12027 +                       break;
12028 +
12029 +               case RAETH_MII_WRITE:
12030 +                       copy_from_user(&mii, ifr->ifr_data, sizeof(mii));
12031 +                       //printk("phy %d, reg %d, val 0x%x\n", mii.phy_id, mii.reg_num, mii.val_in);
12032 +                       mii_mgr_write(mii.phy_id, mii.reg_num, mii.val_in);
12033 +                       break;
12034 +#if defined (CONFIG_RALINK_MT7621) || defined (CONFIG_RALINK_MT7620) || defined (CONFIG_ARCH_MT7623)
12035 +               case RAETH_MII_READ_CL45:
12036 +                       copy_from_user(&mii, ifr->ifr_data, sizeof(mii));
12037 +                       //mii_mgr_cl45_set_address(mii.port_num, mii.dev_addr, mii.reg_addr);
12038 +                       mii_mgr_read_cl45(mii.port_num, mii.dev_addr, mii.reg_addr, &mii.val_out);
12039 +                       copy_to_user(ifr->ifr_data, &mii, sizeof(mii));
12040 +                       break;
12041 +               case RAETH_MII_WRITE_CL45:
12042 +                       copy_from_user(&mii, ifr->ifr_data, sizeof(mii));
12043 +                       //mii_mgr_cl45_set_address(mii.port_num, mii.dev_addr, mii.reg_addr);
12044 +                       mii_mgr_write_cl45(mii.port_num, mii.dev_addr, mii.reg_addr, mii.val_in);
12045 +                       break;
12046 +#endif
12047 +
12048 +#if defined(CONFIG_RT_3052_ESW)
12049 +#define _ESW_REG(x)    (*((volatile u32 *)(RALINK_ETH_SW_BASE + x)))
12050 +               case RAETH_ESW_REG_READ:
12051 +                       copy_from_user(&reg, ifr->ifr_data, sizeof(reg));
12052 +                       if (reg.off > REG_ESW_MAX) {
12053 +                               ret = -EINVAL;
12054 +                               break;
12055 +                       }
12056 +                       reg.val = _ESW_REG(reg.off);
12057 +                       //printk("read reg off:%x val:%x\n", reg.off, reg.val);
12058 +                       copy_to_user(ifr->ifr_data, &reg, sizeof(reg));
12059 +                       break;
12060 +               case RAETH_ESW_REG_WRITE:
12061 +                       copy_from_user(&reg, ifr->ifr_data, sizeof(reg));
12062 +                       if (reg.off > REG_ESW_MAX) {
12063 +                               ret = -EINVAL;
12064 +                               break;
12065 +                       }
12066 +                       _ESW_REG(reg.off) = reg.val;
12067 +                       //printk("write reg off:%x val:%x\n", reg.off, reg.val);
12068 +                       break;
12069 +               case RAETH_ESW_PHY_DUMP:
12070 +                       copy_from_user(&reg, ifr->ifr_data, sizeof(reg));
12071 +#if defined (CONFIG_RALINK_RT3052) || defined (CONFIG_RALINK_RT3352) || defined (CONFIG_RALINK_RT5350)
12072 +                       if (reg.val ==32 ) {//dump all phy register
12073 +                           /* Global Register 0~31
12074 +                            * Local Register 0~31
12075 +                            */
12076 +                           dump_phy_reg(0, 0, 31, 0); //dump global register
12077 +                           for(offset=0;offset<5;offset++) {
12078 +                               dump_phy_reg(offset, 0, 31, 1); //dump local register
12079 +                           }
12080 +                       } else {
12081 +                           dump_phy_reg(reg.val, 0, 31, 0); //dump global register
12082 +                           dump_phy_reg(reg.val, 0, 31, 1); //dump local register
12083 +                       }
12084 +#else
12085 +                       /* SPEC defined Register 0~15
12086 +                        * Global Register 16~31 for each page
12087 +                        * Local Register 16~31 for each page
12088 +                        */
12089 +                       printk("SPEC defined Register");
12090 +                       if (reg.val ==32 ) {//dump all phy register
12091 +                           int i = 0;
12092 +                           for(i=0; i<5; i++){
12093 +                               printk("\n[Port %d]===============",i);
12094 +                               for(offset=0;offset<16;offset++) {
12095 +                                   if(offset%8==0) {
12096 +                                       printk("\n");
12097 +                               }
12098 +                               mii_mgr_read(i,offset, &value);
12099 +                               printk("%02d: %04X ",offset, value);
12100 +                               }
12101 +                           }
12102 +                       }
12103 +                       else{
12104 +                               printk("\n[Port %d]===============",reg.val);
12105 +                               for(offset=0;offset<16;offset++) {
12106 +                                   if(offset%8==0) {
12107 +                                       printk("\n");
12108 +                               }
12109 +                               mii_mgr_read(reg.val,offset, &value);
12110 +                               printk("%02d: %04X ",offset, value);
12111 +                               }
12112 +                       }
12113 +
12114 +#if defined (CONFIG_RALINK_MT7628)
12115 +                       for(offset=0;offset<7;offset++) { //global register  page 0~6
12116 +#else
12117 +                       for(offset=0;offset<5;offset++) { //global register  page 0~4
12118 +#endif
12119 +                           if(reg.val == 32) //dump all phy register
12120 +                               dump_phy_reg(0, 16, 31, 0, offset);
12121 +                           else
12122 +                               dump_phy_reg(reg.val, 16, 31, 0, offset);
12123 +                       }
12124 +
12125 +                       if (reg.val == 32) {//dump all phy register
12126 +#if !defined (CONFIG_RAETH_HAS_PORT4)
12127 +                               for(offset=0;offset<5;offset++) { //local register port 0-port4
12128 +#else
12129 +                               for(offset=0;offset<4;offset++) { //local register port 0-port3
12130 +#endif
12131 +                                       dump_phy_reg(offset, 16, 31, 1, 0); //dump local page 0
12132 +                                       dump_phy_reg(offset, 16, 31, 1, 1); //dump local page 1
12133 +                                       dump_phy_reg(offset, 16, 31, 1, 2); //dump local page 2
12134 +                                       dump_phy_reg(offset, 16, 31, 1, 3); //dump local page 3
12135 +                               }
12136 +                       }else {
12137 +                               dump_phy_reg(reg.val, 16, 31, 1, 0); //dump local page 0
12138 +                               dump_phy_reg(reg.val, 16, 31, 1, 1); //dump local page 1
12139 +                               dump_phy_reg(reg.val, 16, 31, 1, 2); //dump local page 2
12140 +                               dump_phy_reg(reg.val, 16, 31, 1, 3); //dump local page 3
12141 +                       }
12142 +#endif
12143 +                       break;
12144 +
12145 +#if defined (CONFIG_RALINK_RT3352) || defined (CONFIG_RALINK_RT5350) || defined (CONFIG_RALINK_MT7628)
12146 +#define _ESW_REG(x)    (*((volatile u32 *)(RALINK_ETH_SW_BASE + x)))
12147 +               case RAETH_ESW_INGRESS_RATE:
12148 +                       copy_from_user(&ratelimit, ifr->ifr_data, sizeof(ratelimit));
12149 +                       offset = 0x11c + (4 * (ratelimit.port / 2));
12150 +                        value = _ESW_REG(offset);
12151 +
12152 +                       if((ratelimit.port % 2) == 0)
12153 +                       {
12154 +                               value &= 0xffff0000;
12155 +                               if(ratelimit.on_off == 1)
12156 +                               {
12157 +                                       value |= (ratelimit.on_off << 14);
12158 +                                       value |= (0x07 << 10);
12159 +                                       value |= ratelimit.bw;
12160 +                               }
12161 +                       }
12162 +                       else if((ratelimit.port % 2) == 1)
12163 +                       {
12164 +                               value &= 0x0000ffff;
12165 +                               if(ratelimit.on_off == 1)
12166 +                               {
12167 +                                       value |= (ratelimit.on_off << 30);
12168 +                                       value |= (0x07 << 26);
12169 +                                       value |= (ratelimit.bw << 16);
12170 +                               }
12171 +                       }
12172 +                       printk("offset = 0x%4x value=0x%x\n\r", offset, value);
12173 +
12174 +                       _ESW_REG(offset) = value;
12175 +                       break;
12176 +
12177 +               case RAETH_ESW_EGRESS_RATE:
12178 +                       copy_from_user(&ratelimit, ifr->ifr_data, sizeof(ratelimit));
12179 +                       offset = 0x140 + (4 * (ratelimit.port / 2));
12180 +                        value = _ESW_REG(offset);
12181 +
12182 +                       if((ratelimit.port % 2) == 0)
12183 +                       {
12184 +                               value &= 0xffff0000;
12185 +                               if(ratelimit.on_off == 1)
12186 +                               {
12187 +                                       value |= (ratelimit.on_off << 12);
12188 +                                       value |= (0x03 << 10);
12189 +                                       value |= ratelimit.bw;
12190 +                               }
12191 +                       }
12192 +                       else if((ratelimit.port % 2) == 1)
12193 +                       {
12194 +                               value &= 0x0000ffff;
12195 +                               if(ratelimit.on_off == 1)
12196 +                               {
12197 +                                       value |= (ratelimit.on_off << 28);
12198 +                                       value |= (0x03 << 26);
12199 +                                       value |= (ratelimit.bw << 16);
12200 +                               }
12201 +                       }
12202 +                       printk("offset = 0x%4x value=0x%x\n\r", offset, value);
12203 +                       _ESW_REG(offset) = value;
12204 +                       break;
12205 +#elif  defined (CONFIG_RALINK_RT6855) || defined(CONFIG_RALINK_RT6855A) || \
12206 +       defined(CONFIG_RALINK_MT7620) || defined(CONFIG_RALINK_MT7621) || defined (CONFIG_ARCH_MT7623)
12207 +#define _ESW_REG(x)    (*((volatile u32 *)(RALINK_ETH_SW_BASE + x)))
12208 +               case RAETH_ESW_INGRESS_RATE:
12209 +                       copy_from_user(&ratelimit, ifr->ifr_data, sizeof(ratelimit));
12210 +#if defined(CONFIG_RALINK_RT6855A) || defined(CONFIG_RALINK_MT7621) || defined (CONFIG_ARCH_MT7623)
12211 +                       offset = 0x1800 + (0x100 * ratelimit.port);
12212 +#else
12213 +                       offset = 0x1080 + (0x100 * ratelimit.port);
12214 +#endif
12215 +                        value = _ESW_REG(offset);
12216 +
12217 +                       value &= 0xffff0000;
12218 +                       if(ratelimit.on_off == 1)
12219 +                       {
12220 +                               value |= (ratelimit.on_off << 15);
12221 +                               if (ratelimit.bw < 100)
12222 +                               {
12223 +                                       value |= (0x0 << 8);
12224 +                                       value |= ratelimit.bw;
12225 +                               }else if(ratelimit.bw < 1000)
12226 +                               {
12227 +                                       value |= (0x1 << 8);
12228 +                                       value |= ratelimit.bw/10;
12229 +                               }else if(ratelimit.bw < 10000)
12230 +                               {
12231 +                                       value |= (0x2 << 8);
12232 +                                       value |= ratelimit.bw/100;
12233 +                               }else if(ratelimit.bw < 100000)
12234 +                               {
12235 +                                       value |= (0x3 << 8);
12236 +                                       value |= ratelimit.bw/1000;
12237 +                               }else
12238 +                               {
12239 +                                       value |= (0x4 << 8);
12240 +                                       value |= ratelimit.bw/10000;
12241 +                               }
12242 +                       }
12243 +                       printk("offset = 0x%4x value=0x%x\n\r", offset, value);
12244 +#if defined (CONFIG_RALINK_MT7621) || defined (CONFIG_ARCH_MT7623)
12245 +                       mii_mgr_write(0x1f, offset, value);
12246 +#else
12247 +                       _ESW_REG(offset) = value;
12248 +#endif
12249 +                       break;
12250 +
12251 +               case RAETH_ESW_EGRESS_RATE:
12252 +                       copy_from_user(&ratelimit, ifr->ifr_data, sizeof(ratelimit));
12253 +                       offset = 0x1040 + (0x100 * ratelimit.port);
12254 +                        value = _ESW_REG(offset);
12255 +
12256 +                       value &= 0xffff0000;
12257 +                       if(ratelimit.on_off == 1)
12258 +                       {
12259 +                               value |= (ratelimit.on_off << 15);
12260 +                               if (ratelimit.bw < 100)
12261 +                               {
12262 +                                       value |= (0x0 << 8);
12263 +                                       value |= ratelimit.bw;
12264 +                               }else if(ratelimit.bw < 1000)
12265 +                               {
12266 +                                       value |= (0x1 << 8);
12267 +                                       value |= ratelimit.bw/10;
12268 +                               }else if(ratelimit.bw < 10000)
12269 +                               {
12270 +                                       value |= (0x2 << 8);
12271 +                                       value |= ratelimit.bw/100;
12272 +                               }else if(ratelimit.bw < 100000)
12273 +                               {
12274 +                                       value |= (0x3 << 8);
12275 +                                       value |= ratelimit.bw/1000;
12276 +                               }else
12277 +                               {
12278 +                                       value |= (0x4 << 8);
12279 +                                       value |= ratelimit.bw/10000;
12280 +                               }
12281 +                       }
12282 +                       printk("offset = 0x%4x value=0x%x\n\r", offset, value);
12283 +#if defined (CONFIG_RALINK_MT7621) || defined (CONFIG_ARCH_MT7623)
12284 +                       mii_mgr_write(0x1f, offset, value);
12285 +#else
12286 +                       _ESW_REG(offset) = value;
12287 +#endif
12288 +                       break;
12289 +#endif
12290 +#endif // CONFIG_RT_3052_ESW
12291 +               default:
12292 +                       ret = -EOPNOTSUPP;
12293 +                       break;
12294 +
12295 +       }
12296 +
12297 +       spin_unlock_irq(&ei_local->page_lock);
12298 +       return ret;
12299 +}
12300 +
12301 +/*
12302 + * Set new MTU size
12303 + * Change the mtu of Raeth Ethernet Device
12304 + */
12305 +static int ei_change_mtu(struct net_device *dev, int new_mtu)
12306 +{
12307 +       END_DEVICE *ei_local = netdev_priv(dev);  // get priv ei_local pointer from net_dev structure
12308 +
12309 +       if ( ei_local == NULL ) {
12310 +               printk(KERN_EMERG "%s: ei_change_mtu passed a non-existent private pointer from net_dev!\n", dev->name);
12311 +               return -ENXIO;
12312 +       }
12313 +
12314 +
12315 +       if ( (new_mtu > 4096) || (new_mtu < 64)) {
12316 +               return -EINVAL;
12317 +       }
12318 +
12319 +#ifndef CONFIG_RAETH_JUMBOFRAME
12320 +       if ( new_mtu > 1500 ) {
12321 +               return -EINVAL;
12322 +       }
12323 +#endif
12324 +
12325 +       dev->mtu = new_mtu;
12326 +
12327 +       return 0;
12328 +}
12329 +
12330 +#ifdef CONFIG_RAETH_HW_VLAN_RX
12331 +static void ei_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
12332 +{
12333 +       END_DEVICE *ei_local = netdev_priv(dev);
12334 +
12335 +       ei_local->vlgrp = grp;
12336 +
12337 +       /* enable HW VLAN RX */
12338 +       sysRegWrite(CDMP_EG_CTRL, 1);
12339 +
12340 +}
12341 +#endif
12342 +
12343 +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,35)
12344 +static const struct net_device_ops ei_netdev_ops = {
12345 +        .ndo_init               = rather_probe,
12346 +        .ndo_open               = ei_open,
12347 +        .ndo_stop               = ei_close,
12348 +        .ndo_start_xmit         = ei_start_xmit_fake,
12349 +        .ndo_get_stats          = ra_get_stats,
12350 +        .ndo_set_mac_address    = eth_mac_addr,
12351 +        .ndo_change_mtu         = ei_change_mtu,
12352 +        .ndo_do_ioctl           = ei_ioctl,
12353 +        .ndo_validate_addr      = eth_validate_addr,
12354 +#ifdef CONFIG_RAETH_HW_VLAN_RX
12355 +       .ndo_vlan_rx_register   = ei_vlan_rx_register,
12356 +#endif
12357 +#ifdef CONFIG_NET_POLL_CONTROLLER
12358 +        .ndo_poll_controller    = raeth_clean,
12359 +#endif
12360 +//     .ndo_tx_timeout         = ei_tx_timeout,
12361 +};
12362 +#endif
12363 +
12364 +void ra2880_setup_dev_fptable(struct net_device *dev)
12365 +{
12366 +       RAETH_PRINT(__FUNCTION__ "is called!\n");
12367 +
12368 +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,35)
12369 +       dev->netdev_ops         = &ei_netdev_ops;
12370 +#else
12371 +       dev->open               = ei_open;
12372 +       dev->stop               = ei_close;
12373 +       dev->hard_start_xmit    = ei_start_xmit_fake;
12374 +       dev->get_stats          = ra_get_stats;
12375 +       dev->set_mac_address    = ei_set_mac_addr;
12376 +       dev->change_mtu         = ei_change_mtu;
12377 +       dev->mtu                = 1500;
12378 +       dev->do_ioctl           = ei_ioctl;
12379 +//     dev->tx_timeout         = ei_tx_timeout;
12380 +
12381 +#ifdef CONFIG_RAETH_NAPI
12382 +        dev->poll = &raeth_clean;
12383 +#if defined (CONFIG_RAETH_ROUTER)
12384 +       dev->weight = 32;
12385 +#elif defined (CONFIG_RT_3052_ESW)
12386 +       dev->weight = 32;
12387 +#else
12388 +       dev->weight = 128;
12389 +#endif
12390 +#endif
12391 +#endif
12392 +#if defined (CONFIG_ETHTOOL) /*&& defined (CONFIG_RAETH_ROUTER)*/
12393 +       dev->ethtool_ops        = &ra_ethtool_ops;
12394 +#endif
12395 +#define TX_TIMEOUT (5*HZ)
12396 +       dev->watchdog_timeo = TX_TIMEOUT;
12397 +
12398 +}
12399 +
12400 +/* reset frame engine */
12401 +void fe_reset(void)
12402 +{
12403 +#if defined (CONFIG_RALINK_RT6855A)
12404 +       /* FIXME */
12405 +#else
12406 +       u32 val;
12407 +
12408 +       //val = *(volatile u32 *)(0x1b000000);
12409 +       //printk("0x1b000000 is 0x%x\n", val);
12410 +       //val = sysRegRead(0xFB110100);
12411 +       //val = 0x8000;
12412 +       //sysRegWrite(0xFB110100, val);
12413 +
12414 +
12415 +
12416 +       val = sysRegRead(RSTCTRL);
12417 +
12418 +// RT5350 need to reset ESW and FE at the same to avoid PDMA panic //
12419 +#if defined (CONFIG_RALINK_RT5350) || defined (CONFIG_RALINK_MT7628)
12420 +       val = val | RALINK_FE_RST | RALINK_ESW_RST ;
12421 +#else
12422 +       val = val | RALINK_FE_RST;
12423 +#endif
12424 +       sysRegWrite(RSTCTRL, val);
12425 +#if defined (CONFIG_RALINK_RT5350) || defined (CONFIG_RALINK_MT7620) || defined (CONFIG_RALINK_MT7628)
12426 +       val = val & ~(RALINK_FE_RST | RALINK_ESW_RST);
12427 +#else
12428 +       val = val & ~(RALINK_FE_RST);
12429 +#endif
12430 +
12431 +       sysRegWrite(RSTCTRL, val);
12432 +#endif
12433 +}
12434 +
12435 +/* set TRGMII */
12436 +#if defined (CONFIG_GE1_TRGMII_FORCE_1200) && defined (CONFIG_MT7621_ASIC)
12437 +void trgmii_set_7621(void)
12438 +{
12439 +       u32 val = 0;
12440 +       u32 val_0 = 0;
12441 +
12442 +       val = sysRegRead(RSTCTRL);
12443 +// MT7621 need to reset GMAC and FE first //
12444 +       val = val | RALINK_FE_RST | RALINK_ETH_RST ;
12445 +       sysRegWrite(RSTCTRL, val);
12446 +
12447 +//set TRGMII clock//
12448 +       val_0 = sysRegRead(CLK_CFG_0);
12449 +       val_0 &= 0xffffff9f;
12450 +       val_0 |= (0x1 << 5);
12451 +       sysRegWrite(CLK_CFG_0, val_0);
12452 +       mdelay(1);
12453 +       val_0 = sysRegRead(CLK_CFG_0);
12454 +       printk("set CLK_CFG_0 = 0x%x!!!!!!!!!!!!!!!!!!1\n",val_0);
12455 +       val = val & ~(RALINK_FE_RST | RALINK_ETH_RST);
12456 +       sysRegWrite(RSTCTRL, val);
12457 +}
12458 +
12459 +void trgmii_set_7530(void)
12460 +{
12461 +// set MT7530 //
12462 +#if 0
12463 +
12464 +       mii_mgr_write(31, 103, 0x0020);
12465 +
12466 +
12467 +       //disable EEE
12468 +       mii_mgr_write(0, 0x16, 0);
12469 +       mii_mgr_write(1, 0x16, 0);
12470 +       mii_mgr_write(2, 0x16, 0);
12471 +       mii_mgr_write(3, 0x16, 0);
12472 +       mii_mgr_write(4, 0x16, 0);
12473 +
12474 +
12475 +       //PLL reset for E2
12476 +       mii_mgr_write(31, 104, 0x0608);
12477 +       mii_mgr_write(31, 104, 0x2608);
12478 +
12479 +       mii_mgr_write(31, 0x7808, 0x0);
12480 +       mdelay(1);
12481 +       mii_mgr_write(31, 0x7804, 0x01017e8f);
12482 +       mdelay(1);
12483 +       mii_mgr_write(31, 0x7808, 0x1);
12484 +       mdelay(1);
12485 +
12486 +#endif
12487 +#if 1
12488 +       //CL45 command
12489 +       //PLL to 150Mhz
12490 +       mii_mgr_write(0, 13, 0x1f);
12491 +       mii_mgr_write(0, 14, 0x404);
12492 +       mii_mgr_write(0, 13, 0x401f);
12493 +       mii_mgr_read(31, 0x7800, &regValue);
12494 +       regValue = (regValue >> 9) & 0x3;
12495 +       if(regValue == 0x3) { //25Mhz Xtal
12496 +               mii_mgr_write(0, 14, 0x0A00);//25Mhz XTAL for 150Mhz CLK
12497 +       } else if(regValue == 0x2) { //40Mhz
12498 +               mii_mgr_write(0, 14, 0x0780);//40Mhz XTAL for 150Mhz CLK
12499 +       }
12500 +       //mii_mgr_write(0, 14, 0x0C00);//ori
12501 +       mdelay(1);
12502 +
12503 +       mii_mgr_write(0, 13, 0x1f);
12504 +       mii_mgr_write(0, 14, 0x409);
12505 +       mii_mgr_write(0, 13, 0x401f);
12506 +       mii_mgr_write(0, 14, 0x57);
12507 +       mdelay(1);
12508 +
12509 +       mii_mgr_write(0, 13, 0x1f);
12510 +       mii_mgr_write(0, 14, 0x40a);
12511 +       mii_mgr_write(0, 13, 0x401f);
12512 +       mii_mgr_write(0, 14, 0x57);
12513 +
12514 +//PLL BIAS en
12515 +       mii_mgr_write(0, 13, 0x1f);
12516 +       mii_mgr_write(0, 14, 0x403);
12517 +       mii_mgr_write(0, 13, 0x401f);
12518 +       mii_mgr_write(0, 14, 0x1800);
12519 +       mdelay(1);
12520 +
12521 +//BIAS LPF en
12522 +       mii_mgr_write(0, 13, 0x1f);
12523 +       mii_mgr_write(0, 14, 0x403);
12524 +       mii_mgr_write(0, 13, 0x401f);
12525 +       mii_mgr_write(0, 14, 0x1c00);
12526 +
12527 +//sys PLL en
12528 +       mii_mgr_write(0, 13, 0x1f);
12529 +       mii_mgr_write(0, 14, 0x401);
12530 +       mii_mgr_write(0, 13, 0x401f);
12531 +       mii_mgr_write(0, 14, 0xc020);
12532 +
12533 +//LCDDDS PWDS
12534 +       mii_mgr_write(0, 13, 0x1f);
12535 +       mii_mgr_write(0, 14, 0x406);
12536 +       mii_mgr_write(0, 13, 0x401f);
12537 +       mii_mgr_write(0, 14, 0xa030);
12538 +       mdelay(1);
12539 +
12540 +//GSW_2X_CLK
12541 +       mii_mgr_write(0, 13, 0x1f);
12542 +       mii_mgr_write(0, 14, 0x410);
12543 +       mii_mgr_write(0, 13, 0x401f);
12544 +       mii_mgr_write(0, 14, 0x0003);
12545 +
12546 +//enable P6
12547 +       mii_mgr_write(31, 0x3600, 0x5e33b);
12548 +
12549 +//enable TRGMII
12550 +       mii_mgr_write(31, 0x7830, 0x1);
12551 +#endif
12552 +
12553 +}
12554 +#endif
12555 +
12556 +void ei_reset_task(struct work_struct *work)
12557 +{
12558 +       struct net_device *dev = dev_raether;
12559 +
12560 +       ei_close(dev);
12561 +       ei_open(dev);
12562 +
12563 +       return;
12564 +}
12565 +
12566 +void ei_tx_timeout(struct net_device *dev)
12567 +{
12568 +        END_DEVICE *ei_local = netdev_priv(dev);
12569 +
12570 +        schedule_work(&ei_local->reset_task);
12571 +}
12572 +
12573 +void setup_statistics(END_DEVICE* ei_local)
12574 +{
12575 +       ei_local->stat.tx_packets       = 0;
12576 +       ei_local->stat.tx_bytes         = 0;
12577 +       ei_local->stat.tx_dropped       = 0;
12578 +       ei_local->stat.tx_errors        = 0;
12579 +       ei_local->stat.tx_aborted_errors= 0;
12580 +       ei_local->stat.tx_carrier_errors= 0;
12581 +       ei_local->stat.tx_fifo_errors   = 0;
12582 +       ei_local->stat.tx_heartbeat_errors = 0;
12583 +       ei_local->stat.tx_window_errors = 0;
12584 +
12585 +       ei_local->stat.rx_packets       = 0;
12586 +       ei_local->stat.rx_bytes         = 0;
12587 +       ei_local->stat.rx_dropped       = 0;
12588 +       ei_local->stat.rx_errors        = 0;
12589 +       ei_local->stat.rx_length_errors = 0;
12590 +       ei_local->stat.rx_over_errors   = 0;
12591 +       ei_local->stat.rx_crc_errors    = 0;
12592 +       ei_local->stat.rx_frame_errors  = 0;
12593 +       ei_local->stat.rx_fifo_errors   = 0;
12594 +       ei_local->stat.rx_missed_errors = 0;
12595 +
12596 +       ei_local->stat.collisions       = 0;
12597 +#if defined (CONFIG_RAETH_QOS)
12598 +       ei_local->tx3_full = 0;
12599 +       ei_local->tx2_full = 0;
12600 +       ei_local->tx1_full = 0;
12601 +       ei_local->tx0_full = 0;
12602 +#else
12603 +       ei_local->tx_full = 0;
12604 +#endif
12605 +#ifdef CONFIG_RAETH_NAPI
12606 +       atomic_set(&ei_local->irq_sem, 1);
12607 +#endif
12608 +
12609 +}
12610 +
12611 +/**
12612 + * rather_probe - pick up ethernet port at boot time
12613 + * @dev: network device to probe
12614 + *
12615 + * This routine probe the ethernet port at boot time.
12616 + *
12617 + *
12618 + */
12619 +
12620 +int __init rather_probe(struct net_device *dev)
12621 +{
12622 +       int i;
12623 +       END_DEVICE *ei_local = netdev_priv(dev);
12624 +       struct sockaddr addr;
12625 +       unsigned char zero1[6]={0xFF,0xFF,0xFF,0xFF,0xFF,0xFF};
12626 +       unsigned char zero2[6]={0x00,0x00,0x00,0x00,0x00,0x00};
12627 +
12628 +       fe_reset();
12629 +
12630 +       //Get mac0 address from flash
12631 +#ifdef RA_MTD_RW_BY_NUM
12632 +       i = ra_mtd_read(2, GMAC0_OFFSET, 6, addr.sa_data);
12633 +#else
12634 +       i = ra_mtd_read_nm("Factory", GMAC0_OFFSET, 6, addr.sa_data);
12635 +#endif
12636 +       //If reading mtd failed or mac0 is empty, generate a mac address
12637 +       if (i < 0 || ((memcmp(addr.sa_data, zero1, 6) == 0) || (addr.sa_data[0] & 0x1)) ||
12638 +           (memcmp(addr.sa_data, zero2, 6) == 0)) {
12639 +               unsigned char mac_addr01234[5] = {0x00, 0x0C, 0x43, 0x28, 0x80};
12640 +       //      net_srandom(jiffies);
12641 +               memcpy(addr.sa_data, mac_addr01234, 5);
12642 +       //      addr.sa_data[5] = net_random()&0xFF;
12643 +       }
12644 +
12645 +#ifdef CONFIG_RAETH_NAPI
12646 +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,35)
12647 +       netif_napi_add(dev, &ei_local->napi, raeth_clean, 128);
12648 +#endif
12649 +#endif
12650 +       ei_set_mac_addr(dev, &addr);
12651 +       spin_lock_init(&ei_local->page_lock);
12652 +       ether_setup(dev);
12653 +
12654 +#ifdef CONFIG_RAETH_LRO
12655 +       ei_local->lro_mgr.dev = dev;
12656 +        memset(&ei_local->lro_mgr.stats, 0, sizeof(ei_local->lro_mgr.stats));
12657 +        ei_local->lro_mgr.features = LRO_F_NAPI;
12658 +        ei_local->lro_mgr.ip_summed = CHECKSUM_UNNECESSARY;
12659 +        ei_local->lro_mgr.ip_summed_aggr = CHECKSUM_UNNECESSARY;
12660 +        ei_local->lro_mgr.max_desc = ARRAY_SIZE(ei_local->lro_arr);
12661 +        ei_local->lro_mgr.max_aggr = 64;
12662 +        ei_local->lro_mgr.frag_align_pad = 0;
12663 +        ei_local->lro_mgr.lro_arr = ei_local->lro_arr;
12664 +        ei_local->lro_mgr.get_skb_header = rt_get_skb_header;
12665 +#endif
12666 +
12667 +       setup_statistics(ei_local);
12668 +
12669 +       return 0;
12670 +}
12671 +
12672 +#ifdef CONFIG_PSEUDO_SUPPORT
12673 +int VirtualIF_ioctl(struct net_device * net_dev,
12674 +                   struct ifreq * ifr, int cmd)
12675 +{
12676 +       ra_mii_ioctl_data mii;
12677 +
12678 +       switch (cmd) {
12679 +               case RAETH_MII_READ:
12680 +                       copy_from_user(&mii, ifr->ifr_data, sizeof(mii));
12681 +                       mii_mgr_read(mii.phy_id, mii.reg_num, &mii.val_out);
12682 +                       //printk("phy %d, reg %d, val 0x%x\n", mii.phy_id, mii.reg_num, mii.val_out);
12683 +                       copy_to_user(ifr->ifr_data, &mii, sizeof(mii));
12684 +                       break;
12685 +
12686 +               case RAETH_MII_WRITE:
12687 +                       copy_from_user(&mii, ifr->ifr_data, sizeof(mii));
12688 +                       //printk("phy %d, reg %d, val 0x%x\n", mii.phy_id, mii.reg_num, mii.val_in);
12689 +                       mii_mgr_write(mii.phy_id, mii.reg_num, mii.val_in);
12690 +                       break;
12691 +               default:
12692 +                       return -EOPNOTSUPP;
12693 +       }
12694 +
12695 +       return 0;
12696 +}
12697 +
12698 +struct net_device_stats *VirtualIF_get_stats(struct net_device *dev)
12699 +{
12700 +       PSEUDO_ADAPTER *pAd = netdev_priv(dev);
12701 +       return &pAd->stat;
12702 +}
12703 +
12704 +int VirtualIF_open(struct net_device * dev)
12705 +{
12706 +    PSEUDO_ADAPTER *pPesueoAd = netdev_priv(dev);
12707 +
12708 +    printk("%s: ===> VirtualIF_open\n", dev->name);
12709 +
12710 +#if defined (CONFIG_GE_RGMII_INTERNAL_P0_AN) || defined (CONFIG_GE_RGMII_INTERNAL_P4_AN)
12711 +    *((volatile u32 *)(FE_INT_ENABLE2)) |= (1<<25); //enable GE2 link change intr for MT7530 delay setting
12712 +#endif
12713 +
12714 +    netif_start_queue(pPesueoAd->PseudoDev);
12715 +
12716 +    return 0;
12717 +}
12718 +
12719 +int VirtualIF_close(struct net_device * dev)
12720 +{
12721 +    PSEUDO_ADAPTER *pPesueoAd = netdev_priv(dev);
12722 +
12723 +    printk("%s: ===> VirtualIF_close\n", dev->name);
12724 +
12725 +    netif_stop_queue(pPesueoAd->PseudoDev);
12726 +
12727 +    return 0;
12728 +}
12729 +
12730 +int VirtualIFSendPackets(struct sk_buff * pSkb,
12731 +                        struct net_device * dev)
12732 +{
12733 +    PSEUDO_ADAPTER *pPesueoAd = netdev_priv(dev);
12734 +    END_DEVICE *ei_local __maybe_unused;
12735 +
12736 +
12737 +    //printk("VirtualIFSendPackets --->\n");
12738 +
12739 +    ei_local = netdev_priv(dev);
12740 +    if (!(pPesueoAd->RaethDev->flags & IFF_UP)) {
12741 +       dev_kfree_skb_any(pSkb);
12742 +       return 0;
12743 +    }
12744 +    //pSkb->cb[40]=0x5a;
12745 +    pSkb->dev = pPesueoAd->RaethDev;
12746 +    ei_start_xmit(pSkb, pPesueoAd->RaethDev, 2);
12747 +    return 0;
12748 +}
12749 +
12750 +void virtif_setup_statistics(PSEUDO_ADAPTER* pAd)
12751 +{
12752 +       pAd->stat.tx_packets    = 0;
12753 +       pAd->stat.tx_bytes      = 0;
12754 +       pAd->stat.tx_dropped    = 0;
12755 +       pAd->stat.tx_errors     = 0;
12756 +       pAd->stat.tx_aborted_errors= 0;
12757 +       pAd->stat.tx_carrier_errors= 0;
12758 +       pAd->stat.tx_fifo_errors        = 0;
12759 +       pAd->stat.tx_heartbeat_errors = 0;
12760 +       pAd->stat.tx_window_errors      = 0;
12761 +
12762 +       pAd->stat.rx_packets    = 0;
12763 +       pAd->stat.rx_bytes      = 0;
12764 +       pAd->stat.rx_dropped    = 0;
12765 +       pAd->stat.rx_errors     = 0;
12766 +       pAd->stat.rx_length_errors = 0;
12767 +       pAd->stat.rx_over_errors        = 0;
12768 +       pAd->stat.rx_crc_errors = 0;
12769 +       pAd->stat.rx_frame_errors       = 0;
12770 +       pAd->stat.rx_fifo_errors        = 0;
12771 +       pAd->stat.rx_missed_errors      = 0;
12772 +
12773 +       pAd->stat.collisions    = 0;
12774 +}
12775 +
12776 +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,35)
12777 +static const struct net_device_ops VirtualIF_netdev_ops = {
12778 +        .ndo_open               = VirtualIF_open,
12779 +        .ndo_stop               = VirtualIF_close,
12780 +        .ndo_start_xmit         = VirtualIFSendPackets,
12781 +        .ndo_get_stats          = VirtualIF_get_stats,
12782 +        .ndo_set_mac_address    = ei_set_mac2_addr,
12783 +        .ndo_change_mtu         = ei_change_mtu,
12784 +        .ndo_do_ioctl           = VirtualIF_ioctl,
12785 +        .ndo_validate_addr      = eth_validate_addr,
12786 +};
12787 +#endif
12788 +// Register pseudo interface
12789 +void RAETH_Init_PSEUDO(pEND_DEVICE pAd, struct net_device *net_dev)
12790 +{
12791 +    int index;
12792 +    struct net_device *dev;
12793 +    PSEUDO_ADAPTER *pPseudoAd;
12794 +    int i = 0;
12795 +    struct sockaddr addr;
12796 +    unsigned char zero1[6]={0xFF,0xFF,0xFF,0xFF,0xFF,0xFF};
12797 +    unsigned char zero2[6]={0x00,0x00,0x00,0x00,0x00,0x00};
12798 +
12799 +    for (index = 0; index < MAX_PSEUDO_ENTRY; index++) {
12800 +
12801 +       dev = alloc_etherdev(sizeof(PSEUDO_ADAPTER));
12802 +       if (NULL == dev)
12803 +       {
12804 +               printk(" alloc_etherdev for PSEUDO_ADAPTER failed.\n");
12805 +               return;
12806 +       }
12807 +       strcpy(dev->name, DEV2_NAME);
12808 +
12809 +       //Get mac2 address from flash
12810 +#ifdef RA_MTD_RW_BY_NUM
12811 +       i = ra_mtd_read(2, GMAC2_OFFSET, 6, addr.sa_data);
12812 +#else
12813 +       i = ra_mtd_read_nm("Factory", GMAC2_OFFSET, 6, addr.sa_data);
12814 +#endif
12815 +
12816 +       //If reading mtd failed or mac0 is empty, generate a mac address
12817 +       if (i < 0 || ((memcmp(addr.sa_data, zero1, 6) == 0) || (addr.sa_data[0] & 0x1)) ||
12818 +           (memcmp(addr.sa_data, zero2, 6) == 0)) {
12819 +               unsigned char mac_addr01234[5] = {0x00, 0x0C, 0x43, 0x28, 0x80};
12820 +       //      net_srandom(jiffies);
12821 +               memcpy(addr.sa_data, mac_addr01234, 5);
12822 +       //      addr.sa_data[5] = net_random()&0xFF;
12823 +       }
12824 +
12825 +       ei_set_mac2_addr(dev, &addr);
12826 +       ether_setup(dev);
12827 +       pPseudoAd = netdev_priv(dev);
12828 +
12829 +       pPseudoAd->PseudoDev = dev;
12830 +       pPseudoAd->RaethDev = net_dev;
12831 +       virtif_setup_statistics(pPseudoAd);
12832 +       pAd->PseudoDev = dev;
12833 +
12834 +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,35)
12835 +       dev->netdev_ops         = &VirtualIF_netdev_ops;
12836 +#else
12837 +       dev->hard_start_xmit = VirtualIFSendPackets;
12838 +       dev->stop = VirtualIF_close;
12839 +       dev->open = VirtualIF_open;
12840 +       dev->do_ioctl = VirtualIF_ioctl;
12841 +       dev->set_mac_address = ei_set_mac2_addr;
12842 +       dev->get_stats = VirtualIF_get_stats;
12843 +       dev->change_mtu = ei_change_mtu;
12844 +       dev->mtu = 1500;
12845 +#endif
12846 +
12847 +#if defined (CONFIG_RAETH_HW_LRO)
12848 +    dev->features |= NETIF_F_HW_CSUM;
12849 +#else
12850 +       dev->features |= NETIF_F_IP_CSUM; /* Can checksum TCP/UDP over IPv4 */
12851 +#endif  /* CONFIG_RAETH_HW_LRO */
12852 +
12853 +#if defined(CONFIG_RALINK_MT7620)
12854 +#if defined (CONFIG_RAETH_TSO)
12855 +       if ((sysRegRead(0xB000000C) & 0xf) >= 0x5) {
12856 +               dev->features |= NETIF_F_SG;
12857 +               dev->features |= NETIF_F_TSO;
12858 +       }
12859 +#endif // CONFIG_RAETH_TSO //
12860 +
12861 +#if defined (CONFIG_RAETH_TSOV6)
12862 +       if ((sysRegRead(0xB000000C) & 0xf) >= 0x5) {
12863 +               dev->features |= NETIF_F_TSO6;
12864 +               dev->features |= NETIF_F_IPV6_CSUM; /* Can checksum TCP/UDP over IPv6 */
12865 +       }
12866 +#endif
12867 +#else
12868 +#if defined (CONFIG_RAETH_TSO)
12869 +        dev->features |= NETIF_F_SG;
12870 +        dev->features |= NETIF_F_TSO;
12871 +#endif // CONFIG_RAETH_TSO //
12872 +
12873 +#if defined (CONFIG_RAETH_TSOV6)
12874 +        dev->features |= NETIF_F_TSO6;
12875 +        dev->features |= NETIF_F_IPV6_CSUM; /* Can checksum TCP/UDP over IPv6 */
12876 +#endif
12877 +#endif // CONFIG_RALINK_MT7620 //
12878 +
12879 +#if LINUX_VERSION_CODE > KERNEL_VERSION(3,10,0)
12880 +       dev->vlan_features = dev->features;
12881 +#endif
12882 +
12883 +
12884 +#if defined (CONFIG_ETHTOOL) /*&& defined (CONFIG_RAETH_ROUTER)*/
12885 +       dev->ethtool_ops = &ra_virt_ethtool_ops;
12886 +    // init mii structure
12887 +       pPseudoAd->mii_info.dev = dev;
12888 +       pPseudoAd->mii_info.mdio_read = mdio_virt_read;
12889 +       pPseudoAd->mii_info.mdio_write = mdio_virt_write;
12890 +       pPseudoAd->mii_info.phy_id_mask = 0x1f;
12891 +       pPseudoAd->mii_info.reg_num_mask = 0x1f;
12892 +       pPseudoAd->mii_info.phy_id = 0x1e;
12893 +       pPseudoAd->mii_info.supports_gmii = mii_check_gmii_support(&pPseudoAd->mii_info);
12894 +#endif
12895 +
12896 +       // Register this device
12897 +       register_netdevice(dev);
12898 +    }
12899 +}
12900 +#endif
12901 +
12902 +/**
12903 + * ei_open - Open/Initialize the ethernet port.
12904 + * @dev: network device to initialize
12905 + *
12906 + * This routine goes all-out, setting everything
12907 + * up a new at each open, even though many of these registers should only need to be set once at boot.
12908 + */
12909 +int ei_open(struct net_device *dev)
12910 +{
12911 +       int i, err;
12912 +#if !defined (CONFIG_MT7623_FPGA)
12913 +       unsigned long flags;
12914 +#endif
12915 +       END_DEVICE *ei_local;
12916 +
12917 +#ifdef CONFIG_RAETH_LRO
12918 +       const char *lan_ip_tmp;
12919 +#ifdef CONFIG_DUAL_IMAGE
12920 +#define RT2860_NVRAM   1
12921 +#else
12922 +#define RT2860_NVRAM   0
12923 +#endif
12924 +#endif // CONFIG_RAETH_LRO //
12925 +
12926 +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,5,0)
12927 +       if (!try_module_get(THIS_MODULE))
12928 +       {
12929 +               printk("%s: Cannot reserve module\n", __FUNCTION__);
12930 +               return -1;
12931 +       }
12932 +#else
12933 +       MOD_INC_USE_COUNT;
12934 +#endif
12935 +
12936 +       printk("Raeth %s (",RAETH_VERSION);
12937 +#if defined (CONFIG_RAETH_NAPI)
12938 +       printk("NAPI\n");
12939 +#elif defined (CONFIG_RA_NETWORK_TASKLET_BH)
12940 +       printk("Tasklet");
12941 +#elif defined (CONFIG_RA_NETWORK_WORKQUEUE_BH)
12942 +       printk("Workqueue");
12943 +#endif
12944 +
12945 +#if defined (CONFIG_RAETH_SKB_RECYCLE_2K)
12946 +       printk(",SkbRecycle");
12947 +#endif
12948 +       printk(")\n");
12949 +
12950 +
12951 +       ei_local = netdev_priv(dev); // get device pointer from System
12952 +       // unsigned int flags;
12953 +
12954 +       if (ei_local == NULL)
12955 +       {
12956 +               printk(KERN_EMERG "%s: ei_open passed a non-existent device!\n", dev->name);
12957 +               return -ENXIO;
12958 +       }
12959 +
12960 +        /* receiving packet buffer allocation - NUM_RX_DESC x MAX_RX_LENGTH */
12961 +        for ( i = 0; i < NUM_RX_DESC; i++)
12962 +        {
12963 +#if defined (CONFIG_RAETH_SKB_RECYCLE_2K)
12964 +                ei_local->netrx0_skbuf[i] = skbmgr_dev_alloc_skb2k();
12965 +#else
12966 +                ei_local->netrx0_skbuf[i] = dev_alloc_skb(MAX_RX_LENGTH + NET_IP_ALIGN);
12967 +#endif
12968 +                if (ei_local->netrx0_skbuf[i] == NULL ) {
12969 +                        printk("rx skbuff buffer allocation failed!");
12970 +               } else {
12971 +#if !defined (CONFIG_RAETH_SCATTER_GATHER_RX_DMA)
12972 +                   skb_reserve(ei_local->netrx0_skbuf[i], NET_IP_ALIGN);
12973 +#endif
12974 +               }
12975 +
12976 +
12977 +#if defined (CONFIG_RAETH_HW_LRO)
12978 +               ei_local->netrx3_skbuf[i] = dev_alloc_skb(MAX_LRO_RX_LENGTH + NET_IP_ALIGN);
12979 +        if (ei_local->netrx3_skbuf[i] == NULL ) {
12980 +            printk("rx3 skbuff buffer allocation failed!");
12981 +               } else {
12982 +#if !defined (CONFIG_RAETH_SCATTER_GATHER_RX_DMA)
12983 +                   skb_reserve(ei_local->netrx3_skbuf[i], NET_IP_ALIGN);
12984 +#endif
12985 +               }
12986 +               ei_local->netrx2_skbuf[i] = dev_alloc_skb(MAX_LRO_RX_LENGTH + NET_IP_ALIGN);
12987 +        if (ei_local->netrx2_skbuf[i] == NULL ) {
12988 +            printk("rx2 skbuff buffer allocation failed!");
12989 +               } else {
12990 +#if !defined (CONFIG_RAETH_SCATTER_GATHER_RX_DMA)
12991 +                   skb_reserve(ei_local->netrx2_skbuf[i], NET_IP_ALIGN);
12992 +#endif
12993 +               }
12994 +               ei_local->netrx1_skbuf[i] = dev_alloc_skb(MAX_LRO_RX_LENGTH + NET_IP_ALIGN);
12995 +        if (ei_local->netrx1_skbuf[i] == NULL ) {
12996 +            printk("rx1 skbuff buffer allocation failed!");
12997 +               } else {
12998 +#if !defined (CONFIG_RAETH_SCATTER_GATHER_RX_DMA)
12999 +                   skb_reserve(ei_local->netrx1_skbuf[i], NET_IP_ALIGN);
13000 +#endif
13001 +               }
13002 +#elif defined (CONFIG_RAETH_MULTIPLE_RX_RING)
13003 +#if defined(CONFIG_ARCH_MT7623)
13004 +               ei_local->netrx3_skbuf[i] = dev_alloc_skb(MAX_RX_LENGTH + NET_IP_ALIGN);
13005 +        if (ei_local->netrx3_skbuf[i] == NULL ) {
13006 +            printk("rx3 skbuff buffer allocation failed!");
13007 +               } else {
13008 +#if !defined (CONFIG_RAETH_SCATTER_GATHER_RX_DMA)
13009 +                   skb_reserve(ei_local->netrx3_skbuf[i], NET_IP_ALIGN);
13010 +#endif
13011 +               }
13012 +               ei_local->netrx2_skbuf[i] = dev_alloc_skb(MAX_RX_LENGTH + NET_IP_ALIGN);
13013 +        if (ei_local->netrx2_skbuf[i] == NULL ) {
13014 +            printk("rx2 skbuff buffer allocation failed!");
13015 +               } else {
13016 +#if !defined (CONFIG_RAETH_SCATTER_GATHER_RX_DMA)
13017 +                   skb_reserve(ei_local->netrx2_skbuf[i], NET_IP_ALIGN);
13018 +#endif
13019 +               }
13020 +#endif  /* CONFIG_ARCH_MT7623 */
13021 +               ei_local->netrx1_skbuf[i] = dev_alloc_skb(MAX_RX_LENGTH + NET_IP_ALIGN);
13022 +                if (ei_local->netrx1_skbuf[i] == NULL ) {
13023 +                        printk("rx1 skbuff buffer allocation failed!");
13024 +               } else {
13025 +#if !defined (CONFIG_RAETH_SCATTER_GATHER_RX_DMA)
13026 +                   skb_reserve(ei_local->netrx1_skbuf[i], NET_IP_ALIGN);
13027 +#endif
13028 +               }
13029 +#endif
13030 +        }
13031 +#if defined (CONFIG_GE1_TRGMII_FORCE_1200) && defined (CONFIG_MT7621_ASIC)
13032 +       trgmii_set_7621(); //reset FE/GMAC in this function
13033 +#endif
13034 +
13035 +        fe_dma_init(dev);
13036 +
13037 +#if defined (CONFIG_RAETH_HW_LRO)
13038 +    fe_hw_lro_init(dev);
13039 +#endif  /* CONFIG_RAETH_HW_LRO */
13040 +
13041 +       fe_sw_init(); //initialize fe and switch register
13042 +#if defined (CONFIG_MIPS)
13043 +       err = request_irq( dev->irq, ei_interrupt, IRQF_DISABLED, dev->name, dev);      // try to fix irq in open
13044 +#else
13045 +       err = request_irq(dev->irq, ei_interrupt, /*IRQF_TRIGGER_LOW*/ 0, dev->name, dev);      // try to fix irq in open
13046 +#endif
13047 +       if (err)
13048 +           return err;
13049 +
13050 +       if ( dev->dev_addr != NULL) {
13051 +           ra2880MacAddressSet((void *)(dev->dev_addr));
13052 +       } else {
13053 +           printk("dev->dev_addr is empty !\n");
13054 +       }
13055 +/*TODO: MT7623 MCM INT */
13056 +#if defined (CONFIG_RT_3052_ESW) && !defined(CONFIG_ARCH_MT7623)
13057 +       err = request_irq(SURFBOARDINT_ESW, esw_interrupt, IRQF_DISABLED, "Ralink_ESW", dev);
13058 +       if (err)
13059 +               return err;
13060 +       INIT_WORK(&ei_local->kill_sig_wq, kill_sig_workq);
13061 +#if defined (CONFIG_RALINK_MT7621)
13062 +        mii_mgr_write(31, 0x7008, 0x1f); //enable switch link change intr
13063 +
13064 +#else
13065 +       *((volatile u32 *)(RALINK_INTCL_BASE + 0x34)) = (1<<17);
13066 +       *((volatile u32 *)(ESW_IMR)) &= ~(ESW_INT_ALL);
13067 +
13068 +#if defined (CONFIG_RALINK_RT6855) || defined (CONFIG_RALINK_RT6855A) || \
13069 +    defined (CONFIG_RALINK_MT7620)
13070 +       *((volatile u32 *)(ESW_P0_IntMn)) &= ~(MSK_CNT_INT_ALL);
13071 +       *((volatile u32 *)(ESW_P1_IntMn)) &= ~(MSK_CNT_INT_ALL);
13072 +       *((volatile u32 *)(ESW_P2_IntMn)) &= ~(MSK_CNT_INT_ALL);
13073 +       *((volatile u32 *)(ESW_P3_IntMn)) &= ~(MSK_CNT_INT_ALL);
13074 +       *((volatile u32 *)(ESW_P4_IntMn)) &= ~(MSK_CNT_INT_ALL);
13075 +       *((volatile u32 *)(ESW_P5_IntMn)) &= ~(MSK_CNT_INT_ALL);
13076 +       *((volatile u32 *)(ESW_P6_IntMn)) &= ~(MSK_CNT_INT_ALL);
13077 +#endif
13078 +#if defined(CONFIG_RALINK_MT7620)
13079 +       *((volatile u32 *)(ESW_P7_IntMn)) &= ~(MSK_CNT_INT_ALL);
13080 +#endif
13081 +
13082 +#endif
13083 +#endif // CONFIG_RT_3052_ESW //
13084 +
13085 +/*TODO*/
13086 +#if !defined (CONFIG_MT7623_FPGA)
13087 +        spin_lock_irqsave(&(ei_local->page_lock), flags);
13088 +#endif
13089 +
13090 +
13091 +#ifdef DELAY_INT
13092 +        sysRegWrite(RAETH_DLY_INT_CFG, DELAY_INT_INIT);
13093 +       sysRegWrite(RAETH_FE_INT_ENABLE, RAETH_FE_INT_DLY_INIT);
13094 +    #if defined (CONFIG_RAETH_HW_LRO)
13095 +        sysRegWrite(RAETH_FE_INT_ENABLE, RAETH_FE_INT_DLY_INIT | ALT_RPLC_INT3 | ALT_RPLC_INT2 | ALT_RPLC_INT1);
13096 +    #endif  /* CONFIG_RAETH_HW_LRO */
13097 +#else
13098 +       sysRegWrite(RAETH_FE_INT_ENABLE, RAETH_FE_INT_ALL);
13099 +    #if defined (CONFIG_RAETH_HW_LRO)
13100 +        sysRegWrite(RAETH_FE_INT_ENABLE, RAETH_FE_INT_ALL | ALT_RPLC_INT3 | ALT_RPLC_INT2 | ALT_RPLC_INT1);
13101 +    #endif  /* CONFIG_RAETH_HW_LRO */
13102 +#endif
13103 +
13104 +#ifdef CONFIG_RAETH_QDMA
13105 +#ifdef DELAY_INT
13106 +        sysRegWrite(QDMA_DELAY_INT, DELAY_INT_INIT);
13107 +       sysRegWrite(QFE_INT_ENABLE, QFE_INT_DLY_INIT);
13108 +#else
13109 +       sysRegWrite(QFE_INT_ENABLE, QFE_INT_ALL);
13110 +
13111 +#endif
13112 +#endif
13113 +
13114 +       INIT_WORK(&ei_local->reset_task, ei_reset_task);
13115 +
13116 +#ifdef WORKQUEUE_BH
13117 +#ifndef CONFIG_RAETH_NAPI
13118 +       INIT_WORK(&ei_local->rx_wq, ei_receive_workq);
13119 +#endif // CONFIG_RAETH_NAPI //
13120 +#else
13121 +#ifndef CONFIG_RAETH_NAPI
13122 +#if defined (TASKLET_WORKQUEUE_SW)
13123 +       working_schedule = init_schedule;
13124 +       INIT_WORK(&ei_local->rx_wq, ei_receive_workq);
13125 +       tasklet_init(&ei_local->rx_tasklet, ei_receive_workq, 0);
13126 +#else
13127 +       tasklet_init(&ei_local->rx_tasklet, ei_receive, 0);
13128 +#endif
13129 +#endif // CONFIG_RAETH_NAPI //
13130 +#endif // WORKQUEUE_BH //
13131 +
13132 +       netif_start_queue(dev);
13133 +
13134 +#ifdef CONFIG_RAETH_NAPI
13135 +       atomic_dec(&ei_local->irq_sem);
13136 +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,35)
13137 +        napi_enable(&ei_local->napi);
13138 +#else
13139 +        netif_poll_enable(dev);
13140 +#endif
13141 +#endif
13142 +//*TODO*/
13143 +#if !defined (CONFIG_MT7623_FPGA)
13144 +       spin_unlock_irqrestore(&(ei_local->page_lock), flags);
13145 +#endif
13146 +
13147 +#ifdef CONFIG_PSEUDO_SUPPORT
13148 +       if(ei_local->PseudoDev == NULL) {
13149 +           RAETH_Init_PSEUDO(ei_local, dev);
13150 +       }
13151 +
13152 +       if(ei_local->PseudoDev == NULL)
13153 +               printk("Open PseudoDev failed.\n");
13154 +       else
13155 +               VirtualIF_open(ei_local->PseudoDev);
13156 +
13157 +#endif
13158 +
13159 +#ifdef CONFIG_RAETH_LRO
13160 +       lan_ip_tmp = nvram_get(RT2860_NVRAM, "lan_ipaddr");
13161 +       str_to_ip(&lan_ip, lan_ip_tmp);
13162 +       lro_para.lan_ip1 = lan_ip = htonl(lan_ip);
13163 +#endif // CONFIG_RAETH_LRO //
13164 +
13165 +#if defined (CONFIG_RAETH_HW_LRO)
13166 +    INIT_WORK(&ei_local->hw_lro_wq, ei_hw_lro_workq);
13167 +#endif  /* CONFIG_RAETH_HW_LRO */
13168 +
13169 +       forward_config(dev);
13170 +       return 0;
13171 +}
13172 +
13173 +/**
13174 + * ei_close - shut down network device
13175 + * @dev: network device to clear
13176 + *
13177 + * This routine shut down network device.
13178 + *
13179 + *
13180 + */
13181 +int ei_close(struct net_device *dev)
13182 +{
13183 +       int i;
13184 +       END_DEVICE *ei_local = netdev_priv(dev);        // device pointer
13185 +
13186 +       netif_stop_queue(dev);
13187 +        ra2880stop(ei_local);
13188 +
13189 +       free_irq(dev->irq, dev);
13190 +
13191 +/*TODO: MT7623 MCM INT */
13192 +#if defined (CONFIG_RT_3052_ESW) && !defined(CONFIG_ARCH_MT7623)
13193 +       free_irq(SURFBOARDINT_ESW, dev);
13194 +#endif
13195 +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,35)
13196 +       cancel_work_sync(&ei_local->reset_task);
13197 +#endif
13198 +
13199 +#ifdef CONFIG_PSEUDO_SUPPORT
13200 +       VirtualIF_close(ei_local->PseudoDev);
13201 +#endif
13202 +
13203 +
13204 +#ifdef WORKQUEUE_BH
13205 +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,35)
13206 +       cancel_work_sync(&ei_local->rx_wq);
13207 +#endif
13208 +#else
13209 +#if defined (TASKLET_WORKQUEUE_SW)
13210 +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,35)
13211 +       cancel_work_sync(&ei_local->rx_wq);
13212 +#endif
13213 +#endif
13214 +       tasklet_kill(&ei_local->tx_tasklet);
13215 +       tasklet_kill(&ei_local->rx_tasklet);
13216 +#endif // WORKQUEUE_BH //
13217 +
13218 +#ifdef CONFIG_RAETH_NAPI
13219 +       atomic_inc(&ei_local->irq_sem);
13220 +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,35)
13221 +        napi_disable(&ei_local->napi);
13222 +#else
13223 +        netif_poll_disable(dev);
13224 +#endif
13225 +#endif
13226 +
13227 +
13228 +#if defined (CONFIG_RAETH_HW_LRO)
13229 +    cancel_work_sync(&ei_local->hw_lro_wq);
13230 +#endif  /* CONFIG_RAETH_HW_LRO */
13231 +
13232 +        for ( i = 0; i < NUM_RX_DESC; i++)
13233 +        {
13234 +                if (ei_local->netrx0_skbuf[i] != NULL) {
13235 +                        dev_kfree_skb(ei_local->netrx0_skbuf[i]);
13236 +                       ei_local->netrx0_skbuf[i] = NULL;
13237 +               }
13238 +#if defined (CONFIG_RAETH_HW_LRO)
13239 +                if (ei_local->netrx3_skbuf[i] != NULL) {
13240 +                        dev_kfree_skb(ei_local->netrx3_skbuf[i]);
13241 +                       ei_local->netrx3_skbuf[i] = NULL;
13242 +               }
13243 +                if (ei_local->netrx2_skbuf[i] != NULL) {
13244 +                        dev_kfree_skb(ei_local->netrx2_skbuf[i]);
13245 +                       ei_local->netrx2_skbuf[i] = NULL;
13246 +               }
13247 +                if (ei_local->netrx1_skbuf[i] != NULL) {
13248 +                        dev_kfree_skb(ei_local->netrx1_skbuf[i]);
13249 +                       ei_local->netrx1_skbuf[i] = NULL;
13250 +               }
13251 +#elif defined (CONFIG_RAETH_MULTIPLE_RX_RING)
13252 +#if defined(CONFIG_ARCH_MT7623)
13253 +                if (ei_local->netrx3_skbuf[i] != NULL) {
13254 +                        dev_kfree_skb(ei_local->netrx3_skbuf[i]);
13255 +                       ei_local->netrx3_skbuf[i] = NULL;
13256 +               }
13257 +                if (ei_local->netrx2_skbuf[i] != NULL) {
13258 +                        dev_kfree_skb(ei_local->netrx2_skbuf[i]);
13259 +                       ei_local->netrx2_skbuf[i] = NULL;
13260 +               }
13261 +#endif  /* CONFIG_ARCH_MT7623 */
13262 +                if (ei_local->netrx1_skbuf[i] != NULL) {
13263 +                        dev_kfree_skb(ei_local->netrx1_skbuf[i]);
13264 +                       ei_local->netrx1_skbuf[i] = NULL;
13265 +               }
13266 +#endif
13267 +        }
13268 +
13269 +       for ( i = 0; i < NUM_TX_DESC; i++)
13270 +       {
13271 +               if((ei_local->skb_free[i]!=(struct  sk_buff *)0xFFFFFFFF) && (ei_local->skb_free[i]!= 0))
13272 +               {
13273 +                       dev_kfree_skb_any(ei_local->skb_free[i]);
13274 +               }
13275 +       }
13276 +
13277 +       /* TX Ring */
13278 +#ifdef CONFIG_RAETH_QDMA
13279 +       if (ei_local->txd_pool != NULL) {
13280 +          pci_free_consistent(NULL, NUM_TX_DESC*sizeof(struct QDMA_txdesc), ei_local->txd_pool, ei_local->phy_txd_pool);
13281 +       }
13282 +       if (ei_local->free_head != NULL){
13283 +              pci_free_consistent(NULL, NUM_QDMA_PAGE * sizeof(struct QDMA_txdesc), ei_local->free_head, ei_local->phy_free_head);
13284 +       }
13285 +       if (ei_local->free_page_head != NULL){
13286 +              pci_free_consistent(NULL, NUM_QDMA_PAGE * QDMA_PAGE_SIZE, ei_local->free_page_head, ei_local->phy_free_page_head);
13287 +       }
13288 +#else
13289 +       if (ei_local->tx_ring0 != NULL) {
13290 +          pci_free_consistent(NULL, NUM_TX_DESC*sizeof(struct PDMA_txdesc), ei_local->tx_ring0, ei_local->phy_tx_ring0);
13291 +       }
13292 +#endif
13293 +
13294 +#if defined (CONFIG_RAETH_QOS)
13295 +       if (ei_local->tx_ring1 != NULL) {
13296 +          pci_free_consistent(NULL, NUM_TX_DESC*sizeof(struct PDMA_txdesc), ei_local->tx_ring1, ei_local->phy_tx_ring1);
13297 +       }
13298 +
13299 +#if !defined (CONFIG_RALINK_RT2880)
13300 +       if (ei_local->tx_ring2 != NULL) {
13301 +          pci_free_consistent(NULL, NUM_TX_DESC*sizeof(struct PDMA_txdesc), ei_local->tx_ring2, ei_local->phy_tx_ring2);
13302 +       }
13303 +
13304 +       if (ei_local->tx_ring3 != NULL) {
13305 +          pci_free_consistent(NULL, NUM_TX_DESC*sizeof(struct PDMA_txdesc), ei_local->tx_ring3, ei_local->phy_tx_ring3);
13306 +       }
13307 +#endif
13308 +#endif
13309 +       /* RX Ring */
13310 +#ifdef CONFIG_32B_DESC
13311 +       kfree(ei_local->rx_ring0);
13312 +#else
13313 +        pci_free_consistent(NULL, NUM_RX_DESC*sizeof(struct PDMA_rxdesc), ei_local->rx_ring0, ei_local->phy_rx_ring0);
13314 +#endif
13315 +#if defined CONFIG_RAETH_QDMA && !defined(CONFIG_RAETH_QDMATX_QDMARX)
13316 +#ifdef CONFIG_32B_DESC
13317 +       kfree(ei_local->qrx_ring);
13318 +#else
13319 +       pci_free_consistent(NULL, NUM_QRX_DESC*sizeof(struct PDMA_rxdesc), ei_local->qrx_ring, ei_local->phy_qrx_ring);
13320 +#endif
13321 +#endif
13322 +#if defined (CONFIG_RAETH_HW_LRO)
13323 +        pci_free_consistent(NULL, NUM_LRO_RX_DESC*sizeof(struct PDMA_rxdesc), ei_local->rx_ring3, ei_local->phy_rx_ring3);
13324 +        pci_free_consistent(NULL, NUM_LRO_RX_DESC*sizeof(struct PDMA_rxdesc), ei_local->rx_ring2, ei_local->phy_rx_ring2);
13325 +        pci_free_consistent(NULL, NUM_LRO_RX_DESC*sizeof(struct PDMA_rxdesc), ei_local->rx_ring1, ei_local->phy_rx_ring1);
13326 +#elif defined (CONFIG_RAETH_MULTIPLE_RX_RING)
13327 +#ifdef CONFIG_32B_DESC
13328 +       kfree(ei_local->rx_ring1);
13329 +#else
13330 +#if defined(CONFIG_ARCH_MT7623)
13331 +        pci_free_consistent(NULL, NUM_RX_DESC*sizeof(struct PDMA_rxdesc), ei_local->rx_ring3, ei_local->phy_rx_ring3);
13332 +        pci_free_consistent(NULL, NUM_RX_DESC*sizeof(struct PDMA_rxdesc), ei_local->rx_ring2, ei_local->phy_rx_ring2);
13333 +#endif  /* CONFIG_ARCH_MT7623 */
13334 +        pci_free_consistent(NULL, NUM_RX_DESC*sizeof(struct PDMA_rxdesc), ei_local->rx_ring1, ei_local->phy_rx_ring1);
13335 +#endif
13336 +#endif
13337 +
13338 +       printk("Free TX/RX Ring Memory!\n");
13339 +
13340 +       fe_reset();
13341 +
13342 +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,5,0)
13343 +       module_put(THIS_MODULE);
13344 +#else
13345 +       MOD_DEC_USE_COUNT;
13346 +#endif
13347 +       return 0;
13348 +}
13349 +
13350 +#if defined (CONFIG_RT6855A_FPGA)
13351 +void rt6855A_eth_gpio_reset(void)
13352 +{
13353 +       u8 ether_gpio = 12;
13354 +
13355 +       /* Load the ethernet gpio value to reset Ethernet PHY */
13356 +       *(unsigned long *)(RALINK_PIO_BASE + 0x00) |= 1<<(ether_gpio<<1);
13357 +       *(unsigned long *)(RALINK_PIO_BASE + 0x14) |= 1<<(ether_gpio);
13358 +       *(unsigned long *)(RALINK_PIO_BASE + 0x04) &= ~(1<<ether_gpio);
13359 +
13360 +       udelay(100000);
13361 +
13362 +       *(unsigned long *)(RALINK_PIO_BASE + 0x04) |= (1<<ether_gpio);
13363 +
13364 +       /* must wait for 0.6 seconds after reset*/
13365 +       udelay(600000);
13366 +}
13367 +#endif
13368 +
13369 +#if defined(CONFIG_RALINK_RT6855A)
13370 +void rt6855A_gsw_init(void)
13371 +{
13372 +       u32 phy_val=0;
13373 +       u32 rev=0;
13374 +
13375 +#if defined (CONFIG_RT6855A_FPGA)
13376 +    /*keep dump switch mode */
13377 +    rt6855A_eth_gpio_reset();
13378 +
13379 +    *(unsigned long *)(RALINK_ETH_SW_BASE+0x3000) = 0x5e353;//(P0,Force mode,Link Up,100Mbps,Full-Duplex,FC ON)
13380 +    *(unsigned long *)(RALINK_ETH_SW_BASE+0x3100) = 0x5e353;//(P1,Force mode,Link Up,100Mbps,Full-Duplex,FC ON)
13381 +    //*(unsigned long *)(RALINK_ETH_SW_BASE+0x3000) = 0x5e333;//(P0,Force mode,Link Up,10Mbps,Full-Duplex,FC ON)
13382 +    //*(unsigned long *)(RALINK_ETH_SW_BASE+0x3100) = 0x5e333;//(P1,Force mode,Link Up,10Mbps,Full-Duplex,FC ON)
13383 +    *(unsigned long *)(RALINK_ETH_SW_BASE+0x3200) = 0x8000;//link down
13384 +    *(unsigned long *)(RALINK_ETH_SW_BASE+0x3300) = 0x8000;//link down
13385 +    *(unsigned long *)(RALINK_ETH_SW_BASE+0x3400) = 0x8000;//link down
13386 +    *(unsigned long *)(RALINK_ETH_SW_BASE+0x3500) = 0x8000;//link down
13387 +    *(unsigned long *)(RALINK_ETH_SW_BASE+0x3600) = 0x5e33b;//CPU Port6 Force Link 1G, FC ON
13388 +
13389 +    *(unsigned long *)(RALINK_ETH_SW_BASE+0x0010) = 0xffffffe0;//Set Port6 CPU Port
13390 +
13391 +    /* In order to use 10M/Full on FPGA board. We configure phy capable to
13392 +     * 10M Full/Half duplex, so we can use auto-negotiation on PC side */
13393 +    for(i=6;i<8;i++){
13394 +       mii_mgr_write(i, 4, 0x07e1);   //Capable of 10M&100M Full/Half Duplex, flow control on/off
13395 +       //mii_mgr_write(i, 4, 0x0461);   //Capable of 10M Full/Half Duplex, flow control on/off
13396 +       mii_mgr_write(i, 0, 0xB100);   //reset all digital logic, except phy_reg
13397 +       mii_mgr_read(i, 9, &phy_val);
13398 +       phy_val &= ~(3<<8); //turn off 1000Base-T Advertisement  (9.9=1000Full, 9.8=1000Half)
13399 +       mii_mgr_write(i, 9, phy_val);
13400 +    }
13401 +#elif defined (CONFIG_RT6855A_ASIC)
13402 +    *(unsigned long *)(RALINK_ETH_SW_BASE+0x3600) = 0x5e33b;//CPU Port6 Force Link 1G, FC ON
13403 +    *(unsigned long *)(RALINK_ETH_SW_BASE+0x0010) = 0xffffffe0;//Set Port6 CPU Port
13404 +
13405 +    *(unsigned long *)(RALINK_FRAME_ENGINE_BASE+0x1ec) = 0x0fffffff;//Set PSE should pause 4 tx ring as default
13406 +    *(unsigned long *)(RALINK_FRAME_ENGINE_BASE+0x1f0) = 0x0fffffff;//switch IOT more stable
13407 +
13408 +    *(unsigned long *)(CKGCR) &= ~(0x3 << 4); //keep rx/tx port clock ticking, disable internal clock-gating to avoid switch stuck
13409 +
13410 +    /*
13411 +     *Reg 31: Page Control
13412 +     * Bit 15     => PortPageSel, 1=local, 0=global
13413 +     * Bit 14:12  => PageSel, local:0~3, global:0~4
13414 +     *
13415 +     *Reg16~30:Local/Global registers
13416 +     *
13417 +    */
13418 +    /*correct  PHY  setting J8.0*/
13419 +    mii_mgr_read(0, 31, &rev);
13420 +    rev &= (0x0f);
13421 +
13422 +    mii_mgr_write(1, 31, 0x4000); //global, page 4
13423 +
13424 +    mii_mgr_write(1, 16, 0xd4cc);
13425 +    mii_mgr_write(1, 17, 0x7444);
13426 +    mii_mgr_write(1, 19, 0x0112);
13427 +    mii_mgr_write(1, 21, 0x7160);
13428 +    mii_mgr_write(1, 22, 0x10cf);
13429 +    mii_mgr_write(1, 26, 0x0777);
13430 +
13431 +    if(rev == 0){
13432 +           mii_mgr_write(1, 25, 0x0102);
13433 +           mii_mgr_write(1, 29, 0x8641);
13434 +    }
13435 +    else{
13436 +            mii_mgr_write(1, 25, 0x0212);
13437 +           mii_mgr_write(1, 29, 0x4640);
13438 +    }
13439 +
13440 +    mii_mgr_write(1, 31, 0x2000); //global, page 2
13441 +    mii_mgr_write(1, 21, 0x0655);
13442 +    mii_mgr_write(1, 22, 0x0fd3);
13443 +    mii_mgr_write(1, 23, 0x003d);
13444 +    mii_mgr_write(1, 24, 0x096e);
13445 +    mii_mgr_write(1, 25, 0x0fed);
13446 +    mii_mgr_write(1, 26, 0x0fc4);
13447 +
13448 +    mii_mgr_write(1, 31, 0x1000); //global, page 1
13449 +    mii_mgr_write(1, 17, 0xe7f8);
13450 +
13451 +
13452 +    mii_mgr_write(1, 31, 0xa000); //local, page 2
13453 +
13454 +    mii_mgr_write(0, 16, 0x0e0e);
13455 +    mii_mgr_write(1, 16, 0x0c0c);
13456 +    mii_mgr_write(2, 16, 0x0f0f);
13457 +    mii_mgr_write(3, 16, 0x1010);
13458 +    mii_mgr_write(4, 16, 0x0909);
13459 +
13460 +    mii_mgr_write(0, 17, 0x0000);
13461 +    mii_mgr_write(1, 17, 0x0000);
13462 +    mii_mgr_write(2, 17, 0x0000);
13463 +    mii_mgr_write(3, 17, 0x0000);
13464 +    mii_mgr_write(4, 17, 0x0000);
13465 +#endif
13466 +
13467 +#if defined (CONFIG_RT6855A_ASIC)
13468 +
13469 +#if defined (CONFIG_P5_RGMII_TO_MAC_MODE)
13470 +        *(unsigned long *)(RALINK_ETH_SW_BASE+0x3500) = 0x5e33b;//(P5, Force mode, Link Up, 1000Mbps, Full-Duplex, FC ON)
13471 +       *(unsigned long *)(RALINK_ETH_SW_BASE+0x7014) = 0x1f0c000c;//disable port0-port4 internal phy, set phy base address to 12
13472 +       *(unsigned long *)(RALINK_ETH_SW_BASE+0x250c) = 0x000fff10;//disable port5 mac learning
13473 +       *(unsigned long *)(RALINK_ETH_SW_BASE+0x260c) = 0x000fff10;//disable port6 mac learning
13474 +
13475 +#elif defined (CONFIG_P5_MII_TO_MAC_MODE)
13476 +       *(unsigned long *)(RALINK_ETH_SW_BASE+0x3500) = 0x5e337;//(P5, Force mode, Link Up, 100Mbps, Full-Duplex, FC ON)
13477 +#elif defined (CONFIG_P5_MAC_TO_PHY_MODE)
13478 +       //rt6855/6 need to modify TX/RX phase
13479 +       *(unsigned long *)(RALINK_ETH_SW_BASE+0x7014) = 0xc;//TX/RX CLOCK Phase select
13480 +
13481 +       enable_auto_negotiate(1);
13482 +
13483 +       if (isICPlusGigaPHY(1)) {
13484 +               mii_mgr_read(CONFIG_MAC_TO_GIGAPHY_MODE_ADDR, 4, &phy_val);
13485 +               phy_val |= 1<<10; //enable pause ability
13486 +               mii_mgr_write(CONFIG_MAC_TO_GIGAPHY_MODE_ADDR, 4, phy_val);
13487 +
13488 +               mii_mgr_read(CONFIG_MAC_TO_GIGAPHY_MODE_ADDR, 0, &phy_val);
13489 +               phy_val |= 1<<9; //restart AN
13490 +               mii_mgr_write(CONFIG_MAC_TO_GIGAPHY_MODE_ADDR, 0, phy_val);
13491 +       }
13492 +
13493 +       if (isMarvellGigaPHY(1)) {
13494 +               printk("Reset MARVELL phy1\n");
13495 +               mii_mgr_read(CONFIG_MAC_TO_GIGAPHY_MODE_ADDR, 20, &phy_val);
13496 +               phy_val |= 1<<7; //Add delay to RX_CLK for RXD Outputs
13497 +               mii_mgr_write(CONFIG_MAC_TO_GIGAPHY_MODE_ADDR, 20, phy_val);
13498 +
13499 +               mii_mgr_read(CONFIG_MAC_TO_GIGAPHY_MODE_ADDR, 0, &phy_val);
13500 +               phy_val |= 1<<15; //PHY Software Reset
13501 +               mii_mgr_write(CONFIG_MAC_TO_GIGAPHY_MODE_ADDR, 0, phy_val);
13502 +        }
13503 +       if (isVtssGigaPHY(1)) {
13504 +               mii_mgr_write(CONFIG_MAC_TO_GIGAPHY_MODE_ADDR, 31, 0x0001); //extended page
13505 +               mii_mgr_read(CONFIG_MAC_TO_GIGAPHY_MODE_ADDR, 28, &phy_val);
13506 +               printk("Vitesse phy skew: %x --> ", phy_val);
13507 +               phy_val |= (0x3<<12); // RGMII RX skew compensation= 2.0 ns
13508 +               phy_val &= ~(0x3<<14);// RGMII TX skew compensation= 0 ns
13509 +               printk("%x\n", phy_val);
13510 +               mii_mgr_write(CONFIG_MAC_TO_GIGAPHY_MODE_ADDR, 28, phy_val);
13511 +               mii_mgr_write(CONFIG_MAC_TO_GIGAPHY_MODE_ADDR, 31, 0x0000); //main registers
13512 +        }
13513 +#elif defined (CONFIG_P5_RMII_TO_MAC_MODE)
13514 +       *(unsigned long *)(RALINK_ETH_SW_BASE+0x3500) = 0x5e337;//(P5, Force mode, Link Up, 100Mbps, Full-Duplex, FC ON)
13515 +#else // Port 5 Disabled //
13516 +    *(unsigned long *)(RALINK_ETH_SW_BASE+0x3500) = 0x8000;//link down
13517 +#endif
13518 +#endif
13519 +}
13520 +#endif
13521 +
13522 +
13523 +
13524 +
13525 +#if defined (CONFIG_MT7623_FPGA)
13526 +void setup_fpga_gsw(void)
13527 +{
13528 +       u32     i;
13529 +       u32     regValue;
13530 +
13531 +       /* reduce RGMII2 PAD driving strength */
13532 +       *(volatile u_long *)(PAD_RGMII2_MDIO_CFG) &= ~(0x3 << 4);
13533 +
13534 +       //RGMII1=Normal mode
13535 +       *(volatile u_long *)(RALINK_SYSCTL_BASE + 0x60) &= ~(0x1 << 14);
13536 +
13537 +       //GMAC1= RGMII mode
13538 +       *(volatile u_long *)(SYSCFG1) &= ~(0x3 << 12);
13539 +
13540 +       //enable MDIO to control MT7530
13541 +       regValue = le32_to_cpu(*(volatile u_long *)(RALINK_SYSCTL_BASE + 0x60));
13542 +       regValue &= ~(0x3 << 12);
13543 +       *(volatile u_long *)(RALINK_SYSCTL_BASE + 0x60) = regValue;
13544 +
13545 +       for(i=0;i<=4;i++)
13546 +        {
13547 +               //turn off PHY
13548 +               mii_mgr_read(i, 0x0 ,&regValue);
13549 +              regValue |= (0x1<<11);
13550 +              mii_mgr_write(i, 0x0, regValue);
13551 +       }
13552 +        mii_mgr_write(31, 0x7000, 0x3); //reset switch
13553 +        udelay(10);
13554 +       sysRegWrite(RALINK_ETH_SW_BASE+0x100, 0x2105e337);//(GE1, Force 100M/FD, FC ON)
13555 +       mii_mgr_write(31, 0x3600, 0x5e337);
13556 +
13557 +       sysRegWrite(RALINK_ETH_SW_BASE+0x200, 0x00008000);//(GE2, Link down)
13558 +       mii_mgr_write(31, 0x3500, 0x8000);
13559 +
13560 +#if defined (CONFIG_GE1_RGMII_FORCE_1000) || defined (CONFIG_GE1_TRGMII_FORCE_1200) || defined (CONFIG_GE1_TRGMII_FORCE_2000) || defined (CONFIG_GE1_TRGMII_FORCE_2600)
13561 +       //regValue = 0x117ccf; //Enable Port 6, P5 as GMAC5, P5 disable*/
13562 +       mii_mgr_read(31, 0x7804 ,&regValue);
13563 +       regValue &= ~(1<<8); //Enable Port 6
13564 +       regValue |= (1<<6); //Disable Port 5
13565 +       regValue |= (1<<13); //Port 5 as GMAC, no Internal PHY
13566 +
13567 +#if defined (CONFIG_RAETH_GMAC2)
13568 +       //RGMII2=Normal mode
13569 +       *(volatile u_long *)(RALINK_SYSCTL_BASE + 0x60) &= ~(0x1 << 15);
13570 +
13571 +       //GMAC2= RGMII mode
13572 +       *(volatile u_long *)(SYSCFG1) &= ~(0x3 << 14);
13573 +
13574 +       mii_mgr_write(31, 0x3500, 0x56300); //MT7530 P5 AN, we can ignore this setting??????
13575 +       sysRegWrite(RALINK_ETH_SW_BASE+0x200, 0x21056300);//(GE2, auto-polling)
13576 +
13577 +       enable_auto_negotiate(0);//set polling address
13578 +       /* set MT7530 Port 5 to PHY 0/4 mode */
13579 +#if defined (CONFIG_GE_RGMII_INTERNAL_P0_AN)
13580 +       regValue &= ~((1<<13)|(1<<6));
13581 +       regValue |= ((1<<7)|(1<<16)|(1<<20));
13582 +#elif defined (CONFIG_GE_RGMII_INTERNAL_P4_AN)
13583 +       regValue &= ~((1<<13)|(1<<6)|((1<<20)));
13584 +       regValue |= ((1<<7)|(1<<16));
13585 +#endif
13586 +
13587 +       //sysRegWrite(GDMA2_FWD_CFG, 0x20710000);
13588 +#endif
13589 +       regValue |= (1<<16);//change HW-TRAP
13590 +       printk("change HW-TRAP to 0x%x\n",regValue);
13591 +       mii_mgr_write(31, 0x7804 ,regValue);
13592 +#endif
13593 +       mii_mgr_write(0, 14, 0x1);  /*RGMII*/
13594 +/* set MT7530 central align */
13595 +        mii_mgr_read(31, 0x7830, &regValue);
13596 +        regValue &= ~1;
13597 +        regValue |= 1<<1;
13598 +        mii_mgr_write(31, 0x7830, regValue);
13599 +
13600 +        mii_mgr_read(31, 0x7a40, &regValue);
13601 +        regValue &= ~(1<<30);
13602 +        mii_mgr_write(31, 0x7a40, regValue);
13603 +
13604 +        regValue = 0x855;
13605 +        mii_mgr_write(31, 0x7a78, regValue);
13606 +
13607 +/*to check!!*/
13608 +       mii_mgr_write(31, 0x7b00, 0x102);  //delay setting for 10/1000M
13609 +       mii_mgr_write(31, 0x7b04, 0x14);  //delay setting for 10/1000M
13610 +
13611 +       for(i=0;i<=4;i++) {
13612 +               mii_mgr_read(i, 4, &regValue);
13613 +                regValue |= (3<<7); //turn on 100Base-T Advertisement
13614 +                //regValue &= ~(3<<7); //turn off 100Base-T Advertisement
13615 +               mii_mgr_write(i, 4, regValue);
13616 +
13617 +               mii_mgr_read(i, 9, &regValue);
13618 +                //regValue |= (3<<8); //turn on 1000Base-T Advertisement
13619 +               regValue &= ~(3<<8); //turn off 1000Base-T Advertisement
13620 +                mii_mgr_write(i, 9, regValue);
13621 +
13622 +               //restart AN
13623 +               mii_mgr_read(i, 0, &regValue);
13624 +               regValue |= (1 << 9);
13625 +               mii_mgr_write(i, 0, regValue);
13626 +       }
13627 +
13628 +       /*Tx Driving*/
13629 +       mii_mgr_write(31, 0x7a54, 0x44);  //lower driving
13630 +       mii_mgr_write(31, 0x7a5c, 0x44);  //lower driving
13631 +       mii_mgr_write(31, 0x7a64, 0x44);  //lower driving
13632 +       mii_mgr_write(31, 0x7a6c, 0x44);  //lower driving
13633 +       mii_mgr_write(31, 0x7a74, 0x44);  //lower driving
13634 +       mii_mgr_write(31, 0x7a7c, 0x44);  //lower driving
13635 +
13636 +       for(i=0;i<=4;i++)
13637 +        {
13638 +       //turn on PHY
13639 +                mii_mgr_read(i, 0x0 ,&regValue);
13640 +               regValue &= ~(0x1<<11);
13641 +               mii_mgr_write(i, 0x0, regValue);
13642 +       }
13643 +}
13644 +#endif
13645 +
13646 +
13647 +#if defined (CONFIG_RALINK_MT7621)
13648 +
13649 +
13650 +void setup_external_gsw(void)
13651 +{
13652 +       u32     regValue;
13653 +
13654 +       /* reduce RGMII2 PAD driving strength */
13655 +       *(volatile u_long *)(PAD_RGMII2_MDIO_CFG) &= ~(0x3 << 4);
13656 +       //enable MDIO
13657 +       regValue = le32_to_cpu(*(volatile u_long *)(RALINK_SYSCTL_BASE + 0x60));
13658 +       regValue &= ~(0x3 << 12);
13659 +       *(volatile u_long *)(RALINK_SYSCTL_BASE + 0x60) = regValue;
13660 +
13661 +       //RGMII1=Normal mode
13662 +       *(volatile u_long *)(RALINK_SYSCTL_BASE + 0x60) &= ~(0x1 << 14);
13663 +       //GMAC1= RGMII mode
13664 +       *(volatile u_long *)(SYSCFG1) &= ~(0x3 << 12);
13665 +
13666 +       sysRegWrite(RALINK_ETH_SW_BASE+0x100, 0x00008000);//(GE1, Link down)
13667 +
13668 +       //RGMII2=Normal mode
13669 +       *(volatile u_long *)(RALINK_SYSCTL_BASE + 0x60) &= ~(0x1 << 15);
13670 +       //GMAC2= RGMII mode
13671 +       *(volatile u_long *)(SYSCFG1) &= ~(0x3 << 14);
13672 +
13673 +       sysRegWrite(RALINK_ETH_SW_BASE+0x200, 0x2105e33b);//(GE2, Force 1000M/FD, FC ON)
13674 +
13675 +}
13676 +
13677 +
13678 +
13679 +
13680 +
13681 +
13682 +
13683 +
13684 +
13685 +
13686 +void IsSwitchVlanTableBusy(void)
13687 +{
13688 +       int j = 0;
13689 +       unsigned int value = 0;
13690 +
13691 +       for (j = 0; j < 20; j++) {
13692 +           mii_mgr_read(31, 0x90, &value);
13693 +           if ((value & 0x80000000) == 0 ){ //table busy
13694 +               break;
13695 +           }
13696 +           udelay(70000);
13697 +       }
13698 +       if (j == 20)
13699 +           printk("set vlan timeout value=0x%x.\n", value);
13700 +}
13701 +
13702 +void LANWANPartition(void)
13703 +{
13704 +/*Set  MT7530 */
13705 +#ifdef CONFIG_WAN_AT_P0
13706 +       printk("set LAN/WAN WLLLL\n");
13707 +       //WLLLL, wan at P0
13708 +       //LAN/WAN ports as security mode
13709 +       mii_mgr_write(31, 0x2004, 0xff0003);//port0
13710 +       mii_mgr_write(31, 0x2104, 0xff0003);//port1
13711 +       mii_mgr_write(31, 0x2204, 0xff0003);//port2
13712 +       mii_mgr_write(31, 0x2304, 0xff0003);//port3
13713 +       mii_mgr_write(31, 0x2404, 0xff0003);//port4
13714 +
13715 +       //set PVID
13716 +       mii_mgr_write(31, 0x2014, 0x10002);//port0
13717 +       mii_mgr_write(31, 0x2114, 0x10001);//port1
13718 +       mii_mgr_write(31, 0x2214, 0x10001);//port2
13719 +       mii_mgr_write(31, 0x2314, 0x10001);//port3
13720 +       mii_mgr_write(31, 0x2414, 0x10001);//port4
13721 +       /*port6 */
13722 +       //VLAN member
13723 +       IsSwitchVlanTableBusy();
13724 +       mii_mgr_write(31, 0x94, 0x407e0001);//VAWD1
13725 +       mii_mgr_write(31, 0x90, 0x80001001);//VTCR, VID=1
13726 +       IsSwitchVlanTableBusy();
13727 +
13728 +       mii_mgr_write(31, 0x94, 0x40610001);//VAWD1
13729 +       mii_mgr_write(31, 0x90, 0x80001002);//VTCR, VID=2
13730 +       IsSwitchVlanTableBusy();
13731 +#endif
13732 +#ifdef CONFIG_WAN_AT_P4
13733 +       printk("set LAN/WAN LLLLW\n");
13734 +       //LLLLW, wan at P4
13735 +       //LAN/WAN ports as security mode
13736 +       mii_mgr_write(31, 0x2004, 0xff0003);//port0
13737 +       mii_mgr_write(31, 0x2104, 0xff0003);//port1
13738 +       mii_mgr_write(31, 0x2204, 0xff0003);//port2
13739 +       mii_mgr_write(31, 0x2304, 0xff0003);//port3
13740 +       mii_mgr_write(31, 0x2404, 0xff0003);//port4
13741 +
13742 +       //set PVID
13743 +       mii_mgr_write(31, 0x2014, 0x10001);//port0
13744 +       mii_mgr_write(31, 0x2114, 0x10001);//port1
13745 +       mii_mgr_write(31, 0x2214, 0x10001);//port2
13746 +       mii_mgr_write(31, 0x2314, 0x10001);//port3
13747 +       mii_mgr_write(31, 0x2414, 0x10002);//port4
13748 +
13749 +       //VLAN member
13750 +       IsSwitchVlanTableBusy();
13751 +       mii_mgr_write(31, 0x94, 0x404f0001);//VAWD1
13752 +       mii_mgr_write(31, 0x90, 0x80001001);//VTCR, VID=1
13753 +       IsSwitchVlanTableBusy();
13754 +       mii_mgr_write(31, 0x94, 0x40500001);//VAWD1
13755 +       mii_mgr_write(31, 0x90, 0x80001002);//VTCR, VID=2
13756 +       IsSwitchVlanTableBusy();
13757 +#endif
13758 +}
13759 +
13760 +#if defined (CONFIG_RAETH_8023AZ_EEE) && defined (CONFIG_RALINK_MT7621)
13761 +void mt7621_eee_patch(void)
13762 +{
13763 +       u32 i;
13764 +
13765 +       for(i=0;i<5;i++)
13766 +       {
13767 +               /* Enable EEE */
13768 +               mii_mgr_write(i, 13, 0x07);
13769 +               mii_mgr_write(i, 14, 0x3c);
13770 +               mii_mgr_write(i, 13, 0x4007);
13771 +               mii_mgr_write(i, 14, 0x6);
13772 +
13773 +               /* Forced Slave mode */
13774 +               mii_mgr_write(i, 31, 0x0);
13775 +               mii_mgr_write(i, 9, 0x1600);
13776 +               /* Increase SlvDPSready time */
13777 +               mii_mgr_write(i, 31, 0x52b5);
13778 +               mii_mgr_write(i, 16, 0xafae);
13779 +               mii_mgr_write(i, 18, 0x2f);
13780 +               mii_mgr_write(i, 16, 0x8fae);
13781 +               /* Incease post_update_timer */
13782 +               mii_mgr_write(i, 31, 0x3);
13783 +               mii_mgr_write(i, 17, 0x4b);
13784 +               /* Adjust 100_mse_threshold */
13785 +               mii_mgr_write(i, 13, 0x1e);
13786 +               mii_mgr_write(i, 14, 0x123);
13787 +               mii_mgr_write(i, 13, 0x401e);
13788 +               mii_mgr_write(i, 14, 0xffff);
13789 +               /* Disable mcc
13790 +                  mii_mgr_write(i, 13, 0x1e);
13791 +                  mii_mgr_write(i, 14, 0xa6);
13792 +                  mii_mgr_write(i, 13, 0x401e);
13793 +                  mii_mgr_write(i, 14, 0x300);
13794 +               */
13795 +       }
13796 +
13797 +}
13798 +#endif
13799 +
13800 +
13801 +#if defined (CONFIG_RALINK_MT7621)
13802 +void setup_internal_gsw(void)
13803 +{
13804 +       u32     i;
13805 +       u32     regValue;
13806 +
13807 +#if defined (CONFIG_GE1_RGMII_FORCE_1000) || defined (CONFIG_GE1_TRGMII_FORCE_1200) || defined (CONFIG_GE1_TRGMII_FORCE_2000) || defined (CONFIG_GE1_TRGMII_FORCE_2600)
13808 +       /*Hardware reset Switch*/
13809 +       *(volatile u_long *)(RALINK_SYSCTL_BASE + 0x34) |= (0x1 << 2);
13810 +        udelay(1000);
13811 +       *(volatile u_long *)(RALINK_SYSCTL_BASE + 0x34) &= ~(0x1 << 2);
13812 +        udelay(10000);
13813 +
13814 +       /* reduce RGMII2 PAD driving strength */
13815 +       *(volatile u_long *)(PAD_RGMII2_MDIO_CFG) &= ~(0x3 << 4);
13816 +
13817 +       //RGMII1=Normal mode
13818 +       *(volatile u_long *)(RALINK_SYSCTL_BASE + 0x60) &= ~(0x1 << 14);
13819 +
13820 +       //GMAC1= RGMII mode
13821 +       *(volatile u_long *)(SYSCFG1) &= ~(0x3 << 12);
13822 +
13823 +       //enable MDIO to control MT7530
13824 +       regValue = le32_to_cpu(*(volatile u_long *)(RALINK_SYSCTL_BASE + 0x60));
13825 +       regValue &= ~(0x3 << 12);
13826 +       *(volatile u_long *)(RALINK_SYSCTL_BASE + 0x60) = regValue;
13827 +
13828 +       for(i=0;i<=4;i++)
13829 +        {
13830 +               //turn off PHY
13831 +               mii_mgr_read(i, 0x0 ,&regValue);
13832 +              regValue |= (0x1<<11);
13833 +              mii_mgr_write(i, 0x0, regValue);
13834 +       }
13835 +        mii_mgr_write(31, 0x7000, 0x3); //reset switch
13836 +        udelay(100);
13837 +
13838 +
13839 +#if defined (CONFIG_GE1_TRGMII_FORCE_1200) && defined (CONFIG_MT7621_ASIC)
13840 +       trgmii_set_7530();   //reset FE, config MDIO again
13841 +
13842 +       //enable MDIO to control MT7530
13843 +       regValue = le32_to_cpu(*(volatile u_long *)(RALINK_SYSCTL_BASE + 0x60));
13844 +       regValue &= ~(0x3 << 12);
13845 +       *(volatile u_long *)(RALINK_SYSCTL_BASE + 0x60) = regValue;
13846 +
13847 +       // switch to APLL if TRGMII and DDR2
13848 +       if ((sysRegRead(0xBE000010)>>4)&0x1)
13849 +       {
13850 +               apll_xtal_enable();
13851 +       }
13852 +#endif
13853 +
13854 +#if defined (CONFIG_MT7621_ASIC)
13855 +       if((sysRegRead(0xbe00000c)&0xFFFF)==0x0101) {
13856 +               sysRegWrite(RALINK_ETH_SW_BASE+0x100, 0x2105e30b);//(GE1, Force 1000M/FD, FC ON)
13857 +               mii_mgr_write(31, 0x3600, 0x5e30b);
13858 +       } else {
13859 +               sysRegWrite(RALINK_ETH_SW_BASE+0x100, 0x2105e33b);//(GE1, Force 1000M/FD, FC ON)
13860 +               mii_mgr_write(31, 0x3600, 0x5e33b);
13861 +       }
13862 +#elif defined (CONFIG_MT7621_FPGA)
13863 +       sysRegWrite(RALINK_ETH_SW_BASE+0x100, 0x2105e337);//(GE1, Force 100M/FD, FC ON)
13864 +       mii_mgr_write(31, 0x3600, 0x5e337);
13865 +#endif
13866 +
13867 +       sysRegWrite(RALINK_ETH_SW_BASE+0x200, 0x00008000);//(GE2, Link down)
13868 +#endif
13869 +
13870 +#if defined (CONFIG_GE1_RGMII_FORCE_1000) || defined (CONFIG_GE1_TRGMII_FORCE_1200) || defined (CONFIG_GE1_TRGMII_FORCE_2000) || defined (CONFIG_GE1_TRGMII_FORCE_2600)
13871 +       //regValue = 0x117ccf; //Enable Port 6, P5 as GMAC5, P5 disable*/
13872 +       mii_mgr_read(31, 0x7804 ,&regValue);
13873 +       regValue &= ~(1<<8); //Enable Port 6
13874 +       regValue |= (1<<6); //Disable Port 5
13875 +       regValue |= (1<<13); //Port 5 as GMAC, no Internal PHY
13876 +
13877 +#if defined (CONFIG_RAETH_GMAC2)
13878 +       //RGMII2=Normal mode
13879 +       *(volatile u_long *)(RALINK_SYSCTL_BASE + 0x60) &= ~(0x1 << 15);
13880 +
13881 +       //GMAC2= RGMII mode
13882 +       *(volatile u_long *)(SYSCFG1) &= ~(0x3 << 14);
13883 +#if !defined (CONFIG_RAETH_8023AZ_EEE)
13884 +       mii_mgr_write(31, 0x3500, 0x56300); //MT7530 P5 AN, we can ignore this setting??????
13885 +       sysRegWrite(RALINK_ETH_SW_BASE+0x200, 0x21056300);//(GE2, auto-polling)
13886 +
13887 +       enable_auto_negotiate(0);//set polling address
13888 +#endif
13889 +#if defined (CONFIG_RAETH_8023AZ_EEE)
13890 +       mii_mgr_write(31, 0x3500, 0x5e33b); //MT7530 P5 Force 1000, we can ignore this setting??????
13891 +       sysRegWrite(RALINK_ETH_SW_BASE+0x200, 0x2105e33b);//(GE2, Force 1000)
13892 +#endif
13893 +
13894 +
13895 +
13896 +       /* set MT7530 Port 5 to PHY 0/4 mode */
13897 +#if defined (CONFIG_GE_RGMII_INTERNAL_P0_AN)
13898 +       regValue &= ~((1<<13)|(1<<6));
13899 +       regValue |= ((1<<7)|(1<<16)|(1<<20));
13900 +#elif defined (CONFIG_GE_RGMII_INTERNAL_P4_AN)
13901 +       regValue &= ~((1<<13)|(1<<6)|(1<<20));
13902 +       regValue |= ((1<<7)|(1<<16));
13903 +#endif
13904 +
13905 +#if defined (CONFIG_RAETH_8023AZ_EEE)
13906 +       regValue |= (1<<13); //Port 5 as GMAC, no Internal PHY
13907 +#endif
13908 +       //sysRegWrite(GDMA2_FWD_CFG, 0x20710000);
13909 +#endif
13910 +       regValue |= (1<<16);//change HW-TRAP
13911 +       //printk("change HW-TRAP to 0x%x\n",regValue);
13912 +       mii_mgr_write(31, 0x7804 ,regValue);
13913 +#endif
13914 +       mii_mgr_read(31, 0x7800, &regValue);
13915 +       regValue = (regValue >> 9) & 0x3;
13916 +       if(regValue == 0x3) { //25Mhz Xtal
13917 +               /* do nothing */
13918 +       } else if(regValue == 0x2) { //40Mhz
13919 +
13920 +           mii_mgr_write(0, 13, 0x1f);  // disable MT7530 core clock
13921 +           mii_mgr_write(0, 14, 0x410);
13922 +           mii_mgr_write(0, 13, 0x401f);
13923 +           mii_mgr_write(0, 14, 0x0);
13924 +
13925 +           mii_mgr_write(0, 13, 0x1f);  // disable MT7530 PLL
13926 +           mii_mgr_write(0, 14, 0x40d);
13927 +           mii_mgr_write(0, 13, 0x401f);
13928 +           mii_mgr_write(0, 14, 0x2020);
13929 +
13930 +           mii_mgr_write(0, 13, 0x1f);  // for MT7530 core clock = 500Mhz
13931 +           mii_mgr_write(0, 14, 0x40e);
13932 +           mii_mgr_write(0, 13, 0x401f);
13933 +           mii_mgr_write(0, 14, 0x119);
13934 +
13935 +           mii_mgr_write(0, 13, 0x1f);  // enable MT7530 PLL
13936 +           mii_mgr_write(0, 14, 0x40d);
13937 +           mii_mgr_write(0, 13, 0x401f);
13938 +           mii_mgr_write(0, 14, 0x2820);
13939 +
13940 +           udelay(20); //suggest by CD
13941 +
13942 +           mii_mgr_write(0, 13, 0x1f);  // enable MT7530 core clock
13943 +           mii_mgr_write(0, 14, 0x410);
13944 +           mii_mgr_write(0, 13, 0x401f);
13945 +       }else { //20Mhz Xtal
13946 +
13947 +               /* TODO */
13948 +
13949 +       }
13950 +#if defined (CONFIG_GE1_TRGMII_FORCE_1200) && defined (CONFIG_MT7621_ASIC)
13951 +       mii_mgr_write(0, 14, 0x3); /*TRGMII*/
13952 +#else
13953 +       mii_mgr_write(0, 14, 0x1);  /*RGMII*/
13954 +/* set MT7530 central align */
13955 +        mii_mgr_read(31, 0x7830, &regValue);
13956 +        regValue &= ~1;
13957 +        regValue |= 1<<1;
13958 +        mii_mgr_write(31, 0x7830, regValue);
13959 +
13960 +        mii_mgr_read(31, 0x7a40, &regValue);
13961 +        regValue &= ~(1<<30);
13962 +        mii_mgr_write(31, 0x7a40, regValue);
13963 +
13964 +        regValue = 0x855;
13965 +        mii_mgr_write(31, 0x7a78, regValue);
13966 +
13967 +#endif
13968 +#if !defined (CONFIG_RAETH_8023AZ_EEE)
13969 +       mii_mgr_write(31, 0x7b00, 0x102);  //delay setting for 10/1000M
13970 +       mii_mgr_write(31, 0x7b04, 0x14);  //delay setting for 10/1000M
13971 +#endif
13972 +#if 0
13973 +       for(i=0;i<=4;i++) {
13974 +               mii_mgr_read(i, 4, &regValue);
13975 +                regValue |= (3<<7); //turn on 100Base-T Advertisement
13976 +                //regValue &= ~(3<<7); //turn off 100Base-T Advertisement
13977 +               mii_mgr_write(i, 4, regValue);
13978 +
13979 +               mii_mgr_read(i, 9, &regValue);
13980 +                regValue |= (3<<8); //turn on 1000Base-T Advertisement
13981 +               //regValue &= ~(3<<8); //turn off 1000Base-T Advertisement
13982 +                mii_mgr_write(i, 9, regValue);
13983 +
13984 +               //restart AN
13985 +               mii_mgr_read(i, 0, &regValue);
13986 +               regValue |= (1 << 9);
13987 +               mii_mgr_write(i, 0, regValue);
13988 +       }
13989 +#endif
13990 +
13991 +       /*Tx Driving*/
13992 +       mii_mgr_write(31, 0x7a54, 0x44);  //lower driving
13993 +       mii_mgr_write(31, 0x7a5c, 0x44);  //lower driving
13994 +       mii_mgr_write(31, 0x7a64, 0x44);  //lower driving
13995 +       mii_mgr_write(31, 0x7a6c, 0x44);  //lower driving
13996 +       mii_mgr_write(31, 0x7a74, 0x44);  //lower driving
13997 +       mii_mgr_write(31, 0x7a7c, 0x44);  //lower driving
13998 +
13999 +
14000 +       LANWANPartition();
14001 +
14002 +#if !defined (CONFIG_RAETH_8023AZ_EEE)
14003 +       //disable EEE
14004 +       for(i=0;i<=4;i++)
14005 +       {
14006 +           mii_mgr_write(i, 13, 0x7);
14007 +           mii_mgr_write(i, 14, 0x3C);
14008 +           mii_mgr_write(i, 13, 0x4007);
14009 +           mii_mgr_write(i, 14, 0x0);
14010 +       }
14011 +
14012 +       //Disable EEE 10Base-Te:
14013 +       for(i=0;i<=4;i++)
14014 +       {
14015 +           mii_mgr_write(i, 13, 0x1f);
14016 +           mii_mgr_write(i, 14, 0x027b);
14017 +           mii_mgr_write(i, 13, 0x401f);
14018 +           mii_mgr_write(i, 14, 0x1177);
14019 +       }
14020 +#endif
14021 +
14022 +       for(i=0;i<=4;i++)
14023 +        {
14024 +       //turn on PHY
14025 +                mii_mgr_read(i, 0x0 ,&regValue);
14026 +               regValue &= ~(0x1<<11);
14027 +               mii_mgr_write(i, 0x0, regValue);
14028 +       }
14029 +
14030 +       mii_mgr_read(31, 0x7808 ,&regValue);
14031 +        regValue |= (3<<16); //Enable INTR
14032 +       mii_mgr_write(31, 0x7808 ,regValue);
14033 +#if defined (CONFIG_RAETH_8023AZ_EEE) && defined (CONFIG_RALINK_MT7621)
14034 +                       mt7621_eee_patch();
14035 +#endif
14036 +}
14037 +#endif
14038 +
14039 +#if defined (CONFIG_GE1_TRGMII_FORCE_1200)
14040 +void apll_xtal_enable(void)
14041 +{
14042 +        unsigned long data = 0;
14043 +        unsigned long regValue = 0;
14044 +
14045 +        /* Firstly, reset all required register to default value */
14046 +        sysRegWrite(RALINK_ANA_CTRL_BASE, 0x00008000);
14047 +        sysRegWrite(RALINK_ANA_CTRL_BASE+0x0014, 0x01401d61);
14048 +        sysRegWrite(RALINK_ANA_CTRL_BASE+0x0018, 0x38233d0e);
14049 +        sysRegWrite(RALINK_ANA_CTRL_BASE+0x001c, 0x80120004);
14050 +        sysRegWrite(RALINK_ANA_CTRL_BASE+0x0020, 0x1c7dbf48);
14051 +
14052 +        /* toggle RG_XPTL_CHG */
14053 +        sysRegWrite(RALINK_ANA_CTRL_BASE, 0x00008800);
14054 +        sysRegWrite(RALINK_ANA_CTRL_BASE, 0x00008c00);
14055 +
14056 +        data = sysRegRead(RALINK_ANA_CTRL_BASE+0x0014);
14057 +        data &= ~(0x0000ffc0);
14058 +
14059 +       regValue = *(volatile u_long *)(RALINK_SYSCTL_BASE + 0x10);
14060 +       regValue = (regValue >> 6) & 0x7;
14061 +       if(regValue < 6) { //20/40Mhz Xtal
14062 +               data |= REGBIT(0x1d, 8);
14063 +       }else {
14064 +               data |= REGBIT(0x17, 8);
14065 +       }
14066 +
14067 +       if(regValue < 6) { //20/40Mhz Xtal
14068 +               data |= REGBIT(0x1, 6);
14069 +       }
14070 +
14071 +       sysRegWrite(RALINK_ANA_CTRL_BASE+0x0014, data);
14072 +
14073 +        data = sysRegRead(RALINK_ANA_CTRL_BASE+0x0018);
14074 +        data &= ~(0xf0773f00);
14075 +        data |= REGBIT(0x3, 28);
14076 +        data |= REGBIT(0x2, 20);
14077 +       if(regValue < 6) { //20/40Mhz Xtal
14078 +               data |= REGBIT(0x3, 16);
14079 +       }else {
14080 +               data |= REGBIT(0x2, 16);
14081 +       }
14082 +        data |= REGBIT(0x3, 12);
14083 +
14084 +       if(regValue < 6) { //20/40Mhz Xtal
14085 +               data |= REGBIT(0xd, 8);
14086 +       }else {
14087 +               data |= REGBIT(0x7, 8);
14088 +       }
14089 +        sysRegWrite(RALINK_ANA_CTRL_BASE+0x0018, data);
14090 +
14091 +       if(regValue < 6) { //20/40Mhz Xtal
14092 +               sysRegWrite(RALINK_ANA_CTRL_BASE+0x0020, 0x1c7dbf48);
14093 +       }else {
14094 +               sysRegWrite(RALINK_ANA_CTRL_BASE+0x0020, 0x1697cc39);
14095 +       }
14096 +       //*Common setting - Set PLLGP_CTRL_4 *//
14097 +       ///* 1. Bit 31 */
14098 +        data = sysRegRead(RALINK_ANA_CTRL_BASE+0x001c);
14099 +        data &= ~(REGBIT(0x1, 31));
14100 +        sysRegWrite(RALINK_ANA_CTRL_BASE+0x001c, data);
14101 +
14102 +       /* 2. Bit 0 */
14103 +       data = sysRegRead(RALINK_ANA_CTRL_BASE+0x001c);
14104 +        data |= REGBIT(0x1, 0);
14105 +        sysRegWrite(RALINK_ANA_CTRL_BASE+0x001c, data);
14106 +
14107 +       /* 3. Bit 3 */
14108 +       data = sysRegRead(RALINK_ANA_CTRL_BASE+0x001c);
14109 +        data |= REGBIT(0x1, 3);
14110 +        sysRegWrite(RALINK_ANA_CTRL_BASE+0x001c, data);
14111 +
14112 +       /* 4. Bit 8 */
14113 +       data = sysRegRead(RALINK_ANA_CTRL_BASE+0x001c);
14114 +        data |= REGBIT(0x1, 8);
14115 +        sysRegWrite(RALINK_ANA_CTRL_BASE+0x001c, data);
14116 +
14117 +       /* 5. Bit 6 */
14118 +        data = sysRegRead(RALINK_ANA_CTRL_BASE+0x001c);
14119 +        data |= REGBIT(0x1, 6);
14120 +        sysRegWrite(RALINK_ANA_CTRL_BASE+0x001c, data);
14121 +
14122 +       /* 6. Bit 7 */
14123 +        data = sysRegRead(RALINK_ANA_CTRL_BASE+0x001c);
14124 +        data |= REGBIT(0x1, 5);
14125 +        data |= REGBIT(0x1, 7);
14126 +        sysRegWrite(RALINK_ANA_CTRL_BASE+0x001c, data);
14127 +
14128 +       /* 7. Bit 17 */
14129 +        data = sysRegRead(RALINK_ANA_CTRL_BASE+0x001c);
14130 +        data &= ~REGBIT(0x1, 17);
14131 +       sysRegWrite(RALINK_ANA_CTRL_BASE+0x001c, data);
14132 +
14133 +       /* 8. TRGMII TX CLK SEL APLL */
14134 +       data = sysRegRead(0xbe00002c);
14135 +       data &= 0xffffff9f;
14136 +       data |= 0x40;
14137 +       sysRegWrite(0xbe00002c, data);
14138 +
14139 +}
14140 +#endif
14141 +
14142 +#endif
14143 +#if defined(CONFIG_RALINK_RT6855) || defined(CONFIG_RALINK_MT7620)
14144 +void rt_gsw_init(void)
14145 +{
14146 +#if defined (CONFIG_P4_MAC_TO_PHY_MODE) || defined (CONFIG_P5_MAC_TO_PHY_MODE)
14147 +       u32 phy_val=0;
14148 +#endif
14149 +#if defined (CONFIG_RT6855_FPGA) || defined (CONFIG_MT7620_FPGA)
14150 +       u32 i=0;
14151 +#elif defined (CONFIG_MT7620_ASIC)
14152 +       u32 is_BGA=0;
14153 +#endif
14154 +#if defined (CONFIG_P5_RGMII_TO_MT7530_MODE)
14155 +        unsigned int regValue = 0;
14156 +#endif
14157 +#if defined (CONFIG_RT6855_FPGA) || defined (CONFIG_MT7620_FPGA)
14158 +    /*keep dump switch mode */
14159 +    *(unsigned long *)(RALINK_ETH_SW_BASE+0x3000) = 0x5e333;//(P0, Force mode, Link Up, 10Mbps, Full-Duplex, FC ON)
14160 +    *(unsigned long *)(RALINK_ETH_SW_BASE+0x3100) = 0x5e333;//(P1, Force mode, Link Up, 10Mbps, Full-Duplex, FC ON)
14161 +    *(unsigned long *)(RALINK_ETH_SW_BASE+0x3200) = 0x5e333;//(P2, Force mode, Link Up, 10Mbps, Full-Duplex, FC ON)
14162 +    *(unsigned long *)(RALINK_ETH_SW_BASE+0x3300) = 0x5e333;//(P3, Force mode, Link Up, 10Mbps, Full-Duplex, FC ON)
14163 +#if defined (CONFIG_RAETH_HAS_PORT4)
14164 +    *(unsigned long *)(RALINK_ETH_SW_BASE+0x3400) = 0x5e337;//(P4, Force mode, Link Up, 100Mbps, Full-Duplex, FC ON)
14165 +#else
14166 +    *(unsigned long *)(RALINK_ETH_SW_BASE+0x3400) = 0x5e333;//(P4, Force mode, Link Up, 10Mbps, Full-Duplex, FC ON)
14167 +#endif
14168 +    *(unsigned long *)(RALINK_ETH_SW_BASE+0x3500) = 0x5e337;//(P5, Force mode, Link Up, 100Mbps, Full-Duplex, FC ON)
14169 +
14170 +    /* In order to use 10M/Full on FPGA board. We configure phy capable to
14171 +     * 10M Full/Half duplex, so we can use auto-negotiation on PC side */
14172 +#if defined (CONFIG_RAETH_HAS_PORT4)
14173 +    for(i=0;i<4;i++){
14174 +#else
14175 +    for(i=0;i<5;i++){
14176 +#endif
14177 +       mii_mgr_write(i, 4, 0x0461);   //Capable of 10M Full/Half Duplex, flow control on/off
14178 +       mii_mgr_write(i, 0, 0xB100);   //reset all digital logic, except phy_reg
14179 +    }
14180 +
14181 +#endif
14182 +
14183 +#if defined (CONFIG_PDMA_NEW)
14184 +    *(unsigned long *)(SYSCFG1) |= (0x1 << 8); //PCIE_RC_MODE=1
14185 +#endif
14186 +
14187 +
14188 +#if defined (CONFIG_MT7620_ASIC) && !defined (CONFIG_P5_RGMII_TO_MT7530_MODE)
14189 +    is_BGA = (sysRegRead(RALINK_SYSCTL_BASE + 0xc) >> 16) & 0x1;
14190 +    /*
14191 +    * Reg 31: Page Control
14192 +    * Bit 15     => PortPageSel, 1=local, 0=global
14193 +    * Bit 14:12  => PageSel, local:0~3, global:0~4
14194 +    *
14195 +    * Reg16~30:Local/Global registers
14196 +    *
14197 +    */
14198 +    /*correct  PHY  setting L3.0 BGA*/
14199 +    mii_mgr_write(1, 31, 0x4000); //global, page 4
14200 +
14201 +    mii_mgr_write(1, 17, 0x7444);
14202 +    if(is_BGA){
14203 +       mii_mgr_write(1, 19, 0x0114);
14204 +    }else{
14205 +       mii_mgr_write(1, 19, 0x0117);
14206 +    }
14207 +
14208 +    mii_mgr_write(1, 22, 0x10cf);
14209 +    mii_mgr_write(1, 25, 0x6212);
14210 +    mii_mgr_write(1, 26, 0x0777);
14211 +    mii_mgr_write(1, 29, 0x4000);
14212 +    mii_mgr_write(1, 28, 0xc077);
14213 +    mii_mgr_write(1, 24, 0x0000);
14214 +
14215 +    mii_mgr_write(1, 31, 0x3000); //global, page 3
14216 +    mii_mgr_write(1, 17, 0x4838);
14217 +
14218 +    mii_mgr_write(1, 31, 0x2000); //global, page 2
14219 +    if(is_BGA){
14220 +       mii_mgr_write(1, 21, 0x0515);
14221 +       mii_mgr_write(1, 22, 0x0053);
14222 +       mii_mgr_write(1, 23, 0x00bf);
14223 +       mii_mgr_write(1, 24, 0x0aaf);
14224 +       mii_mgr_write(1, 25, 0x0fad);
14225 +       mii_mgr_write(1, 26, 0x0fc1);
14226 +    }else{
14227 +       mii_mgr_write(1, 21, 0x0517);
14228 +       mii_mgr_write(1, 22, 0x0fd2);
14229 +       mii_mgr_write(1, 23, 0x00bf);
14230 +       mii_mgr_write(1, 24, 0x0aab);
14231 +       mii_mgr_write(1, 25, 0x00ae);
14232 +       mii_mgr_write(1, 26, 0x0fff);
14233 +    }
14234 +    mii_mgr_write(1, 31, 0x1000); //global, page 1
14235 +    mii_mgr_write(1, 17, 0xe7f8);
14236 +
14237 +    mii_mgr_write(1, 31, 0x8000); //local, page 0
14238 +    mii_mgr_write(0, 30, 0xa000);
14239 +    mii_mgr_write(1, 30, 0xa000);
14240 +    mii_mgr_write(2, 30, 0xa000);
14241 +    mii_mgr_write(3, 30, 0xa000);
14242 +#if !defined (CONFIG_RAETH_HAS_PORT4)
14243 +    mii_mgr_write(4, 30, 0xa000);
14244 +#endif
14245 +
14246 +    mii_mgr_write(0, 4, 0x05e1);
14247 +    mii_mgr_write(1, 4, 0x05e1);
14248 +    mii_mgr_write(2, 4, 0x05e1);
14249 +    mii_mgr_write(3, 4, 0x05e1);
14250 +#if !defined (CONFIG_RAETH_HAS_PORT4)
14251 +    mii_mgr_write(4, 4, 0x05e1);
14252 +#endif
14253 +
14254 +    mii_mgr_write(1, 31, 0xa000); //local, page 2
14255 +    mii_mgr_write(0, 16, 0x1111);
14256 +    mii_mgr_write(1, 16, 0x1010);
14257 +    mii_mgr_write(2, 16, 0x1515);
14258 +    mii_mgr_write(3, 16, 0x0f0f);
14259 +#if !defined (CONFIG_RAETH_HAS_PORT4)
14260 +    mii_mgr_write(4, 16, 0x1313);
14261 +#endif
14262 +
14263 +#if !defined (CONFIG_RAETH_8023AZ_EEE)
14264 +    mii_mgr_write(1, 31, 0xb000); //local, page 3
14265 +    mii_mgr_write(0, 17, 0x0);
14266 +    mii_mgr_write(1, 17, 0x0);
14267 +    mii_mgr_write(2, 17, 0x0);
14268 +    mii_mgr_write(3, 17, 0x0);
14269 +#if !defined (CONFIG_RAETH_HAS_PORT4)
14270 +    mii_mgr_write(4, 17, 0x0);
14271 +#endif
14272 +#endif
14273 +
14274 +
14275 +
14276 +#if 0
14277 +    // for ethernet extended mode
14278 +    mii_mgr_write(1, 31, 0x3000);
14279 +    mii_mgr_write(1, 19, 0x122);
14280 +    mii_mgr_write(1, 20, 0x0044);
14281 +    mii_mgr_write(1, 23, 0xa80c);
14282 +    mii_mgr_write(1, 24, 0x129d);
14283 +    mii_mgr_write(1, 31, 9000);
14284 +    mii_mgr_write(0, 18, 0x140c);
14285 +    mii_mgr_write(1, 18, 0x140c);
14286 +    mii_mgr_write(2, 18, 0x140c);
14287 +    mii_mgr_write(3, 18, 0x140c);
14288 +    mii_mgr_write(0, 0, 0x3300);
14289 +    mii_mgr_write(1, 0, 0x3300);
14290 +    mii_mgr_write(2, 0, 0x3300);
14291 +    mii_mgr_write(3, 0, 0x3300);
14292 +#if !defined (CONFIG_RAETH_HAS_PORT4)
14293 +    mii_mgr_write(4, 18, 0x140c);
14294 +    mii_mgr_write(4, 0, 0x3300);
14295 +#endif
14296 +#endif
14297 +
14298 +#endif
14299 +
14300 +#if defined(CONFIG_RALINK_MT7620)
14301 +       if ((sysRegRead(0xB000000C) & 0xf) >= 0x5) {
14302 +               *(unsigned long *)(RALINK_ETH_SW_BASE+0x701c) = 0x800000c; //enlarge FE2SW_IPG
14303 +       }
14304 +#endif // CONFIG_RAETH_7620 //
14305 +
14306 +
14307 +
14308 +#if defined (CONFIG_MT7620_FPGA)|| defined (CONFIG_MT7620_ASIC)
14309 +       *(unsigned long *)(RALINK_ETH_SW_BASE+0x3600) = 0x5e33b;//CPU Port6 Force Link 1G, FC ON
14310 +       *(unsigned long *)(RALINK_ETH_SW_BASE+0x0010) = 0x7f7f7fe0;//Set Port6 CPU Port
14311 +
14312 +#if defined (CONFIG_P5_RGMII_TO_MAC_MODE) || defined (CONFIG_P5_RGMII_TO_MT7530_MODE)
14313 +        *(unsigned long *)(RALINK_ETH_SW_BASE+0x3500) = 0x5e33b;//(P5, Force mode, Link Up, 1000Mbps, Full-Duplex, FC ON)
14314 +       *(unsigned long *)(RALINK_ETH_SW_BASE+0x7014) = 0x1f0c000c; //disable port 0 ~ 4 internal phy, set phy base address to 12
14315 +       /*MT7620 need mac learning for PPE*/
14316 +       //*(unsigned long *)(RALINK_ETH_SW_BASE+0x250c) = 0x000fff10;//disable port5 mac learning
14317 +       //*(unsigned long *)(RALINK_ETH_SW_BASE+0x260c) = 0x000fff10;//disable port6 mac learning
14318 +       *(unsigned long *)(0xb0000060) &= ~(1 << 9); //set RGMII to Normal mode
14319 +       //rxclk_skew, txclk_skew = 0
14320 +       *(unsigned long *)(SYSCFG1) &= ~(0x3 << 12); //GE1_MODE=RGMii Mode
14321 +#if defined (CONFIG_P5_RGMII_TO_MT7530_MODE)
14322 +
14323 +       *(unsigned long *)(0xb0000060) &= ~(3 << 7); //set MDIO to Normal mode
14324 +
14325 +       *(unsigned long *)(RALINK_ETH_SW_BASE+0x3400) = 0x56330;//(P4, AN)
14326 +       *(unsigned long *)(0xb0000060) &= ~(1 << 10); //set GE2 to Normal mode
14327 +       //rxclk_skew, txclk_skew = 0
14328 +       *(unsigned long *)(SYSCFG1) &= ~(0x3 << 14); //GE2_MODE=RGMii Mode
14329 +
14330 +
14331 +       /* set MT7530 Port 0 to PHY mode */
14332 +       mii_mgr_read(31, 0x7804 ,&regValue);
14333 +#if defined (CONFIG_GE_RGMII_MT7530_P0_AN)
14334 +       regValue &= ~((1<<13)|(1<<6)|(1<<5)|(1<<15));
14335 +       regValue |= ((1<<7)|(1<<16)|(1<<20)|(1<<24));
14336 +       //mii_mgr_write(31, 0x7804 ,0x115c8f);
14337 +#elif defined (CONFIG_GE_RGMII_MT7530_P4_AN)
14338 +       regValue &= ~((1<<13)|(1<<6)|(1<<20)|(1<<5)|(1<<15));
14339 +       regValue |= ((1<<7)|(1<<16)|(1<<24));
14340 +#endif
14341 +       regValue &= ~(1<<8); //Enable Port 6
14342 +       mii_mgr_write(31, 0x7804 ,regValue); //bit 24 standalone switch
14343 +
14344 +/* set MT7530 central align */
14345 +        mii_mgr_read(31, 0x7830, &regValue);
14346 +        regValue &= ~1;
14347 +        regValue |= 1<<1;
14348 +        mii_mgr_write(31, 0x7830, regValue);
14349 +
14350 +        mii_mgr_read(31, 0x7a40, &regValue);
14351 +        regValue &= ~(1<<30);
14352 +        mii_mgr_write(31, 0x7a40, regValue);
14353 +
14354 +        regValue = 0x855;
14355 +        mii_mgr_write(31, 0x7a78, regValue);
14356 +
14357 +       /*AN should be set after MT7530 HWSTRAP*/
14358 +#if defined (CONFIG_GE_RGMII_MT7530_P0_AN)
14359 +       *(unsigned long *)(RALINK_ETH_SW_BASE+0x7000) = 0xc5000100;//(P0, AN polling)
14360 +#elif defined (CONFIG_GE_RGMII_MT7530_P4_AN)
14361 +       *(unsigned long *)(RALINK_ETH_SW_BASE+0x7000) = 0xc5000504;//(P4, AN polling)
14362 +#endif
14363 +#endif
14364 +
14365 +#elif defined (CONFIG_P5_MII_TO_MAC_MODE)
14366 +       *(unsigned long *)(RALINK_ETH_SW_BASE+0x3500) = 0x5e337;//(P5, Force mode, Link Up, 100Mbps, Full-Duplex, FC ON)
14367 +       *(unsigned long *)(0xb0000060) &= ~(1 << 9); //set RGMII to Normal mode
14368 +       *(unsigned long *)(SYSCFG1) &= ~(0x3 << 12); //GE1_MODE=Mii Mode
14369 +       *(unsigned long *)(SYSCFG1) |= (0x1 << 12);
14370 +
14371 +#elif defined (CONFIG_P5_MAC_TO_PHY_MODE)
14372 +       *(unsigned long *)(0xb0000060) &= ~(1 << 9); //set RGMII to Normal mode
14373 +       *(unsigned long *)(0xb0000060) &= ~(3 << 7); //set MDIO to Normal mode
14374 +       *(unsigned long *)(SYSCFG1) &= ~(0x3 << 12); //GE1_MODE=RGMii Mode
14375 +
14376 +       enable_auto_negotiate(1);
14377 +
14378 +       if (isICPlusGigaPHY(1)) {
14379 +               mii_mgr_read(CONFIG_MAC_TO_GIGAPHY_MODE_ADDR, 4, &phy_val);
14380 +               phy_val |= 1<<10; //enable pause ability
14381 +               mii_mgr_write(CONFIG_MAC_TO_GIGAPHY_MODE_ADDR, 4, phy_val);
14382 +
14383 +               mii_mgr_read(CONFIG_MAC_TO_GIGAPHY_MODE_ADDR, 0, &phy_val);
14384 +               phy_val |= 1<<9; //restart AN
14385 +               mii_mgr_write(CONFIG_MAC_TO_GIGAPHY_MODE_ADDR, 0, phy_val);
14386 +       }else if (isMarvellGigaPHY(1)) {
14387 +#if defined (CONFIG_MT7620_FPGA)
14388 +               mii_mgr_read(CONFIG_MAC_TO_GIGAPHY_MODE_ADDR, 9, &phy_val);
14389 +               phy_val &= ~(3<<8); //turn off 1000Base-T Advertisement  (9.9=1000Full, 9.8=1000Half)
14390 +               mii_mgr_write(CONFIG_MAC_TO_GIGAPHY_MODE_ADDR, 9, phy_val);
14391 +#endif
14392 +               printk("Reset MARVELL phy1\n");
14393 +               mii_mgr_read(CONFIG_MAC_TO_GIGAPHY_MODE_ADDR, 20, &phy_val);
14394 +               phy_val |= 1<<7; //Add delay to RX_CLK for RXD Outputs
14395 +               mii_mgr_write(CONFIG_MAC_TO_GIGAPHY_MODE_ADDR, 20, phy_val);
14396 +
14397 +               mii_mgr_read(CONFIG_MAC_TO_GIGAPHY_MODE_ADDR, 0, &phy_val);
14398 +               phy_val |= 1<<15; //PHY Software Reset
14399 +               mii_mgr_write(CONFIG_MAC_TO_GIGAPHY_MODE_ADDR, 0, phy_val);
14400 +        }else if (isVtssGigaPHY(1)) {
14401 +               mii_mgr_write(CONFIG_MAC_TO_GIGAPHY_MODE_ADDR, 31, 0x0001); //extended page
14402 +               mii_mgr_read(CONFIG_MAC_TO_GIGAPHY_MODE_ADDR, 28, &phy_val);
14403 +               printk("Vitesse phy skew: %x --> ", phy_val);
14404 +               phy_val |= (0x3<<12); // RGMII RX skew compensation= 2.0 ns
14405 +               phy_val &= ~(0x3<<14);// RGMII TX skew compensation= 0 ns
14406 +               printk("%x\n", phy_val);
14407 +               mii_mgr_write(CONFIG_MAC_TO_GIGAPHY_MODE_ADDR, 28, phy_val);
14408 +               mii_mgr_write(CONFIG_MAC_TO_GIGAPHY_MODE_ADDR, 31, 0x0000); //main registers
14409 +        }
14410 +
14411 +
14412 +#elif defined (CONFIG_P5_RMII_TO_MAC_MODE)
14413 +       *(unsigned long *)(RALINK_ETH_SW_BASE+0x3500) = 0x5e337;//(P5, Force mode, Link Up, 100Mbps, Full-Duplex, FC ON)
14414 +       *(unsigned long *)(0xb0000060) &= ~(1 << 9); //set RGMII to Normal mode
14415 +       *(unsigned long *)(SYSCFG1) &= ~(0x3 << 12); //GE1_MODE=RvMii Mode
14416 +       *(unsigned long *)(SYSCFG1) |= (0x2 << 12);
14417 +
14418 +#else // Port 5 Disabled //
14419 +        *(unsigned long *)(RALINK_ETH_SW_BASE+0x3500) = 0x8000;//link down
14420 +       *(unsigned long *)(0xb0000060) |= (1 << 9); //set RGMII to GPIO mode
14421 +#endif
14422 +#endif
14423 +
14424 +#if defined (CONFIG_P4_RGMII_TO_MAC_MODE)
14425 +       *(unsigned long *)(RALINK_ETH_SW_BASE+0x3400) = 0x5e33b;//(P4, Force mode, Link Up, 1000Mbps, Full-Duplex, FC ON)
14426 +       *(unsigned long *)(0xb0000060) &= ~(1 << 10); //set GE2 to Normal mode
14427 +       //rxclk_skew, txclk_skew = 0
14428 +       *(unsigned long *)(SYSCFG1) &= ~(0x3 << 14); //GE2_MODE=RGMii Mode
14429 +
14430 +#elif defined (CONFIG_P4_MII_TO_MAC_MODE)
14431 +       *(unsigned long *)(0xb0000060) &= ~(1 << 10); //set GE2 to Normal mode
14432 +       *(unsigned long *)(SYSCFG1) &= ~(0x3 << 14); //GE2_MODE=Mii Mode
14433 +       *(unsigned long *)(SYSCFG1) |= (0x1 << 14);
14434 +
14435 +#elif defined (CONFIG_P4_MAC_TO_PHY_MODE)
14436 +       *(unsigned long *)(0xb0000060) &= ~(1 << 10); //set GE2 to Normal mode
14437 +       *(unsigned long *)(0xb0000060) &= ~(3 << 7); //set MDIO to Normal mode
14438 +       *(unsigned long *)(SYSCFG1) &= ~(0x3 << 14); //GE2_MODE=RGMii Mode
14439 +
14440 +       enable_auto_negotiate(1);
14441 +
14442 +       if (isICPlusGigaPHY(2)) {
14443 +               mii_mgr_read(CONFIG_MAC_TO_GIGAPHY_MODE_ADDR2, 4, &phy_val);
14444 +               phy_val |= 1<<10; //enable pause ability
14445 +               mii_mgr_write(CONFIG_MAC_TO_GIGAPHY_MODE_ADDR2, 4, phy_val);
14446 +
14447 +               mii_mgr_read(CONFIG_MAC_TO_GIGAPHY_MODE_ADDR2, 0, &phy_val);
14448 +               phy_val |= 1<<9; //restart AN
14449 +               mii_mgr_write(CONFIG_MAC_TO_GIGAPHY_MODE_ADDR2, 0, phy_val);
14450 +       }else if (isMarvellGigaPHY(2)) {
14451 +#if defined (CONFIG_MT7620_FPGA)
14452 +               mii_mgr_read(CONFIG_MAC_TO_GIGAPHY_MODE_ADDR2, 9, &phy_val);
14453 +               phy_val &= ~(3<<8); //turn off 1000Base-T Advertisement  (9.9=1000Full, 9.8=1000Half)
14454 +               mii_mgr_write(CONFIG_MAC_TO_GIGAPHY_MODE_ADDR2, 9, phy_val);
14455 +#endif
14456 +               printk("Reset MARVELL phy2\n");
14457 +               mii_mgr_read(CONFIG_MAC_TO_GIGAPHY_MODE_ADDR2, 20, &phy_val);
14458 +               phy_val |= 1<<7; //Add delay to RX_CLK for RXD Outputs
14459 +               mii_mgr_write(CONFIG_MAC_TO_GIGAPHY_MODE_ADDR2, 20, phy_val);
14460 +
14461 +               mii_mgr_read(CONFIG_MAC_TO_GIGAPHY_MODE_ADDR2, 0, &phy_val);
14462 +               phy_val |= 1<<15; //PHY Software Reset
14463 +               mii_mgr_write(CONFIG_MAC_TO_GIGAPHY_MODE_ADDR2, 0, phy_val);
14464 +        }else if (isVtssGigaPHY(2)) {
14465 +               mii_mgr_write(CONFIG_MAC_TO_GIGAPHY_MODE_ADDR2, 31, 0x0001); //extended page
14466 +               mii_mgr_read(CONFIG_MAC_TO_GIGAPHY_MODE_ADDR2, 28, &phy_val);
14467 +               printk("Vitesse phy skew: %x --> ", phy_val);
14468 +               phy_val |= (0x3<<12); // RGMII RX skew compensation= 2.0 ns
14469 +               phy_val &= ~(0x3<<14);// RGMII TX skew compensation= 0 ns
14470 +               printk("%x\n", phy_val);
14471 +               mii_mgr_write(CONFIG_MAC_TO_GIGAPHY_MODE_ADDR2, 28, phy_val);
14472 +               mii_mgr_write(CONFIG_MAC_TO_GIGAPHY_MODE_ADDR2, 31, 0x0000); //main registers
14473 +        }
14474 +
14475 +#elif defined (CONFIG_P4_RMII_TO_MAC_MODE)
14476 +       *(unsigned long *)(RALINK_ETH_SW_BASE+0x3400) = 0x5e337;//(P5, Force mode, Link Up, 100Mbps, Full-Duplex, FC ON)
14477 +       *(unsigned long *)(0xb0000060) &= ~(1 << 10); //set GE2 to Normal mode
14478 +       *(unsigned long *)(SYSCFG1) &= ~(0x3 << 14); //GE1_MODE=RvMii Mode
14479 +       *(unsigned long *)(SYSCFG1) |= (0x2 << 14);
14480 +#elif defined (CONFIG_GE_RGMII_MT7530_P0_AN) || defined (CONFIG_GE_RGMII_MT7530_P4_AN)
14481 +#else // Port 4 Disabled //
14482 +        *(unsigned long *)(SYSCFG1) |= (0x3 << 14); //GE2_MODE=RJ45 Mode
14483 +       *(unsigned long *)(0xb0000060) |= (1 << 10); //set RGMII2 to GPIO mode
14484 +#endif
14485 +
14486 +}
14487 +#endif
14488 +
14489 +#if defined (CONFIG_RALINK_MT7628)
14490 +
14491 +void mt7628_ephy_init(void)
14492 +{
14493 +       int i;
14494 +       u32 phy_val;
14495 +       mii_mgr_write(0, 31, 0x2000); //change G2 page
14496 +       mii_mgr_write(0, 26, 0x0000);
14497 +
14498 +       for(i=0; i<5; i++){
14499 +               mii_mgr_write(i, 31, 0x8000); //change L0 page
14500 +               mii_mgr_write(i,  0, 0x3100);
14501 +
14502 +#if defined (CONFIG_RAETH_8023AZ_EEE)
14503 +               mii_mgr_read(i, 26, &phy_val);// EEE setting
14504 +               phy_val |= (1 << 5);
14505 +               mii_mgr_write(i, 26, phy_val);
14506 +#else
14507 +               //disable EEE
14508 +               mii_mgr_write(i, 13, 0x7);
14509 +               mii_mgr_write(i, 14, 0x3C);
14510 +               mii_mgr_write(i, 13, 0x4007);
14511 +               mii_mgr_write(i, 14, 0x0);
14512 +#endif
14513 +               mii_mgr_write(i, 30, 0xa000);
14514 +               mii_mgr_write(i, 31, 0xa000); // change L2 page
14515 +               mii_mgr_write(i, 16, 0x0606);
14516 +               mii_mgr_write(i, 23, 0x0f0e);
14517 +               mii_mgr_write(i, 24, 0x1610);
14518 +               mii_mgr_write(i, 30, 0x1f15);
14519 +               mii_mgr_write(i, 28, 0x6111);
14520 +
14521 +               mii_mgr_read(i, 4, &phy_val);
14522 +               phy_val |= (1 << 10);
14523 +               mii_mgr_write(i, 4, phy_val);
14524 +       }
14525 +
14526 +        //100Base AOI setting
14527 +       mii_mgr_write(0, 31, 0x5000);  //change G5 page
14528 +       mii_mgr_write(0, 19, 0x004a);
14529 +       mii_mgr_write(0, 20, 0x015a);
14530 +       mii_mgr_write(0, 21, 0x00ee);
14531 +       mii_mgr_write(0, 22, 0x0033);
14532 +       mii_mgr_write(0, 23, 0x020a);
14533 +       mii_mgr_write(0, 24, 0x0000);
14534 +       mii_mgr_write(0, 25, 0x024a);
14535 +       mii_mgr_write(0, 26, 0x035a);
14536 +       mii_mgr_write(0, 27, 0x02ee);
14537 +       mii_mgr_write(0, 28, 0x0233);
14538 +       mii_mgr_write(0, 29, 0x000a);
14539 +       mii_mgr_write(0, 30, 0x0000);
14540 +       /* Fix EPHY idle state abnormal behavior */
14541 +       mii_mgr_write(0, 31, 0x4000); //change G4 page
14542 +       mii_mgr_write(0, 29, 0x000d);
14543 +       mii_mgr_write(0, 30, 0x0500);
14544 +
14545 +}
14546 +
14547 +#endif
14548 +
14549 +
14550 +#if defined (CONFIG_RALINK_RT3052) || defined (CONFIG_RALINK_RT3352) || defined (CONFIG_RALINK_RT5350) || defined (CONFIG_RALINK_MT7628)
14551 +void rt305x_esw_init(void)
14552 +{
14553 +       int i=0;
14554 +       u32 phy_val=0, val=0;
14555 +#if defined (CONFIG_RT3052_ASIC)
14556 +       u32 phy_val2;
14557 +#endif
14558 +
14559 +#if defined (CONFIG_RT5350_ASIC)
14560 +       *(unsigned long *)(RALINK_ETH_SW_BASE+0x0168) = 0x17;
14561 +#endif
14562 +
14563 +       /*
14564 +        * FC_RLS_TH=200, FC_SET_TH=160
14565 +        * DROP_RLS=120, DROP_SET_TH=80
14566 +        */
14567 +        *(unsigned long *)(RALINK_ETH_SW_BASE+0x0008) = 0xC8A07850;
14568 +        *(unsigned long *)(RALINK_ETH_SW_BASE+0x00E4) = 0x00000000;
14569 +        *(unsigned long *)(RALINK_ETH_SW_BASE+0x0014) = 0x00405555;
14570 +        *(unsigned long *)(RALINK_ETH_SW_BASE+0x0050) = 0x00002001;
14571 +        *(unsigned long *)(RALINK_ETH_SW_BASE+0x0090) = 0x00007f7f;
14572 +        *(unsigned long *)(RALINK_ETH_SW_BASE+0x0098) = 0x00007f3f; //disable VLAN
14573 +        *(unsigned long *)(RALINK_ETH_SW_BASE+0x00CC) = 0x0002500c;
14574 +#ifndef CONFIG_UNH_TEST
14575 +        *(unsigned long *)(RALINK_ETH_SW_BASE+0x009C) = 0x0008a301; //hashing algorithm=XOR48, aging interval=300sec
14576 +#else
14577 +       /*
14578 +        * bit[30]:1    Backoff Algorithm Option: The latest one to pass UNH test
14579 +        * bit[29]:1    Length of Received Frame Check Enable
14580 +        * bit[8]:0     Enable collision 16 packet abort and late collision abort
14581 +        * bit[7:6]:01  Maximum Packet Length: 1518
14582 +        */
14583 +        *(unsigned long *)(RALINK_ETH_SW_BASE+0x009C) = 0x6008a241;
14584 +#endif
14585 +        *(unsigned long *)(RALINK_ETH_SW_BASE+0x008C) = 0x02404040;
14586 +#if defined (CONFIG_RT3052_ASIC) || defined (CONFIG_RT3352_ASIC) || defined (CONFIG_RT5350_ASIC) || defined (CONFIG_MT7628_ASIC)
14587 +        *(unsigned long *)(RALINK_ETH_SW_BASE+0x00C8) = 0x3f502b28; //Change polling Ext PHY Addr=0x1F
14588 +        *(unsigned long *)(RALINK_ETH_SW_BASE+0x0084) = 0x00000000;
14589 +        *(unsigned long *)(RALINK_ETH_SW_BASE+0x0110) = 0x7d000000; //1us cycle number=125 (FE's clock=125Mhz)
14590 +#elif defined (CONFIG_RT3052_FPGA) || defined (CONFIG_RT3352_FPGA) || defined (CONFIG_RT5350_FPGA) || defined (CONFIG_MT7628_FPGA)
14591 +        *(unsigned long *)(RALINK_ETH_SW_BASE+0x00C8) = 0x00f03ff9; //polling Ext PHY Addr=0x0, force port5 as 100F/D (disable auto-polling)
14592 +        *(unsigned long *)(RALINK_ETH_SW_BASE+0x0084) = 0xffdf1f00;
14593 +        *(unsigned long *)(RALINK_ETH_SW_BASE+0x0110) = 0x0d000000; //1us cycle number=13 (FE's clock=12.5Mhz)
14594 +
14595 +       /* In order to use 10M/Full on FPGA board. We configure phy capable to
14596 +        * 10M Full/Half duplex, so we can use auto-negotiation on PC side */
14597 +        for(i=0;i<5;i++){
14598 +           mii_mgr_write(i, 4, 0x0461);   //Capable of 10M Full/Half Duplex, flow control on/off
14599 +           mii_mgr_write(i, 0, 0xB100);   //reset all digital logic, except phy_reg
14600 +       }
14601 +#endif
14602 +
14603 +       /*
14604 +        * set port 5 force to 1000M/Full when connecting to switch or iNIC
14605 +        */
14606 +#if defined (CONFIG_P5_RGMII_TO_MAC_MODE)
14607 +       *(unsigned long *)(0xb0000060) &= ~(1 << 9); //set RGMII to Normal mode
14608 +        *(unsigned long *)(RALINK_ETH_SW_BASE+0x00C8) &= ~(1<<29); //disable port 5 auto-polling
14609 +        *(unsigned long *)(RALINK_ETH_SW_BASE+0x00C8) |= 0x3fff; //force 1000M full duplex
14610 +        *(unsigned long *)(RALINK_ETH_SW_BASE+0x00C8) &= ~(0xf<<20); //rxclk_skew, txclk_skew = 0
14611 +#elif defined (CONFIG_P5_MII_TO_MAC_MODE)
14612 +       *(unsigned long *)(0xb0000060) &= ~(1 << 9); //set RGMII to Normal mode
14613 +        *(unsigned long *)(RALINK_ETH_SW_BASE+0x00C8) &= ~(1<<29); //disable port 5 auto-polling
14614 +        *(unsigned long *)(RALINK_ETH_SW_BASE+0x00C8) &= ~(0x3fff);
14615 +        *(unsigned long *)(RALINK_ETH_SW_BASE+0x00C8) |= 0x3ffd; //force 100M full duplex
14616 +
14617 +#if defined (CONFIG_RALINK_RT3352)
14618 +        *(unsigned long *)(SYSCFG1) &= ~(0x3 << 12); //GE1_MODE=Mii Mode
14619 +        *(unsigned long *)(SYSCFG1) |= (0x1 << 12);
14620 +#endif
14621 +
14622 +#elif defined (CONFIG_P5_MAC_TO_PHY_MODE)
14623 +       *(unsigned long *)(0xb0000060) &= ~(1 << 9); //set RGMII to Normal mode
14624 +       *(unsigned long *)(0xb0000060) &= ~(1 << 7); //set MDIO to Normal mode
14625 +#if defined (CONFIG_RT3052_ASIC) || defined (CONFIG_RT3352_ASIC)
14626 +       enable_auto_negotiate(1);
14627 +#endif
14628 +        if (isMarvellGigaPHY(1)) {
14629 +#if defined (CONFIG_RT3052_FPGA) || defined (CONFIG_RT3352_FPGA)
14630 +               mii_mgr_read(CONFIG_MAC_TO_GIGAPHY_MODE_ADDR, 9, &phy_val);
14631 +               phy_val &= ~(3<<8); //turn off 1000Base-T Advertisement  (9.9=1000Full, 9.8=1000Half)
14632 +               mii_mgr_write(CONFIG_MAC_TO_GIGAPHY_MODE_ADDR, 9, phy_val);
14633 +#endif
14634 +               printk("\n Reset MARVELL phy\n");
14635 +               mii_mgr_read(CONFIG_MAC_TO_GIGAPHY_MODE_ADDR, 20, &phy_val);
14636 +               phy_val |= 1<<7; //Add delay to RX_CLK for RXD Outputs
14637 +               mii_mgr_write(CONFIG_MAC_TO_GIGAPHY_MODE_ADDR, 20, phy_val);
14638 +
14639 +               mii_mgr_read(CONFIG_MAC_TO_GIGAPHY_MODE_ADDR, 0, &phy_val);
14640 +               phy_val |= 1<<15; //PHY Software Reset
14641 +               mii_mgr_write(CONFIG_MAC_TO_GIGAPHY_MODE_ADDR, 0, phy_val);
14642 +        }
14643 +       if (isVtssGigaPHY(1)) {
14644 +               mii_mgr_write(CONFIG_MAC_TO_GIGAPHY_MODE_ADDR, 31, 0x0001); //extended page
14645 +               mii_mgr_read(CONFIG_MAC_TO_GIGAPHY_MODE_ADDR, 28, &phy_val);
14646 +               printk("Vitesse phy skew: %x --> ", phy_val);
14647 +               phy_val |= (0x3<<12); // RGMII RX skew compensation= 2.0 ns
14648 +               phy_val &= ~(0x3<<14);// RGMII TX skew compensation= 0 ns
14649 +               printk("%x\n", phy_val);
14650 +               mii_mgr_write(CONFIG_MAC_TO_GIGAPHY_MODE_ADDR, 28, phy_val);
14651 +               mii_mgr_write(CONFIG_MAC_TO_GIGAPHY_MODE_ADDR, 31, 0x0000); //main registers
14652 +        }
14653 +
14654 +#elif defined (CONFIG_P5_RMII_TO_MAC_MODE)
14655 +       *(unsigned long *)(0xb0000060) &= ~(1 << 9); //set RGMII to Normal mode
14656 +        *(unsigned long *)(RALINK_ETH_SW_BASE+0x00C8) &= ~(1<<29); //disable port 5 auto-polling
14657 +        *(unsigned long *)(RALINK_ETH_SW_BASE+0x00C8) &= ~(0x3fff);
14658 +        *(unsigned long *)(RALINK_ETH_SW_BASE+0x00C8) |= 0x3ffd; //force 100M full duplex
14659 +
14660 +#if defined (CONFIG_RALINK_RT3352)
14661 +       *(unsigned long *)(SYSCFG1) &= ~(0x3 << 12); //GE1_MODE=RvMii Mode
14662 +        *(unsigned long *)(SYSCFG1) |= (0x2 << 12);
14663 +#endif
14664 +#else // Port 5 Disabled //
14665 +
14666 +#if defined (CONFIG_RALINK_RT3052)
14667 +        *(unsigned long *)(RALINK_ETH_SW_BASE+0x00C8) &= ~(1 << 29); //port5 auto polling disable
14668 +        *(unsigned long *)(0xb0000060) |= (1 << 7); //set MDIO to GPIO mode (GPIO22-GPIO23)
14669 +        *(unsigned long *)(0xb0000060) |= (1 << 9); //set RGMII to GPIO mode (GPIO41-GPIO50)
14670 +        *(unsigned long *)(0xb0000674) = 0xFFF; //GPIO41-GPIO50 output mode
14671 +        *(unsigned long *)(0xb000067C) = 0x0; //GPIO41-GPIO50 output low
14672 +#elif defined (CONFIG_RALINK_RT3352)
14673 +        *(unsigned long *)(RALINK_ETH_SW_BASE+0x00C8) &= ~(1 << 29); //port5 auto polling disable
14674 +       *(unsigned long *)(0xb0000060) |= (1 << 7); //set MDIO to GPIO mode (GPIO22-GPIO23)
14675 +        *(unsigned long *)(0xb0000624) = 0xC0000000; //GPIO22-GPIO23 output mode
14676 +        *(unsigned long *)(0xb000062C) = 0xC0000000; //GPIO22-GPIO23 output high
14677 +
14678 +        *(unsigned long *)(0xb0000060) |= (1 << 9); //set RGMII to GPIO mode (GPIO24-GPIO35)
14679 +       *(unsigned long *)(0xb000064C) = 0xFFF; //GPIO24-GPIO35 output mode
14680 +        *(unsigned long *)(0xb0000654) = 0xFFF; //GPIO24-GPIO35 output high
14681 +#elif defined (CONFIG_RALINK_RT5350) || defined (CONFIG_RALINK_MT7628)
14682 +       /* do nothing */
14683 +#endif
14684 +#endif // CONFIG_P5_RGMII_TO_MAC_MODE //
14685 +
14686 +
14687 +#if defined (CONFIG_RT3052_ASIC)
14688 +       rw_rf_reg(0, 0, &phy_val);
14689 +        phy_val = phy_val >> 4;
14690 +
14691 +        if(phy_val > 0x5) {
14692 +
14693 +            rw_rf_reg(0, 26, &phy_val);
14694 +            phy_val2 = (phy_val | (0x3 << 5));
14695 +            rw_rf_reg(1, 26, &phy_val2);
14696 +
14697 +                       // reset EPHY
14698 +                       val = sysRegRead(RSTCTRL);
14699 +                       val = val | RALINK_EPHY_RST;
14700 +                       sysRegWrite(RSTCTRL, val);
14701 +                       val = val & ~(RALINK_EPHY_RST);
14702 +                       sysRegWrite(RSTCTRL, val);
14703 +
14704 +            rw_rf_reg(1, 26, &phy_val);
14705 +
14706 +            //select local register
14707 +            mii_mgr_write(0, 31, 0x8000);
14708 +            for(i=0;i<5;i++){
14709 +                mii_mgr_write(i, 26, 0x1600);   //TX10 waveform coefficient //LSB=0 disable PHY
14710 +                mii_mgr_write(i, 29, 0x7058);   //TX100/TX10 AD/DA current bias
14711 +                mii_mgr_write(i, 30, 0x0018);   //TX100 slew rate control
14712 +            }
14713 +
14714 +            //select global register
14715 +            mii_mgr_write(0, 31, 0x0);
14716 +            mii_mgr_write(0,  1, 0x4a40); //enlarge agcsel threshold 3 and threshold 2
14717 +            mii_mgr_write(0,  2, 0x6254); //enlarge agcsel threshold 5 and threshold 4
14718 +            mii_mgr_write(0,  3, 0xa17f); //enlarge agcsel threshold 6
14719 +//#define ENABLE_LDPS
14720 +#if defined (ENABLE_LDPS)
14721 +            mii_mgr_write(0, 12, 0x7eaa);
14722 +            mii_mgr_write(0, 22, 0x252f); //tune TP_IDL tail and head waveform, enable power down slew rate control
14723 +#else
14724 +            mii_mgr_write(0, 12, 0x0);
14725 +            mii_mgr_write(0, 22, 0x052f);
14726 +#endif
14727 +            mii_mgr_write(0, 14, 0x65);   //longer TP_IDL tail length
14728 +            mii_mgr_write(0, 16, 0x0684); //increased squelch pulse count threshold.
14729 +            mii_mgr_write(0, 17, 0x0fe0); //set TX10 signal amplitude threshold to minimum
14730 +            mii_mgr_write(0, 18, 0x40ba); //set squelch amplitude to higher threshold
14731 +            mii_mgr_write(0, 27, 0x2fce); //set PLL/Receive bias current are calibrated
14732 +            mii_mgr_write(0, 28, 0xc410); //change PLL/Receive bias current to internal(RT3350)
14733 +            mii_mgr_write(0, 29, 0x598b); //change PLL bias current to internal(RT3052_MP3)
14734 +           mii_mgr_write(0, 31, 0x8000); //select local register
14735 +
14736 +            for(i=0;i<5;i++){
14737 +                //LSB=1 enable PHY
14738 +                mii_mgr_read(i, 26, &phy_val);
14739 +                phy_val |= 0x0001;
14740 +                mii_mgr_write(i, 26, phy_val);
14741 +            }
14742 +       } else {
14743 +           //select local register
14744 +            mii_mgr_write(0, 31, 0x8000);
14745 +            for(i=0;i<5;i++){
14746 +                mii_mgr_write(i, 26, 0x1600);   //TX10 waveform coefficient //LSB=0 disable PHY
14747 +                mii_mgr_write(i, 29, 0x7058);   //TX100/TX10 AD/DA current bias
14748 +                mii_mgr_write(i, 30, 0x0018);   //TX100 slew rate control
14749 +            }
14750 +
14751 +            //select global register
14752 +            mii_mgr_write(0, 31, 0x0);
14753 +            mii_mgr_write(0,  1, 0x4a40); //enlarge agcsel threshold 3 and threshold 2
14754 +            mii_mgr_write(0,  2, 0x6254); //enlarge agcsel threshold 5 and threshold 4
14755 +            mii_mgr_write(0,  3, 0xa17f); //enlarge agcsel threshold 6
14756 +            mii_mgr_write(0, 14, 0x65);   //longer TP_IDL tail length
14757 +            mii_mgr_write(0, 16, 0x0684); //increased squelch pulse count threshold.
14758 +            mii_mgr_write(0, 17, 0x0fe0); //set TX10 signal amplitude threshold to minimum
14759 +            mii_mgr_write(0, 18, 0x40ba); //set squelch amplitude to higher threshold
14760 +            mii_mgr_write(0, 22, 0x052f); //tune TP_IDL tail and head waveform
14761 +            mii_mgr_write(0, 27, 0x2fce); //set PLL/Receive bias current are calibrated
14762 +            mii_mgr_write(0, 28, 0xc410); //change PLL/Receive bias current to internal(RT3350)
14763 +           mii_mgr_write(0, 29, 0x598b); //change PLL bias current to internal(RT3052_MP3)
14764 +           mii_mgr_write(0, 31, 0x8000); //select local register
14765 +
14766 +            for(i=0;i<5;i++){
14767 +                //LSB=1 enable PHY
14768 +                mii_mgr_read(i, 26, &phy_val);
14769 +                phy_val |= 0x0001;
14770 +                mii_mgr_write(i, 26, phy_val);
14771 +            }
14772 +       }
14773 +#elif defined (CONFIG_RT3352_ASIC)
14774 +       //PHY IOT
14775 +       // reset EPHY
14776 +       val = sysRegRead(RSTCTRL);
14777 +       val = val | RALINK_EPHY_RST;
14778 +       sysRegWrite(RSTCTRL, val);
14779 +       val = val & ~(RALINK_EPHY_RST);
14780 +       sysRegWrite(RSTCTRL, val);
14781 +
14782 +       //select local register
14783 +        mii_mgr_write(0, 31, 0x8000);
14784 +        for(i=0;i<5;i++){
14785 +            mii_mgr_write(i, 26, 0x1600);   //TX10 waveform coefficient //LSB=0 disable PHY
14786 +            mii_mgr_write(i, 29, 0x7016);   //TX100/TX10 AD/DA current bias
14787 +            mii_mgr_write(i, 30, 0x0038);   //TX100 slew rate control
14788 +        }
14789 +
14790 +        //select global register
14791 +        mii_mgr_write(0, 31, 0x0);
14792 +        mii_mgr_write(0,  1, 0x4a40); //enlarge agcsel threshold 3 and threshold 2
14793 +        mii_mgr_write(0,  2, 0x6254); //enlarge agcsel threshold 5 and threshold 4
14794 +        mii_mgr_write(0,  3, 0xa17f); //enlarge agcsel threshold 6
14795 +        mii_mgr_write(0, 12, 0x7eaa);
14796 +        mii_mgr_write(0, 14, 0x65);   //longer TP_IDL tail length
14797 +        mii_mgr_write(0, 16, 0x0684); //increased squelch pulse count threshold.
14798 +        mii_mgr_write(0, 17, 0x0fe0); //set TX10 signal amplitude threshold to minimum
14799 +        mii_mgr_write(0, 18, 0x40ba); //set squelch amplitude to higher threshold
14800 +        mii_mgr_write(0, 22, 0x253f); //tune TP_IDL tail and head waveform, enable power down slew rate control
14801 +        mii_mgr_write(0, 27, 0x2fda); //set PLL/Receive bias current are calibrated
14802 +        mii_mgr_write(0, 28, 0xc410); //change PLL/Receive bias current to internal(RT3350)
14803 +        mii_mgr_write(0, 29, 0x598b); //change PLL bias current to internal(RT3052_MP3)
14804 +        mii_mgr_write(0, 31, 0x8000); //select local register
14805 +
14806 +        for(i=0;i<5;i++){
14807 +            //LSB=1 enable PHY
14808 +            mii_mgr_read(i, 26, &phy_val);
14809 +            phy_val |= 0x0001;
14810 +            mii_mgr_write(i, 26, phy_val);
14811 +        }
14812 +
14813 +#elif defined (CONFIG_RT5350_ASIC)
14814 +       //PHY IOT
14815 +       // reset EPHY
14816 +       val = sysRegRead(RSTCTRL);
14817 +       val = val | RALINK_EPHY_RST;
14818 +       sysRegWrite(RSTCTRL, val);
14819 +       val = val & ~(RALINK_EPHY_RST);
14820 +       sysRegWrite(RSTCTRL, val);
14821 +
14822 +       //select local register
14823 +        mii_mgr_write(0, 31, 0x8000);
14824 +        for(i=0;i<5;i++){
14825 +            mii_mgr_write(i, 26, 0x1600);   //TX10 waveform coefficient //LSB=0 disable PHY
14826 +            mii_mgr_write(i, 29, 0x7015);   //TX100/TX10 AD/DA current bias
14827 +            mii_mgr_write(i, 30, 0x0038);   //TX100 slew rate control
14828 +        }
14829 +
14830 +        //select global register
14831 +        mii_mgr_write(0, 31, 0x0);
14832 +        mii_mgr_write(0,  1, 0x4a40); //enlarge agcsel threshold 3 and threshold 2
14833 +        mii_mgr_write(0,  2, 0x6254); //enlarge agcsel threshold 5 and threshold 4
14834 +        mii_mgr_write(0,  3, 0xa17f); //enlarge agcsel threshold 6
14835 +        mii_mgr_write(0, 12, 0x7eaa);
14836 +        mii_mgr_write(0, 14, 0x65);   //longer TP_IDL tail length
14837 +        mii_mgr_write(0, 16, 0x0684); //increased squelch pulse count threshold.
14838 +        mii_mgr_write(0, 17, 0x0fe0); //set TX10 signal amplitude threshold to minimum
14839 +        mii_mgr_write(0, 18, 0x40ba); //set squelch amplitude to higher threshold
14840 +        mii_mgr_write(0, 22, 0x253f); //tune TP_IDL tail and head waveform, enable power down slew rate control
14841 +        mii_mgr_write(0, 27, 0x2fda); //set PLL/Receive bias current are calibrated
14842 +        mii_mgr_write(0, 28, 0xc410); //change PLL/Receive bias current to internal(RT3350)
14843 +        mii_mgr_write(0, 29, 0x598b); //change PLL bias current to internal(RT3052_MP3)
14844 +        mii_mgr_write(0, 31, 0x8000); //select local register
14845 +
14846 +        for(i=0;i<5;i++){
14847 +            //LSB=1 enable PHY
14848 +            mii_mgr_read(i, 26, &phy_val);
14849 +            phy_val |= 0x0001;
14850 +            mii_mgr_write(i, 26, phy_val);
14851 +        }
14852 +#elif defined (CONFIG_MT7628_ASIC)
14853 +/*INIT MT7628 PHY HERE*/
14854 +       val = sysRegRead(RT2880_AGPIOCFG_REG);
14855 +#if defined (CONFIG_ETH_ONE_PORT_ONLY)
14856 +       val |= (MT7628_P0_EPHY_AIO_EN | MT7628_P1_EPHY_AIO_EN | MT7628_P2_EPHY_AIO_EN | MT7628_P3_EPHY_AIO_EN | MT7628_P4_EPHY_AIO_EN);
14857 +       val = val & ~(MT7628_P0_EPHY_AIO_EN);
14858 +#else
14859 +       val = val & ~(MT7628_P0_EPHY_AIO_EN | MT7628_P1_EPHY_AIO_EN | MT7628_P2_EPHY_AIO_EN | MT7628_P3_EPHY_AIO_EN | MT7628_P4_EPHY_AIO_EN);
14860 +#endif
14861 +       if ((*((volatile u32 *)(RALINK_SYSCTL_BASE + 0x8))) & 0x10000)
14862 +               val &= ~0x1f0000;
14863 +       sysRegWrite(RT2880_AGPIOCFG_REG, val);
14864 +
14865 +       val = sysRegRead(RSTCTRL);
14866 +       val = val | RALINK_EPHY_RST;
14867 +       sysRegWrite(RSTCTRL, val);
14868 +       val = val & ~(RALINK_EPHY_RST);
14869 +       sysRegWrite(RSTCTRL, val);
14870 +
14871 +
14872 +       val = sysRegRead(RALINK_SYSCTL_BASE + 0x64);
14873 +#if defined (CONFIG_ETH_ONE_PORT_ONLY)
14874 +       val &= 0xf003f003;
14875 +       val |= 0x05540554;
14876 +       sysRegWrite(RALINK_SYSCTL_BASE + 0x64, val); // set P0 EPHY LED mode
14877 +#else
14878 +       val &= 0xf003f003;
14879 +       sysRegWrite(RALINK_SYSCTL_BASE + 0x64, val); // set P0~P4 EPHY LED mode
14880 +#endif
14881 +
14882 +       udelay(5000);
14883 +       mt7628_ephy_init();
14884 +
14885 +#endif
14886 +}
14887 +#endif
14888 +
14889 +#if defined (CONFIG_ARCH_MT7623)       /* TODO: just for bring up, should be removed!!! */
14890 +void mt7623_pinmux_set(void)
14891 +{
14892 +       unsigned long regValue;
14893 +
14894 +       //printk("[mt7623_pinmux_set]start\n");
14895 +       /* Pin277: ESW_RST (1) */
14896 +       regValue = le32_to_cpu(*(volatile u_long *)(0xf0005ad0));
14897 +       regValue &= ~(BITS(6,8));
14898 +       regValue |= BIT(6);
14899 +       *(volatile u_long *)(0xf0005ad0) = regValue;
14900 +
14901 +       /* Pin262: G2_TXEN (1) */
14902 +       regValue = le32_to_cpu(*(volatile u_long *)(0xf0005aa0));
14903 +       regValue &= ~(BITS(6,8));
14904 +       regValue |= BIT(6);
14905 +       *(volatile u_long *)(0xf0005aa0) = regValue;
14906 +       /* Pin263: G2_TXD3 (1) */
14907 +       regValue = le32_to_cpu(*(volatile u_long *)(0xf0005aa0));
14908 +       regValue &= ~(BITS(9,11));
14909 +       regValue |= BIT(9);
14910 +       *(volatile u_long *)(0xf0005aa0) = regValue;
14911 +       /* Pin264: G2_TXD2 (1) */
14912 +       regValue = le32_to_cpu(*(volatile u_long *)(0xf0005aa0));
14913 +       regValue &= ~(BITS(12,14));
14914 +       regValue |= BIT(12);
14915 +       *(volatile u_long *)(0xf0005aa0) = regValue;
14916 +       /* Pin265: G2_TXD1 (1) */
14917 +       regValue = le32_to_cpu(*(volatile u_long *)(0xf0005ab0));
14918 +       regValue &= ~(BITS(0,2));
14919 +       regValue |= BIT(0);
14920 +       *(volatile u_long *)(0xf0005ab0) = regValue;
14921 +       /* Pin266: G2_TXD0 (1) */
14922 +       regValue = le32_to_cpu(*(volatile u_long *)(0xf0005ab0));
14923 +       regValue &= ~(BITS(3,5));
14924 +       regValue |= BIT(3);
14925 +       *(volatile u_long *)(0xf0005ab0) = regValue;
14926 +       /* Pin267: G2_TXC (1) */
14927 +       regValue = le32_to_cpu(*(volatile u_long *)(0xf0005ab0));
14928 +       regValue &= ~(BITS(6,8));
14929 +       regValue |= BIT(6);
14930 +       *(volatile u_long *)(0xf0005ab0) = regValue;
14931 +       /* Pin268: G2_RXC (1) */
14932 +       regValue = le32_to_cpu(*(volatile u_long *)(0xf0005ab0));
14933 +       regValue &= ~(BITS(9,11));
14934 +       regValue |= BIT(9);
14935 +       *(volatile u_long *)(0xf0005ab0) = regValue;
14936 +       /* Pin269: G2_RXD0 (1) */
14937 +       regValue = le32_to_cpu(*(volatile u_long *)(0xf0005ab0));
14938 +       regValue &= ~(BITS(12,14));
14939 +       regValue |= BIT(12);
14940 +       *(volatile u_long *)(0xf0005ab0) = regValue;
14941 +       /* Pin270: G2_RXD1 (1) */
14942 +       regValue = le32_to_cpu(*(volatile u_long *)(0xf0005ac0));
14943 +       regValue &= ~(BITS(0,2));
14944 +       regValue |= BIT(0);
14945 +       *(volatile u_long *)(0xf0005ac0) = regValue;
14946 +       /* Pin271: G2_RXD2 (1) */
14947 +       regValue = le32_to_cpu(*(volatile u_long *)(0xf0005ac0));
14948 +       regValue &= ~(BITS(3,5));
14949 +       regValue |= BIT(3);
14950 +       *(volatile u_long *)(0xf0005ac0) = regValue;
14951 +       /* Pin272: G2_RXD3 (1) */
14952 +       regValue = le32_to_cpu(*(volatile u_long *)(0xf0005ac0));
14953 +       regValue &= ~(BITS(6,8));
14954 +       regValue |= BIT(6);
14955 +       *(volatile u_long *)(0xf0005ac0) = regValue;
14956 +       /* Pin274: G2_RXDV (1) */
14957 +       regValue = le32_to_cpu(*(volatile u_long *)(0xf0005ac0));
14958 +       regValue &= ~(BITS(12,14));
14959 +       regValue |= BIT(12);
14960 +       *(volatile u_long *)(0xf0005ac0) = regValue;
14961 +
14962 +       /* Pin275: MDC (1) */
14963 +       regValue = le32_to_cpu(*(volatile u_long *)(0xf0005ad0));
14964 +       regValue &= ~(BITS(0,2));
14965 +       regValue |= BIT(0);
14966 +       *(volatile u_long *)(0xf0005ad0) = regValue;
14967 +       /* Pin276: MDIO (1) */
14968 +       regValue = le32_to_cpu(*(volatile u_long *)(0xf0005ad0));
14969 +       regValue &= ~(BITS(3,5));
14970 +       regValue |= BIT(3);
14971 +       *(volatile u_long *)(0xf0005ad0) = regValue;
14972 +       //printk("[mt7623_pinmux_set]end\n");
14973 +}
14974 +
14975 +void wait_loop(void) {
14976 +       int i,j;
14977 +       int read_data;
14978 +       j =0;
14979 +       while (j< 10) {
14980 +               for(i = 0; i<32; i = i+1){
14981 +                       read_data = *(volatile u_long *)(0xFB110610);
14982 +               }
14983 +               j++;
14984 +       }
14985 +}
14986 +
14987 +void trgmii_calibration_7623(void) {
14988 +
14989 +       unsigned int  tap_a[5]; // minumum delay for all correct
14990 +       unsigned int  tap_b[5]; // maximum delay for all correct
14991 +       unsigned int  final_tap[5];
14992 +       unsigned int  bslip_en;
14993 +       unsigned int  rxc_step_size;
14994 +       unsigned int  rxd_step_size;
14995 +       unsigned int  read_data;
14996 +       unsigned int  tmp;
14997 +       unsigned int  rd_wd;
14998 +       int  i;
14999 +       unsigned int err_cnt[5];
15000 +       unsigned int init_toggle_data;
15001 +       unsigned int err_flag[5];
15002 +       unsigned int err_total_flag;
15003 +       unsigned int training_word;
15004 +       unsigned int rd_tap;
15005 +
15006 +       u32  TRGMII_7623_base;
15007 +       u32  TRGMII_7623_RD_0;
15008 +       u32  TRGMII_RD_1;
15009 +       u32  TRGMII_RD_2;
15010 +       u32  TRGMII_RD_3;
15011 +       u32  TRGMII_RXCTL;
15012 +       u32  TRGMII_RCK_CTRL;
15013 +       u32 TRGMII_7530_base;
15014 +       TRGMII_7623_base = 0xFB110300;
15015 +       TRGMII_7623_RD_0 = TRGMII_7623_base + 0x10;
15016 +       TRGMII_RCK_CTRL = TRGMII_7623_base;
15017 +       rxd_step_size =0x1;
15018 +       rxc_step_size =0x4;
15019 +       init_toggle_data = 0x00000055;
15020 +       training_word    = 0x000000AC;
15021 +
15022 +       //printk("Calibration begin ........");
15023 +       *(volatile u_long *)(TRGMII_7623_base +0x04) &= 0x3fffffff;   // RX clock gating in MT7623
15024 +       *(volatile u_long *)(TRGMII_7623_base +0x00) |= 0x80000000;   // Assert RX  reset in MT7623
15025 +       *(volatile u_long *)(TRGMII_7623_base +0x78) |= 0x00002000;   // Set TX OE edge in  MT7623
15026 +       *(volatile u_long *)(TRGMII_7623_base +0x04) |= 0xC0000000;   // Disable RX clock gating in MT7623
15027 +       *(volatile u_long *)(TRGMII_7623_base )      &= 0x7fffffff;   // Release RX reset in MT7623
15028 +       //printk("Check Point 1 .....\n");
15029 +       for (i = 0 ; i<5 ; i++) {
15030 +               *(volatile u_long *)(TRGMII_7623_RD_0 + i*8) |= 0x80000000;   // Set bslip_en = 1
15031 +       }
15032 +
15033 +       //printk("Enable Training Mode in MT7530\n");
15034 +       mii_mgr_read(0x1F,0x7A40,&read_data);
15035 +       read_data |= 0xc0000000;
15036 +       mii_mgr_write(0x1F,0x7A40,read_data);  //Enable Training Mode in MT7530
15037 +       err_total_flag = 0;
15038 +       //printk("Adjust RXC delay in MT7623\n");
15039 +       read_data =0x0;
15040 +       while (err_total_flag == 0 && read_data != 0x68) {
15041 +               //printk("2nd Enable EDGE CHK in MT7623\n");
15042 +               /* Enable EDGE CHK in MT7623*/
15043 +               for (i = 0 ; i<5 ; i++) {
15044 +                       tmp = *(volatile u_long *)(TRGMII_7623_RD_0 + i*8);
15045 +                       tmp |= 0x40000000;
15046 +                       *(volatile u_long *)(TRGMII_7623_RD_0 + i*8) = tmp & 0x4fffffff;
15047 +               }
15048 +               wait_loop();
15049 +               err_total_flag = 1;
15050 +               for  (i = 0 ; i<5 ; i++) {
15051 +                       err_cnt[i] = ((*(volatile u_long *)(TRGMII_7623_RD_0 + i*8)) >> 8)  & 0x0000000f;
15052 +                       rd_wd = ((*(volatile u_long *)(TRGMII_7623_RD_0 + i*8)) >> 16)  & 0x000000ff;
15053 +                       //printk("ERR_CNT = %d, RD_WD =%x\n",err_cnt[i],rd_wd);
15054 +                       if ( err_cnt[i] !=0 ) {
15055 +                               err_flag[i] = 1;
15056 +                       }
15057 +                       else if (rd_wd != 0x55) {
15058 +                               err_flag[i] = 1;
15059 +                       }
15060 +                       else {
15061 +                               err_flag[i] = 0;
15062 +                       }
15063 +                       err_total_flag = err_flag[i] &  err_total_flag;
15064 +               }
15065 +
15066 +               //printk("2nd Disable EDGE CHK in MT7623\n");
15067 +               /* Disable EDGE CHK in MT7623*/
15068 +               for (i = 0 ; i<5 ; i++) {
15069 +                       tmp = *(volatile u_long *)(TRGMII_7623_RD_0 + i*8);
15070 +                       tmp |= 0x40000000;
15071 +                       *(volatile u_long *)(TRGMII_7623_RD_0 + i*8) = tmp & 0x4fffffff;
15072 +               }
15073 +               wait_loop();
15074 +               //printk("2nd Disable EDGE CHK in MT7623\n");
15075 +               /* Adjust RXC delay */
15076 +               *(volatile u_long *)(TRGMII_7623_base +0x00) |= 0x80000000;   // Assert RX  reset in MT7623
15077 +               *(volatile u_long *)(TRGMII_7623_base +0x04) &= 0x3fffffff;   // RX clock gating in MT7623
15078 +               read_data = *(volatile u_long *)(TRGMII_7623_base);
15079 +               if (err_total_flag == 0) {
15080 +                 tmp = (read_data & 0x0000007f) + rxc_step_size;
15081 +                 //printk(" RXC delay = %d\n", tmp);
15082 +                 read_data >>= 8;
15083 +                 read_data &= 0xffffff80;
15084 +                 read_data |= tmp;
15085 +                 read_data <<=8;
15086 +                 read_data &= 0xffffff80;
15087 +                 read_data |=tmp;
15088 +                 *(volatile u_long *)(TRGMII_7623_base)  =   read_data;
15089 +               }
15090 +                 read_data &=0x000000ff;
15091 +                 *(volatile u_long *)(TRGMII_7623_base )      &= 0x7fffffff;   // Release RX reset in MT7623
15092 +                 *(volatile u_long *)(TRGMII_7623_base +0x04) |= 0xC0000000;   // Disable RX clock gating in MT7623
15093 +                 for (i = 0 ; i<5 ; i++) {
15094 +                       *(volatile u_long *)(TRGMII_7623_RD_0 + i*8) =  (*(volatile u_long *)(TRGMII_7623_RD_0 + i*8)) | 0x80000000;  // Set bslip_en = ~bit_slip_en
15095 +                 }
15096 +       }
15097 +       //printk("Finish RXC Adjustment while loop\n");
15098 +       //printk("Read RD_WD MT7623\n");
15099 +       /* Read RD_WD MT7623*/
15100 +       for  (i = 0 ; i<5 ; i++) {
15101 +               rd_tap=0;
15102 +               while (err_flag[i] != 0) {
15103 +                       /* Enable EDGE CHK in MT7623*/
15104 +                       tmp = *(volatile u_long *)(TRGMII_7623_RD_0 + i*8);
15105 +                       tmp |= 0x40000000;
15106 +                       *(volatile u_long *)(TRGMII_7623_RD_0 + i*8) = tmp & 0x4fffffff;
15107 +                       wait_loop();
15108 +                       read_data = *(volatile u_long *)(TRGMII_7623_RD_0 + i*8);
15109 +                       err_cnt[i] = (read_data >> 8)  & 0x0000000f;     // Read MT7623 Errcnt
15110 +                       rd_wd = (read_data >> 16)  & 0x000000ff;
15111 +                       if (err_cnt[i] != 0 || rd_wd !=0x55){
15112 +                          err_flag [i] =  1;
15113 +                       }
15114 +                       else {
15115 +                          err_flag[i] =0;
15116 +                       }
15117 +                       /* Disable EDGE CHK in MT7623*/
15118 +                       *(volatile u_long *)(TRGMII_7623_RD_0 + i*8) &= 0x4fffffff;
15119 +                       tmp |= 0x40000000;
15120 +                       *(volatile u_long *)(TRGMII_7623_RD_0 + i*8) = tmp & 0x4fffffff;
15121 +                       wait_loop();
15122 +                       //err_cnt[i] = ((read_data) >> 8)  & 0x0000000f;     // Read MT7623 Errcnt
15123 +                       if (err_flag[i] !=0) {
15124 +                           rd_tap    = (read_data & 0x0000007f) + rxd_step_size;                     // Add RXD delay in MT7623
15125 +                           read_data = (read_data & 0xffffff80) | rd_tap;
15126 +                           *(volatile u_long *)(TRGMII_7623_RD_0 + i*8) = read_data;
15127 +                           tap_a[i] = rd_tap;
15128 +                       } else {
15129 +                            rd_tap    = (read_data & 0x0000007f) + 4;
15130 +                           read_data = (read_data & 0xffffff80) | rd_tap;
15131 +                           *(volatile u_long *)(TRGMII_7623_RD_0 + i*8) = read_data;
15132 +                       }
15133 +                       //err_cnt[i] = (*(volatile u_long *)(TRGMII_7623_RD_0 + i*8) >> 8)  & 0x0000000f;     // Read MT7623 Errcnt
15134 +
15135 +               }
15136 +               //printk("%dth bit  Tap_a = %d\n", i, tap_a[i]);
15137 +       }
15138 +       //printk("Last While Loop\n");
15139 +       for  (i = 0 ; i<5 ; i++) {
15140 +               //printk(" Bit%d\n", i);
15141 +               rd_tap =0;
15142 +               while ((err_cnt[i] == 0) && (rd_tap !=128)) {
15143 +                       read_data = *(volatile u_long *)(TRGMII_7623_RD_0 + i*8);
15144 +                       rd_tap    = (read_data & 0x0000007f) + rxd_step_size;                     // Add RXD delay in MT7623
15145 +                       read_data = (read_data & 0xffffff80) | rd_tap;
15146 +                       *(volatile u_long *)(TRGMII_7623_RD_0 + i*8) = read_data;
15147 +                       /* Enable EDGE CHK in MT7623*/
15148 +                       tmp = *(volatile u_long *)(TRGMII_7623_RD_0 + i*8);
15149 +                       tmp |= 0x40000000;
15150 +                       *(volatile u_long *)(TRGMII_7623_RD_0 + i*8) = tmp & 0x4fffffff;
15151 +                       wait_loop();
15152 +                       err_cnt[i] = ((*(volatile u_long *)(TRGMII_7623_RD_0 + i*8)) >> 8)  & 0x0000000f;     // Read MT7623 Errcnt
15153 +                       /* Disable EDGE CHK in MT7623*/
15154 +                       tmp = *(volatile u_long *)(TRGMII_7623_RD_0 + i*8);
15155 +                       tmp |= 0x40000000;
15156 +                       *(volatile u_long *)(TRGMII_7623_RD_0 + i*8) = tmp & 0x4fffffff;
15157 +                       wait_loop();
15158 +                       //err_cnt[i] = ((*(volatile u_long *)(TRGMII_7623_RD_0 + i*8)) >> 8)  & 0x0000000f;     // Read MT7623 Errcnt
15159 +
15160 +               }
15161 +               tap_b[i] =   rd_tap;// -rxd_step_size;                                        // Record the max delay TAP_B
15162 +               //printk("tap_b[%d] is %d \n", i,tap_b[i]);
15163 +               final_tap[i] = (tap_a[i]+tap_b[i])/2;                                              //  Calculate RXD delay = (TAP_A + TAP_B)/2
15164 +               //printk("%dth bit Final Tap = %d\n", i, final_tap[i]);
15165 +               read_data = (read_data & 0xffffff80) | final_tap[i];
15166 +               *(volatile u_long *)(TRGMII_7623_RD_0 + i*8) = read_data;
15167 +       }
15168 +//     /*word alignment*/
15169 +//     mii_mgr_read(0x1F,0x7A50,&read_data);
15170 +//     read_data &= ~(0xff);
15171 +//     read_data |= 0xac;
15172 +//     mii_mgr_write(0x1F,0x7A50,read_data);
15173 +//     while (i <10) {
15174 +//             i++;
15175 +//             wait_loop();
15176 +//     }
15177 +//     /* Enable EDGE CHK in MT7623*/
15178 +//     for (i=0; i<5; i++) {
15179 +//             tmp = *(volatile u_long *)(TRGMII_7623_RD_0 + i*8);
15180 +//             tmp |= 0x40000000;
15181 +//             *(volatile u_long *)(TRGMII_7623_RD_0 + i*8) = tmp & 0x4fffffff;
15182 +//             wait_loop();
15183 +//             /* Disable EDGE CHK in MT7623*/
15184 +//             tmp = *(volatile u_long *)(TRGMII_7623_RD_0 + i*8);
15185 +//             tmp |= 0x40000000;
15186 +//             *(volatile u_long *)(TRGMII_7623_RD_0 + i*8) = tmp & 0x4fffffff;
15187 +//             wait_loop();
15188 +//             read_data = *(volatile u_long *)(TRGMII_7623_RD_0+i*8);
15189 +//             printk(" MT7623 training word = %x\n", read_data);
15190 +//     }
15191 +
15192 +
15193 +       mii_mgr_read(0x1F,0x7A40,&read_data);
15194 +       //printk(" MT7530 0x7A40 = %x\n", read_data);
15195 +       read_data &=0x3fffffff;
15196 +       mii_mgr_write(0x1F,0x7A40,read_data);
15197 +}
15198 +
15199 +
15200 +void trgmii_calibration_7530(void){
15201 +
15202 +       unsigned int  tap_a[5];
15203 +       unsigned int  tap_b[5];
15204 +       unsigned int  final_tap[5];
15205 +       unsigned int  bslip_en;
15206 +       unsigned int  rxc_step_size;
15207 +       unsigned int  rxd_step_size;
15208 +       unsigned int  read_data;
15209 +       unsigned int  tmp;
15210 +       int  i,j;
15211 +       unsigned int err_cnt[5];
15212 +       unsigned int rd_wd;
15213 +       unsigned int init_toggle_data;
15214 +       unsigned int err_flag[5];
15215 +       unsigned int err_total_flag;
15216 +       unsigned int training_word;
15217 +       unsigned int rd_tap;
15218 +
15219 +       u32  TRGMII_7623_base;
15220 +       u32  TRGMII_7530_RD_0;
15221 +       u32  TRGMII_RD_1;
15222 +       u32  TRGMII_RD_2;
15223 +       u32  TRGMII_RD_3;
15224 +       u32  TRGMII_RXCTL;
15225 +       u32  TRGMII_RCK_CTRL;
15226 +       u32 TRGMII_7530_base;
15227 +       u32 TRGMII_7530_TX_base;
15228 +       TRGMII_7623_base = 0xFB110300;
15229 +       TRGMII_7530_base = 0x7A00;
15230 +       TRGMII_7530_RD_0 = TRGMII_7530_base + 0x10;
15231 +       TRGMII_RCK_CTRL = TRGMII_7623_base;
15232 +       rxd_step_size = 0x1;
15233 +       rxc_step_size = 0x8;
15234 +       init_toggle_data = 0x00000055;
15235 +       training_word = 0x000000AC;
15236 +
15237 +       TRGMII_7530_TX_base = TRGMII_7530_base + 0x50;
15238 +
15239 +       //printk("Calibration begin ........\n");
15240 +       *(volatile u_long *)(TRGMII_7623_base + 0x40) |= 0x80000000;
15241 +       mii_mgr_read(0x1F, 0x7a10, &read_data);
15242 +       //printk("TRGMII_7530_RD_0 is %x\n", read_data);
15243 +
15244 +       mii_mgr_read(0x1F,TRGMII_7530_base+0x04,&read_data);
15245 +       read_data &= 0x3fffffff;
15246 +       mii_mgr_write(0x1F,TRGMII_7530_base+0x04,read_data);     // RX clock gating in MT7530
15247 +
15248 +       mii_mgr_read(0x1F,TRGMII_7530_base+0x78,&read_data);
15249 +       read_data |= 0x00002000;
15250 +       mii_mgr_write(0x1F,TRGMII_7530_base+0x78,read_data);     // Set TX OE edge in  MT7530
15251 +
15252 +       mii_mgr_read(0x1F,TRGMII_7530_base,&read_data);
15253 +       read_data |= 0x80000000;
15254 +       mii_mgr_write(0x1F,TRGMII_7530_base,read_data);          // Assert RX  reset in MT7530
15255 +
15256 +
15257 +       mii_mgr_read(0x1F,TRGMII_7530_base,&read_data);
15258 +       read_data &= 0x7fffffff;
15259 +       mii_mgr_write(0x1F,TRGMII_7530_base,read_data);          // Release RX reset in MT7530
15260 +
15261 +       mii_mgr_read(0x1F,TRGMII_7530_base+0x04,&read_data);
15262 +       read_data |= 0xC0000000;
15263 +       mii_mgr_write(0x1F,TRGMII_7530_base+0x04,read_data);     // Disable RX clock gating in MT7530
15264 +
15265 +       //printk("Enable Training Mode in MT7623\n");
15266 +       /*Enable Training Mode in MT7623*/
15267 +       *(volatile u_long *)(TRGMII_7623_base + 0x40) &= 0xbfffffff;
15268 +       *(volatile u_long *)(TRGMII_7623_base + 0x40) |= 0x80000000;
15269 +       *(volatile u_long *)(TRGMII_7623_base + 0x78) &= 0xfffff0ff;
15270 +       *(volatile u_long *)(TRGMII_7623_base + 0x78) |= 0x00000400;
15271 +
15272 +       err_total_flag =0;
15273 +       //printk("Adjust RXC delay in MT7530\n");
15274 +       read_data =0x0;
15275 +       while (err_total_flag == 0 && (read_data != 0x68)) {
15276 +               //printk("2nd Enable EDGE CHK in MT7530\n");
15277 +               /* Enable EDGE CHK in MT7530*/
15278 +               for (i = 0 ; i<5 ; i++) {
15279 +                       mii_mgr_read(0x1F,TRGMII_7530_RD_0+i*8,&read_data);
15280 +                       read_data |= 0x40000000;
15281 +                       read_data &= 0x4fffffff;
15282 +                       mii_mgr_write(0x1F,TRGMII_7530_RD_0+i*8,read_data);
15283 +                       wait_loop();
15284 +                       //printk("2nd Disable EDGE CHK in MT7530\n");
15285 +                       mii_mgr_read(0x1F,TRGMII_7530_RD_0+i*8,&err_cnt[i]);
15286 +                       //printk("***** MT7530 %dth bit ERR_CNT =%x\n",i, err_cnt[i]);
15287 +                       //printk("MT7530 %dth bit ERR_CNT =%x\n",i, err_cnt[i]);
15288 +                       err_cnt[i] >>= 8;
15289 +                       err_cnt[i] &= 0x0000ff0f;
15290 +                       rd_wd  = err_cnt[i] >> 8;
15291 +                       rd_wd &= 0x000000ff;
15292 +                       err_cnt[i] &= 0x0000000f;
15293 +                       //mii_mgr_read(0x1F,0x7a10,&read_data);
15294 +                       if ( err_cnt[i] !=0 ) {
15295 +                               err_flag[i] = 1;
15296 +                       }
15297 +                       else if (rd_wd != 0x55) {
15298 +                                err_flag[i] = 1;
15299 +                       } else {
15300 +                               err_flag[i] = 0;
15301 +                       }
15302 +                       if (i==0) {
15303 +                          err_total_flag = err_flag[i];
15304 +                       } else {
15305 +                          err_total_flag = err_flag[i] & err_total_flag;
15306 +                       }
15307 +               /* Disable EDGE CHK in MT7530*/
15308 +                       mii_mgr_read(0x1F,TRGMII_7530_RD_0+i*8,&read_data);
15309 +                       read_data |= 0x40000000;
15310 +                       read_data &= 0x4fffffff;
15311 +                       mii_mgr_write(0x1F,TRGMII_7530_RD_0+i*8,read_data);
15312 +                         wait_loop();
15313 +               }
15314 +               /*Adjust RXC delay*/
15315 +               if (err_total_flag ==0) {
15316 +                  mii_mgr_read(0x1F,TRGMII_7530_base,&read_data);
15317 +                  read_data |= 0x80000000;
15318 +                  mii_mgr_write(0x1F,TRGMII_7530_base,read_data);          // Assert RX  reset in MT7530
15319 +
15320 +                  mii_mgr_read(0x1F,TRGMII_7530_base+0x04,&read_data);
15321 +                  read_data &= 0x3fffffff;
15322 +                  mii_mgr_write(0x1F,TRGMII_7530_base+0x04,read_data);       // RX clock gating in MT7530
15323 +
15324 +                  mii_mgr_read(0x1F,TRGMII_7530_base,&read_data);
15325 +                  tmp = read_data;
15326 +                  tmp &= 0x0000007f;
15327 +                  tmp += rxc_step_size;
15328 +                  //printk("Current rxc delay = %d\n", tmp);
15329 +                  read_data &= 0xffffff80;
15330 +                  read_data |= tmp;
15331 +                  mii_mgr_write (0x1F,TRGMII_7530_base,read_data);
15332 +                  mii_mgr_read(0x1F,TRGMII_7530_base,&read_data);
15333 +                  //printk("Current RXC delay = %x\n", read_data);
15334 +
15335 +                  mii_mgr_read(0x1F,TRGMII_7530_base,&read_data);
15336 +                  read_data &= 0x7fffffff;
15337 +                  mii_mgr_write(0x1F,TRGMII_7530_base,read_data);          // Release RX reset in MT7530
15338 +
15339 +                  mii_mgr_read(0x1F,TRGMII_7530_base+0x04,&read_data);
15340 +                  read_data |= 0xc0000000;
15341 +                  mii_mgr_write(0x1F,TRGMII_7530_base+0x04,read_data);       // Disable RX clock gating in MT7530
15342 +                }
15343 +               read_data = tmp;
15344 +       }
15345 +       //printk("RXC delay is %d\n", tmp);
15346 +       //printk("Finish RXC Adjustment while loop\n");
15347 +
15348 +       //printk("Read RD_WD MT7530\n");
15349 +       /* Read RD_WD MT7530*/
15350 +       for  (i = 0 ; i<5 ; i++) {
15351 +               rd_tap = 0;
15352 +               while (err_flag[i] != 0) {
15353 +                       /* Enable EDGE CHK in MT7530*/
15354 +                       mii_mgr_read(0x1F,TRGMII_7530_RD_0+i*8,&read_data);
15355 +                       read_data |= 0x40000000;
15356 +                       read_data &= 0x4fffffff;
15357 +                       mii_mgr_write(0x1F,TRGMII_7530_RD_0+i*8,read_data);
15358 +                       wait_loop();
15359 +                       err_cnt[i] = (read_data >> 8) & 0x0000000f;
15360 +                       rd_wd = (read_data >> 16) & 0x000000ff;
15361 +                       //printk("##### %dth bit  ERR_CNT = %x RD_WD =%x ######\n", i, err_cnt[i],rd_wd);
15362 +                       if (err_cnt[i] != 0 || rd_wd !=0x55){
15363 +                          err_flag [i] =  1;
15364 +                       }
15365 +                       else {
15366 +                          err_flag[i] =0;
15367 +                       }
15368 +                       if (err_flag[i] !=0 ) {
15369 +                          rd_tap = (read_data & 0x0000007f) + rxd_step_size;                        // Add RXD delay in MT7530
15370 +                          read_data = (read_data & 0xffffff80) | rd_tap;
15371 +                          mii_mgr_write(0x1F,TRGMII_7530_RD_0+i*8,read_data);
15372 +                          tap_a[i] = rd_tap;
15373 +                       } else {
15374 +                          tap_a[i] = (read_data & 0x0000007f);                                     // Record the min delay TAP_A
15375 +                          rd_tap   =  tap_a[i] + 0x4;
15376 +                          read_data = (read_data & 0xffffff80) | rd_tap  ;
15377 +                          mii_mgr_write(0x1F,TRGMII_7530_RD_0+i*8,read_data);
15378 +                       }
15379 +
15380 +                       /* Disable EDGE CHK in MT7530*/
15381 +                       mii_mgr_read(0x1F,TRGMII_7530_RD_0+i*8,&read_data);
15382 +                       read_data |= 0x40000000;
15383 +                       read_data &= 0x4fffffff;
15384 +                       mii_mgr_write(0x1F,TRGMII_7530_RD_0+i*8,read_data);
15385 +                       wait_loop();
15386 +
15387 +               }
15388 +               //printk("%dth bit  Tap_a = %d\n", i, tap_a[i]);
15389 +       }
15390 +       //printk("Last While Loop\n");
15391 +       for  (i = 0 ; i<5 ; i++) {
15392 +       rd_tap =0;
15393 +               while (err_cnt[i] == 0 && (rd_tap!=128)) {
15394 +                       /* Enable EDGE CHK in MT7530*/
15395 +                       mii_mgr_read(0x1F,TRGMII_7530_RD_0+i*8,&read_data);
15396 +                       read_data |= 0x40000000;
15397 +                       read_data &= 0x4fffffff;
15398 +                       mii_mgr_write(0x1F,TRGMII_7530_RD_0+i*8,read_data);
15399 +                       wait_loop();
15400 +                       err_cnt[i] = (read_data >> 8) & 0x0000000f;
15401 +                       //rd_tap = (read_data & 0x0000007f) + 0x4;                                    // Add RXD delay in MT7530
15402 +                       if (err_cnt[i] == 0 && (rd_tap!=128)) {
15403 +                           rd_tap = (read_data & 0x0000007f) + rxd_step_size;                        // Add RXD delay in MT7530
15404 +                           read_data = (read_data & 0xffffff80) | rd_tap;
15405 +                           mii_mgr_write(0x1F,TRGMII_7530_RD_0+i*8,read_data);
15406 +                       }
15407 +                       /* Disable EDGE CHK in MT7530*/
15408 +                       mii_mgr_read(0x1F,TRGMII_7530_RD_0+i*8,&read_data);
15409 +                       read_data |= 0x40000000;
15410 +                       read_data &= 0x4fffffff;
15411 +                       mii_mgr_write(0x1F,TRGMII_7530_RD_0+i*8,read_data);
15412 +                       wait_loop();
15413 +               }
15414 +               tap_b[i] = rd_tap;// - rxd_step_size;                                     // Record the max delay TAP_B
15415 +               //printk("%dth bit  Tap_b = %d, ERR_CNT=%d\n", i, tap_b[i],err_cnt[i]);
15416 +               final_tap[i] = (tap_a[i]+tap_b[i])/2;                                     //  Calculate RXD delay = (TAP_A + TAP_B)/2
15417 +               //printk("%dth bit Final Tap = %d\n", i, final_tap[i]);
15418 +
15419 +               read_data = ( read_data & 0xffffff80) | final_tap[i];
15420 +               mii_mgr_write(0x1F,TRGMII_7530_RD_0+i*8,read_data);
15421 +       }
15422 +               *(volatile u_long *)(TRGMII_7623_base + 0x40) &=0x3fffffff;
15423 +
15424 +}
15425 +
15426 +void set_trgmii_325_delay_setting(void)
15427 +{
15428 +       /*mt7530 side*/
15429 +       *(volatile u_long *)(0xfb110300) = 0x80020050;
15430 +       *(volatile u_long *)(0xfb110304) = 0x00980000;
15431 +       *(volatile u_long *)(0xfb110300) = 0x40020050;
15432 +       *(volatile u_long *)(0xfb110304) = 0xc0980000;
15433 +       *(volatile u_long *)(0xfb110310) = 0x00000028;
15434 +       *(volatile u_long *)(0xfb110318) = 0x0000002e;
15435 +       *(volatile u_long *)(0xfb110320) = 0x0000002d;
15436 +       *(volatile u_long *)(0xfb110328) = 0x0000002b;
15437 +       *(volatile u_long *)(0xfb110330) = 0x0000002a;
15438 +       *(volatile u_long *)(0xfb110340) = 0x00020000;
15439 +       /*mt7530 side*/
15440 +       mii_mgr_write(31, 0x7a00, 0x10);
15441 +       mii_mgr_write(31, 0x7a10, 0x23);
15442 +       mii_mgr_write(31, 0x7a18, 0x27);
15443 +       mii_mgr_write(31, 0x7a20, 0x24);
15444 +       mii_mgr_write(31, 0x7a28, 0x29);
15445 +       mii_mgr_write(31, 0x7a30, 0x24);
15446 +
15447 +}
15448 +
15449 +
15450 +void setup_internal_gsw(void)
15451 +{
15452 +       u32     i;
15453 +       u32     regValue;
15454 +       u32     xtal_mode;
15455 +
15456 +       mt7623_pinmux_set();    /* TODO: just for bring up, should be removed!!! */
15457 +
15458 +#if 0
15459 +       /* GE1: RGMII mode setting */
15460 +       *(volatile u_long *)(0xfb110300) = 0x80020000;
15461 +       *(volatile u_long *)(0xfb110304) = 0x00980000;
15462 +       *(volatile u_long *)(0xfb110300) = 0x40020000;
15463 +       *(volatile u_long *)(0xfb110304) = 0xc0980000;
15464 +       *(volatile u_long *)(0xfb110310) = 0x00000041;
15465 +       *(volatile u_long *)(0xfb110318) = 0x00000044;
15466 +       *(volatile u_long *)(0xfb110320) = 0x00000043;
15467 +       *(volatile u_long *)(0xfb110328) = 0x00000042;
15468 +       *(volatile u_long *)(0xfb110330) = 0x00000042;
15469 +       *(volatile u_long *)(0xfb110340) = 0x00020000;
15470 +       *(volatile u_long *)(0xfb110390) &= 0xfffffff8; //RGMII mode
15471 +#else
15472 +       /* GE1: TRGMII mode setting */
15473 +       *(volatile u_long *)(0xfb110390) |= 0x00000002; //TRGMII mode
15474 +#endif
15475 +
15476 +       /*Todo: Hardware reset Switch*/
15477 +       /*Hardware reset Switch*/
15478 +#if defined(CONFIG_ARCH_MT7623)
15479 +       regValue = *(volatile u_long *)(0xfb00000c);
15480 +       /*MT7530 Reset. Flows for MT7623 and MT7683 are both excuted.*/
15481 +       /* Should Modify this section if EFUSE is ready*/
15482 +       /*For MT7683 reset MT7530*/
15483 +       if(!(regValue & (1<<16)))
15484 +       {
15485 +               *(volatile u_long *)(0xf0005520) &= ~(1<<1);
15486 +               udelay(1000);
15487 +               *(volatile u_long *)(0xf0005520) |= (1<<1);
15488 +               mdelay(100);
15489 +       }
15490 +       //printk("Assert MT7623 RXC reset\n");
15491 +       *(volatile u_long *)(0xfb110300) |= 0x80000000;   // Assert MT7623 RXC reset
15492 +        /*For MT7623 reset MT7530*/
15493 +       *(volatile u_long *)(RALINK_SYSCTL_BASE + 0x34) |= (0x1 << 2);
15494 +       udelay(1000);
15495 +       *(volatile u_long *)(RALINK_SYSCTL_BASE + 0x34) &= ~(0x1 << 2);
15496 +       mdelay(100);
15497 +#endif
15498 +
15499 +#if defined (CONFIG_GE1_RGMII_FORCE_1000) || defined (CONFIG_GE1_TRGMII_FORCE_1200) || defined (CONFIG_GE1_TRGMII_FORCE_2000) || defined (CONFIG_GE1_TRGMII_FORCE_2600)
15500 +       for(i=0;i<=4;i++)
15501 +        {
15502 +               //turn off PHY
15503 +               mii_mgr_read(i, 0x0 ,&regValue);
15504 +              regValue |= (0x1<<11);
15505 +              mii_mgr_write(i, 0x0, regValue);
15506 +       }
15507 +        mii_mgr_write(31, 0x7000, 0x3); //reset switch
15508 +        udelay(100);
15509 +
15510 +#if defined (CONFIG_MT7621_ASIC) || defined (CONFIG_ARCH_MT7623)
15511 +#if 0
15512 +       if((sysRegRead(0xbe00000c)&0xFFFF)==0x0101) {
15513 +               sysRegWrite(RALINK_ETH_SW_BASE+0x100, 0x2105e30b);//(GE1, Force 1000M/FD, FC ON)
15514 +               mii_mgr_write(31, 0x3600, 0x5e30b);
15515 +       } else
15516 +#endif
15517 +       {
15518 +               sysRegWrite(RALINK_ETH_SW_BASE+0x100, 0x2105e33b);//(GE1, Force 1000M/FD, FC ON)
15519 +               mii_mgr_write(31, 0x3600, 0x5e33b);
15520 +               mii_mgr_read(31, 0x3600 ,&regValue);
15521 +       }
15522 +#endif
15523 +       sysRegWrite(RALINK_ETH_SW_BASE+0x200, 0x00008000);//(GE2, Link down)
15524 +#endif
15525 +
15526 +#if defined (CONFIG_GE1_RGMII_FORCE_1000) || defined (CONFIG_GE1_TRGMII_FORCE_1200) || defined (CONFIG_GE1_TRGMII_FORCE_2000) || defined (CONFIG_GE1_TRGMII_FORCE_2600)
15527 +       //regValue = 0x117ccf; //Enable Port 6, P5 as GMAC5, P5 disable*/
15528 +       mii_mgr_read(31, 0x7804 ,&regValue);
15529 +       regValue &= ~(1<<8); //Enable Port 6
15530 +       regValue |= (1<<6); //Disable Port 5
15531 +       regValue |= (1<<13); //Port 5 as GMAC, no Internal PHY
15532 +
15533 +#if defined (CONFIG_RAETH_GMAC2)
15534 +       //RGMII2=Normal mode
15535 +       *(volatile u_long *)(RALINK_SYSCTL_BASE + 0x60) &= ~(0x1 << 15);
15536 +
15537 +       //GMAC2= RGMII mode
15538 +       *(volatile u_long *)(SYSCFG1) &= ~(0x3 << 14);
15539 +       mii_mgr_write(31, 0x3500, 0x56300); //MT7530 P5 AN, we can ignore this setting??????
15540 +       sysRegWrite(RALINK_ETH_SW_BASE+0x200, 0x21056300);//(GE2, auto-polling)
15541 +       enable_auto_negotiate(0);//set polling address
15542 +
15543 +       /* set MT7530 Port 5 to PHY 0/4 mode */
15544 +#if defined (CONFIG_GE_RGMII_INTERNAL_P0_AN)
15545 +       regValue &= ~((1<<13)|(1<<6));
15546 +       regValue |= ((1<<7)|(1<<16)|(1<<20));
15547 +#elif defined (CONFIG_GE_RGMII_INTERNAL_P4_AN)
15548 +       regValue &= ~((1<<13)|(1<<6)|(1<<20));
15549 +       regValue |= ((1<<7)|(1<<16));
15550 +#endif
15551 +       /*Set MT7530 phy direct access mode**/
15552 +       regValue &= ~(1<<5);
15553 +
15554 +       //sysRegWrite(GDMA2_FWD_CFG, 0x20710000);
15555 +#endif
15556 +       regValue |= (1<<16);//change HW-TRAP
15557 +       printk("change HW-TRAP to 0x%x\n",regValue);
15558 +       mii_mgr_write(31, 0x7804 ,regValue);
15559 +#endif
15560 +       mii_mgr_read(31, 0x7800, &regValue);
15561 +       regValue = (regValue >> 9) & 0x3;
15562 +       if(regValue == 0x3)//25Mhz Xtal
15563 +               xtal_mode = 1;
15564 +       else if(regValue == 0x2) //40Mhz
15565 +               xtal_mode = 2;
15566 +       else
15567 +               xtal_mode = 3;
15568 +
15569 +       if(xtal_mode == 1) { //25Mhz Xtal
15570 +               /* do nothing */
15571 +       } else if(xtal_mode = 2) { //40Mhz
15572 +               mii_mgr_write(0, 13, 0x1f);  // disable MT7530 core clock
15573 +               mii_mgr_write(0, 14, 0x410);
15574 +               mii_mgr_write(0, 13, 0x401f);
15575 +               mii_mgr_write(0, 14, 0x0);
15576 +
15577 +               mii_mgr_write(0, 13, 0x1f);  // disable MT7530 PLL
15578 +               mii_mgr_write(0, 14, 0x40d);
15579 +               mii_mgr_write(0, 13, 0x401f);
15580 +               mii_mgr_write(0, 14, 0x2020);
15581 +
15582 +               mii_mgr_write(0, 13, 0x1f);  // for MT7530 core clock = 500Mhz
15583 +               mii_mgr_write(0, 14, 0x40e);
15584 +               mii_mgr_write(0, 13, 0x401f);
15585 +               mii_mgr_write(0, 14, 0x119);
15586 +
15587 +               mii_mgr_write(0, 13, 0x1f);  // enable MT7530 PLL
15588 +               mii_mgr_write(0, 14, 0x40d);
15589 +               mii_mgr_write(0, 13, 0x401f);
15590 +               mii_mgr_write(0, 14, 0x2820);
15591 +
15592 +               udelay(20); //suggest by CD
15593 +
15594 +               mii_mgr_write(0, 13, 0x1f);  // enable MT7530 core clock
15595 +               mii_mgr_write(0, 14, 0x410);
15596 +               mii_mgr_write(0, 13, 0x401f);
15597 +       }else {//20MHz
15598 +               /*TODO*/
15599 +       }
15600 +
15601 +#if defined (CONFIG_GE1_TRGMII_FORCE_1200) && defined (CONFIG_MT7621_ASIC)
15602 +       mii_mgr_write(0, 14, 0x3); /*TRGMII*/
15603 +#else
15604 +       mii_mgr_write(0, 14, 0x1);  /*RGMII*/
15605 +/* set MT7530 central align */
15606 +        mii_mgr_read(31, 0x7830, &regValue);
15607 +        regValue &= ~1;
15608 +        regValue |= 1<<1;
15609 +        mii_mgr_write(31, 0x7830, regValue);
15610 +
15611 +        mii_mgr_read(31, 0x7a40, &regValue);
15612 +        regValue &= ~(1<<30);
15613 +        mii_mgr_write(31, 0x7a40, regValue);
15614 +
15615 +        regValue = 0x855;
15616 +        mii_mgr_write(31, 0x7a78, regValue);
15617 +
15618 +#endif
15619 +       mii_mgr_write(31, 0x7b00, 0x104);  //delay setting for 10/1000M
15620 +       mii_mgr_write(31, 0x7b04, 0x10);  //delay setting for 10/1000M
15621 +
15622 +       /*Tx Driving*/
15623 +       mii_mgr_write(31, 0x7a54, 0x88);  //lower GE1 driving
15624 +       mii_mgr_write(31, 0x7a5c, 0x88);  //lower GE1 driving
15625 +       mii_mgr_write(31, 0x7a64, 0x88);  //lower GE1 driving
15626 +       mii_mgr_write(31, 0x7a6c, 0x88);  //lower GE1 driving
15627 +       mii_mgr_write(31, 0x7a74, 0x88);  //lower GE1 driving
15628 +       mii_mgr_write(31, 0x7a7c, 0x88);  //lower GE1 driving
15629 +       mii_mgr_write(31, 0x7810, 0x11);  //lower GE2 driving
15630 +       /*Set MT7623/MT7683 TX Driving*/
15631 +       *(volatile u_long *)(0xfb110354) = 0x88;
15632 +       *(volatile u_long *)(0xfb11035c) = 0x88;
15633 +       *(volatile u_long *)(0xfb110364) = 0x88;
15634 +       *(volatile u_long *)(0xfb11036c) = 0x88;
15635 +       *(volatile u_long *)(0xfb110374) = 0x88;
15636 +       *(volatile u_long *)(0xfb11037c) = 0x88;
15637 +#if defined (CONFIG_GE2_RGMII_AN)
15638 +       *(volatile u_long *)(0xf0005f00) = 0xe00; //Set GE2 driving and slew rate
15639 +#else
15640 +       *(volatile u_long *)(0xf0005f00) = 0xa00; //Set GE2 driving and slew rate
15641 +#endif
15642 +       *(volatile u_long *)(0xf00054c0) = 0x5;   //set GE2 TDSEL
15643 +       *(volatile u_long *)(0xf0005ed0) = 0;     //set GE2 TUNE
15644 +
15645 +       /* TRGMII Clock */
15646 +//     printk("Set TRGMII mode clock stage 1\n");
15647 +       mii_mgr_write(0, 13, 0x1f);
15648 +       mii_mgr_write(0, 14, 0x404);
15649 +       mii_mgr_write(0, 13, 0x401f);
15650 +       if (xtal_mode == 1){ //25MHz
15651 +#if defined (CONFIG_GE1_TRGMII_FORCE_2900)
15652 +               mii_mgr_write(0, 14, 0x1d00); // 362.5MHz
15653 +#elif defined (CONFIG_GE1_TRGMII_FORCE_2600)
15654 +               mii_mgr_write(0, 14, 0x1a00); // 325MHz
15655 +#elif defined (CONFIG_GE1_TRGMII_FORCE_2000)
15656 +               mii_mgr_write(0, 14, 0x1400); //250MHz
15657 +#elif defined (CONFIG_GE1_RGMII_FORCE_1000)
15658 +               mii_mgr_write(0, 14, 0x00a0); //125MHz
15659 +#endif
15660 +       }else if(xtal_mode == 2){//40MHz
15661 +#if defined (CONFIG_GE1_TRGMII_FORCE_2900)
15662 +               mii_mgr_write(0, 14, 0x1220); // 362.5MHz
15663 +#elif defined (CONFIG_GE1_TRGMII_FORCE_2600)
15664 +               mii_mgr_write(0, 14, 0x1040); // 325MHz
15665 +#elif defined (CONFIG_GE1_TRGMII_FORCE_2000)
15666 +               mii_mgr_write(0, 14, 0x0c80); //250MHz
15667 +#elif defined (CONFIG_GE1_RGMII_FORCE_1000)
15668 +               mii_mgr_write(0, 14, 0x0640); //125MHz
15669 +#endif
15670 +       }
15671 +//     printk("Set TRGMII mode clock stage 2\n");
15672 +       mii_mgr_write(0, 13, 0x1f);
15673 +       mii_mgr_write(0, 14, 0x405);
15674 +       mii_mgr_write(0, 13, 0x401f);
15675 +       mii_mgr_write(0, 14, 0x0);
15676 +
15677 +//     printk("Set TRGMII mode clock stage 3\n");
15678 +       mii_mgr_write(0, 13, 0x1f);
15679 +       mii_mgr_write(0, 14, 0x409);
15680 +       mii_mgr_write(0, 13, 0x401f);
15681 +       mii_mgr_write(0, 14, 0x0087);
15682 +
15683 +//     printk("Set TRGMII mode clock stage 4\n");
15684 +       mii_mgr_write(0, 13, 0x1f);
15685 +       mii_mgr_write(0, 14, 0x40a);
15686 +       mii_mgr_write(0, 13, 0x401f);
15687 +       mii_mgr_write(0, 14, 0x0087);
15688 +
15689 +//     printk("Set TRGMII mode clock stage 5\n");
15690 +       mii_mgr_write(0, 13, 0x1f);
15691 +       mii_mgr_write(0, 14, 0x403);
15692 +       mii_mgr_write(0, 13, 0x401f);
15693 +       mii_mgr_write(0, 14, 0x1800);
15694 +
15695 +//     printk("Set TRGMII mode clock stage 6\n");
15696 +       mii_mgr_write(0, 13, 0x1f);
15697 +       mii_mgr_write(0, 14, 0x403);
15698 +       mii_mgr_write(0, 13, 0x401f);
15699 +       mii_mgr_write(0, 14, 0x1c00);
15700 +
15701 +//     printk("Set TRGMII mode clock stage 7\n");
15702 +       mii_mgr_write(0, 13, 0x1f);
15703 +       mii_mgr_write(0, 14, 0x401);
15704 +       mii_mgr_write(0, 13, 0x401f);
15705 +       mii_mgr_write(0, 14, 0xc020);
15706 +
15707 +//     printk("Set TRGMII mode clock stage 8\n");
15708 +       mii_mgr_write(0, 13, 0x1f);
15709 +       mii_mgr_write(0, 14, 0x406);
15710 +       mii_mgr_write(0, 13, 0x401f);
15711 +       mii_mgr_write(0, 14, 0xa030);
15712 +
15713 +//     printk("Set TRGMII mode clock stage 9\n");
15714 +       mii_mgr_write(0, 13, 0x1f);
15715 +       mii_mgr_write(0, 14, 0x406);
15716 +       mii_mgr_write(0, 13, 0x401f);
15717 +       mii_mgr_write(0, 14, 0xa038);
15718 +
15719 +       udelay(120); // for MT7623 bring up test
15720 +
15721 +//     printk("Set TRGMII mode clock stage 10\n");
15722 +       mii_mgr_write(0, 13, 0x1f);
15723 +       mii_mgr_write(0, 14, 0x410);
15724 +       mii_mgr_write(0, 13, 0x401f);
15725 +       mii_mgr_write(0, 14, 0x3);
15726 +
15727 +//     printk("Set TRGMII mode clock stage 11\n");
15728 +
15729 +       mii_mgr_read(31, 0x7830 ,&regValue);
15730 +       regValue &=0xFFFFFFFC;
15731 +       regValue |=0x00000001;
15732 +       mii_mgr_write(31, 0x7830, regValue);
15733 +
15734 +//     printk("Set TRGMII mode clock stage 12\n");
15735 +       mii_mgr_read(31, 0x7a40 ,&regValue);
15736 +       regValue &= ~(0x1<<30);
15737 +       regValue &= ~(0x1<<28);
15738 +       mii_mgr_write(31, 0x7a40, regValue);
15739 +
15740 +       //mii_mgr_write(31, 0x7a78, 0x855);
15741 +       mii_mgr_write(31, 0x7a78, 0x55);
15742 +//     printk(" Adjust MT7530 TXC delay\n");
15743 +       udelay(100); // for mt7623 bring up test
15744 +
15745 +//     printk(" Release MT7623 RXC Reset\n");
15746 +       *(volatile u_long *)(0xfb110300) &= 0x7fffffff;   // Release MT7623 RXC reset
15747 +       //disable EEE
15748 +       for(i=0;i<=4;i++)
15749 +       {
15750 +           mii_mgr_write(i, 13, 0x7);
15751 +           mii_mgr_write(i, 14, 0x3C);
15752 +           mii_mgr_write(i, 13, 0x4007);
15753 +           mii_mgr_write(i, 14, 0x0);
15754 +       }
15755 +
15756 +       //Disable EEE 10Base-Te:
15757 +       for(i=0;i<=4;i++)
15758 +       {
15759 +           mii_mgr_write(i, 13, 0x1f);
15760 +           mii_mgr_write(i, 14, 0x027b);
15761 +           mii_mgr_write(i, 13, 0x401f);
15762 +           mii_mgr_write(i, 14, 0x1177);
15763 +       }
15764 +
15765 +       for(i=0;i<=4;i++)
15766 +        {
15767 +       //turn on PHY
15768 +                mii_mgr_read(i, 0x0 ,&regValue);
15769 +               regValue &= ~(0x1<<11);
15770 +               mii_mgr_write(i, 0x0, regValue);
15771 +       }
15772 +
15773 +       for(i=0;i<=4;i++) {
15774 +               mii_mgr_read(i, 4, &regValue);
15775 +                regValue |= (3<<7); //turn on 100Base-T Advertisement
15776 +               mii_mgr_write(i, 4, regValue);
15777 +
15778 +               mii_mgr_read(i, 9, &regValue);
15779 +                regValue |= (3<<8); //turn on 1000Base-T Advertisement
15780 +                mii_mgr_write(i, 9, regValue);
15781 +
15782 +               //restart AN
15783 +               mii_mgr_read(i, 0, &regValue);
15784 +               regValue |= (1 << 9);
15785 +               mii_mgr_write(i, 0, regValue);
15786 +       }
15787 +
15788 +       mii_mgr_read(31, 0x7808 ,&regValue);
15789 +        regValue |= (3<<16); //Enable INTR
15790 +       mii_mgr_write(31, 0x7808 ,regValue);
15791 +}
15792 +
15793 +void mt7623_ethifsys_init(void)
15794 +{
15795 +#define TRGPLL_CON0             (0xF0209280)
15796 +#define TRGPLL_CON1             (0xF0209284)
15797 +#define TRGPLL_CON2             (0xF0209288)
15798 +#define TRGPLL_PWR_CON0         (0xF020928C)
15799 +#define ETHPLL_CON0             (0xF0209290)
15800 +#define ETHPLL_CON1             (0xF0209294)
15801 +#define ETHPLL_CON2             (0xF0209298)
15802 +#define ETHPLL_PWR_CON0         (0xF020929C)
15803 +#define ETH_PWR_CON             (0xF00062A0)
15804 +#define HIF_PWR_CON             (0xF00062A4)
15805 +
15806 +        u32 temp, pwr_ack_status;
15807 +        /*=========================================================================*/
15808 +        /* Enable ETHPLL & TRGPLL*/
15809 +        /*=========================================================================*/
15810 +        /* xPLL PWR ON*/
15811 +        temp = sysRegRead(ETHPLL_PWR_CON0);
15812 +        sysRegWrite(ETHPLL_PWR_CON0, temp | 0x1);
15813 +
15814 +        temp = sysRegRead(TRGPLL_PWR_CON0);
15815 +        sysRegWrite(TRGPLL_PWR_CON0, temp | 0x1);
15816 +
15817 +        udelay(5); /* wait for xPLL_PWR_ON ready (min delay is 1us)*/
15818 +
15819 +        /* xPLL ISO Disable*/
15820 +        temp = sysRegRead(ETHPLL_PWR_CON0);
15821 +        sysRegWrite(ETHPLL_PWR_CON0, temp & ~0x2);
15822 +
15823 +        temp = sysRegRead(TRGPLL_PWR_CON0);
15824 +        sysRegWrite(TRGPLL_PWR_CON0, temp & ~0x2);
15825 +
15826 +        /* xPLL Frequency Set*/
15827 +        temp = sysRegRead(ETHPLL_CON0);
15828 +        sysRegWrite(ETHPLL_CON0, temp | 0x1);
15829 +#if defined (CONFIG_GE1_TRGMII_FORCE_2900)
15830 +       temp = sysRegRead(TRGPLL_CON0);
15831 +       sysRegWrite(TRGPLL_CON0,  temp | 0x1);
15832 +#elif defined (CONFIG_GE1_TRGMII_FORCE_2600)
15833 +        sysRegWrite(TRGPLL_CON1,  0xB2000000);
15834 +        temp = sysRegRead(TRGPLL_CON0);
15835 +        sysRegWrite(TRGPLL_CON0, temp | 0x1);
15836 +#elif defined (CONFIG_GE1_TRGMII_FORCE_2000)
15837 +        sysRegWrite(TRGPLL_CON1, 0xCCEC4EC5);
15838 +        sysRegWrite(TRGPLL_CON0,  0x121);
15839 +#endif
15840 +        udelay(40); /* wait for PLL stable (min delay is 20us)*/
15841 +
15842 +
15843 +       /*=========================================================================*/
15844 +       /* Power on ETHDMASYS and HIFSYS*/
15845 +       /*=========================================================================*/
15846 +       /* Power on ETHDMASYS*/
15847 +       sysRegWrite(0xF0006000, 0x0b160001);
15848 +       pwr_ack_status = (sysRegRead(ETH_PWR_CON) & 0x0000f000) >> 12;
15849 +
15850 +       if(pwr_ack_status == 0x0) {
15851 +               printk("ETH already turn on and power on flow will be skipped...\n");
15852 +       }else {
15853 +               temp = sysRegRead(ETH_PWR_CON)  ;
15854 +               sysRegWrite(ETH_PWR_CON, temp | 0x4);          /* PWR_ON*/
15855 +               temp = sysRegRead(ETH_PWR_CON)  ;
15856 +               sysRegWrite(ETH_PWR_CON, temp | 0x8);          /* PWR_ON_S*/
15857 +
15858 +               udelay(5); /* wait power settle time (min delay is 1us)*/
15859 +
15860 +               temp = sysRegRead(ETH_PWR_CON)  ;
15861 +               sysRegWrite(ETH_PWR_CON, temp & ~0x10);      /* PWR_CLK_DIS*/
15862 +               temp = sysRegRead(ETH_PWR_CON)  ;
15863 +               sysRegWrite(ETH_PWR_CON, temp & ~0x2);        /* PWR_ISO*/
15864 +               temp = sysRegRead(ETH_PWR_CON)  ;
15865 +               sysRegWrite(ETH_PWR_CON, temp & ~0x100);   /* SRAM_PDN 0*/
15866 +               temp = sysRegRead(ETH_PWR_CON)  ;
15867 +               sysRegWrite(ETH_PWR_CON, temp & ~0x200);   /* SRAM_PDN 1*/
15868 +               temp = sysRegRead(ETH_PWR_CON)  ;
15869 +               sysRegWrite(ETH_PWR_CON, temp & ~0x400);   /* SRAM_PDN 2*/
15870 +               temp = sysRegRead(ETH_PWR_CON)  ;
15871 +               sysRegWrite(ETH_PWR_CON, temp & ~0x800);   /* SRAM_PDN 3*/
15872 +
15873 +               udelay(5); /* wait SRAM settle time (min delay is 1Us)*/
15874 +
15875 +               temp = sysRegRead(ETH_PWR_CON)  ;
15876 +               sysRegWrite(ETH_PWR_CON, temp | 0x1);          /* PWR_RST_B*/
15877 +       }
15878 +
15879 +       /* Power on HIFSYS*/
15880 +       pwr_ack_status = (sysRegRead(HIF_PWR_CON) & 0x0000f000) >> 12;
15881 +       if(pwr_ack_status == 0x0) {
15882 +               printk("HIF already turn on and power on flow will be skipped...\n");
15883 +       }
15884 +       else {
15885 +               temp = sysRegRead(HIF_PWR_CON)  ;
15886 +               sysRegWrite(HIF_PWR_CON, temp | 0x4);          /* PWR_ON*/
15887 +               temp = sysRegRead(HIF_PWR_CON)  ;
15888 +               sysRegWrite(HIF_PWR_CON, temp | 0x8);          /* PWR_ON_S*/
15889 +
15890 +               udelay(5); /* wait power settle time (min delay is 1us)*/
15891 +
15892 +               temp = sysRegRead(HIF_PWR_CON)  ;
15893 +               sysRegWrite(HIF_PWR_CON, temp & ~0x10);      /* PWR_CLK_DIS*/
15894 +               temp = sysRegRead(HIF_PWR_CON)  ;
15895 +               sysRegWrite(HIF_PWR_CON, temp & ~0x2);        /* PWR_ISO*/
15896 +               temp = sysRegRead(HIF_PWR_CON)  ;
15897 +               sysRegWrite(HIF_PWR_CON, temp & ~0x100);   /* SRAM_PDN 0*/
15898 +               temp = sysRegRead(HIF_PWR_CON)  ;
15899 +               sysRegWrite(HIF_PWR_CON, temp & ~0x200);   /* SRAM_PDN 1*/
15900 +               temp = sysRegRead(HIF_PWR_CON)  ;
15901 +               sysRegWrite(HIF_PWR_CON, temp & ~0x400);   /* SRAM_PDN 2*/
15902 +               temp = sysRegRead(HIF_PWR_CON)  ;
15903 +               sysRegWrite(HIF_PWR_CON, temp & ~0x800);   /* SRAM_PDN 3*/
15904 +
15905 +               udelay(5); /* wait SRAM settle time (min delay is 1Us)*/
15906 +
15907 +               temp = sysRegRead(HIF_PWR_CON)  ;
15908 +               sysRegWrite(HIF_PWR_CON, temp | 0x1);          /* PWR_RST_B*/
15909 +       }
15910 +
15911 +       /* Release mt7530 reset */
15912 +       temp = le32_to_cpu(*(volatile u_long *)(0xfb000034));
15913 +       temp &= ~(BIT(2));
15914 +       *(volatile u_long *)(0xfb000034) = temp;
15915 +}
15916 +#endif
15917 +
15918 +/**
15919 + * ra2882eth_init - Module Init code
15920 + *
15921 + * Called by kernel to register net_device
15922 + *
15923 + */
15924 +
15925 +static int fe_probe(struct platform_device *pdev)
15926 +{
15927 +       int ret;
15928 +       struct net_device *dev = alloc_etherdev(sizeof(END_DEVICE));
15929 +
15930 +        fe_irq = platform_get_irq(pdev, 0);
15931 +
15932 +#ifdef CONFIG_RALINK_VISTA_BASIC
15933 +       int sw_id=0;
15934 +       mii_mgr_read(29, 31, &sw_id);
15935 +       is_switch_175c = (sw_id == 0x175c) ? 1:0;
15936 +#endif
15937 +
15938 +       if (!dev)
15939 +               return -ENOMEM;
15940 +
15941 +       strcpy(dev->name, DEV_NAME);
15942 +       printk("%s:%s[%d]%d\n", __FILE__, __func__, __LINE__, fe_irq);
15943 +       dev->irq  = fe_irq;
15944 +       dev->addr_len = 6;
15945 +       dev->base_addr = RALINK_FRAME_ENGINE_BASE;
15946 +
15947 +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,35)
15948 +       rather_probe(dev);
15949 +#else
15950 +       dev->init =  rather_probe;
15951 +#endif
15952 +       ra2880_setup_dev_fptable(dev);
15953 +
15954 +       /* net_device structure Init */
15955 +       ethtool_init(dev);
15956 +       printk("Ralink APSoC Ethernet Driver Initilization. %s  %d rx/tx descriptors allocated, mtu = %d!\n", RAETH_VERSION, NUM_RX_DESC, dev->mtu);
15957 +#ifdef CONFIG_RAETH_NAPI
15958 +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,35)
15959 +       printk("NAPI enable, Tx Ring = %d, Rx Ring = %d\n", NUM_TX_DESC, NUM_RX_DESC);
15960 +#else
15961 +       printk("NAPI enable, weight = %d, Tx Ring = %d, Rx Ring = %d\n", dev->weight, NUM_TX_DESC, NUM_RX_DESC);
15962 +#endif
15963 +#endif
15964 +
15965 +       /* Register net device for the driver */
15966 +       if ( register_netdev(dev) != 0) {
15967 +               printk(KERN_WARNING " " __FILE__ ": No ethernet port found.\n");
15968 +               return -ENXIO;
15969 +       }
15970 +
15971 +
15972 +#ifdef CONFIG_RAETH_NETLINK
15973 +       csr_netlink_init();
15974 +#endif
15975 +       ret = debug_proc_init();
15976 +
15977 +       dev_raether = dev;
15978 +#ifdef CONFIG_ARCH_MT7623
15979 +       mt7623_ethifsys_init();
15980 +#endif
15981 +       return ret;
15982 +}
15983 +
15984 +
15985 +
15986 +
15987 +
15988 +
15989 +
15990 +void fe_sw_init(void)
15991 +{
15992 +#if defined (CONFIG_GIGAPHY) || defined (CONFIG_RAETH_ROUTER) || defined (CONFIG_100PHY)
15993 +        unsigned int regValue = 0;
15994 +#endif
15995 +
15996 +       // Case1: RT288x/RT3883/MT7621 GE1 + GigaPhy
15997 +#if defined (CONFIG_GE1_RGMII_AN)
15998 +       enable_auto_negotiate(1);
15999 +       if (isMarvellGigaPHY(1)) {
16000 +#if defined (CONFIG_RT3883_FPGA)
16001 +               mii_mgr_read(CONFIG_MAC_TO_GIGAPHY_MODE_ADDR, 9, &regValue);
16002 +               regValue &= ~(3<<8); //turn off 1000Base-T Advertisement  (9.9=1000Full, 9.8=1000Half)
16003 +               mii_mgr_write(CONFIG_MAC_TO_GIGAPHY_MODE_ADDR, 9, regValue);
16004 +
16005 +               printk("\n Reset MARVELL phy\n");
16006 +               mii_mgr_read(CONFIG_MAC_TO_GIGAPHY_MODE_ADDR, 20, &regValue);
16007 +               regValue |= 1<<7; //Add delay to RX_CLK for RXD Outputs
16008 +               mii_mgr_write(CONFIG_MAC_TO_GIGAPHY_MODE_ADDR, 20, regValue);
16009 +
16010 +               mii_mgr_read(CONFIG_MAC_TO_GIGAPHY_MODE_ADDR, 0, &regValue);
16011 +               regValue |= 1<<15; //PHY Software Reset
16012 +               mii_mgr_write(CONFIG_MAC_TO_GIGAPHY_MODE_ADDR, 0, regValue);
16013 +#elif defined (CONFIG_MT7621_FPGA) || defined (CONFIG_MT7623_FPGA)
16014 +               mii_mgr_read(CONFIG_MAC_TO_GIGAPHY_MODE_ADDR, 9, &regValue);
16015 +               regValue &= ~(3<<8); //turn off 1000Base-T Advertisement  (9.9=1000Full, 9.8=1000Half)
16016 +               mii_mgr_write(CONFIG_MAC_TO_GIGAPHY_MODE_ADDR, 9, regValue);
16017 +
16018 +               /*10Mbps, debug*/
16019 +               mii_mgr_write(CONFIG_MAC_TO_GIGAPHY_MODE_ADDR, 4, 0x461);
16020 +
16021 +               mii_mgr_read(CONFIG_MAC_TO_GIGAPHY_MODE_ADDR, 0, &regValue);
16022 +               regValue |= 1<<9; //restart AN
16023 +               mii_mgr_write(CONFIG_MAC_TO_GIGAPHY_MODE_ADDR, 0, regValue);
16024 +#endif
16025 +
16026 +       }
16027 +       if (isVtssGigaPHY(1)) {
16028 +               mii_mgr_write(CONFIG_MAC_TO_GIGAPHY_MODE_ADDR, 31, 1);
16029 +               mii_mgr_read(CONFIG_MAC_TO_GIGAPHY_MODE_ADDR, 28, &regValue);
16030 +               printk("Vitesse phy skew: %x --> ", regValue);
16031 +               regValue |= (0x3<<12);
16032 +               regValue &= ~(0x3<<14);
16033 +               printk("%x\n", regValue);
16034 +               mii_mgr_write(CONFIG_MAC_TO_GIGAPHY_MODE_ADDR, 28, regValue);
16035 +               mii_mgr_write(CONFIG_MAC_TO_GIGAPHY_MODE_ADDR, 31, 0);
16036 +        }
16037 +#if defined (CONFIG_RALINK_MT7621)
16038 +       sysRegWrite(RALINK_ETH_SW_BASE+0x100, 0x21056300);//(P0, Auto mode)
16039 +#endif
16040 +#endif // CONFIG_GE1_RGMII_AN //
16041 +
16042 +       // Case2: RT3883/MT7621 GE2 + GigaPhy
16043 +#if defined (CONFIG_GE2_RGMII_AN)
16044 +       enable_auto_negotiate(2);
16045 +       if (isMarvellGigaPHY(2)) {
16046 +#if defined (CONFIG_RT3883_FPGA)
16047 +               mii_mgr_read(CONFIG_MAC_TO_GIGAPHY_MODE_ADDR2, 9, &regValue);
16048 +               regValue &= ~(3<<8); //turn off 1000Base-T Advertisement (9.9=1000Full, 9.8=1000Half)
16049 +               mii_mgr_write(CONFIG_MAC_TO_GIGAPHY_MODE_ADDR2, 9, regValue);
16050 +
16051 +               mii_mgr_read(CONFIG_MAC_TO_GIGAPHY_MODE_ADDR2, 20, &regValue);
16052 +               regValue |= 1<<7; //Add delay to RX_CLK for RXD Outputs
16053 +               mii_mgr_write(CONFIG_MAC_TO_GIGAPHY_MODE_ADDR2, 20, regValue);
16054 +
16055 +               mii_mgr_read(CONFIG_MAC_TO_GIGAPHY_MODE_ADDR2, 0, &regValue);
16056 +               regValue |= 1<<15; //PHY Software Reset
16057 +               mii_mgr_write(CONFIG_MAC_TO_GIGAPHY_MODE_ADDR2, 0, regValue);
16058 +#elif defined (CONFIG_MT7621_FPGA) || defined (CONFIG_MT7623_FPGA)
16059 +               mii_mgr_read(CONFIG_MAC_TO_GIGAPHY_MODE_ADDR2, 9, &regValue);
16060 +               regValue &= ~(3<<8); //turn off 1000Base-T Advertisement (9.9=1000Full, 9.8=1000Half)
16061 +               mii_mgr_write(CONFIG_MAC_TO_GIGAPHY_MODE_ADDR2, 9, regValue);
16062 +
16063 +               /*10Mbps, debug*/
16064 +               mii_mgr_write(CONFIG_MAC_TO_GIGAPHY_MODE_ADDR2, 4, 0x461);
16065 +
16066 +
16067 +               mii_mgr_read(CONFIG_MAC_TO_GIGAPHY_MODE_ADDR2, 0, &regValue);
16068 +               regValue |= 1<<9; //restart AN
16069 +               mii_mgr_write(CONFIG_MAC_TO_GIGAPHY_MODE_ADDR2, 0, regValue);
16070 +#endif
16071 +
16072 +       }
16073 +       if (isVtssGigaPHY(2)) {
16074 +               mii_mgr_write(CONFIG_MAC_TO_GIGAPHY_MODE_ADDR2, 31, 1);
16075 +               mii_mgr_read(CONFIG_MAC_TO_GIGAPHY_MODE_ADDR2, 28, &regValue);
16076 +               printk("Vitesse phy skew: %x --> ", regValue);
16077 +               regValue |= (0x3<<12);
16078 +               regValue &= ~(0x3<<14);
16079 +               printk("%x\n", regValue);
16080 +               mii_mgr_write(CONFIG_MAC_TO_GIGAPHY_MODE_ADDR2, 28, regValue);
16081 +               mii_mgr_write(CONFIG_MAC_TO_GIGAPHY_MODE_ADDR2, 31, 0);
16082 +       }
16083 +#if defined (CONFIG_RALINK_MT7621)
16084 +       //RGMII2=Normal mode
16085 +       *(volatile u_long *)(RALINK_SYSCTL_BASE + 0x60) &= ~(0x1 << 15);
16086 +       //GMAC2= RGMII mode
16087 +       *(volatile u_long *)(SYSCFG1) &= ~(0x3 << 14);
16088 +
16089 +       sysRegWrite(RALINK_ETH_SW_BASE+0x200, 0x21056300);//(P1, Auto mode)
16090 +#endif
16091 +#endif // CONFIG_GE2_RGMII_AN //
16092 +
16093 +       // Case3: RT305x/RT335x/RT6855/RT6855A/MT7620 + EmbeddedSW
16094 +#if defined (CONFIG_RT_3052_ESW) && !defined(CONFIG_RALINK_MT7621) && !defined(CONFIG_ARCH_MT7623)
16095 +#if defined (CONFIG_RALINK_RT6855) || defined(CONFIG_RALINK_MT7620)
16096 +       rt_gsw_init();
16097 +#elif defined(CONFIG_RALINK_RT6855A)
16098 +       rt6855A_gsw_init();
16099 +#else
16100 +       rt305x_esw_init();
16101 +#endif
16102 +#endif
16103 +       // Case4:  RT288x/RT388x/MT7621 GE1 + Internal GigaSW
16104 +#if defined (CONFIG_GE1_RGMII_FORCE_1000) || defined (CONFIG_GE1_TRGMII_FORCE_1200)  || defined (CONFIG_GE1_TRGMII_FORCE_2000) || defined (CONFIG_GE1_TRGMII_FORCE_2600)
16105 +#if defined (CONFIG_RALINK_MT7621)
16106 +       setup_internal_gsw();
16107 +       /*MT7530 Init*/
16108 +#elif defined (CONFIG_ARCH_MT7623)
16109 +#if defined (CONFIG_GE1_TRGMII_FORCE_2000) || defined (CONFIG_GE1_TRGMII_FORCE_2600)
16110 +       *(volatile u_long *)(0xfb00002c) |=  (1<<11);
16111 +#else
16112 +       *(volatile u_long *)(0xfb00002c) &= ~(1<<11);
16113 +#endif
16114 +       setup_internal_gsw();
16115 +       trgmii_calibration_7623();
16116 +       trgmii_calibration_7530();
16117 +       //*(volatile u_long *)(0xfb110300) |= (0x1f << 24);     //Just only for 312.5/325MHz
16118 +       *(volatile u_long *)(0xfb110340) = 0x00020000;
16119 +       *(volatile u_long *)(0xfb110304) &= 0x3fffffff;         // RX clock gating in MT7623
16120 +       *(volatile u_long *)(0xfb110300) |= 0x80000000;         // Assert RX  reset in MT7623
16121 +       *(volatile u_long *)(0xfb110300 )      &= 0x7fffffff;   // Release RX reset in MT7623
16122 +       *(volatile u_long *)(0xfb110300 +0x04) |= 0xC0000000;   // Disable RX clock gating in MT7623
16123 +/*GE1@125MHz(RGMII mode) TX delay adjustment*/
16124 +#if defined (CONFIG_GE1_RGMII_FORCE_1000)
16125 +        *(volatile u_long *)(0xfb110350) = 0x55;
16126 +        *(volatile u_long *)(0xfb110358) = 0x55;
16127 +        *(volatile u_long *)(0xfb110360) = 0x55;
16128 +        *(volatile u_long *)(0xfb110368) = 0x55;
16129 +        *(volatile u_long *)(0xfb110370) = 0x55;
16130 +        *(volatile u_long *)(0xfb110378) = 0x855;
16131 +#endif
16132 +
16133 +
16134 +#elif defined (CONFIG_MT7623_FPGA)     /* Nelson: remove for bring up, should be added!!! */
16135 +       setup_fpga_gsw();
16136 +#else
16137 +       sysRegWrite(MDIO_CFG, INIT_VALUE_OF_FORCE_1000_FD);
16138 +#endif
16139 +#endif
16140 +
16141 +       // Case5: RT388x/MT7621 GE2 + GigaSW
16142 +#if defined (CONFIG_GE2_RGMII_FORCE_1000)
16143 +#if defined (CONFIG_RALINK_MT7621)
16144 +       setup_external_gsw();
16145 +#else
16146 +       sysRegWrite(MDIO_CFG2, INIT_VALUE_OF_FORCE_1000_FD);
16147 +#endif
16148 +#endif
16149 +
16150 +       // Case6: RT288x GE1 /RT388x,MT7621 GE1/GE2 + (10/100 Switch or 100PHY)
16151 +#if defined (CONFIG_RAETH_ROUTER) || defined (CONFIG_100PHY)
16152 +
16153 +       //set GMAC to MII or RvMII mode
16154 +#if defined (CONFIG_RALINK_RT3883)
16155 +       regValue = sysRegRead(SYSCFG1);
16156 +#if defined (CONFIG_GE1_MII_FORCE_100) || defined (CONFIG_GE1_MII_AN)
16157 +       regValue &= ~(0x3 << 12);
16158 +       regValue |= 0x1 << 12; // GE1 MII Mode
16159 +#elif defined (CONFIG_GE1_RVMII_FORCE_100)
16160 +       regValue &= ~(0x3 << 12);
16161 +       regValue |= 0x2 << 12; // GE1 RvMII Mode
16162 +#endif
16163 +
16164 +#if defined (CONFIG_GE2_MII_FORCE_100) || defined (CONFIG_GE2_MII_AN)
16165 +       regValue &= ~(0x3 << 14);
16166 +       regValue |= 0x1 << 14; // GE2 MII Mode
16167 +#elif defined (CONFIG_GE2_RVMII_FORCE_100)
16168 +       regValue &= ~(0x3 << 14);
16169 +       regValue |= 0x2 << 14; // GE2 RvMII Mode
16170 +#endif
16171 +       sysRegWrite(SYSCFG1, regValue);
16172 +#endif // CONFIG_RALINK_RT3883 //
16173 +
16174 +#elif defined (CONFIG_RALINK_MT7621) || defined (CONFIG_ARCH_MT7623)
16175 +
16176 +#if defined (CONFIG_GE1_MII_FORCE_100)
16177 +       sysRegWrite(RALINK_ETH_SW_BASE+0x100, 0x5e337);//(P0, Force mode, Link Up, 100Mbps, Full-Duplex, FC ON)
16178 +#endif
16179 +#if defined (CONFIG_GE2_MII_FORCE_100)
16180 +       sysRegWrite(RALINK_ETH_SW_BASE+0x200, 0x5e337);//(P1, Force mode, Link Up, 100Mbps, Full-Duplex, FC ON)
16181 +#endif
16182 +#if defined (CONFIG_GE1_MII_AN) || defined (CONFIG_GE1_RGMII_AN)
16183 +       enable_auto_negotiate(1);
16184 +#if defined (CONFIG_RALINK_MT7621)
16185 +       sysRegWrite(RALINK_ETH_SW_BASE+0x100, 0x21056300);//(P0, Auto mode)
16186 +#endif
16187 +#endif
16188 +#if defined (CONFIG_GE2_MII_AN) || defined (CONFIG_GE1_RGMII_AN)
16189 +       enable_auto_negotiate(2);
16190 +#if defined (CONFIG_RALINK_MT7621)
16191 +       sysRegWrite(RALINK_ETH_SW_BASE+0x200, 0x21056300);//(P1, Auto mode)
16192 +#endif
16193 +#endif
16194 +
16195 +#else
16196 +#if defined (CONFIG_GE1_MII_FORCE_100)
16197 +#if defined (CONFIG_RALINK_MT7621)
16198 +#else
16199 +       sysRegWrite(MDIO_CFG, INIT_VALUE_OF_FORCE_100_FD);
16200 +#endif
16201 +#endif
16202 +#if defined (CONFIG_GE2_MII_FORCE_100)
16203 +#if defined (CONFIG_RALINK_MT7621)
16204 +#else
16205 +       sysRegWrite(MDIO_CFG2, INIT_VALUE_OF_FORCE_100_FD);
16206 +#endif
16207 +#endif
16208 +       //add switch configuration here for other switch chips.
16209 +#if defined (CONFIG_GE1_MII_FORCE_100) ||  defined (CONFIG_GE2_MII_FORCE_100)
16210 +       // IC+ 175x: force IC+ switch cpu port is 100/FD
16211 +       mii_mgr_write(29, 22, 0x8420);
16212 +#endif
16213 +
16214 +
16215 +#endif // defined (CONFIG_RAETH_ROUTER) || defined (CONFIG_100PHY) //
16216 +
16217 +}
16218 +
16219 +
16220 +/**
16221 + * ra2882eth_cleanup_module - Module Exit code
16222 + *
16223 + * Cmd 'rmmod' will invode the routine to exit the module
16224 + *
16225 + */
16226 +#if 0
16227 + void ra2882eth_cleanup_module(void)
16228 +{
16229 +       struct net_device *dev = dev_raether;
16230 +       END_DEVICE *ei_local;
16231 +
16232 +       ei_local = netdev_priv(dev);
16233 +
16234 +#ifdef CONFIG_PSEUDO_SUPPORT
16235 +       unregister_netdev(ei_local->PseudoDev);
16236 +       free_netdev(ei_local->PseudoDev);
16237 +#endif
16238 +       unregister_netdev(dev);
16239 +       RAETH_PRINT("Free ei_local and unregister netdev...\n");
16240 +
16241 +       free_netdev(dev);
16242 +       debug_proc_exit();
16243 +#ifdef CONFIG_RAETH_NETLINK
16244 +       csr_netlink_end();
16245 +#endif
16246 +}
16247 +#endif
16248 +EXPORT_SYMBOL(set_fe_dma_glo_cfg);
16249 +//module_init(ra2882eth_init);
16250 +//module_exit(ra2882eth_cleanup_module);
16251 +
16252 +const struct of_device_id of_fe_match[] = {
16253 +       { .compatible = "mediatek,mt7623-net", },
16254 +       {},
16255 +};
16256 +
16257 +MODULE_DEVICE_TABLE(of, of_fe_match);
16258 +
16259 +static struct platform_driver fe_driver = {
16260 +       .probe = fe_probe,
16261 +//     .remove = ra2882eth_cleanup_module,
16262 +       .driver = {
16263 +               .name = "ralink_soc_eth",
16264 +               .owner = THIS_MODULE,
16265 +               .of_match_table = of_fe_match,
16266 +       },
16267 +};
16268 +
16269 +static int __init init_rtfe(void)
16270 +{
16271 +       int ret;
16272 +       ret = platform_driver_register(&fe_driver);
16273 +       return ret;
16274 +}
16275 +
16276 +static void __exit exit_rtfe(void)
16277 +{
16278 +       platform_driver_unregister(&fe_driver);
16279 +}
16280 +
16281 +module_init(init_rtfe);
16282 +module_exit(exit_rtfe);
16283 +
16284 +
16285 +MODULE_LICENSE("GPL");
16286 diff --git a/drivers/net/ethernet/raeth/raether.h b/drivers/net/ethernet/raeth/raether.h
16287 new file mode 100644
16288 index 0000000..7a97109
16289 --- /dev/null
16290 +++ b/drivers/net/ethernet/raeth/raether.h
16291 @@ -0,0 +1,126 @@
16292 +#ifndef RA2882ETHEND_H
16293 +#define RA2882ETHEND_H
16294 +
16295 +#ifdef DSP_VIA_NONCACHEABLE
16296 +#define ESRAM_BASE     0xa0800000      /* 0x0080-0000  ~ 0x00807FFF */
16297 +#else
16298 +#define ESRAM_BASE     0x80800000      /* 0x0080-0000  ~ 0x00807FFF */
16299 +#endif
16300 +
16301 +#define RX_RING_BASE   ((int)(ESRAM_BASE + 0x7000))
16302 +#define TX_RING_BASE   ((int)(ESRAM_BASE + 0x7800))
16303 +
16304 +#if defined(CONFIG_RALINK_RT2880)
16305 +#define NUM_TX_RINGS   1
16306 +#else
16307 +#define NUM_TX_RINGS   4
16308 +#endif
16309 +#ifdef MEMORY_OPTIMIZATION
16310 +#ifdef CONFIG_RAETH_ROUTER
16311 +#define NUM_RX_DESC     32 //128
16312 +#define NUM_TX_DESC            32 //128
16313 +#elif CONFIG_RT_3052_ESW
16314 +#define NUM_RX_DESC     16 //64
16315 +#define NUM_TX_DESC     16 //64
16316 +#else
16317 +#define NUM_RX_DESC     32 //128
16318 +#define NUM_TX_DESC     32 //128
16319 +#endif
16320 +//#define NUM_RX_MAX_PROCESS 32
16321 +#define NUM_RX_MAX_PROCESS 32
16322 +#else
16323 +#if defined (CONFIG_RAETH_ROUTER)
16324 +#define NUM_RX_DESC     256
16325 +#define NUM_TX_DESC            256
16326 +#elif defined (CONFIG_RT_3052_ESW)
16327 +#if defined (CONFIG_RALINK_MT7621)
16328 +#define NUM_RX_DESC     512
16329 +#define NUM_QRX_DESC     16
16330 +#define NUM_TX_DESC     512
16331 +#else
16332 +#define NUM_RX_DESC     256
16333 +#define NUM_QRX_DESC NUM_RX_DESC
16334 +#define NUM_TX_DESC     256
16335 +#endif
16336 +#else
16337 +#define NUM_RX_DESC     256
16338 +#define NUM_QRX_DESC NUM_RX_DESC
16339 +#define NUM_TX_DESC     256
16340 +#endif
16341 +#if defined(CONFIG_RALINK_RT3883) || defined(CONFIG_RALINK_MT7620)
16342 +#define NUM_RX_MAX_PROCESS 2
16343 +#else
16344 +#define NUM_RX_MAX_PROCESS 16
16345 +#endif
16346 +#endif
16347 +#define NUM_LRO_RX_DESC        16
16348 +
16349 +#if defined (CONFIG_SUPPORT_OPENWRT)
16350 +#define DEV_NAME        "eth0"
16351 +#define DEV2_NAME       "eth1"
16352 +#else
16353 +#define DEV_NAME        "eth2"
16354 +#define DEV2_NAME       "eth3"
16355 +#endif
16356 +
16357 +#if defined (CONFIG_RALINK_RT6855A) || defined (CONFIG_RALINK_MT7621)
16358 +#define GMAC0_OFFSET    0xE000
16359 +#define GMAC2_OFFSET    0xE006
16360 +#else
16361 +#define GMAC0_OFFSET    0x28
16362 +#define GMAC2_OFFSET    0x22
16363 +#endif
16364 +
16365 +#if defined(CONFIG_RALINK_RT6855A)
16366 +#define IRQ_ENET0      22
16367 +#elif defined(CONFIG_ARCH_MT7623)
16368 +#define IRQ_ENET0      232
16369 +#else
16370 +#define IRQ_ENET0      3       /* hardware interrupt #3, defined in RT2880 Soc Design Spec Rev 0.03, pp43 */
16371 +#endif
16372 +
16373 +#if defined (CONFIG_RAETH_HW_LRO)
16374 +#define        HW_LRO_TIMER_UNIT   1
16375 +#define        HW_LRO_REFRESH_TIME 50000
16376 +#define        HW_LRO_MAX_AGG_CNT      64
16377 +#define        HW_LRO_AGG_DELTA        1
16378 +#if defined(CONFIG_RAETH_PDMA_DVT)
16379 +#define        MAX_LRO_RX_LENGTH       10240
16380 +#else
16381 +#define        MAX_LRO_RX_LENGTH       (PAGE_SIZE - SKB_DATA_ALIGN(NET_SKB_PAD + sizeof(struct skb_shared_info)))
16382 +#endif
16383 +#define        HW_LRO_AGG_TIME         10      /* 200us */
16384 +#define        HW_LRO_AGE_TIME         50
16385 +#define        HW_LRO_BW_THRE          3000
16386 +#define        HW_LRO_PKT_INT_ALPHA    100
16387 +#endif  /* CONFIG_RAETH_HW_LRO */
16388 +#define FE_INT_STATUS_REG (*(volatile unsigned long *)(FE_INT_STATUS))
16389 +#define FE_INT_STATUS_CLEAN(reg) (*(volatile unsigned long *)(FE_INT_STATUS)) = reg
16390 +
16391 +//#define RAETH_DEBUG
16392 +#ifdef RAETH_DEBUG
16393 +#define RAETH_PRINT(fmt, args...) printk(KERN_INFO fmt, ## args)
16394 +#else
16395 +#define RAETH_PRINT(fmt, args...) { }
16396 +#endif
16397 +
16398 +struct net_device_stats *ra_get_stats(struct net_device *dev);
16399 +
16400 +void ei_tx_timeout(struct net_device *dev);
16401 +int rather_probe(struct net_device *dev);
16402 +int ei_open(struct net_device *dev);
16403 +int ei_close(struct net_device *dev);
16404 +
16405 +int ra2882eth_init(void);
16406 +void ra2882eth_cleanup_module(void);
16407 +
16408 +void ei_xmit_housekeeping(unsigned long data);
16409 +
16410 +u32 mii_mgr_read(u32 phy_addr, u32 phy_register, u32 *read_data);
16411 +u32 mii_mgr_write(u32 phy_addr, u32 phy_register, u32 write_data);
16412 +u32 mii_mgr_cl45_set_address(u32 port_num, u32 dev_addr, u32 reg_addr);
16413 +u32 mii_mgr_read_cl45(u32 port_num, u32 dev_addr, u32 reg_addr, u32 *read_data);
16414 +u32 mii_mgr_write_cl45(u32 port_num, u32 dev_addr, u32 reg_addr, u32 write_data);
16415 +void fe_sw_init(void);
16416 +
16417 +#endif
16418 diff --git a/drivers/net/ethernet/raeth/raether_hwlro.c b/drivers/net/ethernet/raeth/raether_hwlro.c
16419 new file mode 100755
16420 index 0000000..5fc4f36
16421 --- /dev/null
16422 +++ b/drivers/net/ethernet/raeth/raether_hwlro.c
16423 @@ -0,0 +1,347 @@
16424 +#include <linux/module.h>
16425 +#include <linux/version.h>
16426 +#include <linux/kernel.h>
16427 +#include <linux/types.h>
16428 +#include <linux/pci.h>
16429 +#include <linux/init.h>
16430 +#include <linux/skbuff.h>
16431 +#include <linux/if_vlan.h>
16432 +#include <linux/if_ether.h>
16433 +#include <linux/fs.h>
16434 +#include <asm/uaccess.h>
16435 +#include <asm/rt2880/surfboardint.h>
16436 +#include <linux/delay.h>
16437 +#include <linux/sched.h>
16438 +#include <asm/rt2880/rt_mmap.h>
16439 +#include "ra2882ethreg.h"
16440 +#include "raether.h"
16441 +#include "ra_mac.h"
16442 +#include "ra_ioctl.h"
16443 +#include "ra_rfrw.h"
16444 +
16445 +#if defined(CONFIG_RAETH_HW_LRO_FORCE)
16446 +int set_fe_lro_ring1_cfg(struct net_device *dev)
16447 +{
16448 +       unsigned int ip;
16449 +
16450 +       netdev_printk(KERN_CRIT, dev, "set_fe_lro_ring1_cfg()\n");
16451 +
16452 +       /* 1. Set RX ring mode to force port */
16453 +       SET_PDMA_RXRING_MODE(ADMA_RX_RING1, PDMA_RX_FORCE_PORT);
16454 +
16455 +       /* 2. Configure lro ring */
16456 +       /* 2.1 set src/destination TCP ports */
16457 +       SET_PDMA_RXRING_TCP_SRC_PORT(ADMA_RX_RING1, 1122);
16458 +       SET_PDMA_RXRING_TCP_DEST_PORT(ADMA_RX_RING1, 3344);
16459 +       /* 2.2 set src/destination IPs */
16460 +       str_to_ip(&ip, "10.10.10.3");
16461 +       sysRegWrite(LRO_RX_RING1_SIP_DW0, ip);
16462 +       str_to_ip(&ip, "10.10.10.254");
16463 +       sysRegWrite(LRO_RX_RING1_DIP_DW0, ip);
16464 +       /* 2.3 IPv4 force port mode */
16465 +       SET_PDMA_RXRING_IPV4_FORCE_MODE(ADMA_RX_RING1, 1);
16466 +       /* 2.4 IPv6 force port mode */
16467 +       SET_PDMA_RXRING_IPV6_FORCE_MODE(ADMA_RX_RING1, 1);
16468 +
16469 +       /* 3. Set Age timer: 10 msec. */
16470 +       SET_PDMA_RXRING_AGE_TIME(ADMA_RX_RING1, HW_LRO_AGE_TIME);
16471 +
16472 +       /* 4. Valid LRO ring */
16473 +       SET_PDMA_RXRING_VALID(ADMA_RX_RING1, 1);
16474 +
16475 +       return 0;
16476 +}
16477 +
16478 +int set_fe_lro_ring2_cfg(struct net_device *dev)
16479 +{
16480 +       unsigned int ip;
16481 +
16482 +       netdev_printk(KERN_CRIT, dev, "set_fe_lro_ring2_cfg()\n");
16483 +
16484 +       /* 1. Set RX ring mode to force port */
16485 +       SET_PDMA_RXRING2_MODE(PDMA_RX_FORCE_PORT);
16486 +
16487 +       /* 2. Configure lro ring */
16488 +       /* 2.1 set src/destination TCP ports */
16489 +       SET_PDMA_RXRING_TCP_SRC_PORT(ADMA_RX_RING2, 5566);
16490 +       SET_PDMA_RXRING_TCP_DEST_PORT(ADMA_RX_RING2, 7788);
16491 +       /* 2.2 set src/destination IPs */
16492 +       str_to_ip(&ip, "10.10.10.3");
16493 +       sysRegWrite(LRO_RX_RING2_SIP_DW0, ip);
16494 +       str_to_ip(&ip, "10.10.10.254");
16495 +       sysRegWrite(LRO_RX_RING2_DIP_DW0, ip);
16496 +       /* 2.3 IPv4 force port mode */
16497 +       SET_PDMA_RXRING_IPV4_FORCE_MODE(ADMA_RX_RING2, 1);
16498 +       /* 2.4 IPv6 force port mode */
16499 +       SET_PDMA_RXRING_IPV6_FORCE_MODE(ADMA_RX_RING2, 1);
16500 +
16501 +       /* 3. Set Age timer: 10 msec. */
16502 +       SET_PDMA_RXRING_AGE_TIME(ADMA_RX_RING2, HW_LRO_AGE_TIME);
16503 +
16504 +       /* 4. Valid LRO ring */
16505 +       SET_PDMA_RXRING_VALID(ADMA_RX_RING2, 1);
16506 +
16507 +       return 0;
16508 +}
16509 +
16510 +int set_fe_lro_ring3_cfg(struct net_device *dev)
16511 +{
16512 +       unsigned int ip;
16513 +
16514 +       netdev_printk(KERN_CRIT, dev, "set_fe_lro_ring3_cfg()\n");
16515 +
16516 +       /* 1. Set RX ring mode to force port */
16517 +       SET_PDMA_RXRING3_MODE(PDMA_RX_FORCE_PORT);
16518 +
16519 +       /* 2. Configure lro ring */
16520 +       /* 2.1 set src/destination TCP ports */
16521 +       SET_PDMA_RXRING_TCP_SRC_PORT(ADMA_RX_RING3, 9900);
16522 +       SET_PDMA_RXRING_TCP_DEST_PORT(ADMA_RX_RING3, 99);
16523 +       /* 2.2 set src/destination IPs */
16524 +       str_to_ip(&ip, "10.10.10.3");
16525 +       sysRegWrite(LRO_RX_RING3_SIP_DW0, ip);
16526 +       str_to_ip(&ip, "10.10.10.254");
16527 +       sysRegWrite(LRO_RX_RING3_DIP_DW0, ip);
16528 +       /* 2.3 IPv4 force port mode */
16529 +       SET_PDMA_RXRING_IPV4_FORCE_MODE(ADMA_RX_RING3, 1);
16530 +       /* 2.4 IPv6 force port mode */
16531 +       SET_PDMA_RXRING_IPV6_FORCE_MODE(ADMA_RX_RING3, 1);
16532 +
16533 +       /* 3. Set Age timer: 10 msec. */
16534 +       SET_PDMA_RXRING_AGE_TIME(ADMA_RX_RING3, HW_LRO_AGE_TIME);
16535 +
16536 +       /* 4. Valid LRO ring */
16537 +       SET_PDMA_RXRING3_VALID(1);
16538 +
16539 +       return 0;
16540 +}
16541 +
16542 +int set_fe_lro_glo_cfg(struct net_device *dev)
16543 +{
16544 +       unsigned int regVal = 0;
16545 +
16546 +       netdev_printk(KERN_CRIT, dev, "set_fe_lro_glo_cfg()\n");
16547 +
16548 +       /* 1 Set max AGG timer: 10 msec. */
16549 +       SET_PDMA_LRO_MAX_AGG_TIME(HW_LRO_AGG_TIME);
16550 +
16551 +       /* 2. Set max LRO agg count */
16552 +       SET_PDMA_LRO_MAX_AGG_CNT(HW_LRO_MAX_AGG_CNT);
16553 +
16554 +       /* PDMA prefetch enable setting */
16555 +       SET_PDMA_LRO_RXD_PREFETCH_EN(0x3);
16556 +
16557 +       /* 2.1 IPv4 checksum update enable */
16558 +       SET_PDMA_LRO_IPV4_CSUM_UPDATE_EN(1);
16559 +
16560 +       /* 3. Polling relinguish */
16561 +       while (sysRegRead(ADMA_LRO_CTRL_DW0) & PDMA_LRO_RELINGUISH)
16562 +               ;
16563 +
16564 +       /* 4. Enable LRO */
16565 +       regVal = sysRegRead(ADMA_LRO_CTRL_DW0);
16566 +       regVal |= PDMA_LRO_EN;
16567 +       sysRegWrite(ADMA_LRO_CTRL_DW0, regVal);
16568 +
16569 +       return 0;
16570 +}
16571 +#else
16572 +int set_fe_lro_auto_cfg(struct net_device *dev)
16573 +{
16574 +       unsigned int regVal = 0;
16575 +       unsigned int ip;
16576 +
16577 +       netdev_printk(KERN_CRIT, dev, "set_fe_lro_auto_cfg()\n");
16578 +
16579 +       /* 1.1 Set my IP_1 */
16580 +       str_to_ip(&ip, "10.10.10.254");
16581 +       sysRegWrite(LRO_RX_RING0_DIP_DW0, ip);
16582 +       sysRegWrite(LRO_RX_RING0_DIP_DW1, 0);
16583 +       sysRegWrite(LRO_RX_RING0_DIP_DW2, 0);
16584 +       sysRegWrite(LRO_RX_RING0_DIP_DW3, 0);
16585 +       SET_PDMA_RXRING_MYIP_VALID(ADMA_RX_RING0, 1);
16586 +
16587 +       /* 1.2 Set my IP_2 */
16588 +       str_to_ip(&ip, "10.10.20.254");
16589 +       sysRegWrite(LRO_RX_RING1_DIP_DW0, ip);
16590 +       sysRegWrite(LRO_RX_RING1_DIP_DW1, 0);
16591 +       sysRegWrite(LRO_RX_RING1_DIP_DW2, 0);
16592 +       sysRegWrite(LRO_RX_RING1_DIP_DW3, 0);
16593 +       SET_PDMA_RXRING_MYIP_VALID(ADMA_RX_RING1, 1);
16594 +
16595 +       /* 1.3 Set my IP_3 */
16596 +       sysRegWrite(LRO_RX_RING2_DIP_DW3, 0x20010238);
16597 +       sysRegWrite(LRO_RX_RING2_DIP_DW2, 0x08000000);
16598 +       sysRegWrite(LRO_RX_RING2_DIP_DW1, 0x00000000);
16599 +       sysRegWrite(LRO_RX_RING2_DIP_DW0, 0x00000254);
16600 +       SET_PDMA_RXRING_MYIP_VALID(ADMA_RX_RING2, 1);
16601 +
16602 +       /* 1.4 Set my IP_4 */
16603 +       sysRegWrite(LRO_RX_RING3_DIP_DW3, 0x20010238);
16604 +       sysRegWrite(LRO_RX_RING3_DIP_DW2, 0x08010000);
16605 +       sysRegWrite(LRO_RX_RING3_DIP_DW1, 0x00000000);
16606 +       sysRegWrite(LRO_RX_RING3_DIP_DW0, 0x00000254);
16607 +       SET_PDMA_RXRING_MYIP_VALID(ADMA_RX_RING3, 1);
16608 +
16609 +       /* 2.1 Set RX ring1~3 to auto-learn modes */
16610 +       SET_PDMA_RXRING_MODE(ADMA_RX_RING1, PDMA_RX_AUTO_LEARN);
16611 +       SET_PDMA_RXRING_MODE(ADMA_RX_RING2, PDMA_RX_AUTO_LEARN);
16612 +       SET_PDMA_RXRING_MODE(ADMA_RX_RING3, PDMA_RX_AUTO_LEARN);
16613 +
16614 +       /* 2.2 Valid LRO ring */
16615 +       SET_PDMA_RXRING_VALID(ADMA_RX_RING0, 1);
16616 +       SET_PDMA_RXRING_VALID(ADMA_RX_RING1, 1);
16617 +       SET_PDMA_RXRING_VALID(ADMA_RX_RING2, 1);
16618 +       SET_PDMA_RXRING_VALID(ADMA_RX_RING3, 1);
16619 +
16620 +       /* 2.3 Set AGE timer */
16621 +       SET_PDMA_RXRING_AGE_TIME(ADMA_RX_RING1, HW_LRO_AGE_TIME);
16622 +       SET_PDMA_RXRING_AGE_TIME(ADMA_RX_RING2, HW_LRO_AGE_TIME);
16623 +       SET_PDMA_RXRING_AGE_TIME(ADMA_RX_RING3, HW_LRO_AGE_TIME);
16624 +
16625 +       /* 2.4 Set max AGG timer */
16626 +       SET_PDMA_RXRING_AGG_TIME(ADMA_RX_RING1, HW_LRO_AGG_TIME);
16627 +       SET_PDMA_RXRING_AGG_TIME(ADMA_RX_RING2, HW_LRO_AGG_TIME);
16628 +       SET_PDMA_RXRING_AGG_TIME(ADMA_RX_RING3, HW_LRO_AGG_TIME);
16629 +
16630 +       /* 2.5 Set max LRO agg count */
16631 +       SET_PDMA_RXRING_MAX_AGG_CNT(ADMA_RX_RING1, HW_LRO_MAX_AGG_CNT);
16632 +       SET_PDMA_RXRING_MAX_AGG_CNT(ADMA_RX_RING2, HW_LRO_MAX_AGG_CNT);
16633 +       SET_PDMA_RXRING_MAX_AGG_CNT(ADMA_RX_RING3, HW_LRO_MAX_AGG_CNT);
16634 +
16635 +       /* 3.0 IPv6 LRO enable */
16636 +       SET_PDMA_LRO_IPV6_EN(1);
16637 +
16638 +       /* 3.1 IPv4 checksum update enable */
16639 +       SET_PDMA_LRO_IPV4_CSUM_UPDATE_EN(1);
16640 +
16641 +       /* 3.2 TCP push option check disable */
16642 +       //SET_PDMA_LRO_IPV4_CTRL_PUSH_EN(0);
16643 +
16644 +       /* PDMA prefetch enable setting */
16645 +       SET_PDMA_LRO_RXD_PREFETCH_EN(0x3);
16646 +
16647 +       /* 3.2 switch priority comparison to byte count mode */
16648 +/* SET_PDMA_LRO_ALT_SCORE_MODE(PDMA_LRO_ALT_BYTE_CNT_MODE); */
16649 +       SET_PDMA_LRO_ALT_SCORE_MODE(PDMA_LRO_ALT_PKT_CNT_MODE);
16650 +
16651 +       /* 3.3 bandwidth threshold setting */
16652 +       SET_PDMA_LRO_BW_THRESHOLD(HW_LRO_BW_THRE);
16653 +
16654 +       /* 3.4 auto-learn score delta setting */
16655 +       sysRegWrite(LRO_ALT_SCORE_DELTA, 0);
16656 +
16657 +       /* 3.5 Set ALT timer to 20us: (unit: 20us) */
16658 +       SET_PDMA_LRO_ALT_REFRESH_TIMER_UNIT(HW_LRO_TIMER_UNIT);
16659 +       /* 3.6 Set ALT refresh timer to 1 sec. (unit: 20us) */
16660 +       SET_PDMA_LRO_ALT_REFRESH_TIMER(HW_LRO_REFRESH_TIME);
16661 +
16662 +       /* 3.7 the least remaining room of SDL0 in RXD for lro aggregation */
16663 +       SET_PDMA_LRO_MIN_RXD_SDL(1522);
16664 +
16665 +       /* 4. Polling relinguish */
16666 +       while (sysRegRead(ADMA_LRO_CTRL_DW0) & PDMA_LRO_RELINGUISH)
16667 +               ;
16668 +
16669 +       /* 5. Enable LRO */
16670 +       regVal = sysRegRead(ADMA_LRO_CTRL_DW0);
16671 +       regVal |= PDMA_LRO_EN;
16672 +       sysRegWrite(ADMA_LRO_CTRL_DW0, regVal);
16673 +
16674 +       return 0;
16675 +}
16676 +#endif /* CONFIG_RAETH_HW_LRO_FORCE */
16677 +
16678 +int fe_hw_lro_init(struct net_device *dev)
16679 +{
16680 +       int i;
16681 +       END_DEVICE *ei_local = netdev_priv(dev);
16682 +
16683 +       /* Initial RX Ring 3 */
16684 +       ei_local->rx_ring3 =
16685 +           pci_alloc_consistent(NULL, NUM_LRO_RX_DESC * sizeof(struct PDMA_rxdesc),
16686 +                                &ei_local->phy_rx_ring3);
16687 +       for (i = 0; i < NUM_LRO_RX_DESC; i++) {
16688 +               memset(&ei_local->rx_ring3[i], 0, sizeof(struct PDMA_rxdesc));
16689 +               ei_local->rx_ring3[i].rxd_info2.DDONE_bit = 0;
16690 +               ei_local->rx_ring3[i].rxd_info2.LS0 = 0;
16691 +               ei_local->rx_ring3[i].rxd_info2.PLEN0 =
16692 +                   SET_ADMA_RX_LEN0(MAX_LRO_RX_LENGTH);
16693 +               ei_local->rx_ring3[i].rxd_info2.PLEN1 =
16694 +                   SET_ADMA_RX_LEN1(MAX_LRO_RX_LENGTH >> 14);
16695 +               ei_local->rx_ring3[i].rxd_info1.PDP0 =
16696 +                   dma_map_single(NULL, ei_local->netrx3_skbuf[i]->data,
16697 +                                  MAX_LRO_RX_LENGTH, PCI_DMA_FROMDEVICE);
16698 +       }
16699 +       netdev_printk(KERN_CRIT, dev,
16700 +                     "\nphy_rx_ring3 = 0x%08x, rx_ring3 = 0x%p\n",
16701 +                     ei_local->phy_rx_ring3, ei_local->rx_ring3);
16702 +       /* Initial RX Ring 2 */
16703 +       ei_local->rx_ring2 =
16704 +           pci_alloc_consistent(NULL, NUM_LRO_RX_DESC * sizeof(struct PDMA_rxdesc),
16705 +                                &ei_local->phy_rx_ring2);
16706 +       for (i = 0; i < NUM_LRO_RX_DESC; i++) {
16707 +               memset(&ei_local->rx_ring2[i], 0, sizeof(struct PDMA_rxdesc));
16708 +               ei_local->rx_ring2[i].rxd_info2.DDONE_bit = 0;
16709 +               ei_local->rx_ring2[i].rxd_info2.LS0 = 0;
16710 +               ei_local->rx_ring2[i].rxd_info2.PLEN0 =
16711 +                   SET_ADMA_RX_LEN0(MAX_LRO_RX_LENGTH);
16712 +               ei_local->rx_ring2[i].rxd_info2.PLEN1 =
16713 +                   SET_ADMA_RX_LEN1(MAX_LRO_RX_LENGTH >> 14);
16714 +               ei_local->rx_ring2[i].rxd_info1.PDP0 =
16715 +                   dma_map_single(NULL, ei_local->netrx2_skbuf[i]->data,
16716 +                                  MAX_LRO_RX_LENGTH, PCI_DMA_FROMDEVICE);
16717 +       }
16718 +       netdev_printk(KERN_CRIT, dev,
16719 +                     "\nphy_rx_ring2 = 0x%08x, rx_ring2 = 0x%p\n",
16720 +                     ei_local->phy_rx_ring2, ei_local->rx_ring2);
16721 +       /* Initial RX Ring 1 */
16722 +       ei_local->rx_ring1 =
16723 +           pci_alloc_consistent(NULL, NUM_LRO_RX_DESC * sizeof(struct PDMA_rxdesc),
16724 +                                &ei_local->phy_rx_ring1);
16725 +       for (i = 0; i < NUM_LRO_RX_DESC; i++) {
16726 +               memset(&ei_local->rx_ring1[i], 0, sizeof(struct PDMA_rxdesc));
16727 +               ei_local->rx_ring1[i].rxd_info2.DDONE_bit = 0;
16728 +               ei_local->rx_ring1[i].rxd_info2.LS0 = 0;
16729 +               ei_local->rx_ring1[i].rxd_info2.PLEN0 =
16730 +                   SET_ADMA_RX_LEN0(MAX_LRO_RX_LENGTH);
16731 +               ei_local->rx_ring1[i].rxd_info2.PLEN1 =
16732 +                   SET_ADMA_RX_LEN1(MAX_LRO_RX_LENGTH >> 14);
16733 +               ei_local->rx_ring1[i].rxd_info1.PDP0 =
16734 +                   dma_map_single(NULL, ei_local->netrx1_skbuf[i]->data,
16735 +                                  MAX_LRO_RX_LENGTH, PCI_DMA_FROMDEVICE);
16736 +       }
16737 +       netdev_printk(KERN_CRIT, dev,
16738 +                     "\nphy_rx_ring1 = 0x%08x, rx_ring1 = 0x%p\n",
16739 +                     ei_local->phy_rx_ring1, ei_local->rx_ring1);
16740 +
16741 +       sysRegWrite(RX_BASE_PTR3, phys_to_bus((u32) ei_local->phy_rx_ring3));
16742 +       sysRegWrite(RX_MAX_CNT3, cpu_to_le32((u32) NUM_LRO_RX_DESC));
16743 +       sysRegWrite(RX_CALC_IDX3, cpu_to_le32((u32) (NUM_LRO_RX_DESC - 1)));
16744 +       sysRegWrite(PDMA_RST_CFG, PST_DRX_IDX3);
16745 +       sysRegWrite(RX_BASE_PTR2, phys_to_bus((u32) ei_local->phy_rx_ring2));
16746 +       sysRegWrite(RX_MAX_CNT2, cpu_to_le32((u32) NUM_LRO_RX_DESC));
16747 +       sysRegWrite(RX_CALC_IDX2, cpu_to_le32((u32) (NUM_LRO_RX_DESC - 1)));
16748 +       sysRegWrite(PDMA_RST_CFG, PST_DRX_IDX2);
16749 +       sysRegWrite(RX_BASE_PTR1, phys_to_bus((u32) ei_local->phy_rx_ring1));
16750 +       sysRegWrite(RX_MAX_CNT1, cpu_to_le32((u32) NUM_LRO_RX_DESC));
16751 +       sysRegWrite(RX_CALC_IDX1, cpu_to_le32((u32) (NUM_LRO_RX_DESC - 1)));
16752 +       sysRegWrite(PDMA_RST_CFG, PST_DRX_IDX1);
16753 +
16754 +#if defined(CONFIG_RAETH_HW_LRO_FORCE)
16755 +       set_fe_lro_ring1_cfg(dev);
16756 +       set_fe_lro_ring2_cfg(dev);
16757 +       set_fe_lro_ring3_cfg(dev);
16758 +       set_fe_lro_glo_cfg(dev);
16759 +#else
16760 +       set_fe_lro_auto_cfg(dev);
16761 +#endif /* CONFIG_RAETH_HW_LRO_FORCE */
16762 +
16763 +       /* HW LRO parameter settings */
16764 +       ei_local->hw_lro_alpha = HW_LRO_PKT_INT_ALPHA;
16765 +       ei_local->hw_lro_fix_setting = 1;
16766 +
16767 +       return 1;
16768 +}
16769 +EXPORT_SYMBOL(fe_hw_lro_init);
16770 +
16771 diff --git a/drivers/net/ethernet/raeth/raether_pdma.c b/drivers/net/ethernet/raeth/raether_pdma.c
16772 new file mode 100755
16773 index 0000000..4d47ee2
16774 --- /dev/null
16775 +++ b/drivers/net/ethernet/raeth/raether_pdma.c
16776 @@ -0,0 +1,1121 @@
16777 +#include <linux/module.h>
16778 +#include <linux/version.h>
16779 +#include <linux/kernel.h>
16780 +#include <linux/types.h>
16781 +#include <linux/pci.h>
16782 +#include <linux/init.h>
16783 +#include <linux/skbuff.h>
16784 +#include <linux/if_vlan.h>
16785 +#include <linux/if_ether.h>
16786 +#include <linux/fs.h>
16787 +#include <asm/uaccess.h>
16788 +#include <asm/rt2880/surfboardint.h>
16789 +#if defined (CONFIG_RAETH_TSO)
16790 +#include <linux/tcp.h>
16791 +#include <net/ipv6.h>
16792 +#include <linux/ip.h>
16793 +#include <net/ip.h>
16794 +#include <net/tcp.h>
16795 +#include <linux/in.h>
16796 +#include <linux/ppp_defs.h>
16797 +#include <linux/if_pppox.h>
16798 +#endif
16799 +#if defined (CONFIG_RAETH_LRO)
16800 +#include <linux/inet_lro.h>
16801 +#endif
16802 +#include <linux/delay.h>
16803 +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,35)
16804 +#include <linux/sched.h>
16805 +#endif
16806 +
16807 +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,0)
16808 +#include <asm/rt2880/rt_mmap.h>
16809 +#else
16810 +#include <linux/libata-compat.h>
16811 +#endif
16812 +
16813 +#include "ra2882ethreg.h"
16814 +#include "raether.h"
16815 +#include "ra_mac.h"
16816 +#include "ra_ioctl.h"
16817 +#include "ra_rfrw.h"
16818 +#ifdef CONFIG_RAETH_NETLINK
16819 +#include "ra_netlink.h"
16820 +#endif
16821 +#if defined (CONFIG_RAETH_QOS)
16822 +#include "ra_qos.h"
16823 +#endif
16824 +
16825 +#if defined (CONFIG_RA_HW_NAT) || defined (CONFIG_RA_HW_NAT_MODULE)
16826 +#include "../../../net/nat/hw_nat/ra_nat.h"
16827 +#endif
16828 +#if defined(CONFIG_RAETH_PDMA_DVT)
16829 +#include "dvt/raether_pdma_dvt.h"
16830 +#endif  /* CONFIG_RAETH_PDMA_DVT */
16831 +
16832 +#if !defined(CONFIG_RA_NAT_NONE)
16833 +/* bruce+
16834 + */
16835 +extern int (*ra_sw_nat_hook_rx)(struct sk_buff *skb);
16836 +extern int (*ra_sw_nat_hook_tx)(struct sk_buff *skb, int gmac_no);
16837 +#endif
16838 +
16839 +#if defined(CONFIG_RA_CLASSIFIER)||defined(CONFIG_RA_CLASSIFIER_MODULE)
16840 +/* Qwert+
16841 + */
16842 +#include <asm/mipsregs.h>
16843 +extern int (*ra_classifier_hook_tx)(struct sk_buff *skb, unsigned long cur_cycle);
16844 +extern int (*ra_classifier_hook_rx)(struct sk_buff *skb, unsigned long cur_cycle);
16845 +#endif /* CONFIG_RA_CLASSIFIER */
16846 +
16847 +#if defined (CONFIG_RALINK_RT3052_MP2)
16848 +int32_t mcast_rx(struct sk_buff * skb);
16849 +int32_t mcast_tx(struct sk_buff * skb);
16850 +#endif
16851 +
16852 +#if 0
16853 +#ifdef RA_MTD_RW_BY_NUM
16854 +int ra_mtd_read(int num, loff_t from, size_t len, u_char *buf);
16855 +#else
16856 +int ra_mtd_read_nm(char *name, loff_t from, size_t len, u_char *buf);
16857 +#endif
16858 +#endif
16859 +/* gmac driver feature set config */
16860 +#if defined (CONFIG_RAETH_NAPI) || defined (CONFIG_RAETH_QOS)
16861 +#undef DELAY_INT
16862 +#else
16863 +#if defined     (CONFIG_ARCH_MT7623)
16864 +#undef DELAY_INT
16865 +#else
16866 +#define DELAY_INT       1
16867 +#endif
16868 +#endif
16869 +
16870 +//#define CONFIG_UNH_TEST
16871 +/* end of config */
16872 +
16873 +#if defined (CONFIG_RAETH_JUMBOFRAME)
16874 +#define        MAX_RX_LENGTH   4096
16875 +#else
16876 +#define        MAX_RX_LENGTH   1536
16877 +#endif
16878 +
16879 +extern struct net_device               *dev_raether;
16880 +
16881 +
16882 +#if defined (CONFIG_RAETH_MULTIPLE_RX_RING)
16883 +#ifdef CONFIG_RAETH_RW_PDMAPTR_FROM_VAR
16884 +extern int rx_calc_idx1;
16885 +#endif
16886 +#endif
16887 +#ifdef CONFIG_RAETH_RW_PDMAPTR_FROM_VAR
16888 +extern int rx_calc_idx0;
16889 +static unsigned long tx_cpu_owner_idx0=0;
16890 +#endif
16891 +extern unsigned long tx_ring_full;
16892 +
16893 +#if defined (CONFIG_ETHTOOL) /*&& defined (CONFIG_RAETH_ROUTER)*/
16894 +#include "ra_ethtool.h"
16895 +extern struct ethtool_ops      ra_ethtool_ops;
16896 +#ifdef CONFIG_PSEUDO_SUPPORT
16897 +extern struct ethtool_ops      ra_virt_ethtool_ops;
16898 +#endif // CONFIG_PSEUDO_SUPPORT //
16899 +#endif // (CONFIG_ETHTOOL //
16900 +
16901 +#ifdef CONFIG_RALINK_VISTA_BASIC
16902 +int is_switch_175c = 1;
16903 +#endif
16904 +
16905 +#ifdef CONFIG_RAETH_PDMATX_QDMARX      /* QDMA RX */
16906 +struct QDMA_txdesc *free_head = NULL;
16907 +#endif
16908 +
16909 +//#if defined (CONFIG_RAETH_LRO)
16910 +#if 0
16911 +unsigned int lan_ip;
16912 +struct lro_para_struct lro_para;
16913 +int lro_flush_needed;
16914 +extern char const *nvram_get(int index, char *name);
16915 +#endif
16916 +
16917 +#define KSEG1                   0xa0000000
16918 +#define PHYS_TO_VIRT(x)         ((void *)((x) | KSEG1))
16919 +#define VIRT_TO_PHYS(x)         ((unsigned long)(x) & ~KSEG1)
16920 +
16921 +extern void set_fe_dma_glo_cfg(void);
16922 +
16923 +/*
16924 + *  @brief cal txd number for a page
16925 + *
16926 + *  @parm size
16927 + *
16928 + *  @return frag_txd_num
16929 + */
16930 +
16931 +unsigned int cal_frag_txd_num(unsigned int size)
16932 +{
16933 +       unsigned int frag_txd_num = 0;
16934 +       if(size == 0)
16935 +               return 0;
16936 +       while(size > 0){
16937 +               if(size > MAX_TXD_LEN){
16938 +                       frag_txd_num++;
16939 +                       size -= MAX_TXD_LEN;
16940 +               }else{
16941 +                       frag_txd_num++;
16942 +                       size = 0;
16943 +               }
16944 +       }
16945 +       return frag_txd_num;
16946 +
16947 +}
16948 +
16949 +#ifdef CONFIG_RAETH_PDMATX_QDMARX      /* QDMA RX */
16950 +bool fq_qdma_init(struct net_device *dev)
16951 +{
16952 +       END_DEVICE* ei_local = netdev_priv(dev);
16953 +       unsigned int phy_free_head;
16954 +       unsigned int phy_free_tail;
16955 +       unsigned int *free_page_head = NULL;
16956 +       unsigned int phy_free_page_head;
16957 +       int i;
16958 +
16959 +       free_head = pci_alloc_consistent(NULL, NUM_QDMA_PAGE * sizeof(struct QDMA_txdesc), &phy_free_head);
16960 +       if (unlikely(free_head == NULL)){
16961 +               printk(KERN_ERR "QDMA FQ decriptor not available...\n");
16962 +               return 0;
16963 +       }
16964 +       memset(free_head, 0x0, sizeof(struct QDMA_txdesc) * NUM_QDMA_PAGE);
16965 +
16966 +       free_page_head = pci_alloc_consistent(NULL, NUM_QDMA_PAGE * QDMA_PAGE_SIZE, &phy_free_page_head);
16967 +       if (unlikely(free_page_head == NULL)){
16968 +               printk(KERN_ERR "QDMA FQ page not available...\n");
16969 +               return 0;
16970 +       }
16971 +       for (i=0; i < NUM_QDMA_PAGE; i++) {
16972 +               free_head[i].txd_info1.SDP = (phy_free_page_head + (i * QDMA_PAGE_SIZE));
16973 +               if(i < (NUM_QDMA_PAGE-1)){
16974 +                       free_head[i].txd_info2.NDP = (phy_free_head + ((i+1) * sizeof(struct QDMA_txdesc)));
16975 +
16976 +
16977 +#if 0
16978 +                       printk("free_head_phy[%d] is 0x%x!!!\n",i, VIRT_TO_PHYS(&free_head[i]) );
16979 +                       printk("free_head[%d] is 0x%x!!!\n",i, &free_head[i] );
16980 +                       printk("free_head[%d].txd_info1.SDP is 0x%x!!!\n",i, free_head[i].txd_info1.SDP );
16981 +                       printk("free_head[%d].txd_info2.NDP is 0x%x!!!\n",i, free_head[i].txd_info2.NDP );
16982 +#endif
16983 +               }
16984 +               free_head[i].txd_info3.SDL = QDMA_PAGE_SIZE;
16985 +
16986 +       }
16987 +       phy_free_tail = (phy_free_head + (u32)((NUM_QDMA_PAGE-1) * sizeof(struct QDMA_txdesc)));
16988 +
16989 +       printk("phy_free_head is 0x%x!!!\n", phy_free_head);
16990 +       printk("phy_free_tail_phy is 0x%x!!!\n", phy_free_tail);
16991 +       sysRegWrite(QDMA_FQ_HEAD, (u32)phy_free_head);
16992 +       sysRegWrite(QDMA_FQ_TAIL, (u32)phy_free_tail);
16993 +       sysRegWrite(QDMA_FQ_CNT, ((NUM_TX_DESC << 16) | NUM_QDMA_PAGE));
16994 +       sysRegWrite(QDMA_FQ_BLEN, QDMA_PAGE_SIZE << 16);
16995 +
16996 +       ei_local->free_head = free_head;
16997 +       ei_local->phy_free_head = phy_free_head;
16998 +       ei_local->free_page_head = free_page_head;
16999 +       ei_local->phy_free_page_head = phy_free_page_head;
17000 +    return 1;
17001 +}
17002 +#endif
17003 +
17004 +int fe_dma_init(struct net_device *dev)
17005 +{
17006 +
17007 +       int             i;
17008 +       unsigned int    regVal;
17009 +       END_DEVICE* ei_local = netdev_priv(dev);
17010 +#if defined (CONFIG_RAETH_QOS)
17011 +       int             j;
17012 +#endif
17013 +
17014 +       while(1)
17015 +       {
17016 +               regVal = sysRegRead(PDMA_GLO_CFG);
17017 +               if((regVal & RX_DMA_BUSY))
17018 +               {
17019 +                       printk("\n  RX_DMA_BUSY !!! ");
17020 +                       continue;
17021 +               }
17022 +               if((regVal & TX_DMA_BUSY))
17023 +               {
17024 +                       printk("\n  TX_DMA_BUSY !!! ");
17025 +                       continue;
17026 +               }
17027 +               break;
17028 +       }
17029 +
17030 +#if defined(CONFIG_RAETH_PDMA_DVT)
17031 +       pdma_dvt_set_dma_mode();
17032 +#endif  /* CONFIG_RAETH_PDMA_DVT */
17033 +
17034 +#if defined (CONFIG_RAETH_QOS)
17035 +       for (i=0;i<NUM_TX_RINGS;i++){
17036 +               for (j=0;j<NUM_TX_DESC;j++){
17037 +                       ei_local->skb_free[i][j]=0;
17038 +               }
17039 +                ei_local->free_idx[i]=0;
17040 +       }
17041 +       /*
17042 +        * RT2880: 2 x TX_Ring, 1 x Rx_Ring
17043 +        * RT2883: 4 x TX_Ring, 1 x Rx_Ring
17044 +        * RT3883: 4 x TX_Ring, 1 x Rx_Ring
17045 +        * RT3052: 4 x TX_Ring, 1 x Rx_Ring
17046 +        */
17047 +       fe_tx_desc_init(dev, 0, 3, 1);
17048 +       if (ei_local->tx_ring0 == NULL) {
17049 +               printk("RAETH: tx ring0 allocation failed\n");
17050 +               return 0;
17051 +       }
17052 +
17053 +       fe_tx_desc_init(dev, 1, 3, 1);
17054 +       if (ei_local->tx_ring1 == NULL) {
17055 +               printk("RAETH: tx ring1 allocation failed\n");
17056 +               return 0;
17057 +       }
17058 +
17059 +       printk("\nphy_tx_ring0 = %08x, tx_ring0 = %p, size: %d bytes\n", ei_local->phy_tx_ring0, ei_local->tx_ring0, sizeof(struct PDMA_txdesc));
17060 +
17061 +       printk("\nphy_tx_ring1 = %08x, tx_ring1 = %p, size: %d bytes\n", ei_local->phy_tx_ring1, ei_local->tx_ring1, sizeof(struct PDMA_txdesc));
17062 +
17063 +#if ! defined (CONFIG_RALINK_RT2880)
17064 +       fe_tx_desc_init(dev, 2, 3, 1);
17065 +       if (ei_local->tx_ring2 == NULL) {
17066 +               printk("RAETH: tx ring2 allocation failed\n");
17067 +               return 0;
17068 +       }
17069 +
17070 +       fe_tx_desc_init(dev, 3, 3, 1);
17071 +       if (ei_local->tx_ring3 == NULL) {
17072 +               printk("RAETH: tx ring3 allocation failed\n");
17073 +               return 0;
17074 +       }
17075 +
17076 +       printk("\nphy_tx_ring2 = %08x, tx_ring2 = %p, size: %d bytes\n", ei_local->phy_tx_ring2, ei_local->tx_ring2, sizeof(struct PDMA_txdesc));
17077 +
17078 +       printk("\nphy_tx_ring3 = %08x, tx_ring3 = %p, size: %d bytes\n", ei_local->phy_tx_ring3, ei_local->tx_ring3, sizeof(struct PDMA_txdesc));
17079 +
17080 +#endif // CONFIG_RALINK_RT2880 //
17081 +#else
17082 +       for (i=0;i<NUM_TX_DESC;i++){
17083 +               ei_local->skb_free[i]=0;
17084 +       }
17085 +       ei_local->free_idx =0;
17086 +#if defined (CONFIG_MIPS)
17087 +       ei_local->tx_ring0 = pci_alloc_consistent(NULL, NUM_TX_DESC * sizeof(struct PDMA_txdesc), &ei_local->phy_tx_ring0);
17088 +#else
17089 +       ei_local->tx_ring0 = dma_alloc_coherent(NULL, NUM_TX_DESC * sizeof(struct PDMA_txdesc), &ei_local->phy_tx_ring0, GFP_KERNEL);
17090 +#endif
17091 +       printk("\nphy_tx_ring = 0x%08x, tx_ring = 0x%p\n", ei_local->phy_tx_ring0, ei_local->tx_ring0);
17092 +
17093 +       for (i=0; i < NUM_TX_DESC; i++) {
17094 +               memset(&ei_local->tx_ring0[i],0,sizeof(struct PDMA_txdesc));
17095 +               ei_local->tx_ring0[i].txd_info2.LS0_bit = 1;
17096 +               ei_local->tx_ring0[i].txd_info2.DDONE_bit = 1;
17097 +
17098 +       }
17099 +#endif // CONFIG_RAETH_QOS
17100 +
17101 +#ifdef CONFIG_RAETH_PDMATX_QDMARX      /* QDMA RX */
17102 +
17103 +       fq_qdma_init(dev);
17104 +
17105 +       while(1)
17106 +       {
17107 +               regVal = sysRegRead(QDMA_GLO_CFG);
17108 +               if((regVal & RX_DMA_BUSY))
17109 +               {
17110 +                       printk("\n  RX_DMA_BUSY !!! ");
17111 +                       continue;
17112 +               }
17113 +               if((regVal & TX_DMA_BUSY))
17114 +               {
17115 +                       printk("\n  TX_DMA_BUSY !!! ");
17116 +                       continue;
17117 +               }
17118 +               break;
17119 +       }
17120 +
17121 +       /* Initial RX Ring 0*/
17122 +
17123 +#ifdef CONFIG_32B_DESC
17124 +       ei_local->qrx_ring = kmalloc(NUM_QRX_DESC * sizeof(struct PDMA_rxdesc), GFP_KERNEL);
17125 +       ei_local->phy_qrx_ring = virt_to_phys(ei_local->qrx_ring);
17126 +#else
17127 +       ei_local->qrx_ring = pci_alloc_consistent(NULL, NUM_QRX_DESC * sizeof(struct PDMA_rxdesc), &ei_local->phy_qrx_ring);
17128 +#endif
17129 +       for (i = 0; i < NUM_QRX_DESC; i++) {
17130 +               memset(&ei_local->qrx_ring[i],0,sizeof(struct PDMA_rxdesc));
17131 +               ei_local->qrx_ring[i].rxd_info2.DDONE_bit = 0;
17132 +#if defined (CONFIG_RAETH_SCATTER_GATHER_RX_DMA)
17133 +               ei_local->qrx_ring[i].rxd_info2.LS0 = 0;
17134 +               ei_local->qrx_ring[i].rxd_info2.PLEN0 = MAX_RX_LENGTH;
17135 +#else
17136 +               ei_local->qrx_ring[i].rxd_info2.LS0 = 1;
17137 +#endif
17138 +               ei_local->qrx_ring[i].rxd_info1.PDP0 = dma_map_single(NULL, ei_local->netrx0_skbuf[i]->data, MAX_RX_LENGTH, PCI_DMA_FROMDEVICE);
17139 +       }
17140 +       printk("\nphy_qrx_ring = 0x%08x, qrx_ring = 0x%p\n",ei_local->phy_qrx_ring,ei_local->qrx_ring);
17141 +
17142 +       regVal = sysRegRead(QDMA_GLO_CFG);
17143 +       regVal &= 0x000000FF;
17144 +
17145 +       sysRegWrite(QDMA_GLO_CFG, regVal);
17146 +       regVal=sysRegRead(QDMA_GLO_CFG);
17147 +
17148 +       /* Tell the adapter where the TX/RX rings are located. */
17149 +
17150 +       sysRegWrite(QRX_BASE_PTR_0, phys_to_bus((u32) ei_local->phy_qrx_ring));
17151 +       sysRegWrite(QRX_MAX_CNT_0,  cpu_to_le32((u32) NUM_QRX_DESC));
17152 +       sysRegWrite(QRX_CRX_IDX_0, cpu_to_le32((u32) (NUM_QRX_DESC - 1)));
17153 +#ifdef CONFIG_RAETH_RW_PDMAPTR_FROM_VAR
17154 +       rx_calc_idx0 = rx_dma_owner_idx0 =  sysRegRead(QRX_CRX_IDX_0);
17155 +#endif
17156 +       sysRegWrite(QDMA_RST_CFG, PST_DRX_IDX0);
17157 +
17158 +        ei_local->rx_ring0 = ei_local->qrx_ring;
17159 +
17160 +#else  /* PDMA RX */
17161 +
17162 +       /* Initial RX Ring 0*/
17163 +#ifdef CONFIG_32B_DESC
17164 +       ei_local->rx_ring0 = kmalloc(NUM_RX_DESC * sizeof(struct PDMA_rxdesc), GFP_KERNEL);
17165 +       ei_local->phy_rx_ring0 = virt_to_phys(ei_local->rx_ring0);
17166 +#else
17167 +#if defined (CONFIG_MIPS)
17168 +       ei_local->rx_ring0 = pci_alloc_consistent(NULL, NUM_RX_DESC * sizeof(struct PDMA_rxdesc), &ei_local->phy_rx_ring0);
17169 +#else
17170 +       ei_local->rx_ring0 = dma_alloc_coherent(NULL, NUM_RX_DESC * sizeof(struct PDMA_rxdesc), &ei_local->phy_rx_ring0, GFP_KERNEL);
17171 +#endif
17172 +#endif
17173 +       for (i = 0; i < NUM_RX_DESC; i++) {
17174 +               memset(&ei_local->rx_ring0[i],0,sizeof(struct PDMA_rxdesc));
17175 +               ei_local->rx_ring0[i].rxd_info2.DDONE_bit = 0;
17176 +#if defined (CONFIG_RAETH_SCATTER_GATHER_RX_DMA)
17177 +               ei_local->rx_ring0[i].rxd_info2.LS0 = 0;
17178 +               ei_local->rx_ring0[i].rxd_info2.PLEN0 = MAX_RX_LENGTH;
17179 +#else
17180 +               ei_local->rx_ring0[i].rxd_info2.LS0 = 1;
17181 +#endif
17182 +               ei_local->rx_ring0[i].rxd_info1.PDP0 = dma_map_single(NULL, ei_local->netrx0_skbuf[i]->data, MAX_RX_LENGTH, PCI_DMA_FROMDEVICE);
17183 +       }
17184 +       printk("\nphy_rx_ring0 = 0x%08x, rx_ring0 = 0x%p\n",ei_local->phy_rx_ring0,ei_local->rx_ring0);
17185 +
17186 +#if defined (CONFIG_RAETH_MULTIPLE_RX_RING)
17187 +       /* Initial RX Ring 1*/
17188 +#ifdef CONFIG_32B_DESC
17189 +       ei_local->rx_ring1 = kmalloc(NUM_RX_DESC * sizeof(struct PDMA_rxdesc), GFP_KERNEL);
17190 +       ei_local->phy_rx_ring1 = virt_to_phys(ei_local->rx_ring1);
17191 +#else
17192 +#if defined (CONFIG_MIPS)
17193 +       ei_local->rx_ring1 = pci_alloc_consistent(NULL, NUM_RX_DESC * sizeof(struct PDMA_rxdesc), &ei_local->phy_rx_ring1);
17194 +#else
17195 +       ei_local->rx_ring1 = dma_alloc_coherent(NULL, NUM_RX_DESC * sizeof(struct PDMA_rxdesc), &ei_local->phy_rx_ring1, GFP_KERNEL);
17196 +
17197 +#endif
17198 +#endif
17199 +       for (i = 0; i < NUM_RX_DESC; i++) {
17200 +               memset(&ei_local->rx_ring1[i],0,sizeof(struct PDMA_rxdesc));
17201 +               ei_local->rx_ring1[i].rxd_info2.DDONE_bit = 0;
17202 +#if defined (CONFIG_RAETH_SCATTER_GATHER_RX_DMA)
17203 +               ei_local->rx_ring1[i].rxd_info2.LS0 = 0;
17204 +               ei_local->rx_ring1[i].rxd_info2.PLEN0 = MAX_RX_LENGTH;
17205 +#else
17206 +               ei_local->rx_ring1[i].rxd_info2.LS0 = 1;
17207 +#endif
17208 +               ei_local->rx_ring1[i].rxd_info1.PDP0 = dma_map_single(NULL, ei_local->netrx1_skbuf[i]->data, MAX_RX_LENGTH, PCI_DMA_FROMDEVICE);
17209 +       }
17210 +       printk("\nphy_rx_ring1 = 0x%08x, rx_ring1 = 0x%p\n",ei_local->phy_rx_ring1,ei_local->rx_ring1);
17211 +#if defined(CONFIG_ARCH_MT7623)
17212 +    /* Initial RX Ring 2*/
17213 +    ei_local->rx_ring2 = pci_alloc_consistent(NULL, NUM_RX_DESC * sizeof(struct PDMA_rxdesc), &ei_local->phy_rx_ring2);
17214 +    for (i = 0; i < NUM_RX_DESC; i++) {
17215 +        memset(&ei_local->rx_ring2[i],0,sizeof(struct PDMA_rxdesc));
17216 +        ei_local->rx_ring2[i].rxd_info2.DDONE_bit = 0;
17217 +        ei_local->rx_ring2[i].rxd_info2.LS0 = 0;
17218 +        ei_local->rx_ring2[i].rxd_info2.PLEN0 = SET_ADMA_RX_LEN0(MAX_RX_LENGTH);
17219 +        ei_local->rx_ring2[i].rxd_info2.PLEN1 = SET_ADMA_RX_LEN1(MAX_RX_LENGTH >> 14);
17220 +        ei_local->rx_ring2[i].rxd_info1.PDP0 = dma_map_single(NULL, ei_local->netrx2_skbuf[i]->data, MAX_RX_LENGTH, PCI_DMA_FROMDEVICE);
17221 +    }
17222 +    printk("\nphy_rx_ring2 = 0x%08x, rx_ring2 = 0x%p\n",ei_local->phy_rx_ring2,ei_local->rx_ring2);
17223 +    /* Initial RX Ring 3*/
17224 +       ei_local->rx_ring3 = pci_alloc_consistent(NULL, NUM_RX_DESC * sizeof(struct PDMA_rxdesc), &ei_local->phy_rx_ring3);
17225 +       for (i = 0; i < NUM_RX_DESC; i++) {
17226 +               memset(&ei_local->rx_ring3[i],0,sizeof(struct PDMA_rxdesc));
17227 +       ei_local->rx_ring3[i].rxd_info2.DDONE_bit = 0;
17228 +        ei_local->rx_ring3[i].rxd_info2.LS0 = 0;
17229 +        ei_local->rx_ring3[i].rxd_info2.PLEN0 = SET_ADMA_RX_LEN0(MAX_RX_LENGTH);
17230 +        ei_local->rx_ring3[i].rxd_info2.PLEN1 = SET_ADMA_RX_LEN1(MAX_RX_LENGTH >> 14);
17231 +               ei_local->rx_ring3[i].rxd_info1.PDP0 = dma_map_single(NULL, ei_local->netrx3_skbuf[i]->data, MAX_RX_LENGTH, PCI_DMA_FROMDEVICE);
17232 +       }
17233 +       printk("\nphy_rx_ring3 = 0x%08x, rx_ring3 = 0x%p\n",ei_local->phy_rx_ring3,ei_local->rx_ring3);
17234 +#endif  /* CONFIG_ARCH_MT7623 */
17235 +#endif
17236 +
17237 +#endif
17238 +
17239 +       regVal = sysRegRead(PDMA_GLO_CFG);
17240 +       regVal &= 0x000000FF;
17241 +       sysRegWrite(PDMA_GLO_CFG, regVal);
17242 +       regVal=sysRegRead(PDMA_GLO_CFG);
17243 +
17244 +       /* Tell the adapter where the TX/RX rings are located. */
17245 +#if !defined (CONFIG_RAETH_QOS)
17246 +        sysRegWrite(TX_BASE_PTR0, phys_to_bus((u32) ei_local->phy_tx_ring0));
17247 +       sysRegWrite(TX_MAX_CNT0, cpu_to_le32((u32) NUM_TX_DESC));
17248 +       sysRegWrite(TX_CTX_IDX0, 0);
17249 +#ifdef CONFIG_RAETH_RW_PDMAPTR_FROM_VAR
17250 +       tx_cpu_owner_idx0 = 0;
17251 +#endif
17252 +       sysRegWrite(PDMA_RST_CFG, PST_DTX_IDX0);
17253 +#endif
17254 +
17255 +#ifdef CONFIG_RAETH_PDMATX_QDMARX      /* QDMA RX */
17256 +       sysRegWrite(QRX_BASE_PTR_0, phys_to_bus((u32) ei_local->phy_qrx_ring));
17257 +       sysRegWrite(QRX_MAX_CNT_0,  cpu_to_le32((u32) NUM_QRX_DESC));
17258 +       sysRegWrite(QRX_CRX_IDX_0, cpu_to_le32((u32) (NUM_QRX_DESC - 1)));
17259 +#else  /* PDMA RX */
17260 +       sysRegWrite(RX_BASE_PTR0, phys_to_bus((u32) ei_local->phy_rx_ring0));
17261 +       sysRegWrite(RX_MAX_CNT0,  cpu_to_le32((u32) NUM_RX_DESC));
17262 +       sysRegWrite(RX_CALC_IDX0, cpu_to_le32((u32) (NUM_RX_DESC - 1)));
17263 +#endif
17264 +
17265 +#ifdef CONFIG_RAETH_RW_PDMAPTR_FROM_VAR
17266 +       rx_calc_idx0 =  sysRegRead(RX_CALC_IDX0);
17267 +#endif
17268 +       sysRegWrite(PDMA_RST_CFG, PST_DRX_IDX0);
17269 +#if defined (CONFIG_RAETH_MULTIPLE_RX_RING)
17270 +       sysRegWrite(RX_BASE_PTR1, phys_to_bus((u32) ei_local->phy_rx_ring1));
17271 +       sysRegWrite(RX_MAX_CNT1,  cpu_to_le32((u32) NUM_RX_DESC));
17272 +       sysRegWrite(RX_CALC_IDX1, cpu_to_le32((u32) (NUM_RX_DESC - 1)));
17273 +#ifdef CONFIG_RAETH_RW_PDMAPTR_FROM_VAR
17274 +       rx_calc_idx1 =  sysRegRead(RX_CALC_IDX1);
17275 +#endif
17276 +       sysRegWrite(PDMA_RST_CFG, PST_DRX_IDX1);
17277 +#if defined(CONFIG_ARCH_MT7623)
17278 +       sysRegWrite(RX_BASE_PTR2, phys_to_bus((u32) ei_local->phy_rx_ring2));
17279 +       sysRegWrite(RX_MAX_CNT2,  cpu_to_le32((u32) NUM_RX_DESC));
17280 +       sysRegWrite(RX_CALC_IDX2, cpu_to_le32((u32) (NUM_RX_DESC - 1)));
17281 +       sysRegWrite(PDMA_RST_CFG, PST_DRX_IDX2);
17282 +    sysRegWrite(RX_BASE_PTR3, phys_to_bus((u32) ei_local->phy_rx_ring3));
17283 +       sysRegWrite(RX_MAX_CNT3,  cpu_to_le32((u32) NUM_RX_DESC));
17284 +       sysRegWrite(RX_CALC_IDX3, cpu_to_le32((u32) (NUM_RX_DESC - 1)));
17285 +       sysRegWrite(PDMA_RST_CFG, PST_DRX_IDX3);
17286 +#endif  /* CONFIG_ARCH_MT7623 */
17287 +#endif
17288 +#if defined (CONFIG_RALINK_RT6855A)
17289 +       regVal = sysRegRead(RX_DRX_IDX0);
17290 +       regVal = (regVal == 0)? (NUM_RX_DESC - 1) : (regVal - 1);
17291 +       sysRegWrite(RX_CALC_IDX0, cpu_to_le32(regVal));
17292 +#ifdef CONFIG_RAETH_RW_PDMAPTR_FROM_VAR
17293 +       rx_calc_idx0 =  sysRegRead(RX_CALC_IDX0);
17294 +#endif
17295 +       regVal = sysRegRead(TX_DTX_IDX0);
17296 +       sysRegWrite(TX_CTX_IDX0, cpu_to_le32(regVal));
17297 +#ifdef CONFIG_RAETH_RW_PDMAPTR_FROM_VAR
17298 +       tx_cpu_owner_idx0 = regVal;
17299 +#endif
17300 +       ei_local->free_idx = regVal;
17301 +#endif
17302 +
17303 +#if defined (CONFIG_RAETH_QOS)
17304 +       set_scheduler_weight();
17305 +       set_schedule_pause_condition();
17306 +       set_output_shaper();
17307 +#endif
17308 +
17309 +       set_fe_dma_glo_cfg();
17310 +
17311 +       return 1;
17312 +}
17313 +
17314 +inline int rt2880_eth_send(struct net_device* dev, struct sk_buff *skb, int gmac_no)
17315 +{
17316 +       unsigned int    length=skb->len;
17317 +       END_DEVICE*     ei_local = netdev_priv(dev);
17318 +#ifndef CONFIG_RAETH_RW_PDMAPTR_FROM_VAR
17319 +       unsigned long   tx_cpu_owner_idx0 = sysRegRead(TX_CTX_IDX0);
17320 +#endif
17321 +#if defined (CONFIG_RAETH_TSO)
17322 +#ifdef CONFIG_RAETH_RW_PDMAPTR_FROM_VAR
17323 +       unsigned long   ctx_idx_start_addr = tx_cpu_owner_idx0;
17324 +#endif
17325 +        struct iphdr *iph = NULL;
17326 +        struct tcphdr *th = NULL;
17327 +       struct skb_frag_struct *frag;
17328 +       unsigned int nr_frags = skb_shinfo(skb)->nr_frags;
17329 +       int i=0;
17330 +       unsigned int len, size, offset, frag_txd_num, skb_txd_num ;
17331 +#endif // CONFIG_RAETH_TSO //
17332 +
17333 +#if defined (CONFIG_RAETH_TSOV6)
17334 +       struct ipv6hdr *ip6h = NULL;
17335 +#endif
17336 +
17337 +#ifdef CONFIG_PSEUDO_SUPPORT
17338 +       PSEUDO_ADAPTER *pAd;
17339 +#endif
17340 +
17341 +       while(ei_local->tx_ring0[tx_cpu_owner_idx0].txd_info2.DDONE_bit == 0)
17342 +       {
17343 +#ifdef CONFIG_PSEUDO_SUPPORT
17344 +               if (gmac_no == 2) {
17345 +                       if (ei_local->PseudoDev != NULL) {
17346 +                               pAd = netdev_priv(ei_local->PseudoDev);
17347 +                               pAd->stat.tx_errors++;
17348 +                       }
17349 +               } else
17350 +#endif
17351 +                       ei_local->stat.tx_errors++;
17352 +       }
17353 +
17354 +#if !defined (CONFIG_RAETH_TSO)
17355 +       ei_local->tx_ring0[tx_cpu_owner_idx0].txd_info1.SDP0 = virt_to_phys(skb->data);
17356 +       ei_local->tx_ring0[tx_cpu_owner_idx0].txd_info2.SDL0 = length;
17357 +#if defined (CONFIG_RALINK_MT7620)
17358 +       ei_local->tx_ring0[tx_cpu_owner_idx0].txd_info4.FP_BMAP = 0;
17359 +#elif defined (CONFIG_RALINK_MT7621) || defined (CONFIG_ARCH_MT7623)
17360 +       if (gmac_no == 1) {
17361 +               ei_local->tx_ring0[tx_cpu_owner_idx0].txd_info4.FPORT = 1;
17362 +       }else {
17363 +               ei_local->tx_ring0[tx_cpu_owner_idx0].txd_info4.FPORT = 2;
17364 +       }
17365 +#else
17366 +       ei_local->tx_ring0[tx_cpu_owner_idx0].txd_info4.PN = gmac_no;
17367 +       ei_local->tx_ring0[tx_cpu_owner_idx0].txd_info4.QN = 3;
17368 +#endif
17369 +
17370 +#if defined (CONFIG_RAETH_CHECKSUM_OFFLOAD) && ! defined(CONFIG_RALINK_RT5350) && !defined(CONFIG_RALINK_MT7628)
17371 +       if (skb->ip_summed == CHECKSUM_PARTIAL){
17372 +           ei_local->tx_ring0[tx_cpu_owner_idx0].txd_info4.TUI_CO = 7;
17373 +       }else {
17374 +           ei_local->tx_ring0[tx_cpu_owner_idx0].txd_info4.TUI_CO = 0;
17375 +       }
17376 +#endif
17377 +
17378 +#ifdef CONFIG_RAETH_HW_VLAN_TX
17379 +       if(vlan_tx_tag_present(skb)) {
17380 +#if defined (CONFIG_RALINK_MT7621) || defined (CONFIG_ARCH_MT7623)
17381 +           ei_local->tx_ring0[tx_cpu_owner_idx0].txd_info4.VLAN_TAG = 0x10000 | vlan_tx_tag_get(skb);
17382 +#else
17383 +           ei_local->tx_ring0[tx_cpu_owner_idx0].txd_info4.VPRI_VIDX = 0x80 | (vlan_tx_tag_get(skb) >> 13) << 4 | (vlan_tx_tag_get(skb) & 0xF);
17384 +#endif
17385 +       }else {
17386 +#if defined (CONFIG_RALINK_MT7621) || defined (CONFIG_ARCH_MT7623)
17387 +           ei_local->tx_ring0[tx_cpu_owner_idx0].txd_info4.VLAN_TAG = 0;
17388 +#else
17389 +           ei_local->tx_ring0[tx_cpu_owner_idx0].txd_info4.VPRI_VIDX = 0;
17390 +#endif
17391 +       }
17392 +#endif
17393 +
17394 +#if defined(CONFIG_RAETH_PDMA_DVT)
17395 +    raeth_pdma_tx_vlan_dvt( ei_local, tx_cpu_owner_idx0 );
17396 +#endif  /* CONFIG_RAETH_PDMA_DVT */
17397 +
17398 +#if defined (CONFIG_RA_HW_NAT) || defined (CONFIG_RA_HW_NAT_MODULE)
17399 +       if(FOE_MAGIC_TAG(skb) == FOE_MAGIC_PPE) {
17400 +           if(ra_sw_nat_hook_rx!= NULL){
17401 +#if defined (CONFIG_RALINK_MT7620)
17402 +               ei_local->tx_ring0[tx_cpu_owner_idx0].txd_info4.FP_BMAP = (1 << 7); /* PPE */
17403 +#elif defined (CONFIG_RALINK_MT7621) || defined (CONFIG_ARCH_MT7623)
17404 +               ei_local->tx_ring0[tx_cpu_owner_idx0].txd_info4.FPORT = 4; /* PPE */
17405 +#else
17406 +               ei_local->tx_ring0[tx_cpu_owner_idx0].txd_info4.PN = 6; /* PPE */
17407 +#endif
17408 +               FOE_MAGIC_TAG(skb) = 0;
17409 +           }
17410 +       }
17411 +#endif
17412 +
17413 +#if defined(CONFIG_RAETH_PDMA_DVT)
17414 +    raeth_pdma_tx_desc_dvt( ei_local, tx_cpu_owner_idx0 );
17415 +#endif  /* CONFIG_RAETH_PDMA_DVT */
17416 +
17417 +       ei_local->tx_ring0[tx_cpu_owner_idx0].txd_info2.DDONE_bit = 0;
17418 +
17419 +#if 0
17420 +       printk("---------------\n");
17421 +       printk("tx_info1=%x\n",ei_local->tx_ring0[tx_cpu_owner_idx0].txd_info1);
17422 +       printk("tx_info2=%x\n",ei_local->tx_ring0[tx_cpu_owner_idx0].txd_info2);
17423 +       printk("tx_info3=%x\n",ei_local->tx_ring0[tx_cpu_owner_idx0].txd_info3);
17424 +       printk("tx_info4=%x\n",ei_local->tx_ring0[tx_cpu_owner_idx0].txd_info4);
17425 +#endif
17426 +
17427 +#else
17428 +       ei_local->tx_ring0[tx_cpu_owner_idx0].txd_info1.SDP0 = virt_to_phys(skb->data);
17429 +       ei_local->tx_ring0[tx_cpu_owner_idx0].txd_info2.SDL0 = (length - skb->data_len);
17430 +       ei_local->tx_ring0[tx_cpu_owner_idx0].txd_info2.LS0_bit = nr_frags ? 0:1;
17431 +#if defined (CONFIG_RALINK_MT7620)
17432 +       ei_local->tx_ring0[tx_cpu_owner_idx0].txd_info4.FP_BMAP = 0;
17433 +#elif defined (CONFIG_RALINK_MT7621) || defined (CONFIG_ARCH_MT7623)
17434 +       if (gmac_no == 1) {
17435 +               ei_local->tx_ring0[tx_cpu_owner_idx0].txd_info4.FPORT = 1;
17436 +       }else {
17437 +               ei_local->tx_ring0[tx_cpu_owner_idx0].txd_info4.FPORT = 2;
17438 +       }
17439 +#else
17440 +       ei_local->tx_ring0[tx_cpu_owner_idx0].txd_info4.PN = gmac_no;
17441 +       ei_local->tx_ring0[tx_cpu_owner_idx0].txd_info4.QN = 3;
17442 +#endif
17443 +       ei_local->tx_ring0[tx_cpu_owner_idx0].txd_info4.TSO = 0;
17444 +
17445 +#if defined (CONFIG_RAETH_CHECKSUM_OFFLOAD) && ! defined(CONFIG_RALINK_RT5350) && !defined(CONFIG_RALINK_MT7628)
17446 +       if (skb->ip_summed == CHECKSUM_PARTIAL){
17447 +           ei_local->tx_ring0[tx_cpu_owner_idx0].txd_info4.TUI_CO = 7;
17448 +       }else {
17449 +           ei_local->tx_ring0[tx_cpu_owner_idx0].txd_info4.TUI_CO = 0;
17450 +       }
17451 +#endif
17452 +
17453 +#ifdef CONFIG_RAETH_HW_VLAN_TX
17454 +       if(vlan_tx_tag_present(skb)) {
17455 +#if defined (CONFIG_RALINK_MT7621) || defined (CONFIG_ARCH_MT7623)
17456 +           ei_local->tx_ring0[tx_cpu_owner_idx0].txd_info4.VLAN_TAG = 0x10000 | vlan_tx_tag_get(skb);
17457 +#else
17458 +           ei_local->tx_ring0[tx_cpu_owner_idx0].txd_info4.VPRI_VIDX = 0x80 | (vlan_tx_tag_get(skb) >> 13) << 4 | (vlan_tx_tag_get(skb) & 0xF);
17459 +#endif
17460 +       }else {
17461 +#if defined (CONFIG_RALINK_MT7621) || defined (CONFIG_ARCH_MT7623)
17462 +           ei_local->tx_ring0[tx_cpu_owner_idx0].txd_info4.VLAN_TAG = 0;
17463 +#else
17464 +           ei_local->tx_ring0[tx_cpu_owner_idx0].txd_info4.VPRI_VIDX = 0;
17465 +#endif
17466 +       }
17467 +#endif
17468 +
17469 +#if defined(CONFIG_RAETH_PDMA_DVT)
17470 +    raeth_pdma_tx_vlan_dvt( ei_local, tx_cpu_owner_idx0 );
17471 +#endif  /* CONFIG_RAETH_PDMA_DVT */
17472 +
17473 +#if defined (CONFIG_RA_HW_NAT) || defined (CONFIG_RA_HW_NAT_MODULE)
17474 +       if(FOE_MAGIC_TAG(skb) == FOE_MAGIC_PPE) {
17475 +           if(ra_sw_nat_hook_rx!= NULL){
17476 +#if defined (CONFIG_RALINK_MT7620)
17477 +               ei_local->tx_ring0[tx_cpu_owner_idx0].txd_info4.FP_BMAP = (1 << 7); /* PPE */
17478 +#elif defined (CONFIG_RALINK_MT7621) || defined (CONFIG_ARCH_MT7623)
17479 +               ei_local->tx_ring0[tx_cpu_owner_idx0].txd_info4.FPORT = 4; /* PPE */
17480 +#else
17481 +               ei_local->tx_ring0[tx_cpu_owner_idx0].txd_info4.PN = 6; /* PPE */
17482 +#endif
17483 +               FOE_MAGIC_TAG(skb) = 0;
17484 +           }
17485 +       }
17486 +#endif
17487 +
17488 +       skb_txd_num = 1;
17489 +
17490 +       if(nr_frags > 0) {
17491 +
17492 +               for(i=0;i<nr_frags;i++) {
17493 +                       frag = &skb_shinfo(skb)->frags[i];
17494 +                       offset = frag->page_offset;
17495 +                       len = frag->size;
17496 +                       frag_txd_num = cal_frag_txd_num(len);
17497 +
17498 +                       while(frag_txd_num > 0){
17499 +                               if(len < MAX_TXD_LEN)
17500 +                                       size = len;
17501 +                               else
17502 +                                       size = MAX_TXD_LEN;
17503 +                               if(skb_txd_num%2 == 0) {
17504 +                                       tx_cpu_owner_idx0 = (tx_cpu_owner_idx0+1) % NUM_TX_DESC;
17505 +
17506 +                                       while(ei_local->tx_ring0[tx_cpu_owner_idx0].txd_info2.DDONE_bit == 0)
17507 +                                       {
17508 +#ifdef config_pseudo_support
17509 +                                               if (gmac_no == 2) {
17510 +                                                       if (ei_local->pseudodev != null) {
17511 +                                                               pad = netdev_priv(ei_local->pseudodev);
17512 +                                                               pad->stat.tx_errors++;
17513 +                                                       }
17514 +                                               } else
17515 +#endif
17516 +                                                       ei_local->stat.tx_errors++;
17517 +                                       }
17518 +
17519 +#if LINUX_VERSION_CODE < KERNEL_VERSION(3,2,0)
17520 +                                       ei_local->tx_ring0[tx_cpu_owner_idx0].txd_info1.SDP0 = pci_map_page(NULL, frag->page, offset, size, PCI_DMA_TODEVICE);
17521 +#else
17522 +                                       ei_local->tx_ring0[tx_cpu_owner_idx0].txd_info1.SDP0 = pci_map_page(NULL, frag->page.p, offset, size, PCI_DMA_TODEVICE);
17523 +#endif
17524 +                                       ei_local->tx_ring0[tx_cpu_owner_idx0].txd_info2.SDL0 = size;
17525 +
17526 +                                       if( (i==(nr_frags-1)) && (frag_txd_num == 1))
17527 +                                               ei_local->tx_ring0[tx_cpu_owner_idx0].txd_info2.LS0_bit = 1;
17528 +                                       else
17529 +                                               ei_local->tx_ring0[tx_cpu_owner_idx0].txd_info2.LS0_bit = 0;
17530 +                                       ei_local->tx_ring0[tx_cpu_owner_idx0].txd_info2.DDONE_bit = 0;
17531 +                               }else {
17532 +#if LINUX_VERSION_CODE < KERNEL_VERSION(3,2,0)
17533 +                                       ei_local->tx_ring0[tx_cpu_owner_idx0].txd_info3.SDP1 = pci_map_page(NULL, frag->page, offset, size, PCI_DMA_TODEVICE);
17534 +#else
17535 +                                       ei_local->tx_ring0[tx_cpu_owner_idx0].txd_info3.SDP1 = pci_map_page(NULL, frag->page.p, offset, size, PCI_DMA_TODEVICE);
17536 +
17537 +#endif
17538 +                                       ei_local->tx_ring0[tx_cpu_owner_idx0].txd_info2.SDL1 = size;
17539 +                                       if( (i==(nr_frags-1)) && (frag_txd_num == 1))
17540 +                                               ei_local->tx_ring0[tx_cpu_owner_idx0].txd_info2.LS1_bit = 1;
17541 +                                       else
17542 +                                               ei_local->tx_ring0[tx_cpu_owner_idx0].txd_info2.LS1_bit = 0;
17543 +                               }
17544 +                               offset += size;
17545 +                               len -= size;
17546 +                               frag_txd_num--;
17547 +                               skb_txd_num++;
17548 +                       }
17549 +               }
17550 +       }
17551 +
17552 +#if defined(CONFIG_RAETH_PDMA_DVT)
17553 +    if( (pdma_dvt_get_debug_test_config() & PDMA_TEST_TSO_DEBUG) ){
17554 +        printk("skb_shinfo(skb)->gso_segs = %d\n", skb_shinfo(skb)->gso_segs);
17555 +    }
17556 +#endif  /* CONFIG_RAETH_PDMA_DVT */
17557 +       /* fill in MSS info in tcp checksum field */
17558 +       if(skb_shinfo(skb)->gso_segs > 1) {
17559 +
17560 +//             TsoLenUpdate(skb->len);
17561 +
17562 +               /* TCP over IPv4 */
17563 +               iph = (struct iphdr *)skb_network_header(skb);
17564 +#if defined (CONFIG_RAETH_TSOV6)
17565 +               /* TCP over IPv6 */
17566 +               ip6h = (struct ipv6hdr *)skb_network_header(skb);
17567 +#endif
17568 +               if((iph->version == 4) && (iph->protocol == IPPROTO_TCP)) {
17569 +                       th = (struct tcphdr *)skb_transport_header(skb);
17570 +#ifdef CONFIG_RAETH_RW_PDMAPTR_FROM_VAR
17571 +                       ei_local->tx_ring0[ctx_idx_start_addr].txd_info4.TSO = 1;
17572 +#else
17573 +                       ei_local->tx_ring0[sysRegRead(TX_CTX_IDX0)].txd_info4.TSO = 1;
17574 +#endif
17575 +                       th->check = htons(skb_shinfo(skb)->gso_size);
17576 +#if defined (CONFIG_MIPS)
17577 +                       dma_cache_sync(NULL, th, sizeof(struct tcphdr), DMA_TO_DEVICE);
17578 +#else
17579 +                       dma_sync_single_for_device(NULL, virt_to_phys(th), sizeof(struct tcphdr), DMA_TO_DEVICE);
17580 +#endif
17581 +               }
17582 +
17583 +#if defined (CONFIG_RAETH_TSOV6)
17584 +               /* TCP over IPv6 */
17585 +               else if ((ip6h->version == 6) && (ip6h->nexthdr == NEXTHDR_TCP)) {
17586 +                       th = (struct tcphdr *)skb_transport_header(skb);
17587 +#ifdef CONFIG_RAETH_RW_PDMAPTR_FROM_VAR
17588 +                       ei_local->tx_ring0[ctx_idx_start_addr].txd_info4.TSO = 1;
17589 +#else
17590 +                       ei_local->tx_ring0[sysRegRead(TX_CTX_IDX0)].txd_info4.TSO = 1;
17591 +#endif
17592 +                       th->check = htons(skb_shinfo(skb)->gso_size);
17593 +#if defined (CONFIG_MIPS)
17594 +                       dma_cache_sync(NULL, th, sizeof(struct tcphdr), DMA_TO_DEVICE);
17595 +#else
17596 +                       dma_sync_single_for_device(NULL, virt_to_phys(th), sizeof(struct tcphdr), DMA_TO_DEVICE);
17597 +#endif
17598 +               }
17599 +#endif // CONFIG_RAETH_TSOV6 //
17600 +       }
17601 +
17602 +#if defined(CONFIG_RAETH_PDMA_DVT)
17603 +    raeth_pdma_tx_desc_dvt( ei_local, tx_cpu_owner_idx0 );
17604 +#endif  /* CONFIG_RAETH_PDMA_DVT */
17605 +
17606 +#ifdef CONFIG_RAETH_RW_PDMAPTR_FROM_VAR
17607 +       ei_local->tx_ring0[ctx_idx_start_addr].txd_info2.DDONE_bit = 0;
17608 +#else
17609 +       ei_local->tx_ring0[sysRegRead(TX_CTX_IDX0)].txd_info2.DDONE_bit = 0;
17610 +#endif
17611 +#endif // CONFIG_RAETH_TSO //
17612 +
17613 +       tx_cpu_owner_idx0 = (tx_cpu_owner_idx0+1) % NUM_TX_DESC;
17614 +       while(ei_local->tx_ring0[tx_cpu_owner_idx0].txd_info2.DDONE_bit == 0)
17615 +       {
17616 +//             printk(KERN_ERR "%s: TXD=%lu TX DMA is Busy !!\n", dev->name, tx_cpu_owner_idx0);
17617 +#ifdef CONFIG_PSEUDO_SUPPORT
17618 +               if (gmac_no == 2) {
17619 +                       if (ei_local->PseudoDev != NULL) {
17620 +                               pAd = netdev_priv(ei_local->PseudoDev);
17621 +                               pAd->stat.tx_errors++;
17622 +                       }
17623 +               } else
17624 +#endif
17625 +                       ei_local->stat.tx_errors++;
17626 +       }
17627 +       sysRegWrite(TX_CTX_IDX0, cpu_to_le32((u32)tx_cpu_owner_idx0));
17628 +
17629 +#ifdef CONFIG_PSEUDO_SUPPORT
17630 +       if (gmac_no == 2) {
17631 +               if (ei_local->PseudoDev != NULL) {
17632 +                       pAd = netdev_priv(ei_local->PseudoDev);
17633 +                       pAd->stat.tx_packets++;
17634 +                       pAd->stat.tx_bytes += length;
17635 +               }
17636 +       } else
17637 +#endif
17638 +       {
17639 +               ei_local->stat.tx_packets++;
17640 +               ei_local->stat.tx_bytes += length;
17641 +       }
17642 +#ifdef CONFIG_RAETH_NAPI
17643 +       if ( ei_local->tx_full == 1) {
17644 +               ei_local->tx_full = 0;
17645 +               netif_wake_queue(dev);
17646 +       }
17647 +#endif
17648 +
17649 +       return length;
17650 +}
17651 +
17652 +int ei_start_xmit(struct sk_buff* skb, struct net_device *dev, int gmac_no)
17653 +{
17654 +       END_DEVICE *ei_local = netdev_priv(dev);
17655 +       unsigned long flags;
17656 +       unsigned long tx_cpu_owner_idx;
17657 +       unsigned int tx_cpu_owner_idx_next;
17658 +       unsigned int num_of_txd = 0;
17659 +#if defined (CONFIG_RAETH_TSO)
17660 +       unsigned int nr_frags = skb_shinfo(skb)->nr_frags, i;
17661 +       struct skb_frag_struct *frag;
17662 +#endif
17663 +#if    !defined(CONFIG_RAETH_QOS)
17664 +       unsigned int tx_cpu_owner_idx_next2;
17665 +#else
17666 +       int ring_no, queue_no, port_no;
17667 +#endif
17668 +#ifdef CONFIG_RALINK_VISTA_BASIC
17669 +       struct vlan_ethhdr *veth;
17670 +#endif
17671 +#ifdef CONFIG_PSEUDO_SUPPORT
17672 +       PSEUDO_ADAPTER *pAd;
17673 +#endif
17674 +
17675 +#if !defined(CONFIG_RA_NAT_NONE)
17676 +       if(ra_sw_nat_hook_tx!= NULL)
17677 +       {
17678 +#if defined (CONFIG_RA_HW_NAT) || defined (CONFIG_RA_HW_NAT_MODULE)
17679 +           if(FOE_MAGIC_TAG(skb) != FOE_MAGIC_PPE)
17680 +#endif
17681 +           {
17682 +               //spin_lock_irqsave(&ei_local->page_lock, flags);
17683 +               if(ra_sw_nat_hook_tx(skb, gmac_no)==1){
17684 +                   //spin_unlock_irqrestore(&ei_local->page_lock, flags);
17685 +               }else{
17686 +                   kfree_skb(skb);
17687 +                   //spin_unlock_irqrestore(&ei_local->page_lock, flags);
17688 +                   return 0;
17689 +               }
17690 +           }
17691 +       }
17692 +#endif
17693 +#if defined(CONFIG_RA_CLASSIFIER)||defined(CONFIG_RA_CLASSIFIER_MODULE)
17694 +               /* Qwert+
17695 +                */
17696 +               if(ra_classifier_hook_tx!= NULL)
17697 +               {
17698 +#if defined(CONFIG_RALINK_EXTERNAL_TIMER)
17699 +                       ra_classifier_hook_tx(skb, (*((volatile u32 *)(0xB0000D08))&0x0FFFF));
17700 +#else
17701 +                       ra_classifier_hook_tx(skb, read_c0_count());
17702 +#endif
17703 +               }
17704 +#endif /* CONFIG_RA_CLASSIFIER */
17705 +
17706 +#if defined (CONFIG_RALINK_RT3052_MP2)
17707 +       mcast_tx(skb);
17708 +#endif
17709 +
17710 +#if !defined (CONFIG_RALINK_RT6855) && !defined (CONFIG_RALINK_RT6855A) && \
17711 +    !defined(CONFIG_RALINK_MT7621) && !defined (CONFIG_ARCH_MT7623)
17712 +
17713 +#define MIN_PKT_LEN  60
17714 +        if (skb->len < MIN_PKT_LEN) {
17715 +            if (skb_padto(skb, MIN_PKT_LEN)) {
17716 +                printk("raeth: skb_padto failed\n");
17717 +                return 0;
17718 +            }
17719 +            skb_put(skb, MIN_PKT_LEN - skb->len);
17720 +        }
17721 +#endif
17722 +
17723 +       dev->trans_start = jiffies;     /* save the timestamp */
17724 +       spin_lock_irqsave(&ei_local->page_lock, flags);
17725 +#if defined (CONFIG_MIPS)
17726 +       dma_cache_sync(NULL, skb->data, skb->len, DMA_TO_DEVICE);
17727 +#else
17728 +       dma_sync_single_for_device(NULL, virt_to_phys(skb->data), skb->len, DMA_TO_DEVICE);
17729 +
17730 +#endif
17731 +
17732 +#ifdef CONFIG_RALINK_VISTA_BASIC
17733 +       veth = (struct vlan_ethhdr *)(skb->data);
17734 +       if (is_switch_175c && veth->h_vlan_proto == __constant_htons(ETH_P_8021Q)) {
17735 +               if ((veth->h_vlan_TCI & __constant_htons(VLAN_VID_MASK)) == 0) {
17736 +                       veth->h_vlan_TCI |= htons(VLAN_DEV_INFO(dev)->vlan_id);
17737 +               }
17738 +       }
17739 +#endif
17740 +
17741 +#if defined (CONFIG_RAETH_QOS)
17742 +       if(pkt_classifier(skb, gmac_no, &ring_no, &queue_no, &port_no)) {
17743 +               get_tx_ctx_idx(ring_no, &tx_cpu_owner_idx);
17744 +               tx_cpu_owner_idx_next = (tx_cpu_owner_idx + 1) % NUM_TX_DESC;
17745 +         if(((ei_local->skb_free[ring_no][tx_cpu_owner_idx]) ==0) && (ei_local->skb_free[ring_no][tx_cpu_owner_idx_next]==0)){
17746 +           fe_qos_packet_send(dev, skb, ring_no, queue_no, port_no);
17747 +         }else{
17748 +           ei_local->stat.tx_dropped++;
17749 +           kfree_skb(skb);
17750 +           spin_unlock_irqrestore(&ei_local->page_lock, flags);
17751 +           return 0;
17752 +         }
17753 +       }
17754 +#else
17755 +#ifdef CONFIG_RAETH_RW_PDMAPTR_FROM_VAR
17756 +       tx_cpu_owner_idx = tx_cpu_owner_idx0;
17757 +#else
17758 +       tx_cpu_owner_idx = sysRegRead(TX_CTX_IDX0);
17759 +#endif
17760 +#if defined (CONFIG_RAETH_TSO)
17761 +//     num_of_txd = (nr_frags==0) ? 1 : ((nr_frags>>1) + 1);
17762 +//     NumOfTxdUpdate(num_of_txd);
17763 +       if(nr_frags != 0){
17764 +               for(i=0;i<nr_frags;i++) {
17765 +                       frag = &skb_shinfo(skb)->frags[i];
17766 +                       num_of_txd  += cal_frag_txd_num(frag->size);
17767 +               }
17768 +               num_of_txd = (num_of_txd >> 1) + 1;
17769 +       }else
17770 +               num_of_txd = 1;
17771 +
17772 +#else
17773 +       num_of_txd = 1;
17774 +#endif
17775 +       tx_cpu_owner_idx_next = (tx_cpu_owner_idx + num_of_txd) % NUM_TX_DESC;
17776 +
17777 +       if(((ei_local->skb_free[tx_cpu_owner_idx]) ==0) && (ei_local->skb_free[tx_cpu_owner_idx_next]==0)){
17778 +               rt2880_eth_send(dev, skb, gmac_no);
17779 +
17780 +               tx_cpu_owner_idx_next2 = (tx_cpu_owner_idx_next + 1) % NUM_TX_DESC;
17781 +
17782 +               if(ei_local->skb_free[tx_cpu_owner_idx_next2]!=0){
17783 +#if defined (CONFIG_RAETH_SW_FC)
17784 +                               netif_stop_queue(dev);
17785 +#ifdef CONFIG_PSEUDO_SUPPORT
17786 +                               netif_stop_queue(ei_local->PseudoDev);
17787 +#endif
17788 +                               tx_ring_full=1;
17789 +#endif
17790 +               }
17791 +       }else {
17792 +#ifdef CONFIG_PSEUDO_SUPPORT
17793 +               if (gmac_no == 2) {
17794 +                       if (ei_local->PseudoDev != NULL) {
17795 +                               pAd = netdev_priv(ei_local->PseudoDev);
17796 +                               pAd->stat.tx_dropped++;
17797 +                       }
17798 +               } else
17799 +#endif
17800 +                       ei_local->stat.tx_dropped++;
17801 +#if defined (CONFIG_RAETH_SW_FC)
17802 +               printk("tx_ring_full, drop packet\n");
17803 +#endif
17804 +               kfree_skb(skb);
17805 +               spin_unlock_irqrestore(&ei_local->page_lock, flags);
17806 +               return 0;
17807 +       }
17808 +
17809 +#if defined (CONFIG_RAETH_TSO)
17810 +       /* SG: use multiple TXD to send the packet (only have one skb) */
17811 +       ei_local->skb_free[(tx_cpu_owner_idx + num_of_txd - 1) % NUM_TX_DESC] = skb;
17812 +       while(--num_of_txd) {
17813 +               ei_local->skb_free[(tx_cpu_owner_idx + num_of_txd -1) % NUM_TX_DESC] = (struct  sk_buff *)0xFFFFFFFF; //MAGIC ID
17814 +       }
17815 +#else
17816 +       ei_local->skb_free[tx_cpu_owner_idx] = skb;
17817 +#endif
17818 +#endif
17819 +       spin_unlock_irqrestore(&ei_local->page_lock, flags);
17820 +       return 0;
17821 +}
17822 +
17823 +void ei_xmit_housekeeping(unsigned long unused)
17824 +{
17825 +    struct net_device *dev = dev_raether;
17826 +    END_DEVICE *ei_local = netdev_priv(dev);
17827 +    struct PDMA_txdesc *tx_desc;
17828 +    unsigned long skb_free_idx;
17829 +    unsigned long tx_dtx_idx __maybe_unused;
17830 +#ifndef CONFIG_RAETH_NAPI
17831 +    unsigned long reg_int_mask=0;
17832 +#endif
17833 +
17834 +#ifdef CONFIG_RAETH_QOS
17835 +    int i;
17836 +    for (i=0;i<NUM_TX_RINGS;i++){
17837 +        skb_free_idx = ei_local->free_idx[i];
17838 +       if((ei_local->skb_free[i][skb_free_idx])==0){
17839 +               continue;
17840 +       }
17841 +
17842 +       get_tx_desc_and_dtx_idx(ei_local, i, &tx_dtx_idx, &tx_desc);
17843 +
17844 +       while(tx_desc[skb_free_idx].txd_info2.DDONE_bit==1 && (ei_local->skb_free[i][skb_free_idx])!=0 ){
17845 +               dev_kfree_skb_any((ei_local->skb_free[i][skb_free_idx]));
17846 +
17847 +           ei_local->skb_free[i][skb_free_idx]=0;
17848 +           skb_free_idx = (skb_free_idx +1) % NUM_TX_DESC;
17849 +       }
17850 +       ei_local->free_idx[i] = skb_free_idx;
17851 +    }
17852 +#else
17853 +       tx_dtx_idx = sysRegRead(TX_DTX_IDX0);
17854 +       tx_desc = ei_local->tx_ring0;
17855 +       skb_free_idx = ei_local->free_idx;
17856 +       if ((ei_local->skb_free[skb_free_idx]) != 0 && tx_desc[skb_free_idx].txd_info2.DDONE_bit==1) {
17857 +               while(tx_desc[skb_free_idx].txd_info2.DDONE_bit==1 && (ei_local->skb_free[skb_free_idx])!=0 ){
17858 +#if defined (CONFIG_RAETH_TSO)
17859 +           if(ei_local->skb_free[skb_free_idx]!=(struct  sk_buff *)0xFFFFFFFF) {
17860 +                   dev_kfree_skb_any(ei_local->skb_free[skb_free_idx]);
17861 +           }
17862 +#else
17863 +           dev_kfree_skb_any(ei_local->skb_free[skb_free_idx]);
17864 +#endif
17865 +           ei_local->skb_free[skb_free_idx]=0;
17866 +           skb_free_idx = (skb_free_idx +1) % NUM_TX_DESC;
17867 +       }
17868 +
17869 +       netif_wake_queue(dev);
17870 +#ifdef CONFIG_PSEUDO_SUPPORT
17871 +               netif_wake_queue(ei_local->PseudoDev);
17872 +#endif
17873 +               tx_ring_full=0;
17874 +               ei_local->free_idx = skb_free_idx;
17875 +       }  /* if skb_free != 0 */
17876 +#endif
17877 +
17878 +#ifndef CONFIG_RAETH_NAPI
17879 +    reg_int_mask=sysRegRead(FE_INT_ENABLE);
17880 +#if defined (DELAY_INT)
17881 +    sysRegWrite(FE_INT_ENABLE, reg_int_mask| TX_DLY_INT);
17882 +#else
17883 +
17884 +    sysRegWrite(FE_INT_ENABLE, reg_int_mask | TX_DONE_INT0 \
17885 +                                           | TX_DONE_INT1 \
17886 +                                           | TX_DONE_INT2 \
17887 +                                           | TX_DONE_INT3);
17888 +#endif
17889 +#endif //CONFIG_RAETH_NAPI//
17890 +}
17891 +
17892 +
17893 +
17894 +EXPORT_SYMBOL(ei_start_xmit);
17895 +EXPORT_SYMBOL(ei_xmit_housekeeping);
17896 +EXPORT_SYMBOL(fe_dma_init);
17897 +EXPORT_SYMBOL(rt2880_eth_send);
17898 diff --git a/drivers/net/ethernet/raeth/raether_qdma.c b/drivers/net/ethernet/raeth/raether_qdma.c
17899 new file mode 100644
17900 index 0000000..acf8bfe
17901 --- /dev/null
17902 +++ b/drivers/net/ethernet/raeth/raether_qdma.c
17903 @@ -0,0 +1,1407 @@
17904 +#include <linux/module.h>
17905 +#include <linux/version.h>
17906 +#include <linux/kernel.h>
17907 +#include <linux/types.h>
17908 +#include <linux/pci.h>
17909 +#include <linux/init.h>
17910 +#include <linux/skbuff.h>
17911 +#include <linux/if_vlan.h>
17912 +#include <linux/if_ether.h>
17913 +#include <linux/fs.h>
17914 +#include <asm/uaccess.h>
17915 +#include <asm/rt2880/surfboardint.h>
17916 +#if defined (CONFIG_RAETH_TSO)
17917 +#include <linux/tcp.h>
17918 +#include <net/ipv6.h>
17919 +#include <linux/ip.h>
17920 +#include <net/ip.h>
17921 +#include <net/tcp.h>
17922 +#include <linux/in.h>
17923 +#include <linux/ppp_defs.h>
17924 +#include <linux/if_pppox.h>
17925 +#endif
17926 +#include <linux/delay.h>
17927 +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,35)
17928 +#include <linux/sched.h>
17929 +#endif
17930 +#if defined (CONFIG_HW_SFQ)
17931 +#include <linux/if_vlan.h>
17932 +#include <net/ipv6.h>
17933 +#include <net/ip.h>
17934 +#include <linux/if_pppox.h>
17935 +#include <linux/ppp_defs.h>
17936 +#endif
17937 +
17938 +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,0)
17939 +#include <asm/rt2880/rt_mmap.h>
17940 +#else
17941 +#include <linux/libata-compat.h>
17942 +#endif
17943 +
17944 +#include "ra2882ethreg.h"
17945 +#include "raether.h"
17946 +#include "ra_mac.h"
17947 +#include "ra_ioctl.h"
17948 +#include "ra_rfrw.h"
17949 +#ifdef CONFIG_RAETH_NETLINK
17950 +#include "ra_netlink.h"
17951 +#endif
17952 +#if defined (CONFIG_RAETH_QOS)
17953 +#include "ra_qos.h"
17954 +#endif
17955 +
17956 +#if defined (CONFIG_RA_HW_NAT) || defined (CONFIG_RA_HW_NAT_MODULE)
17957 +#include "../../../net/nat/hw_nat/ra_nat.h"
17958 +#endif
17959 +
17960 +
17961 +#if !defined(CONFIG_RA_NAT_NONE)
17962 +/* bruce+
17963 + */
17964 +extern int (*ra_sw_nat_hook_rx)(struct sk_buff *skb);
17965 +extern int (*ra_sw_nat_hook_tx)(struct sk_buff *skb, int gmac_no);
17966 +#endif
17967 +
17968 +#if defined(CONFIG_RA_CLASSIFIER)||defined(CONFIG_RA_CLASSIFIER_MODULE)
17969 +/* Qwert+
17970 + */
17971 +#include <asm/mipsregs.h>
17972 +extern int (*ra_classifier_hook_tx)(struct sk_buff *skb, unsigned long cur_cycle);
17973 +extern int (*ra_classifier_hook_rx)(struct sk_buff *skb, unsigned long cur_cycle);
17974 +#endif /* CONFIG_RA_CLASSIFIER */
17975 +
17976 +#if defined (CONFIG_RALINK_RT3052_MP2)
17977 +int32_t mcast_rx(struct sk_buff * skb);
17978 +int32_t mcast_tx(struct sk_buff * skb);
17979 +#endif
17980 +
17981 +#ifdef RA_MTD_RW_BY_NUM
17982 +int ra_mtd_read(int num, loff_t from, size_t len, u_char *buf);
17983 +#else
17984 +int ra_mtd_read_nm(char *name, loff_t from, size_t len, u_char *buf);
17985 +#endif
17986 +
17987 +/* gmac driver feature set config */
17988 +#if defined (CONFIG_RAETH_NAPI) || defined (CONFIG_RAETH_QOS)
17989 +#undef DELAY_INT
17990 +#else
17991 +#if defined     (CONFIG_ARCH_MT7623)
17992 +#undef DELAY_INT
17993 +#else
17994 +#define DELAY_INT       1
17995 +#endif
17996 +#endif
17997 +
17998 +//#define CONFIG_UNH_TEST
17999 +/* end of config */
18000 +
18001 +#if defined (CONFIG_RAETH_JUMBOFRAME)
18002 +#define        MAX_RX_LENGTH   4096
18003 +#else
18004 +#define        MAX_RX_LENGTH   1536
18005 +#endif
18006 +
18007 +extern struct net_device               *dev_raether;
18008 +
18009 +#if defined (CONFIG_RAETH_MULTIPLE_RX_RING)
18010 +static int rx_dma_owner_idx1;
18011 +#ifdef CONFIG_RAETH_RW_PDMAPTR_FROM_VAR
18012 +static int rx_calc_idx1;
18013 +#endif
18014 +#endif
18015 +#ifdef CONFIG_RAETH_RW_PDMAPTR_FROM_VAR
18016 +static int rx_calc_idx0;
18017 +static unsigned long tx_cpu_owner_idx0=0;
18018 +#endif
18019 +extern unsigned long tx_ring_full;
18020 +
18021 +#if defined (CONFIG_ETHTOOL) && defined (CONFIG_RAETH_ROUTER)
18022 +#include "ra_ethtool.h"
18023 +extern struct ethtool_ops      ra_ethtool_ops;
18024 +#ifdef CONFIG_PSEUDO_SUPPORT
18025 +extern struct ethtool_ops      ra_virt_ethtool_ops;
18026 +#endif // CONFIG_PSEUDO_SUPPORT //
18027 +#endif // (CONFIG_ETHTOOL //
18028 +
18029 +#ifdef CONFIG_RALINK_VISTA_BASIC
18030 +int is_switch_175c = 1;
18031 +#endif
18032 +
18033 +//skb->mark to queue mapping table
18034 +extern unsigned int M2Q_table[64];
18035 +struct QDMA_txdesc *free_head = NULL;
18036 +extern unsigned int lan_wan_separate;
18037 +#if defined (CONFIG_HW_SFQ)
18038 +extern unsigned int web_sfq_enable;
18039 +#define HwSfqQUp 3
18040 +#define HwSfqQDl 1
18041 +#endif
18042 +int dbg =0;//debug used
18043 +#if defined (CONFIG_HW_SFQ)
18044 +struct SFQ_table *sfq0;
18045 +struct SFQ_table *sfq1;
18046 +struct SFQ_table *sfq2;
18047 +struct SFQ_table *sfq3;
18048 +#endif
18049 +
18050 +#define KSEG1                   0xa0000000
18051 +#if defined (CONFIG_MIPS)
18052 +#define PHYS_TO_VIRT(x)         ((void *)((x) | KSEG1))
18053 +#define VIRT_TO_PHYS(x)         ((unsigned long)(x) & ~KSEG1)
18054 +#else
18055 +#define PHYS_TO_VIRT(x)         phys_to_virt(x)
18056 +#define VIRT_TO_PHYS(x)         virt_to_phys(x)
18057 +#endif
18058 +
18059 +extern void set_fe_dma_glo_cfg(void);
18060 +
18061 +#if defined (CONFIG_HW_SFQ)
18062 +ParseResult            SfqParseResult;
18063 +#endif
18064 +
18065 +/**
18066 + *
18067 + * @brief: get the TXD index from its address
18068 + *
18069 + * @param: cpu_ptr
18070 + *
18071 + * @return: TXD index
18072 +*/
18073 +
18074 +static unsigned int GET_TXD_OFFSET(struct QDMA_txdesc **cpu_ptr)
18075 +{
18076 +       struct net_device *dev = dev_raether;
18077 +       END_DEVICE *ei_local = netdev_priv(dev);
18078 +       int ctx_offset;
18079 +       //ctx_offset = (((((u32)*cpu_ptr) <<8)>>8) - ((((u32)ei_local->txd_pool)<<8)>>8))/ sizeof(struct QDMA_txdesc);
18080 +       //ctx_offset = (*cpu_ptr - ei_local->txd_pool);
18081 +       ctx_offset = (((((u32)*cpu_ptr) <<8)>>8) - ((((u32)ei_local->phy_txd_pool)<<8)>>8))/ sizeof(struct QDMA_txdesc);
18082 +
18083 +       return ctx_offset;
18084 +}
18085 +
18086 +
18087 +
18088 +
18089 +/**
18090 + * @brief cal txd number for a page
18091 + *
18092 + * @parm size
18093 + *
18094 + * @return frag_txd_num
18095 + */
18096 +
18097 +unsigned int cal_frag_txd_num(unsigned int size)
18098 +{
18099 +       unsigned int frag_txd_num = 0;
18100 +       if(size == 0)
18101 +               return 0;
18102 +       while(size > 0){
18103 +               if(size > MAX_TXD_LEN){
18104 +                       frag_txd_num++;
18105 +                       size -= MAX_TXD_LEN;
18106 +               }else{
18107 +                       frag_txd_num++;
18108 +                       size = 0;
18109 +               }
18110 +       }
18111 +        return frag_txd_num;
18112 +
18113 +}
18114 +
18115 +/**
18116 + * @brief get free TXD from TXD queue
18117 + *
18118 + * @param free_txd
18119 + *
18120 + * @return
18121 + */
18122 +static int get_free_txd(struct QDMA_txdesc **free_txd)
18123 +{
18124 +       struct net_device *dev = dev_raether;
18125 +       END_DEVICE *ei_local = netdev_priv(dev);
18126 +       unsigned int tmp_idx;
18127 +
18128 +       if(ei_local->free_txd_num > 0){
18129 +               tmp_idx = ei_local->free_txd_head;
18130 +               ei_local->free_txd_head = ei_local->txd_pool_info[tmp_idx];
18131 +               ei_local->free_txd_num -= 1;
18132 +               //*free_txd = &ei_local->txd_pool[tmp_idx];
18133 +               *free_txd = ei_local->phy_txd_pool + (sizeof(struct QDMA_txdesc) * tmp_idx);
18134 +               return tmp_idx;
18135 +       }else
18136 +               return NUM_TX_DESC;
18137 +}
18138 +
18139 +
18140 +/**
18141 + * @brief add free TXD into TXD queue
18142 + *
18143 + * @param free_txd
18144 + *
18145 + * @return
18146 + */
18147 +int put_free_txd(int free_txd_idx)
18148 +{
18149 +       struct net_device *dev = dev_raether;
18150 +       END_DEVICE *ei_local = netdev_priv(dev);
18151 +       ei_local->txd_pool_info[ei_local->free_txd_tail] = free_txd_idx;
18152 +       ei_local->free_txd_tail = free_txd_idx;
18153 +       ei_local->txd_pool_info[free_txd_idx] = NUM_TX_DESC;
18154 +        ei_local->free_txd_num += 1;
18155 +       return 1;
18156 +}
18157 +
18158 +/*define qdma initial alloc*/
18159 +/**
18160 + * @brief
18161 + *
18162 + * @param net_dev
18163 + *
18164 + * @return  0: fail
18165 + *         1: success
18166 + */
18167 +bool qdma_tx_desc_alloc(void)
18168 +{
18169 +       struct net_device *dev = dev_raether;
18170 +       END_DEVICE *ei_local = netdev_priv(dev);
18171 +       struct QDMA_txdesc *free_txd = NULL;
18172 +       unsigned int txd_idx;
18173 +       int i = 0;
18174 +
18175 +
18176 +       ei_local->txd_pool = pci_alloc_consistent(NULL, sizeof(struct QDMA_txdesc) * NUM_TX_DESC, &ei_local->phy_txd_pool);
18177 +       printk("txd_pool=%p phy_txd_pool=%08X\n", ei_local->txd_pool , ei_local->phy_txd_pool);
18178 +
18179 +       if (ei_local->txd_pool == NULL) {
18180 +               printk("adapter->txd_pool allocation failed!\n");
18181 +               return 0;
18182 +       }
18183 +       printk("ei_local->skb_free start address is 0x%p.\n", ei_local->skb_free);
18184 +       //set all txd_pool_info to 0.
18185 +       for ( i = 0; i < NUM_TX_DESC; i++)
18186 +       {
18187 +               ei_local->skb_free[i]= 0;
18188 +               ei_local->txd_pool_info[i] = i + 1;
18189 +               ei_local->txd_pool[i].txd_info3.LS_bit = 1;
18190 +               ei_local->txd_pool[i].txd_info3.OWN_bit = 1;
18191 +       }
18192 +
18193 +       ei_local->free_txd_head = 0;
18194 +       ei_local->free_txd_tail = NUM_TX_DESC - 1;
18195 +       ei_local->free_txd_num = NUM_TX_DESC;
18196 +
18197 +
18198 +       //get free txd from txd pool
18199 +       txd_idx = get_free_txd(&free_txd);
18200 +       if( txd_idx == NUM_TX_DESC) {
18201 +               printk("get_free_txd fail\n");
18202 +               return 0;
18203 +       }
18204 +
18205 +       //add null TXD for transmit
18206 +       //ei_local->tx_dma_ptr = VIRT_TO_PHYS(free_txd);
18207 +       //ei_local->tx_cpu_ptr = VIRT_TO_PHYS(free_txd);
18208 +       ei_local->tx_dma_ptr = free_txd;
18209 +       ei_local->tx_cpu_ptr = free_txd;
18210 +       sysRegWrite(QTX_CTX_PTR, ei_local->tx_cpu_ptr);
18211 +       sysRegWrite(QTX_DTX_PTR, ei_local->tx_dma_ptr);
18212 +
18213 +       //get free txd from txd pool
18214 +
18215 +       txd_idx = get_free_txd(&free_txd);
18216 +       if( txd_idx == NUM_TX_DESC) {
18217 +               printk("get_free_txd fail\n");
18218 +               return 0;
18219 +       }
18220 +       // add null TXD for release
18221 +       //sysRegWrite(QTX_CRX_PTR, VIRT_TO_PHYS(free_txd));
18222 +       //sysRegWrite(QTX_DRX_PTR, VIRT_TO_PHYS(free_txd));
18223 +       sysRegWrite(QTX_CRX_PTR, free_txd);
18224 +       sysRegWrite(QTX_DRX_PTR, free_txd);
18225 +       printk("free_txd: %p, ei_local->cpu_ptr: %08X\n", free_txd, ei_local->tx_cpu_ptr);
18226 +
18227 +       printk(" POOL  HEAD_PTR | DMA_PTR | CPU_PTR \n");
18228 +       printk("----------------+---------+--------\n");
18229 +       printk("     0x%p 0x%08X 0x%08X\n",ei_local->txd_pool, ei_local->tx_dma_ptr, ei_local->tx_cpu_ptr);
18230 +       return 1;
18231 +}
18232 +#if defined (CONFIG_HW_SFQ)
18233 +bool sfq_init(void)
18234 +{
18235 +       unsigned int regVal;
18236 +
18237 +       unsigned int sfq_phy0;
18238 +       unsigned int sfq_phy1;
18239 +       unsigned int sfq_phy2;
18240 +       unsigned int sfq_phy3;
18241 +  struct SFQ_table *sfq0;
18242 +       struct SFQ_table *sfq1;
18243 +       struct SFQ_table *sfq2;
18244 +       struct SFQ_table *sfq3;
18245 +       int i = 0;
18246 +       regVal = sysRegRead(VQTX_GLO);
18247 +       regVal = regVal | VQTX_MIB_EN |(1<<16) ;
18248 +       sysRegWrite(VQTX_GLO, regVal);// Virtual table extends to 32bytes
18249 +       regVal = sysRegRead(VQTX_GLO);
18250 +       sysRegWrite(VQTX_NUM, (VQTX_NUM_0) | (VQTX_NUM_1) | (VQTX_NUM_2) | (VQTX_NUM_3));
18251 +       sysRegWrite(VQTX_HASH_CFG, 0xF002710); //10 s change hash algorithm
18252 +  sysRegWrite(VQTX_VLD_CFG, 0x00);
18253 +       sysRegWrite(VQTX_HASH_SD, 0x0D);
18254 +       sysRegWrite(QDMA_FC_THRES, 0x9b9b4444);
18255 +       sysRegWrite(QDMA_HRED1, 0);
18256 +       sysRegWrite(QDMA_HRED2, 0);
18257 +       sysRegWrite(QDMA_SRED1, 0);
18258 +       sysRegWrite(QDMA_SRED2, 0);
18259 +       sfq0 = pci_alloc_consistent(NULL, 256*sizeof(struct SFQ_table), &sfq_phy0);
18260 +       memset(sfq0, 0x0, 256*sizeof(struct SFQ_table) );
18261 +       for (i=0; i < 256; i++) {
18262 +                       sfq0[i].sfq_info1.VQHPTR = 0xdeadbeef;
18263 +      sfq0[i].sfq_info2.VQTPTR = 0xdeadbeef;
18264 +       }
18265 +#if(1)
18266 +       sfq1 = pci_alloc_consistent(NULL, 256*sizeof(struct SFQ_table), &sfq_phy1);
18267 +
18268 +       memset(sfq1, 0x0, 256*sizeof(struct SFQ_table) );
18269 +       for (i=0; i < 256; i++) {
18270 +                       sfq1[i].sfq_info1.VQHPTR = 0xdeadbeef;
18271 +      sfq1[i].sfq_info2.VQTPTR = 0xdeadbeef;
18272 +       }
18273 +
18274 +       sfq2 = pci_alloc_consistent(NULL, 256*sizeof(struct SFQ_table), &sfq_phy2);
18275 +       memset(sfq2, 0x0, 256*sizeof(struct SFQ_table) );
18276 +       for (i=0; i < 256; i++) {
18277 +                       sfq2[i].sfq_info1.VQHPTR = 0xdeadbeef;
18278 +      sfq2[i].sfq_info2.VQTPTR = 0xdeadbeef;
18279 +       }
18280 +
18281 +       sfq3 = pci_alloc_consistent(NULL, 256*sizeof(struct SFQ_table), &sfq_phy3);
18282 +       memset(sfq3, 0x0, 256*sizeof(struct SFQ_table) );
18283 +       for (i=0; i < 256; i++) {
18284 +                       sfq3[i].sfq_info1.VQHPTR = 0xdeadbeef;
18285 +      sfq3[i].sfq_info2.VQTPTR = 0xdeadbeef;
18286 +       }
18287 +
18288 +#endif
18289 +               printk("*****sfq_phy0 is 0x%x!!!*******\n", sfq_phy0);
18290 +               printk("*****sfq_phy1 is 0x%x!!!*******\n", sfq_phy1);
18291 +               printk("*****sfq_phy2 is 0x%x!!!*******\n", sfq_phy2);
18292 +               printk("*****sfq_phy3 is 0x%x!!!*******\n", sfq_phy3);
18293 +               printk("*****sfq_virt0 is 0x%x!!!*******\n", sfq0);
18294 +               printk("*****sfq_virt1 is 0x%x!!!*******\n", sfq1);
18295 +               printk("*****sfq_virt2 is 0x%x!!!*******\n", sfq2);
18296 +               printk("*****sfq_virt3 is 0x%x!!!*******\n", sfq3);
18297 +               printk("*****sfq_virt0 is 0x%x!!!*******\n", sfq0);
18298 +               sysRegWrite(VQTX_TB_BASE0, (u32)sfq_phy0);
18299 +               sysRegWrite(VQTX_TB_BASE1, (u32)sfq_phy1);
18300 +               sysRegWrite(VQTX_TB_BASE2, (u32)sfq_phy2);
18301 +               sysRegWrite(VQTX_TB_BASE3, (u32)sfq_phy3);
18302 +
18303 +        return 1;
18304 +}
18305 +#endif
18306 +bool fq_qdma_init(struct net_device *dev)
18307 +{
18308 +       END_DEVICE* ei_local = netdev_priv(dev);
18309 +       //struct QDMA_txdesc *free_head = NULL;
18310 +       unsigned int phy_free_head;
18311 +       unsigned int phy_free_tail;
18312 +       unsigned int *free_page_head = NULL;
18313 +       unsigned int phy_free_page_head;
18314 +       int i;
18315 +
18316 +       free_head = pci_alloc_consistent(NULL, NUM_QDMA_PAGE * sizeof(struct QDMA_txdesc), &phy_free_head);
18317 +       if (unlikely(free_head == NULL)){
18318 +               printk(KERN_ERR "QDMA FQ decriptor not available...\n");
18319 +               return 0;
18320 +       }
18321 +       memset(free_head, 0x0, sizeof(struct QDMA_txdesc) * NUM_QDMA_PAGE);
18322 +
18323 +       free_page_head = pci_alloc_consistent(NULL, NUM_QDMA_PAGE * QDMA_PAGE_SIZE, &phy_free_page_head);
18324 +       if (unlikely(free_page_head == NULL)){
18325 +               printk(KERN_ERR "QDMA FQ page not available...\n");
18326 +               return 0;
18327 +       }
18328 +       for (i=0; i < NUM_QDMA_PAGE; i++) {
18329 +               free_head[i].txd_info1.SDP = (phy_free_page_head + (i * QDMA_PAGE_SIZE));
18330 +               if(i < (NUM_QDMA_PAGE-1)){
18331 +                       free_head[i].txd_info2.NDP = (phy_free_head + ((i+1) * sizeof(struct QDMA_txdesc)));
18332 +
18333 +
18334 +#if 0
18335 +                       printk("free_head_phy[%d] is 0x%x!!!\n",i, VIRT_TO_PHYS(&free_head[i]) );
18336 +                       printk("free_head[%d] is 0x%x!!!\n",i, &free_head[i] );
18337 +                       printk("free_head[%d].txd_info1.SDP is 0x%x!!!\n",i, free_head[i].txd_info1.SDP );
18338 +                       printk("free_head[%d].txd_info2.NDP is 0x%x!!!\n",i, free_head[i].txd_info2.NDP );
18339 +#endif
18340 +               }
18341 +               free_head[i].txd_info3.SDL = QDMA_PAGE_SIZE;
18342 +
18343 +       }
18344 +       phy_free_tail = (phy_free_head + (u32)((NUM_QDMA_PAGE-1) * sizeof(struct QDMA_txdesc)));
18345 +
18346 +       printk("phy_free_head is 0x%x!!!\n", phy_free_head);
18347 +       printk("phy_free_tail_phy is 0x%x!!!\n", phy_free_tail);
18348 +       sysRegWrite(QDMA_FQ_HEAD, (u32)phy_free_head);
18349 +       sysRegWrite(QDMA_FQ_TAIL, (u32)phy_free_tail);
18350 +       sysRegWrite(QDMA_FQ_CNT, ((NUM_TX_DESC << 16) | NUM_QDMA_PAGE));
18351 +       sysRegWrite(QDMA_FQ_BLEN, QDMA_PAGE_SIZE << 16);
18352 +
18353 +       ei_local->free_head = free_head;
18354 +       ei_local->phy_free_head = phy_free_head;
18355 +       ei_local->free_page_head = free_page_head;
18356 +       ei_local->phy_free_page_head = phy_free_page_head;
18357 +    return 1;
18358 +}
18359 +
18360 +int fe_dma_init(struct net_device *dev)
18361 +{
18362 +
18363 +       int i;
18364 +       unsigned int    regVal;
18365 +       END_DEVICE* ei_local = netdev_priv(dev);
18366 +
18367 +
18368 +       #if defined (CONFIG_HW_SFQ)
18369 +       sfq_init();
18370 +  #endif
18371 +       fq_qdma_init(dev);
18372 +
18373 +       while(1)
18374 +       {
18375 +               regVal = sysRegRead(QDMA_GLO_CFG);
18376 +               if((regVal & RX_DMA_BUSY))
18377 +               {
18378 +                       printk("\n  RX_DMA_BUSY !!! ");
18379 +                       continue;
18380 +               }
18381 +               if((regVal & TX_DMA_BUSY))
18382 +               {
18383 +                       printk("\n  TX_DMA_BUSY !!! ");
18384 +                       continue;
18385 +               }
18386 +               break;
18387 +       }
18388 +       /*tx desc alloc, add a NULL TXD to HW*/
18389 +
18390 +       qdma_tx_desc_alloc();
18391 +
18392 +       /* Initial RX Ring 0*/
18393 +
18394 +#ifdef CONFIG_32B_DESC
18395 +       ei_local->qrx_ring = kmalloc(NUM_QRX_DESC * sizeof(struct PDMA_rxdesc), GFP_KERNEL);
18396 +       ei_local->phy_qrx_ring = virt_to_phys(ei_local->qrx_ring);
18397 +#else
18398 +       ei_local->qrx_ring = pci_alloc_consistent(NULL, NUM_QRX_DESC * sizeof(struct PDMA_rxdesc), &ei_local->phy_qrx_ring);
18399 +#endif
18400 +       for (i = 0; i < NUM_QRX_DESC; i++) {
18401 +               memset(&ei_local->qrx_ring[i],0,sizeof(struct PDMA_rxdesc));
18402 +               ei_local->qrx_ring[i].rxd_info2.DDONE_bit = 0;
18403 +#if defined (CONFIG_RAETH_SCATTER_GATHER_RX_DMA)
18404 +               ei_local->qrx_ring[i].rxd_info2.LS0 = 0;
18405 +               ei_local->qrx_ring[i].rxd_info2.PLEN0 = MAX_RX_LENGTH;
18406 +#else
18407 +               ei_local->qrx_ring[i].rxd_info2.LS0 = 1;
18408 +#endif
18409 +               ei_local->qrx_ring[i].rxd_info1.PDP0 = dma_map_single(NULL, ei_local->netrx0_skbuf[i]->data, MAX_RX_LENGTH, PCI_DMA_FROMDEVICE);
18410 +       }
18411 +       printk("\nphy_qrx_ring = 0x%08x, qrx_ring = 0x%p\n",ei_local->phy_qrx_ring,ei_local->qrx_ring);
18412 +
18413 +       regVal = sysRegRead(QDMA_GLO_CFG);
18414 +       regVal &= 0x000000FF;
18415 +
18416 +       sysRegWrite(QDMA_GLO_CFG, regVal);
18417 +       regVal=sysRegRead(QDMA_GLO_CFG);
18418 +
18419 +       /* Tell the adapter where the TX/RX rings are located. */
18420 +
18421 +       sysRegWrite(QRX_BASE_PTR_0, phys_to_bus((u32) ei_local->phy_qrx_ring));
18422 +       sysRegWrite(QRX_MAX_CNT_0,  cpu_to_le32((u32) NUM_QRX_DESC));
18423 +       sysRegWrite(QRX_CRX_IDX_0, cpu_to_le32((u32) (NUM_QRX_DESC - 1)));
18424 +#ifdef CONFIG_RAETH_RW_PDMAPTR_FROM_VAR
18425 +       rx_calc_idx0 = rx_dma_owner_idx0 =  sysRegRead(QRX_CRX_IDX_0);
18426 +#endif
18427 +       sysRegWrite(QDMA_RST_CFG, PST_DRX_IDX0);
18428 +
18429 +        ei_local->rx_ring0 = ei_local->qrx_ring;
18430 +#if !defined (CONFIG_RAETH_QDMATX_QDMARX)
18431 +       /* Initial PDMA RX Ring 0*/
18432 +#ifdef CONFIG_32B_DESC
18433 +        ei_local->rx_ring0 = kmalloc(NUM_RX_DESC * sizeof(struct PDMA_rxdesc), GFP_KERNEL);
18434 +        ei_local->phy_rx_ring0 = virt_to_phys(ei_local->rx_ring0);
18435 +#else
18436 +        ei_local->rx_ring0 = pci_alloc_consistent(NULL, NUM_RX_DESC * sizeof(struct PDMA_rxdesc), &ei_local->phy_rx_ring0);
18437 +#endif
18438 +        for (i = 0; i < NUM_RX_DESC; i++) {
18439 +               memset(&ei_local->rx_ring0[i],0,sizeof(struct PDMA_rxdesc));
18440 +               ei_local->rx_ring0[i].rxd_info2.DDONE_bit = 0;
18441 +#if defined (CONFIG_RAETH_SCATTER_GATHER_RX_DMA)
18442 +       ei_local->rx_ring0[i].rxd_info2.LS0 = 0;
18443 +       ei_local->rx_ring0[i].rxd_info2.PLEN0 = MAX_RX_LENGTH;
18444 +#else
18445 +       ei_local->rx_ring0[i].rxd_info2.LS0 = 1;
18446 +#endif
18447 +       ei_local->rx_ring0[i].rxd_info1.PDP0 = dma_map_single(NULL, ei_local->netrx0_skbuf[i]->data, MAX_RX_LENGTH, PCI_DMA_FROMDEVICE);
18448 +                                                               }
18449 +        printk("\nphy_rx_ring0 = 0x%08x, rx_ring0 = 0x%p\n",ei_local->phy_rx_ring0,ei_local->rx_ring0);
18450 +
18451 +        regVal = sysRegRead(PDMA_GLO_CFG);
18452 +        regVal &= 0x000000FF;
18453 +        sysRegWrite(PDMA_GLO_CFG, regVal);
18454 +        regVal=sysRegRead(PDMA_GLO_CFG);
18455 +
18456 +        sysRegWrite(RX_BASE_PTR0, phys_to_bus((u32) ei_local->phy_rx_ring0));
18457 +        sysRegWrite(RX_MAX_CNT0,  cpu_to_le32((u32) NUM_RX_DESC));
18458 +        sysRegWrite(RX_CALC_IDX0, cpu_to_le32((u32) (NUM_RX_DESC - 1)));
18459 +#ifdef CONFIG_RAETH_RW_PDMAPTR_FROM_VAR
18460 +        rx_calc_idx0 =  sysRegRead(RX_CALC_IDX0);
18461 +#endif
18462 +        sysRegWrite(PDMA_RST_CFG, PST_DRX_IDX0);
18463 +#endif
18464 +#if !defined (CONFIG_HW_SFQ)
18465 +        /* Enable randon early drop and set drop threshold automatically */
18466 +       sysRegWrite(QDMA_FC_THRES, 0x174444);
18467 +#endif
18468 +       sysRegWrite(QDMA_HRED2, 0x0);
18469 +       set_fe_dma_glo_cfg();
18470 +#if defined    (CONFIG_ARCH_MT7623)
18471 +       printk("Enable QDMA TX NDP coherence check and re-read mechanism\n");
18472 +       regVal=sysRegRead(QDMA_GLO_CFG);
18473 +       regVal = regVal | 0x400;
18474 +       sysRegWrite(QDMA_GLO_CFG, regVal);
18475 +       printk("***********QDMA_GLO_CFG=%x\n", sysRegRead(QDMA_GLO_CFG));
18476 +#endif
18477 +
18478 +       return 1;
18479 +}
18480 +
18481 +#if defined (CONFIG_HW_SFQ)
18482 +
18483 +int sfq_prot = 0;
18484 +int proto_id=0;
18485 +int udp_source_port=0;
18486 +int tcp_source_port=0;
18487 +int ack_packt =0;
18488 +int SfqParseLayerInfo(struct sk_buff * skb)
18489 +{
18490 +
18491 +       struct vlan_hdr *vh_sfq = NULL;
18492 +       struct ethhdr *eth_sfq = NULL;
18493 +       struct iphdr *iph_sfq = NULL;
18494 +       struct ipv6hdr *ip6h_sfq = NULL;
18495 +       struct tcphdr *th_sfq = NULL;
18496 +       struct udphdr *uh_sfq = NULL;
18497 +#ifdef CONFIG_RAETH_HW_VLAN_TX
18498 +       struct vlan_hdr pseudo_vhdr_sfq;
18499 +#endif
18500 +
18501 +       memset(&SfqParseResult, 0, sizeof(SfqParseResult));
18502 +
18503 +       eth_sfq = (struct ethhdr *)skb->data;
18504 +       memcpy(SfqParseResult.dmac, eth_sfq->h_dest, ETH_ALEN);
18505 +       memcpy(SfqParseResult.smac, eth_sfq->h_source, ETH_ALEN);
18506 +       SfqParseResult.eth_type = eth_sfq->h_proto;
18507 +
18508 +
18509 +       if (SfqParseResult.eth_type == htons(ETH_P_8021Q)){
18510 +               SfqParseResult.vlan1_gap = VLAN_HLEN;
18511 +               vh_sfq = (struct vlan_hdr *)(skb->data + ETH_HLEN);
18512 +               SfqParseResult.eth_type = vh_sfq->h_vlan_encapsulated_proto;
18513 +       }else{
18514 +               SfqParseResult.vlan1_gap = 0;
18515 +       }
18516 +
18517 +
18518 +
18519 +       LAYER2_HEADER(skb) = skb->data;
18520 +  LAYER3_HEADER(skb) = (skb->data + ETH_HLEN + (SfqParseResult.vlan1_gap));
18521 +
18522 +
18523 +
18524 +       /* set layer4 start addr */
18525 +       if ((SfqParseResult.eth_type == htons(ETH_P_IP)) || (SfqParseResult.eth_type == htons(ETH_P_PPP_SES)
18526 +               && SfqParseResult.ppp_tag == htons(PPP_IP))) {
18527 +               iph_sfq = (struct iphdr *)LAYER3_HEADER(skb);
18528 +
18529 +               //prepare layer3/layer4 info
18530 +               memcpy(&SfqParseResult.iph, iph_sfq, sizeof(struct iphdr));
18531 +               if (iph_sfq->protocol == IPPROTO_TCP) {
18532 +
18533 +                       LAYER4_HEADER(skb) = ((uint8_t *) iph_sfq + (iph_sfq->ihl * 4));
18534 +                       th_sfq = (struct tcphdr *)LAYER4_HEADER(skb);
18535 +                       memcpy(&SfqParseResult.th, th_sfq, sizeof(struct tcphdr));
18536 +                       SfqParseResult.pkt_type = IPV4_HNAPT;
18537 +                       //printk("tcp parsing\n");
18538 +                       tcp_source_port = ntohs(SfqParseResult.th.source);
18539 +                       udp_source_port = 0;
18540 +                       #if(0) //for TCP ack, test use
18541 +                               if(ntohl(SfqParseResult.iph.saddr) == 0xa0a0a04){ // tcp ack packet
18542 +                                       ack_packt = 1;
18543 +                               }else {
18544 +                                       ack_packt = 0;
18545 +                               }
18546 +                       #endif
18547 +      sfq_prot = 2;//IPV4_HNAPT
18548 +      proto_id = 1;//TCP
18549 +                       if(iph_sfq->frag_off & htons(IP_MF|IP_OFFSET)) {
18550 +                               //return 1;
18551 +                       }
18552 +               } else if (iph_sfq->protocol == IPPROTO_UDP) {
18553 +                       LAYER4_HEADER(skb) = ((uint8_t *) iph_sfq + iph_sfq->ihl * 4);
18554 +                       uh_sfq = (struct udphdr *)LAYER4_HEADER(skb);
18555 +                       memcpy(&SfqParseResult.uh, uh_sfq, sizeof(struct udphdr));
18556 +                       SfqParseResult.pkt_type = IPV4_HNAPT;
18557 +                       udp_source_port = ntohs(SfqParseResult.uh.source);
18558 +                       tcp_source_port = 0;
18559 +                       ack_packt = 0;
18560 +                       sfq_prot = 2;//IPV4_HNAPT
18561 +                       proto_id =2;//UDP
18562 +                       if(iph_sfq->frag_off & htons(IP_MF|IP_OFFSET)) {
18563 +                               return 1;
18564 +                       }
18565 +               }else{
18566 +                       sfq_prot = 1;
18567 +               }
18568 +       }else if (SfqParseResult.eth_type == htons(ETH_P_IPV6) ||
18569 +                       (SfqParseResult.eth_type == htons(ETH_P_PPP_SES) &&
18570 +                       SfqParseResult.ppp_tag == htons(PPP_IPV6))) {
18571 +                       ip6h_sfq = (struct ipv6hdr *)LAYER3_HEADER(skb);
18572 +                       memcpy(&SfqParseResult.ip6h, ip6h_sfq, sizeof(struct ipv6hdr));
18573 +
18574 +                       if (ip6h_sfq->nexthdr == NEXTHDR_TCP) {
18575 +                               LAYER4_HEADER(skb) = ((uint8_t *) ip6h_sfq + sizeof(struct ipv6hdr));
18576 +                               th_sfq = (struct tcphdr *)LAYER4_HEADER(skb);
18577 +                               memcpy(&SfqParseResult.th, th_sfq, sizeof(struct tcphdr));
18578 +                               SfqParseResult.pkt_type = IPV6_5T_ROUTE;
18579 +                               sfq_prot = 4;//IPV6_5T
18580 +                       #if(0) //for TCP ack, test use
18581 +            if(ntohl(SfqParseResult.ip6h.saddr.s6_addr32[3]) == 8){
18582 +                               ack_packt = 1;
18583 +                       }else {
18584 +                               ack_packt = 0;
18585 +                       }
18586 +                       #endif
18587 +                       } else if (ip6h_sfq->nexthdr == NEXTHDR_UDP) {
18588 +                               LAYER4_HEADER(skb) = ((uint8_t *) ip6h_sfq + sizeof(struct ipv6hdr));
18589 +                               uh_sfq = (struct udphdr *)LAYER4_HEADER(skb);
18590 +                               memcpy(&SfqParseResult.uh, uh_sfq, sizeof(struct udphdr));
18591 +                               SfqParseResult.pkt_type = IPV6_5T_ROUTE;
18592 +                               ack_packt = 0;
18593 +                               sfq_prot = 4;//IPV6_5T
18594 +
18595 +                       }else{
18596 +                               sfq_prot = 3;//IPV6_3T
18597 +                       }
18598 +       }
18599 +
18600 +       return 0;
18601 +}
18602 +#endif
18603 +
18604 +inline int rt2880_eth_send(struct net_device* dev, struct sk_buff *skb, int gmac_no)
18605 +{
18606 +       unsigned int    length=skb->len;
18607 +       END_DEVICE*     ei_local = netdev_priv(dev);
18608 +
18609 +       struct QDMA_txdesc *cpu_ptr;
18610 +
18611 +       struct QDMA_txdesc *dma_ptr __maybe_unused;
18612 +       struct QDMA_txdesc *free_txd;
18613 +       int  ctx_offset;
18614 +#if defined (CONFIG_RAETH_TSO)
18615 +       struct iphdr *iph = NULL;
18616 +        struct QDMA_txdesc *init_cpu_ptr;
18617 +        struct tcphdr *th = NULL;
18618 +       struct skb_frag_struct *frag;
18619 +       unsigned int nr_frags = skb_shinfo(skb)->nr_frags;
18620 +       unsigned int len, size, offset, frag_txd_num;
18621 +       int init_txd_idx, i;
18622 +#endif // CONFIG_RAETH_TSO //
18623 +
18624 +#if defined (CONFIG_RAETH_TSOV6)
18625 +       struct ipv6hdr *ip6h = NULL;
18626 +#endif
18627 +
18628 +#ifdef CONFIG_PSEUDO_SUPPORT
18629 +       PSEUDO_ADAPTER *pAd;
18630 +#endif
18631 +       //cpu_ptr = PHYS_TO_VIRT(ei_local->tx_cpu_ptr);
18632 +       //dma_ptr = PHYS_TO_VIRT(ei_local->tx_dma_ptr);
18633 +       //ctx_offset = GET_TXD_OFFSET(&cpu_ptr);
18634 +       cpu_ptr = (ei_local->tx_cpu_ptr);
18635 +       ctx_offset = GET_TXD_OFFSET(&cpu_ptr);
18636 +       cpu_ptr = phys_to_virt(ei_local->tx_cpu_ptr);
18637 +       dma_ptr = phys_to_virt(ei_local->tx_dma_ptr);
18638 +       cpu_ptr = (ei_local->txd_pool + (ctx_offset));
18639 +       ei_local->skb_free[ctx_offset] = skb;
18640 +#if defined (CONFIG_RAETH_TSO)
18641 +        init_cpu_ptr = cpu_ptr;
18642 +        init_txd_idx = ctx_offset;
18643 +#endif
18644 +
18645 +#if !defined (CONFIG_RAETH_TSO)
18646 +
18647 +       //2. prepare data
18648 +       //cpu_ptr->txd_info1.SDP = VIRT_TO_PHYS(skb->data);
18649 +       cpu_ptr->txd_info1.SDP = virt_to_phys(skb->data);
18650 +       cpu_ptr->txd_info3.SDL = skb->len;
18651 +#if defined (CONFIG_HW_SFQ)
18652 +       SfqParseLayerInfo(skb);
18653 +  cpu_ptr->txd_info4.VQID0 = 1;//1:HW hash 0:CPU
18654 +
18655 +
18656 +#if(0)// for tcp ack use, test use
18657 +  if (ack_packt==1){
18658 +       cpu_ptr->txd_info3.QID = 0x0a;
18659 +       //cpu_ptr->txd_info3.VQID = 0;
18660 +  }else{
18661 +                       cpu_ptr->txd_info3.QID = 0;
18662 +  }
18663 +#endif
18664 +  cpu_ptr->txd_info3.PROT = sfq_prot;
18665 +  cpu_ptr->txd_info3.IPOFST = 14 + (SfqParseResult.vlan1_gap); //no vlan
18666 +
18667 +#endif
18668 +       if (gmac_no == 1) {
18669 +               cpu_ptr->txd_info4.FPORT = 1;
18670 +       }else {
18671 +               cpu_ptr->txd_info4.FPORT = 2;
18672 +       }
18673 +
18674 +       cpu_ptr->txd_info3.QID = M2Q_table[skb->mark];
18675 +#ifdef CONFIG_PSEUDO_SUPPORT
18676 +       if((lan_wan_separate==1) && (gmac_no==2)){
18677 +               cpu_ptr->txd_info3.QID += 8;
18678 +#if defined (CONFIG_HW_SFQ)
18679 +               if(web_sfq_enable==1 &&(skb->mark == 2)){
18680 +                       cpu_ptr->txd_info3.QID = HwSfqQUp;
18681 +               }
18682 +#endif
18683 +       }
18684 +#if defined (CONFIG_HW_SFQ)
18685 +       if((lan_wan_separate==1) && (gmac_no==1)){
18686 +               if(web_sfq_enable==1 &&(skb->mark == 2)){
18687 +                       cpu_ptr->txd_info3.QID = HwSfqQDl;
18688 +               }
18689 +       }
18690 +#endif
18691 +#endif //end CONFIG_PSEUDO_SUPPORT
18692 +
18693 +       if(dbg==1){
18694 +               printk("M2Q_table[%d]=%d\n", skb->mark, M2Q_table[skb->mark]);
18695 +               printk("cpu_ptr->txd_info3.QID = %d\n", cpu_ptr->txd_info3.QID);
18696 +       }
18697 +#if 0
18698 +       iph = (struct iphdr *)skb_network_header(skb);
18699 +        if (iph->tos == 0xe0)
18700 +               cpu_ptr->txd_info3.QID = 3;
18701 +       else if (iph->tos == 0xa0)
18702 +               cpu_ptr->txd_info3.QID = 2;
18703 +        else if (iph->tos == 0x20)
18704 +               cpu_ptr->txd_info3.QID = 1;
18705 +        else
18706 +               cpu_ptr->txd_info3.QID = 0;
18707 +#endif
18708 +
18709 +#if defined (CONFIG_RAETH_CHECKSUM_OFFLOAD) && ! defined(CONFIG_RALINK_RT5350) && !defined (CONFIG_RALINK_MT7628)
18710 +       if (skb->ip_summed == CHECKSUM_PARTIAL){
18711 +           cpu_ptr->txd_info4.TUI_CO = 7;
18712 +       }else {
18713 +           cpu_ptr->txd_info4.TUI_CO = 0;
18714 +       }
18715 +#endif
18716 +
18717 +#ifdef CONFIG_RAETH_HW_VLAN_TX
18718 +       if(vlan_tx_tag_present(skb)) {
18719 +           cpu_ptr->txd_info4.VLAN_TAG = 0x10000 | vlan_tx_tag_get(skb);
18720 +       }else {
18721 +           cpu_ptr->txd_info4.VLAN_TAG = 0;
18722 +       }
18723 +#endif
18724 +
18725 +#ifdef CONFIG_RAETH_HW_VLAN_TX // QoS Web UI used
18726 +
18727 +       if((lan_wan_separate==1) && (vlan_tx_tag_get(skb)==2)){
18728 +               cpu_ptr->txd_info3.QID += 8;
18729 +#if defined (CONFIG_HW_SFQ)
18730 +               if(web_sfq_enable==1 &&(skb->mark == 2)){
18731 +                       cpu_ptr->txd_info3.QID = HwSfqQUp;
18732 +               }
18733 +#endif
18734 +       }
18735 +#if defined (CONFIG_HW_SFQ)
18736 +       if((lan_wan_separate==1) && (vlan_tx_tag_get(skb)==1)){
18737 +               if(web_sfq_enable==1 &&(skb->mark == 2)){
18738 +                       cpu_ptr->txd_info3.QID = HwSfqQDl;
18739 +               }
18740 +       }
18741 +#endif
18742 +#endif // CONFIG_RAETH_HW_VLAN_TX
18743 +
18744 +
18745 +//no hw van, no GE2, web UI used
18746 +#ifndef CONFIG_PSEUDO_SUPPORT
18747 +#ifndef CONFIG_RAETH_HW_VLAN_TX
18748 +       if(lan_wan_separate==1){
18749 +               struct vlan_hdr *vh = NULL;
18750 +    unsigned short vlanid = 0;
18751 +    unsigned short vlan_TCI;
18752 +               vh = (struct vlan_hdr *)(skb->data + ETH_HLEN);
18753 +               vlan_TCI = vh->h_vlan_TCI;
18754 +    vlanid = (vlan_TCI & VLAN_VID_MASK)>>8;
18755 +               if(vlanid == 2)//to wan
18756 +               {
18757 +                               cpu_ptr->txd_info3.QID += 8;
18758 +#if defined (CONFIG_HW_SFQ)
18759 +                               if(web_sfq_enable==1 &&(skb->mark == 2)){
18760 +                                       cpu_ptr->txd_info3.QID = HwSfqQUp;
18761 +                               }
18762 +#endif
18763 +               }else if(vlanid == 1){ //to lan
18764 +#if defined (CONFIG_HW_SFQ)
18765 +                               if(web_sfq_enable==1 &&(skb->mark == 2)){
18766 +                                       cpu_ptr->txd_info3.QID = HwSfqQDl;
18767 +                               }
18768 +#endif
18769 +               }
18770 +       }
18771 +#endif
18772 +#endif
18773 +#if defined (CONFIG_RA_HW_NAT) || defined (CONFIG_RA_HW_NAT_MODULE)
18774 +       if(FOE_MAGIC_TAG(skb) == FOE_MAGIC_PPE) {
18775 +               if(ra_sw_nat_hook_rx!= NULL){
18776 +                   cpu_ptr->txd_info4.FPORT = 4; /* PPE */
18777 +                   FOE_MAGIC_TAG(skb) = 0;
18778 +           }
18779 +  }
18780 +#endif
18781 +#if 0
18782 +       cpu_ptr->txd_info4.FPORT = 4; /* PPE */
18783 +       cpu_ptr->txd_info4.UDF = 0x2F;
18784 +#endif
18785 +
18786 +#if defined (CONFIG_MIPS)
18787 +       dma_cache_sync(NULL, skb->data, skb->len, DMA_TO_DEVICE);
18788 +#else
18789 +       dma_sync_single_for_device(NULL, virt_to_phys(skb->data), skb->len, DMA_TO_DEVICE);
18790 +#endif
18791 +       cpu_ptr->txd_info3.SWC_bit = 1;
18792 +
18793 +       //3. get NULL TXD and decrease free_tx_num by 1.
18794 +       ctx_offset = get_free_txd(&free_txd);
18795 +       if(ctx_offset == NUM_TX_DESC) {
18796 +           printk("get_free_txd fail\n"); // this should not happen. free_txd_num is 2 at least.
18797 +           return 0;
18798 +       }
18799 +
18800 +       //4. hook new TXD in the end of queue
18801 +       //cpu_ptr->txd_info2.NDP = VIRT_TO_PHYS(free_txd);
18802 +       cpu_ptr->txd_info2.NDP = (free_txd);
18803 +
18804 +
18805 +       //5. move CPU_PTR to new TXD
18806 +       //ei_local->tx_cpu_ptr = VIRT_TO_PHYS(free_txd);
18807 +       ei_local->tx_cpu_ptr = (free_txd);
18808 +       cpu_ptr->txd_info3.OWN_bit = 0;
18809 +       sysRegWrite(QTX_CTX_PTR, ei_local->tx_cpu_ptr);
18810 +
18811 +#if 0
18812 +       printk("----------------------------------------------\n");
18813 +       printk("txd_info1:%08X \n",*(int *)&cpu_ptr->txd_info1);
18814 +       printk("txd_info2:%08X \n",*(int *)&cpu_ptr->txd_info2);
18815 +       printk("txd_info3:%08X \n",*(int *)&cpu_ptr->txd_info3);
18816 +       printk("txd_info4:%08X \n",*(int *)&cpu_ptr->txd_info4);
18817 +#endif
18818 +
18819 +#else //#if !defined (CONFIG_RAETH_TSO)
18820 +       cpu_ptr->txd_info1.SDP = virt_to_phys(skb->data);
18821 +       cpu_ptr->txd_info3.SDL = (length - skb->data_len);
18822 +       cpu_ptr->txd_info3.LS_bit = nr_frags ? 0:1;
18823 +#if defined (CONFIG_HW_SFQ)
18824 +               SfqParseLayerInfo(skb);
18825 +                // printk("tcp_source_port=%d\n", tcp_source_port);
18826 +#if(0)
18827 +   cpu_ptr->txd_info4.VQID0 = 0;//1:HW hash 0:CPU
18828 +  if (tcp_source_port==1000)  cpu_ptr->txd_info3.VQID = 0;
18829 +  else if (tcp_source_port==1100)  cpu_ptr->txd_info3.VQID = 1;
18830 +  else if (tcp_source_port==1200)  cpu_ptr->txd_info3.VQID = 2;
18831 +  else cpu_ptr->txd_info3.VQID = 0;
18832 + #else
18833 +       cpu_ptr->txd_info4.VQID0 = 1;
18834 +  cpu_ptr->txd_info3.PROT = sfq_prot;
18835 +  cpu_ptr->txd_info3.IPOFST = 14 + (SfqParseResult.vlan1_gap); //no vlan
18836 +#endif
18837 +#endif
18838 +       if (gmac_no == 1) {
18839 +               cpu_ptr->txd_info4.FPORT = 1;
18840 +       }else {
18841 +               cpu_ptr->txd_info4.FPORT = 2;
18842 +       }
18843 +
18844 +       cpu_ptr->txd_info4.TSO = 0;
18845 +        cpu_ptr->txd_info3.QID = M2Q_table[skb->mark];
18846 +#ifdef CONFIG_PSEUDO_SUPPORT //web UI used tso
18847 +       if((lan_wan_separate==1) && (gmac_no==2)){
18848 +               cpu_ptr->txd_info3.QID += 8;
18849 +#if defined (CONFIG_HW_SFQ)
18850 +               if(web_sfq_enable == 1 &&(skb->mark == 2)){
18851 +                       cpu_ptr->txd_info3.QID = HwSfqQUp;
18852 +               }
18853 +#endif
18854 +       }
18855 +#if defined (CONFIG_HW_SFQ)
18856 +       if((lan_wan_separate==1) && (gmac_no==1)){
18857 +               if(web_sfq_enable==1 &&(skb->mark == 2)){
18858 +                               cpu_ptr->txd_info3.QID = HwSfqQDl;
18859 +               }
18860 +       }
18861 +#endif
18862 +#endif //CONFIG_PSEUDO_SUPPORT
18863 +       if(dbg==1){
18864 +               printk("M2Q_table[%d]=%d\n", skb->mark, M2Q_table[skb->mark]);
18865 +               printk("cpu_ptr->txd_info3.QID = %d\n", cpu_ptr->txd_info3.QID);
18866 +       }
18867 +#if defined (CONFIG_RAETH_CHECKSUM_OFFLOAD) && ! defined(CONFIG_RALINK_RT5350) && !defined (CONFIG_RALINK_MT7628)
18868 +       if (skb->ip_summed == CHECKSUM_PARTIAL){
18869 +           cpu_ptr->txd_info4.TUI_CO = 7;
18870 +       }else {
18871 +           cpu_ptr->txd_info4.TUI_CO = 0;
18872 +       }
18873 +#endif
18874 +
18875 +#ifdef CONFIG_RAETH_HW_VLAN_TX
18876 +       if(vlan_tx_tag_present(skb)) {
18877 +           cpu_ptr->txd_info4.VLAN_TAG = 0x10000 | vlan_tx_tag_get(skb);
18878 +       }else {
18879 +           cpu_ptr->txd_info4.VLAN_TAG = 0;
18880 +       }
18881 +#endif
18882 +#ifdef CONFIG_RAETH_HW_VLAN_TX // QoS Web UI used tso
18883 +
18884 +       if((lan_wan_separate==1) && (vlan_tx_tag_get(skb)==2)){
18885 +       //cpu_ptr->txd_info3.QID += 8;
18886 +               cpu_ptr->txd_info3.QID += 8;
18887 +#if defined (CONFIG_HW_SFQ)
18888 +               if(web_sfq_enable==1 &&(skb->mark == 2)){
18889 +                       cpu_ptr->txd_info3.QID = HwSfqQUp;
18890 +               }
18891 +#endif
18892 +       }
18893 +#if defined (CONFIG_HW_SFQ)
18894 +       if((lan_wan_separate==1) && (vlan_tx_tag_get(skb)==1)){
18895 +               if(web_sfq_enable==1 &&(skb->mark == 2)){
18896 +                       cpu_ptr->txd_info3.QID = HwSfqQDl;
18897 +               }
18898 +       }
18899 +#endif
18900 +#endif // CONFIG_RAETH_HW_VLAN_TX
18901 +
18902 +
18903 +//no hw van, no GE2, web UI used
18904 +#ifndef CONFIG_PSEUDO_SUPPORT
18905 +#ifndef CONFIG_RAETH_HW_VLAN_TX
18906 +       if(lan_wan_separate==1){
18907 +               struct vlan_hdr *vh = NULL;
18908 +    unsigned short vlanid = 0;
18909 +    unsigned short vlan_TCI;
18910 +               vh = (struct vlan_hdr *)(skb->data + ETH_HLEN);
18911 +               vlan_TCI = vh->h_vlan_TCI;
18912 +    vlanid = (vlan_TCI & VLAN_VID_MASK)>>8;
18913 +               if(vlanid == 2)//eth2.2 to wan
18914 +               {
18915 +                       cpu_ptr->txd_info3.QID += 8;
18916 +#if defined (CONFIG_HW_SFQ)
18917 +                               if(web_sfq_enable==1 &&(skb->mark == 2)){
18918 +                                       cpu_ptr->txd_info3.QID = HwSfqQUp;
18919 +                               }
18920 +#endif
18921 +               }else if(!strcmp(netdev, "eth2.1")){ // eth2.1 to lan
18922 +#if defined (CONFIG_HW_SFQ)
18923 +                       if(web_sfq_enable==1 &&(skb->mark == 2)){
18924 +                               cpu_ptr->txd_info3.QID = HwSfqQDl;
18925 +                       }
18926 +#endif
18927 +               }
18928 +}
18929 +#endif
18930 +#endif
18931 +
18932 +#if defined (CONFIG_RA_HW_NAT) || defined (CONFIG_RA_HW_NAT_MODULE)
18933 +       if(FOE_MAGIC_TAG(skb) == FOE_MAGIC_PPE) {
18934 +           if(ra_sw_nat_hook_rx!= NULL){
18935 +                   cpu_ptr->txd_info4.FPORT = 4; /* PPE */
18936 +                   FOE_MAGIC_TAG(skb) = 0;
18937 +           }
18938 +       }
18939 +#endif
18940 +
18941 +        cpu_ptr->txd_info3.SWC_bit = 1;
18942 +
18943 +        ctx_offset = get_free_txd(&free_txd);
18944 +        if(ctx_offset == NUM_TX_DESC) {
18945 +            printk("get_free_txd fail\n");
18946 +        return 0;
18947 +       }
18948 +        //cpu_ptr->txd_info2.NDP = VIRT_TO_PHYS(free_txd);
18949 +        //ei_local->tx_cpu_ptr = VIRT_TO_PHYS(free_txd);
18950 +       cpu_ptr->txd_info2.NDP = free_txd;
18951 +       ei_local->tx_cpu_ptr = free_txd;
18952 +
18953 +
18954 +       if(nr_frags > 0) {
18955 +               for(i=0;i<nr_frags;i++) {
18956 +                       // 1. set or get init value for current fragment
18957 +                       offset = 0;
18958 +                       frag = &skb_shinfo(skb)->frags[i];
18959 +                       len = frag->size;
18960 +                       frag_txd_num = cal_frag_txd_num(len); // calculate the needed TXD numbers for this fragment
18961 +                       for(frag_txd_num = frag_txd_num;frag_txd_num > 0; frag_txd_num --){
18962 +                               // 2. size will be assigned to SDL and can't be larger than MAX_TXD_LEN
18963 +                               if(len < MAX_TXD_LEN)
18964 +                                       size = len;
18965 +                               else
18966 +                                       size = MAX_TXD_LEN;
18967 +
18968 +                               //3. Update TXD info
18969 +                               cpu_ptr = (ei_local->txd_pool + (ctx_offset));
18970 +                               cpu_ptr->txd_info3.QID = M2Q_table[skb->mark];
18971 +#ifdef CONFIG_PSEUDO_SUPPORT //QoS Web UI used , nr_frags
18972 +                               if((lan_wan_separate==1) && (gmac_no==2)){
18973 +                                       //cpu_ptr->txd_info3.QID += 8;
18974 +                                       cpu_ptr->txd_info3.QID += 8;
18975 +#if defined (CONFIG_HW_SFQ)
18976 +                                       if(web_sfq_enable==1 &&(skb->mark == 2)){
18977 +                                               cpu_ptr->txd_info3.QID = HwSfqQUp;
18978 +                                       }
18979 +#endif
18980 +                               }
18981 +#if defined (CONFIG_HW_SFQ)
18982 +                               if((lan_wan_separate==1) && (gmac_no==1)){
18983 +                                       if(web_sfq_enable==1 &&(skb->mark == 2)){
18984 +                                               cpu_ptr->txd_info3.QID = HwSfqQDl;
18985 +                                       }
18986 +                               }
18987 +#endif
18988 +#endif //CONFIG_PSEUDO_SUPPORT
18989 +
18990 +//QoS web used, nr_frags
18991 +#ifdef CONFIG_RAETH_HW_VLAN_TX
18992 +       if((lan_wan_separate==1) && (vlan_tx_tag_get(skb)==2)){
18993 +               cpu_ptr->txd_info3.QID += 8;
18994 +#if defined (CONFIG_HW_SFQ)
18995 +               if(web_sfq_enable==1 &&(skb->mark == 2)){
18996 +                       cpu_ptr->txd_info3.QID = HwSfqQUp;
18997 +               }
18998 +#endif
18999 +       }
19000 +#if defined (CONFIG_HW_SFQ)
19001 +       if((lan_wan_separate==1) && (vlan_tx_tag_get(skb)==1)){
19002 +               if(web_sfq_enable==1 &&(skb->mark == 2)){
19003 +                       cpu_ptr->txd_info3.QID = HwSfqQDl;
19004 +               }
19005 +       }
19006 +#endif
19007 +#endif // CONFIG_RAETH_HW_VLAN_TX
19008 +//no hw van, no GE2, web UI used
19009 +#ifndef CONFIG_PSEUDO_SUPPORT
19010 +#ifndef CONFIG_RAETH_HW_VLAN_TX
19011 +       if(lan_wan_separate==1){
19012 +               struct vlan_hdr *vh = NULL;
19013 +    unsigned short vlanid = 0;
19014 +    unsigned short vlan_TCI;
19015 +               vh = (struct vlan_hdr *)(skb->data + ETH_HLEN);
19016 +               vlan_TCI = vh->h_vlan_TCI;
19017 +    vlanid = (vlan_TCI & VLAN_VID_MASK)>>8;
19018 +               if(vlanid == 2))//eth2.2 to wan
19019 +               {
19020 +                       cpu_ptr->txd_info3.QID += 8;
19021 +#if defined (CONFIG_HW_SFQ)
19022 +                       if(web_sfq_enable==1 &&(skb->mark == 2)){
19023 +                               cpu_ptr->txd_info3.QID = HwSfqQUp;
19024 +                       }
19025 +#endif
19026 +               }
19027 +               }else if(vlanid == 1){ // eth2.1 to lan
19028 +#if defined (CONFIG_HW_SFQ)
19029 +                       if(web_sfq_enable==1 &&(skb->mark == 2)){
19030 +                               cpu_ptr->txd_info3.QID = HwSfqQDl;
19031 +                       }
19032 +#endif
19033 +               }
19034 +       }
19035 +#endif
19036 +#endif
19037 +       if(dbg==1){
19038 +               printk("M2Q_table[%d]=%d\n", skb->mark, M2Q_table[skb->mark]);
19039 +               printk("cpu_ptr->txd_info3.QID = %d\n", cpu_ptr->txd_info3.QID);
19040 +       }
19041 +#if LINUX_VERSION_CODE < KERNEL_VERSION(3,2,0)
19042 +                               cpu_ptr->txd_info1.SDP = pci_map_page(NULL, frag->page, frag->page_offset, frag->size, PCI_DMA_TODEVICE);
19043 +#else
19044 +                               cpu_ptr->txd_info1.SDP = pci_map_page(NULL, frag->page.p, frag->page_offset + offset, size, PCI_DMA_TODEVICE);
19045 +//                             printk(" frag->page = %08x. frag->page_offset = %08x. frag->size = % 08x.\n", frag->page, (frag->page_offset+offset), size);
19046 +#endif
19047 +                               cpu_ptr->txd_info3.SDL = size;
19048 +                               if( (i==(nr_frags-1)) && (frag_txd_num == 1))
19049 +                                       cpu_ptr->txd_info3.LS_bit = 1;
19050 +                               else
19051 +                                       cpu_ptr->txd_info3.LS_bit = 0;
19052 +                               cpu_ptr->txd_info3.OWN_bit = 0;
19053 +                               cpu_ptr->txd_info3.SWC_bit = 1;
19054 +                               //4. Update skb_free for housekeeping
19055 +                               ei_local->skb_free[ctx_offset] = (cpu_ptr->txd_info3.LS_bit == 1)?skb:(struct  sk_buff *)0xFFFFFFFF; //MAGIC ID
19056 +
19057 +                               //5. Get next TXD
19058 +                               ctx_offset = get_free_txd(&free_txd);
19059 +                               //cpu_ptr->txd_info2.NDP = VIRT_TO_PHYS(free_txd);
19060 +                               //ei_local->tx_cpu_ptr = VIRT_TO_PHYS(free_txd);
19061 +                               cpu_ptr->txd_info2.NDP = free_txd;
19062 +                               ei_local->tx_cpu_ptr = free_txd;
19063 +                               //6. Update offset and len.
19064 +                               offset += size;
19065 +                               len -= size;
19066 +                       }
19067 +               }
19068 +               ei_local->skb_free[init_txd_idx]= (struct  sk_buff *)0xFFFFFFFF; //MAGIC ID
19069 +       }
19070 +
19071 +       if(skb_shinfo(skb)->gso_segs > 1) {
19072 +
19073 +//             TsoLenUpdate(skb->len);
19074 +
19075 +               /* TCP over IPv4 */
19076 +               iph = (struct iphdr *)skb_network_header(skb);
19077 +#if defined (CONFIG_RAETH_TSOV6)
19078 +               /* TCP over IPv6 */
19079 +               ip6h = (struct ipv6hdr *)skb_network_header(skb);
19080 +#endif
19081 +               if((iph->version == 4) && (iph->protocol == IPPROTO_TCP)) {
19082 +                       th = (struct tcphdr *)skb_transport_header(skb);
19083 +#if defined (CONFIG_HW_SFQ)
19084 +#if(0)
19085 +  init_cpu_ptr->txd_info4.VQID0 = 0;//1:HW hash 0:CPU
19086 +  if (tcp_source_port==1000)  init_cpu_ptr->txd_info3.VQID = 0;
19087 +  else if (tcp_source_port==1100)  init_cpu_ptr->txd_info3.VQID = 1;
19088 +  else if (tcp_source_port==1200)  init_cpu_ptr->txd_info3.VQID = 2;
19089 +  else cpu_ptr->txd_info3.VQID = 0;
19090 + #else
19091 + init_cpu_ptr->txd_info4.VQID0 = 1;
19092 +  init_cpu_ptr->txd_info3.PROT = sfq_prot;
19093 +  init_cpu_ptr->txd_info3.IPOFST = 14 + (SfqParseResult.vlan1_gap); //no vlan
19094 +#endif
19095 +#endif
19096 +                       init_cpu_ptr->txd_info4.TSO = 1;
19097 +
19098 +                       th->check = htons(skb_shinfo(skb)->gso_size);
19099 +#if defined (CONFIG_MIPS)
19100 +                       dma_cache_sync(NULL, th, sizeof(struct tcphdr), DMA_TO_DEVICE);
19101 +#else
19102 +                       dma_sync_single_for_device(NULL, virt_to_phys(th), sizeof(struct tcphdr), DMA_TO_DEVICE);
19103 +#endif
19104 +               }
19105 +
19106 +#if defined (CONFIG_RAETH_TSOV6)
19107 +               /* TCP over IPv6 */
19108 +               //ip6h = (struct ipv6hdr *)skb_network_header(skb);
19109 +               else if ((ip6h->version == 6) && (ip6h->nexthdr == NEXTHDR_TCP)) {
19110 +                       th = (struct tcphdr *)skb_transport_header(skb);
19111 +#ifdef CONFIG_RAETH_RW_PDMAPTR_FROM_VAR
19112 +                       init_cpu_ptr->txd_info4.TSO = 1;
19113 +#else
19114 +                       init_cpu_ptr->txd_info4.TSO = 1;
19115 +#endif
19116 +                       th->check = htons(skb_shinfo(skb)->gso_size);
19117 +#if defined (CONFIG_MIPS)
19118 +                       dma_cache_sync(NULL, th, sizeof(struct tcphdr), DMA_TO_DEVICE);
19119 +#else
19120 +                       dma_sync_single_for_device(NULL, virt_to_phys(th), sizeof(struct tcphdr), DMA_TO_DEVICE);
19121 +#endif
19122 +               }
19123 +#endif
19124 +       }
19125 +
19126 +
19127 +//     dma_cache_sync(NULL, skb->data, skb->len, DMA_TO_DEVICE);
19128 +
19129 +       init_cpu_ptr->txd_info3.OWN_bit = 0;
19130 +#endif // CONFIG_RAETH_TSO //
19131 +
19132 +       sysRegWrite(QTX_CTX_PTR, ei_local->tx_cpu_ptr);
19133 +
19134 +#ifdef CONFIG_PSEUDO_SUPPORT
19135 +       if (gmac_no == 2) {
19136 +               if (ei_local->PseudoDev != NULL) {
19137 +                               pAd = netdev_priv(ei_local->PseudoDev);
19138 +                               pAd->stat.tx_packets++;
19139 +                               pAd->stat.tx_bytes += length;
19140 +                       }
19141 +               } else
19142 +
19143 +#endif
19144 +        {
19145 +       ei_local->stat.tx_packets++;
19146 +       ei_local->stat.tx_bytes += skb->len;
19147 +       }
19148 +#ifdef CONFIG_RAETH_NAPI
19149 +       if ( ei_local->tx_full == 1) {
19150 +               ei_local->tx_full = 0;
19151 +               netif_wake_queue(dev);
19152 +       }
19153 +#endif
19154 +
19155 +       return length;
19156 +}
19157 +
19158 +int ei_start_xmit(struct sk_buff* skb, struct net_device *dev, int gmac_no)
19159 +{
19160 +       END_DEVICE *ei_local = netdev_priv(dev);
19161 +       unsigned long flags;
19162 +       unsigned int num_of_txd = 0;
19163 +#if defined (CONFIG_RAETH_TSO)
19164 +       unsigned int nr_frags = skb_shinfo(skb)->nr_frags, i;
19165 +       struct skb_frag_struct *frag;
19166 +#endif
19167 +#ifdef CONFIG_PSEUDO_SUPPORT
19168 +       PSEUDO_ADAPTER *pAd;
19169 +#endif
19170 +
19171 +#if !defined(CONFIG_RA_NAT_NONE)
19172 +         if(ra_sw_nat_hook_tx!= NULL)
19173 +         {
19174 +//        spin_lock_irqsave(&ei_local->page_lock, flags);
19175 +           if(ra_sw_nat_hook_tx(skb, gmac_no)==1){
19176 +//             spin_unlock_irqrestore(&ei_local->page_lock, flags);
19177 +          }else{
19178 +               kfree_skb(skb);
19179 +//             spin_unlock_irqrestore(&ei_local->page_lock, flags);
19180 +               return 0;
19181 +          }
19182 +         }
19183 +#endif
19184 +
19185 +
19186 +
19187 +       dev->trans_start = jiffies;     /* save the timestamp */
19188 +       spin_lock_irqsave(&ei_local->page_lock, flags);
19189 +#if defined (CONFIG_MIPS)
19190 +       dma_cache_sync(NULL, skb->data, skb->len, DMA_TO_DEVICE);
19191 +#else
19192 +       dma_sync_single_for_device(NULL, virt_to_phys(skb->data), skb->len, DMA_TO_DEVICE);
19193 +#endif
19194 +
19195 +
19196 +//check free_txd_num before calling rt288_eth_send()
19197 +
19198 +#if defined (CONFIG_RAETH_TSO)
19199 +       //      num_of_txd = (nr_frags==0) ? 1 : (nr_frags + 1);
19200 +       if(nr_frags != 0){
19201 +               for(i=0;i<nr_frags;i++) {
19202 +                       frag = &skb_shinfo(skb)->frags[i];
19203 +                       num_of_txd  += cal_frag_txd_num(frag->size);
19204 +               }
19205 +       }else
19206 +               num_of_txd = 1;
19207 +#else
19208 +       num_of_txd = 1;
19209 +#endif
19210 +
19211 +#if defined(CONFIG_RALINK_MT7621)
19212 +    if((sysRegRead(0xbe00000c)&0xFFFF) == 0x0101) {
19213 +           ei_xmit_housekeeping(0);
19214 +    }
19215 +#endif
19216 +
19217 +
19218 +    if ((ei_local->free_txd_num > num_of_txd + 1) && (ei_local->free_txd_num != NUM_TX_DESC))
19219 +    {
19220 +        rt2880_eth_send(dev, skb, gmac_no); // need to modify rt2880_eth_send() for QDMA
19221 +               if (ei_local->free_txd_num < 3)
19222 +               {
19223 +#if defined (CONFIG_RAETH_STOP_RX_WHEN_TX_FULL)
19224 +                   netif_stop_queue(dev);
19225 +#ifdef CONFIG_PSEUDO_SUPPORT
19226 +                   netif_stop_queue(ei_local->PseudoDev);
19227 +#endif
19228 +                   tx_ring_full = 1;
19229 +#endif
19230 +               }
19231 +    } else {
19232 +#ifdef CONFIG_PSEUDO_SUPPORT
19233 +               if (gmac_no == 2)
19234 +               {
19235 +                       if (ei_local->PseudoDev != NULL)
19236 +                       {
19237 +                           pAd = netdev_priv(ei_local->PseudoDev);
19238 +                           pAd->stat.tx_dropped++;
19239 +                   }
19240 +               } else
19241 +#endif
19242 +               ei_local->stat.tx_dropped++;
19243 +               kfree_skb(skb);
19244 +                spin_unlock_irqrestore(&ei_local->page_lock, flags);
19245 +               return 0;
19246 +     }
19247 +       spin_unlock_irqrestore(&ei_local->page_lock, flags);
19248 +       return 0;
19249 +}
19250 +
19251 +void ei_xmit_housekeeping(unsigned long unused)
19252 +{
19253 +    struct net_device *dev = dev_raether;
19254 +    END_DEVICE *ei_local = netdev_priv(dev);
19255 +#ifndef CONFIG_RAETH_NAPI
19256 +    unsigned long reg_int_mask=0;
19257 +#endif
19258 +    struct QDMA_txdesc *dma_ptr = NULL;
19259 +    struct QDMA_txdesc *cpu_ptr = NULL;
19260 +    struct QDMA_txdesc *tmp_ptr = NULL;
19261 +    unsigned int ctx_offset = 0;
19262 +    unsigned int dtx_offset = 0;
19263 +
19264 +    cpu_ptr = sysRegRead(QTX_CRX_PTR);
19265 +    dma_ptr = sysRegRead(QTX_DRX_PTR);
19266 +    ctx_offset = GET_TXD_OFFSET(&cpu_ptr);
19267 +    dtx_offset = GET_TXD_OFFSET(&dma_ptr);
19268 +    cpu_ptr     = (ei_local->txd_pool + (ctx_offset));
19269 +    dma_ptr     = (ei_local->txd_pool + (dtx_offset));
19270 +
19271 +       while(cpu_ptr != dma_ptr && (cpu_ptr->txd_info3.OWN_bit == 1)) {
19272 +                //1. keep cpu next TXD
19273 +               tmp_ptr = cpu_ptr->txd_info2.NDP;
19274 +                //2. release TXD
19275 +               put_free_txd(ctx_offset);
19276 +                //3. update ctx_offset and free skb memory
19277 +               ctx_offset = GET_TXD_OFFSET(&tmp_ptr);
19278 +#if defined (CONFIG_RAETH_TSO)
19279 +               if(ei_local->skb_free[ctx_offset]!=(struct  sk_buff *)0xFFFFFFFF) {
19280 +                       dev_kfree_skb_any(ei_local->skb_free[ctx_offset]);
19281 +               }
19282 +#else
19283 +               dev_kfree_skb_any(ei_local->skb_free[ctx_offset]);
19284 +#endif
19285 +               ei_local->skb_free[ctx_offset] = 0;
19286 +
19287 +               netif_wake_queue(dev);
19288 +#ifdef CONFIG_PSEUDO_SUPPORT
19289 +               netif_wake_queue(ei_local->PseudoDev);
19290 +#endif
19291 +               tx_ring_full=0;
19292 +                //4. update cpu_ptr
19293 +               cpu_ptr = (ei_local->txd_pool + ctx_offset);
19294 +       }
19295 +       sysRegWrite(QTX_CRX_PTR, (ei_local->phy_txd_pool + (ctx_offset << 4)));
19296 +#ifndef CONFIG_RAETH_NAPI
19297 +    reg_int_mask=sysRegRead(QFE_INT_ENABLE);
19298 +#if defined (DELAY_INT)
19299 +    sysRegWrite(QFE_INT_ENABLE, reg_int_mask| RLS_DLY_INT);
19300 +#else
19301 +
19302 +    sysRegWrite(QFE_INT_ENABLE, reg_int_mask | RLS_DONE_INT);
19303 +#endif
19304 +#endif //CONFIG_RAETH_NAPI//
19305 +}
19306 +
19307 +EXPORT_SYMBOL(ei_start_xmit);
19308 +EXPORT_SYMBOL(ei_xmit_housekeeping);
19309 +EXPORT_SYMBOL(fe_dma_init);
19310 +EXPORT_SYMBOL(rt2880_eth_send);
19311 diff --git a/drivers/net/ethernet/raeth/raether_qdma_mt7623.c b/drivers/net/ethernet/raeth/raether_qdma_mt7623.c
19312 new file mode 100644
19313 index 0000000..b465b75
19314 --- /dev/null
19315 +++ b/drivers/net/ethernet/raeth/raether_qdma_mt7623.c
19316 @@ -0,0 +1,1020 @@
19317 +#include <linux/module.h>
19318 +#include <linux/version.h>
19319 +#include <linux/kernel.h>
19320 +#include <linux/types.h>
19321 +#include <linux/pci.h>
19322 +#include <linux/init.h>
19323 +#include <linux/skbuff.h>
19324 +#include <linux/if_vlan.h>
19325 +#include <linux/if_ether.h>
19326 +#include <linux/fs.h>
19327 +#include <asm/uaccess.h>
19328 +#include <asm/rt2880/surfboardint.h>
19329 +#if defined (CONFIG_RAETH_TSO)
19330 +#include <linux/tcp.h>
19331 +#include <net/ipv6.h>
19332 +#include <linux/ip.h>
19333 +#include <net/ip.h>
19334 +#include <net/tcp.h>
19335 +#include <linux/in.h>
19336 +#include <linux/ppp_defs.h>
19337 +#include <linux/if_pppox.h>
19338 +#endif
19339 +#include <linux/delay.h>
19340 +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,35)
19341 +#include <linux/sched.h>
19342 +#endif
19343 +
19344 +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,0)
19345 +#include <asm/rt2880/rt_mmap.h>
19346 +#else
19347 +#include <linux/libata-compat.h>
19348 +#endif
19349 +
19350 +#include "ra2882ethreg.h"
19351 +#include "raether.h"
19352 +#include "ra_mac.h"
19353 +#include "ra_ioctl.h"
19354 +#include "ra_rfrw.h"
19355 +#ifdef CONFIG_RAETH_NETLINK
19356 +#include "ra_netlink.h"
19357 +#endif
19358 +#if defined (CONFIG_RAETH_QOS)
19359 +#include "ra_qos.h"
19360 +#endif
19361 +
19362 +#if defined (CONFIG_RA_HW_NAT) || defined (CONFIG_RA_HW_NAT_MODULE)
19363 +#include "../../../net/nat/hw_nat/ra_nat.h"
19364 +#endif
19365 +
19366 +
19367 +#if !defined(CONFIG_RA_NAT_NONE)
19368 +/* bruce+
19369 + */
19370 +extern int (*ra_sw_nat_hook_rx)(struct sk_buff *skb);
19371 +extern int (*ra_sw_nat_hook_tx)(struct sk_buff *skb, int gmac_no);
19372 +#endif
19373 +
19374 +#if defined(CONFIG_RA_CLASSIFIER)||defined(CONFIG_RA_CLASSIFIER_MODULE)
19375 +/* Qwert+
19376 + */
19377 +#include <asm/mipsregs.h>
19378 +extern int (*ra_classifier_hook_tx)(struct sk_buff *skb, unsigned long cur_cycle);
19379 +extern int (*ra_classifier_hook_rx)(struct sk_buff *skb, unsigned long cur_cycle);
19380 +#endif /* CONFIG_RA_CLASSIFIER */
19381 +
19382 +#if defined (CONFIG_RALINK_RT3052_MP2)
19383 +int32_t mcast_rx(struct sk_buff * skb);
19384 +int32_t mcast_tx(struct sk_buff * skb);
19385 +#endif
19386 +
19387 +#ifdef RA_MTD_RW_BY_NUM
19388 +int ra_mtd_read(int num, loff_t from, size_t len, u_char *buf);
19389 +#else
19390 +int ra_mtd_read_nm(char *name, loff_t from, size_t len, u_char *buf);
19391 +#endif
19392 +
19393 +/* gmac driver feature set config */
19394 +#if defined (CONFIG_RAETH_NAPI) || defined (CONFIG_RAETH_QOS)
19395 +#undef DELAY_INT
19396 +#else
19397 +#define DELAY_INT      1
19398 +#endif
19399 +
19400 +//#define CONFIG_UNH_TEST
19401 +/* end of config */
19402 +
19403 +#if defined (CONFIG_RAETH_JUMBOFRAME)
19404 +#define        MAX_RX_LENGTH   4096
19405 +#else
19406 +#define        MAX_RX_LENGTH   1536
19407 +#endif
19408 +
19409 +extern struct net_device               *dev_raether;
19410 +
19411 +#if defined (CONFIG_RAETH_MULTIPLE_RX_RING)
19412 +static int rx_dma_owner_idx1;
19413 +#ifdef CONFIG_RAETH_RW_PDMAPTR_FROM_VAR
19414 +static int rx_calc_idx1;
19415 +#endif
19416 +#endif
19417 +#ifdef CONFIG_RAETH_RW_PDMAPTR_FROM_VAR
19418 +static int rx_calc_idx0;
19419 +static unsigned long tx_cpu_owner_idx0=0;
19420 +#endif
19421 +static unsigned long tx_ring_full=0;
19422 +
19423 +#if defined (CONFIG_ETHTOOL) && defined (CONFIG_RAETH_ROUTER)
19424 +#include "ra_ethtool.h"
19425 +extern struct ethtool_ops      ra_ethtool_ops;
19426 +#ifdef CONFIG_PSEUDO_SUPPORT
19427 +extern struct ethtool_ops      ra_virt_ethtool_ops;
19428 +#endif // CONFIG_PSEUDO_SUPPORT //
19429 +#endif // (CONFIG_ETHTOOL //
19430 +
19431 +#ifdef CONFIG_RALINK_VISTA_BASIC
19432 +int is_switch_175c = 1;
19433 +#endif
19434 +
19435 +//skb->mark to queue mapping table
19436 +extern unsigned int M2Q_table[64];
19437 +
19438 +
19439 +#define KSEG1                   0xa0000000
19440 +#if defined (CONFIG_MIPS)
19441 +#define PHYS_TO_VIRT(x)         ((void *)((x) | KSEG1))
19442 +#define VIRT_TO_PHYS(x)         ((unsigned long)(x) & ~KSEG1)
19443 +#else
19444 +#define PHYS_TO_VIRT(x)         phys_to_virt(x)
19445 +#define VIRT_TO_PHYS(x)         virt_to_phys(x)
19446 +#endif
19447 +
19448 +
19449 +extern void set_fe_dma_glo_cfg(void);
19450 +
19451 +
19452 +/**
19453 + *
19454 + * @brief: get the TXD index from its address
19455 + *
19456 + * @param: cpu_ptr
19457 + *
19458 + * @return: TXD index
19459 +*/
19460 +
19461 +static unsigned int GET_TXD_OFFSET(struct QDMA_txdesc **cpu_ptr)
19462 +{
19463 +       struct net_device *dev = dev_raether;
19464 +       END_DEVICE *ei_local = netdev_priv(dev);
19465 +       int ctx_offset;
19466 +       //ctx_offset = (((((u32)*cpu_ptr) <<8)>>8) - ((((u32)ei_local->txd_pool)<<8)>>8))/ sizeof(struct QDMA_txdesc);
19467 +       //ctx_offset = (*cpu_ptr - ei_local->txd_pool);
19468 +       /*kurtis*/
19469 +       ctx_offset = (((((u32)*cpu_ptr) <<8)>>8) - ((((u32)ei_local->phy_txd_pool)<<8)>>8))/ sizeof(struct QDMA_txdesc);
19470 +       return ctx_offset;
19471 +}
19472 +
19473 +
19474 +
19475 +
19476 +/**
19477 + * @brief cal txd number for a page
19478 + *
19479 + * @parm size
19480 + *
19481 + * @return frag_txd_num
19482 + */
19483 +
19484 +unsigned int cal_frag_txd_num(unsigned int size)
19485 +{
19486 +       unsigned int frag_txd_num = 0;
19487 +       if(size == 0)
19488 +               return 0;
19489 +       while(size > 0){
19490 +               if(size > MAX_TXD_LEN){
19491 +                       frag_txd_num++;
19492 +                       size -= MAX_TXD_LEN;
19493 +               }else{
19494 +                       frag_txd_num++;
19495 +                       size = 0;
19496 +               }
19497 +       }
19498 +        return frag_txd_num;
19499 +
19500 +}
19501 +
19502 +/**
19503 + * @brief get free TXD from TXD queue
19504 + *
19505 + * @param free_txd
19506 + *
19507 + * @return
19508 + */
19509 +static int get_free_txd(struct QDMA_txdesc **free_txd)
19510 +{
19511 +       struct net_device *dev = dev_raether;
19512 +       END_DEVICE *ei_local = netdev_priv(dev);
19513 +       unsigned int tmp_idx;
19514 +
19515 +       if(ei_local->free_txd_num > 0){
19516 +               tmp_idx = ei_local->free_txd_head;
19517 +               ei_local->free_txd_head = ei_local->txd_pool_info[tmp_idx];
19518 +               ei_local->free_txd_num -= 1;
19519 +               //*free_txd = &ei_local->txd_pool[tmp_idx];
19520 +               *free_txd = ei_local->phy_txd_pool + (sizeof(struct QDMA_txdesc) * tmp_idx);
19521 +               return tmp_idx;
19522 +       }else
19523 +               return NUM_TX_DESC;
19524 +}
19525 +
19526 +
19527 +/**
19528 + * @brief add free TXD into TXD queue
19529 + *
19530 + * @param free_txd
19531 + *
19532 + * @return
19533 + */
19534 +int put_free_txd(int free_txd_idx)
19535 +{
19536 +       struct net_device *dev = dev_raether;
19537 +       END_DEVICE *ei_local = netdev_priv(dev);
19538 +       ei_local->txd_pool_info[ei_local->free_txd_tail] = free_txd_idx;
19539 +       ei_local->free_txd_tail = free_txd_idx;
19540 +       ei_local->txd_pool_info[free_txd_idx] = NUM_TX_DESC;
19541 +        ei_local->free_txd_num += 1;
19542 +       return 1;
19543 +}
19544 +
19545 +/*define qdma initial alloc*/
19546 +/**
19547 + * @brief
19548 + *
19549 + * @param net_dev
19550 + *
19551 + * @return  0: fail
19552 + *         1: success
19553 + */
19554 +bool qdma_tx_desc_alloc(void)
19555 +{
19556 +       struct net_device *dev = dev_raether;
19557 +       END_DEVICE *ei_local = netdev_priv(dev);
19558 +       struct QDMA_txdesc *free_txd = NULL;
19559 +       unsigned int txd_idx;
19560 +       int i = 0;
19561 +
19562 +
19563 +       ei_local->txd_pool = pci_alloc_consistent(NULL, sizeof(struct QDMA_txdesc) * NUM_TX_DESC, &ei_local->phy_txd_pool);
19564 +       printk("txd_pool=%p phy_txd_pool=%08X\n", ei_local->txd_pool , ei_local->phy_txd_pool);
19565 +
19566 +       if (ei_local->txd_pool == NULL) {
19567 +               printk("adapter->txd_pool allocation failed!\n");
19568 +               return 0;
19569 +       }
19570 +       printk("ei_local->skb_free start address is 0x%p.\n", ei_local->skb_free);
19571 +       //set all txd_pool_info to 0.
19572 +       for ( i = 0; i < NUM_TX_DESC; i++)
19573 +       {
19574 +               ei_local->skb_free[i]= 0;
19575 +               ei_local->txd_pool_info[i] = i + 1;
19576 +               ei_local->txd_pool[i].txd_info3.LS_bit = 1;
19577 +               ei_local->txd_pool[i].txd_info3.OWN_bit = 1;
19578 +       }
19579 +
19580 +       ei_local->free_txd_head = 0;
19581 +       ei_local->free_txd_tail = NUM_TX_DESC - 1;
19582 +       ei_local->free_txd_num = NUM_TX_DESC;
19583 +
19584 +
19585 +       //get free txd from txd pool
19586 +       txd_idx = get_free_txd(&free_txd);
19587 +       if( txd_idx == NUM_TX_DESC) {
19588 +               printk("get_free_txd fail\n");
19589 +               return 0;
19590 +       }
19591 +
19592 +       //add null TXD for transmit
19593 +
19594 +       /*kurtis test*/
19595 +       ei_local->tx_dma_ptr = free_txd;
19596 +       ei_local->tx_cpu_ptr = free_txd;
19597 +       //ei_local->tx_dma_ptr = virt_to_phys(free_txd);
19598 +       //ei_local->tx_cpu_ptr = virt_to_phys(free_txd);
19599 +       sysRegWrite(QTX_CTX_PTR, ei_local->tx_cpu_ptr);
19600 +       sysRegWrite(QTX_DTX_PTR, ei_local->tx_dma_ptr);
19601 +
19602 +       printk("kurtis: free_txd = 0x%x!!!\n", free_txd);
19603 +       printk("kurtis: ei_local->tx_dma_ptr = 0x%x!!!\n", ei_local->tx_dma_ptr);
19604 +
19605 +       //get free txd from txd pool
19606 +
19607 +       txd_idx = get_free_txd(&free_txd);
19608 +       if( txd_idx == NUM_TX_DESC) {
19609 +               printk("get_free_txd fail\n");
19610 +               return 0;
19611 +       }
19612 +       // add null TXD for release
19613 +       //sysRegWrite(QTX_CRX_PTR, virt_to_phys(free_txd));
19614 +       //sysRegWrite(QTX_DRX_PTR, virt_to_phys(free_txd));
19615 +       sysRegWrite(QTX_CRX_PTR, free_txd);
19616 +       sysRegWrite(QTX_DRX_PTR, free_txd);
19617 +
19618 +       printk("free_txd: %p, ei_local->cpu_ptr: %08X\n", free_txd, ei_local->tx_cpu_ptr);
19619 +
19620 +       printk(" POOL  HEAD_PTR | DMA_PTR | CPU_PTR \n");
19621 +       printk("----------------+---------+--------\n");
19622 +#if 1
19623 +       printk("     0x%p 0x%08X 0x%08X\n",ei_local->txd_pool,
19624 +                       ei_local->tx_dma_ptr, ei_local->tx_cpu_ptr);
19625 +#endif
19626 +       return 1;
19627 +}
19628 +
19629 +bool fq_qdma_init(void)
19630 +{
19631 +       struct QDMA_txdesc *free_head = NULL;
19632 +       unsigned int free_head_phy;
19633 +       unsigned int free_tail_phy;
19634 +       unsigned int *free_page_head = NULL;
19635 +       unsigned int free_page_head_phy;
19636 +       int i;
19637 +
19638 +       free_head = pci_alloc_consistent(NULL, NUM_QDMA_PAGE * sizeof(struct QDMA_txdesc), &free_head_phy);
19639 +       if (unlikely(free_head == NULL)){
19640 +               printk(KERN_ERR "QDMA FQ decriptor not available...\n");
19641 +               return 0;
19642 +       }
19643 +       memset(free_head, 0x0, sizeof(struct QDMA_txdesc) * NUM_QDMA_PAGE);
19644 +
19645 +       free_page_head = pci_alloc_consistent(NULL, NUM_QDMA_PAGE * QDMA_PAGE_SIZE, &free_page_head_phy);
19646 +       if (unlikely(free_page_head == NULL)){
19647 +               printk(KERN_ERR "QDMA FQ pager not available...\n");
19648 +               return 0;
19649 +       }
19650 +       for (i=0; i < NUM_QDMA_PAGE; i++) {
19651 +               free_head[i].txd_info1.SDP = (free_page_head_phy + (i * QDMA_PAGE_SIZE));
19652 +               if(i < (NUM_QDMA_PAGE-1)){
19653 +                       free_head[i].txd_info2.NDP = (free_head_phy + ((i+1) * sizeof(struct QDMA_txdesc)));
19654 +
19655 +
19656 +#if 0
19657 +                       printk("free_head_phy[%d] is 0x%x!!!\n",i, VIRT_TO_PHYS(&free_head[i]) );
19658 +                       printk("free_head[%d] is 0x%x!!!\n",i, &free_head[i] );
19659 +                       printk("free_head[%d].txd_info1.SDP is 0x%x!!!\n",i, free_head[i].txd_info1.SDP );
19660 +                       printk("free_head[%d].txd_info2.NDP is 0x%x!!!\n",i, free_head[i].txd_info2.NDP );
19661 +#endif
19662 +               }
19663 +               free_head[i].txd_info3.SDL = QDMA_PAGE_SIZE;
19664 +
19665 +       }
19666 +       free_tail_phy = (free_head_phy + (u32)((NUM_QDMA_PAGE-1) * sizeof(struct QDMA_txdesc)));
19667 +
19668 +       printk("free_head_phy is 0x%x!!!\n", free_head_phy);
19669 +       printk("free_tail_phy is 0x%x!!!\n", free_tail_phy);
19670 +       sysRegWrite(QDMA_FQ_HEAD, (u32)free_head_phy);
19671 +       sysRegWrite(QDMA_FQ_TAIL, (u32)free_tail_phy);
19672 +       sysRegWrite(QDMA_FQ_CNT, ((NUM_TX_DESC << 16) | NUM_QDMA_PAGE));
19673 +       sysRegWrite(QDMA_FQ_BLEN, QDMA_PAGE_SIZE << 16);
19674 +    return 1;
19675 +}
19676 +
19677 +int fe_dma_init(struct net_device *dev)
19678 +{
19679 +
19680 +       int i;
19681 +       unsigned int    regVal;
19682 +       END_DEVICE* ei_local = netdev_priv(dev);
19683 +
19684 +       fq_qdma_init();
19685 +
19686 +       while(1)
19687 +       {
19688 +               regVal = sysRegRead(QDMA_GLO_CFG);
19689 +               if((regVal & RX_DMA_BUSY))
19690 +               {
19691 +                       printk("\n  RX_DMA_BUSY !!! ");
19692 +                       continue;
19693 +               }
19694 +               if((regVal & TX_DMA_BUSY))
19695 +               {
19696 +                       printk("\n  TX_DMA_BUSY !!! ");
19697 +                       continue;
19698 +               }
19699 +               break;
19700 +       }
19701 +       /*tx desc alloc, add a NULL TXD to HW*/
19702 +
19703 +       qdma_tx_desc_alloc();
19704 +
19705 +
19706 +       /* Initial RX Ring 0*/
19707 +#ifdef CONFIG_32B_DESC
19708 +       ei_local->rx_ring0 = kmalloc(NUM_QRX_DESC * sizeof(struct PDMA_rxdesc), GFP_KERNEL);
19709 +       ei_local->phy_rx_ring0 = virt_to_phys(ei_local->rx_ring0);
19710 +#else
19711 +       ei_local->rx_ring0 = pci_alloc_consistent(NULL, NUM_QRX_DESC * sizeof(struct PDMA_rxdesc), &ei_local->phy_rx_ring0);
19712 +#endif
19713 +       for (i = 0; i < NUM_QRX_DESC; i++) {
19714 +               memset(&ei_local->rx_ring0[i],0,sizeof(struct PDMA_rxdesc));
19715 +               ei_local->rx_ring0[i].rxd_info2.DDONE_bit = 0;
19716 +#if defined (CONFIG_RAETH_SCATTER_GATHER_RX_DMA)
19717 +               ei_local->rx_ring0[i].rxd_info2.LS0 = 0;
19718 +               ei_local->rx_ring0[i].rxd_info2.PLEN0 = MAX_RX_LENGTH;
19719 +#else
19720 +               ei_local->rx_ring0[i].rxd_info2.LS0 = 1;
19721 +#endif
19722 +               ei_local->rx_ring0[i].rxd_info1.PDP0 = dma_map_single(NULL, ei_local->netrx0_skbuf[i]->data, MAX_RX_LENGTH, PCI_DMA_FROMDEVICE);
19723 +       }
19724 +       printk("QDMA_RX:phy_rx_ring0 = 0x%08x, rx_ring0 = 0x%p\n",ei_local->phy_rx_ring0,ei_local->rx_ring0);
19725 +
19726 +#if defined (CONFIG_RAETH_MULTIPLE_RX_RING)
19727 +       /* Initial RX Ring 1*/
19728 +#ifdef CONFIG_32B_DESC
19729 +       ei_local->rx_ring1 = kmalloc(NUM_QRX_DESC * sizeof(struct PDMA_rxdesc), GFP_KERNEL);
19730 +       ei_local->phy_rx_ring1 = virt_to_phys(ei_local->rx_ring1);
19731 +#else
19732 +       ei_local->rx_ring1 = pci_alloc_consistent(NULL, NUM_QRX_DESC * sizeof(struct PDMA_rxdesc), &ei_local->phy_rx_ring1);
19733 +#endif
19734 +       for (i = 0; i < NUM_QRX_DESC; i++) {
19735 +               memset(&ei_local->rx_ring1[i],0,sizeof(struct PDMA_rxdesc));
19736 +               ei_local->rx_ring1[i].rxd_info2.DDONE_bit = 0;
19737 +#if defined (CONFIG_RAETH_SCATTER_GATHER_RX_DMA)
19738 +               ei_local->rx_ring0[i].rxd_info2.LS0 = 0;
19739 +               ei_local->rx_ring0[i].rxd_info2.PLEN0 = MAX_RX_LENGTH;
19740 +#else
19741 +               ei_local->rx_ring1[i].rxd_info2.LS0 = 1;
19742 +#endif
19743 +               ei_local->rx_ring1[i].rxd_info1.PDP0 = dma_map_single(NULL, ei_local->netrx1_skbuf[i]->data, MAX_RX_LENGTH, PCI_DMA_FROMDEVICE);
19744 +       }
19745 +       printk("\nphy_rx_ring1 = 0x%08x, rx_ring1 = 0x%p\n",ei_local->phy_rx_ring1,ei_local->rx_ring1);
19746 +#endif
19747 +
19748 +       regVal = sysRegRead(QDMA_GLO_CFG);
19749 +       regVal &= 0x000000FF;
19750 +       sysRegWrite(QDMA_GLO_CFG, regVal);
19751 +       regVal=sysRegRead(QDMA_GLO_CFG);
19752 +
19753 +       /* Tell the adapter where the TX/RX rings are located. */
19754 +
19755 +       sysRegWrite(QRX_BASE_PTR_0, phys_to_bus((u32) ei_local->phy_rx_ring0));
19756 +       sysRegWrite(QRX_MAX_CNT_0,  cpu_to_le32((u32) NUM_QRX_DESC));
19757 +       sysRegWrite(QRX_CRX_IDX_0, cpu_to_le32((u32) (NUM_QRX_DESC - 1)));
19758 +#ifdef CONFIG_RAETH_RW_PDMAPTR_FROM_VAR
19759 +       rx_calc_idx0 = rx_dma_owner_idx0 =  sysRegRead(QRX_CRX_IDX_0);
19760 +#endif
19761 +       sysRegWrite(QDMA_RST_CFG, PST_DRX_IDX0);
19762 +#if defined (CONFIG_RAETH_MULTIPLE_RX_RING)
19763 +       sysRegWrite(QRX_BASE_PTR_1, phys_to_bus((u32) ei_local->phy_rx_ring1));
19764 +       sysRegWrite(QRX_MAX_CNT_1,  cpu_to_le32((u32) NUM_QRX_DESC));
19765 +       sysRegWrite(QRX_CRX_IDX_1, cpu_to_le32((u32) (NUM_QRX_DESC - 1)));
19766 +#ifdef CONFIG_RAETH_RW_PDMAPTR_FROM_VAR
19767 +       rx_calc_idx1 = rx_dma_owner_idx1 =  sysRegRead(QRX_CRX_IDX_1);
19768 +#endif
19769 +       sysRegWrite(QDMA_RST_CFG, PST_DRX_IDX1);
19770 +#endif
19771 +
19772 +#if !defined (CONFIG_RAETH_QDMATX_QDMARX)
19773 +       /* Initial PDMA RX Ring 0*/
19774 +#ifdef CONFIG_32B_DESC
19775 +        ei_local->rx_ring0 = kmalloc(NUM_RX_DESC * sizeof(struct PDMA_rxdesc), GFP_KERNEL);
19776 +        ei_local->phy_rx_ring0 = virt_to_phys(ei_local->rx_ring0);
19777 +#else
19778 +        ei_local->rx_ring0 = pci_alloc_consistent(NULL, NUM_RX_DESC * sizeof(struct PDMA_rxdesc), &ei_local->phy_rx_ring0);
19779 +#endif
19780 +        for (i = 0; i < NUM_RX_DESC; i++) {
19781 +               memset(&ei_local->rx_ring0[i],0,sizeof(struct PDMA_rxdesc));
19782 +               ei_local->rx_ring0[i].rxd_info2.DDONE_bit = 0;
19783 +#if defined (CONFIG_RAETH_SCATTER_GATHER_RX_DMA)
19784 +       ei_local->rx_ring0[i].rxd_info2.LS0 = 0;
19785 +       ei_local->rx_ring0[i].rxd_info2.PLEN0 = MAX_RX_LENGTH;
19786 +#else
19787 +       ei_local->rx_ring0[i].rxd_info2.LS0 = 1;
19788 +#endif
19789 +       ei_local->rx_ring0[i].rxd_info1.PDP0 = dma_map_single(NULL, ei_local->netrx0_skbuf[i]->data, MAX_RX_LENGTH, PCI_DMA_FROMDEVICE);
19790 +                                                               }
19791 +        printk("PDMA_RX:phy_rx_ring0 = 0x%08x, rx_ring0 = 0x%p\n",ei_local->phy_rx_ring0,ei_local->rx_ring0);
19792 +
19793 +        regVal = sysRegRead(PDMA_GLO_CFG);
19794 +        regVal &= 0x000000FF;
19795 +        sysRegWrite(PDMA_GLO_CFG, regVal);
19796 +        regVal=sysRegRead(PDMA_GLO_CFG);
19797 +
19798 +        sysRegWrite(RX_BASE_PTR0, phys_to_bus((u32) ei_local->phy_rx_ring0));
19799 +        sysRegWrite(RX_MAX_CNT0,  cpu_to_le32((u32) NUM_RX_DESC));
19800 +        sysRegWrite(RX_CALC_IDX0, cpu_to_le32((u32) (NUM_RX_DESC - 1)));
19801 +#ifdef CONFIG_RAETH_RW_PDMAPTR_FROM_VAR
19802 +        rx_calc_idx0 =  sysRegRead(RX_CALC_IDX0);
19803 +#endif
19804 +        sysRegWrite(PDMA_RST_CFG, PST_DRX_IDX0);
19805 +
19806 +#endif/*kurtis*/
19807 +        /* Enable randon early drop and set drop threshold automatically */
19808 +       sysRegWrite(QDMA_FC_THRES, 0x174444);
19809 +       sysRegWrite(QDMA_HRED2, 0x0);
19810 +       set_fe_dma_glo_cfg();
19811 +
19812 +       return 1;
19813 +}
19814 +
19815 +inline int rt2880_eth_send(struct net_device* dev, struct sk_buff *skb, int gmac_no)
19816 +{
19817 +       unsigned int    length=skb->len;
19818 +       END_DEVICE*     ei_local = netdev_priv(dev);
19819 +
19820 +       struct QDMA_txdesc *cpu_ptr;
19821 +
19822 +       struct QDMA_txdesc *dma_ptr __maybe_unused;
19823 +       struct QDMA_txdesc *free_txd;
19824 +       unsigned int  ctx_offset = 0;
19825 +       unsigned int  dtx_offset = 0;
19826 +#if defined (CONFIG_RAETH_TSO)
19827 +       struct iphdr *iph = NULL;
19828 +        struct QDMA_txdesc *init_cpu_ptr;
19829 +        struct tcphdr *th = NULL;
19830 +       struct skb_frag_struct *frag;
19831 +       unsigned int nr_frags = skb_shinfo(skb)->nr_frags;
19832 +       unsigned int len, size, offset, frag_txd_num;
19833 +       int init_txd_idx, i;
19834 +#endif // CONFIG_RAETH_TSO //
19835 +
19836 +#if defined (CONFIG_RAETH_TSOV6)
19837 +       struct ipv6hdr *ip6h = NULL;
19838 +#endif
19839 +
19840 +#ifdef CONFIG_PSEUDO_SUPPORT
19841 +       PSEUDO_ADAPTER *pAd;
19842 +#endif
19843 +       cpu_ptr = (ei_local->tx_cpu_ptr);
19844 +       ctx_offset = GET_TXD_OFFSET(&cpu_ptr);
19845 +       cpu_ptr = phys_to_virt(ei_local->tx_cpu_ptr);
19846 +       dma_ptr = phys_to_virt(ei_local->tx_dma_ptr);
19847 +/*kurtis test*/
19848 +       //dma_ptr = (ei_local->tx_dma_ptr);
19849 +
19850 +
19851 +       /*only modify virtual address*/
19852 +       //cpu_ptr = (ei_local->txd_pool) + (ctx_offset * sizeof(struct QDMA_txdesc));
19853 +       cpu_ptr = (ei_local->txd_pool + (ctx_offset));
19854 +
19855 +       //dtx_offset = GET_TXD_OFFSET(&dma_ptr);
19856 +       //dma_ptr = (ei_local->txd_pool) + (dtx_offset * sizeof(struct QDMA_txdesc));
19857 +
19858 +       //printk("eth_send  ctx_offset = 0x%x!!!\n", ctx_offset);
19859 +       //printk("eth_send  dtx_offset = 0x%x!!!\n", dtx_offset);
19860 +       //printk("eth_send  ei_local->txd_pool = 0x%x!!!\n", ei_local->txd_pool);
19861 +       //printk("eth_send  cpu_ptr = 0x%x!!!\n", cpu_ptr);
19862 +       //printk("eth_send  ctx_offset = 0x%x!!!\n", ctx_offset);
19863 +       //printk("eth_send  ei_local->skb_free[ctx_offset] = 0x%x!!!\n", skb);
19864 +
19865 +
19866 +       ei_local->skb_free[ctx_offset] = skb;
19867 +#if defined (CONFIG_RAETH_TSO)
19868 +        init_cpu_ptr = cpu_ptr;
19869 +        init_txd_idx = ctx_offset;
19870 +#endif
19871 +
19872 +#if !defined (CONFIG_RAETH_TSO)
19873 +
19874 +       //2. prepare data
19875 +       cpu_ptr->txd_info1.SDP = virt_to_phys(skb->data);
19876 +       cpu_ptr->txd_info3.SDL = skb->len;
19877 +
19878 +       if (gmac_no == 1) {
19879 +               cpu_ptr->txd_info4.FPORT = 1;
19880 +       }else {
19881 +               cpu_ptr->txd_info4.FPORT = 2;
19882 +       }
19883 +
19884 +
19885 +  cpu_ptr->txd_info3.QID = M2Q_table[skb->mark];
19886 +#if 0
19887 +       iph = (struct iphdr *)skb_network_header(skb);
19888 +        if (iph->tos == 0xe0)
19889 +               cpu_ptr->txd_info3.QID = 3;
19890 +       else if (iph->tos == 0xa0)
19891 +               cpu_ptr->txd_info3.QID = 2;
19892 +        else if (iph->tos == 0x20)
19893 +               cpu_ptr->txd_info3.QID = 1;
19894 +        else
19895 +               cpu_ptr->txd_info3.QID = 0;
19896 +#endif
19897 +
19898 +#if defined (CONFIG_RAETH_CHECKSUM_OFFLOAD) && ! defined(CONFIG_RALINK_RT5350) && !defined (CONFIG_RALINK_MT7628)
19899 +       if (skb->ip_summed == CHECKSUM_PARTIAL){
19900 +           cpu_ptr->txd_info4.TUI_CO = 7;
19901 +       }else {
19902 +           cpu_ptr->txd_info4.TUI_CO = 0;
19903 +       }
19904 +#endif
19905 +
19906 +#ifdef CONFIG_RAETH_HW_VLAN_TX
19907 +       if(vlan_tx_tag_present(skb)) {
19908 +           cpu_ptr->txd_info4.VLAN_TAG = 0x10000 | vlan_tx_tag_get(skb);
19909 +       }else {
19910 +           cpu_ptr->txd_info4.VLAN_TAG = 0;
19911 +       }
19912 +#endif
19913 +
19914 +#if defined (CONFIG_RA_HW_NAT) || defined (CONFIG_RA_HW_NAT_MODULE)
19915 +       if(FOE_MAGIC_TAG(skb) == FOE_MAGIC_PPE) {
19916 +               if(ra_sw_nat_hook_rx!= NULL){
19917 +                   cpu_ptr->txd_info4.FPORT = 4; /* PPE */
19918 +                   FOE_MAGIC_TAG(skb) = 0;
19919 +           }
19920 +  }
19921 +#endif
19922 +#if 0
19923 +       cpu_ptr->txd_info4.FPORT = 4; /* PPE */
19924 +       cpu_ptr->txd_info4.UDF = 0x2F;
19925 +#endif
19926 +
19927 +#if defined (CONFIG_MIPS)
19928 +       dma_cache_sync(NULL, skb->data, skb->len, DMA_TO_DEVICE);
19929 +#else
19930 +       dma_sync_single_for_device(NULL, virt_to_phys(skb->data), skb->len, DMA_TO_DEVICE);
19931 +#endif
19932 +       cpu_ptr->txd_info3.SWC_bit = 1;
19933 +
19934 +       //3. get NULL TXD and decrease free_tx_num by 1.
19935 +       ctx_offset = get_free_txd(&free_txd);
19936 +       if(ctx_offset == NUM_TX_DESC) {
19937 +           printk("get_free_txd fail\n"); // this should not happen. free_txd_num is 2 at least.
19938 +           return 0;
19939 +       }
19940 +
19941 +       //4. hook new TXD in the end of queue
19942 +       //cpu_ptr->txd_info2.NDP = virt_to_phys(free_txd);
19943 +       cpu_ptr->txd_info2.NDP = (free_txd);
19944 +
19945 +
19946 +       //5. move CPU_PTR to new TXD
19947 +       //ei_local->tx_cpu_ptr = virt_to_phys(free_txd);
19948 +       ei_local->tx_cpu_ptr = (free_txd);
19949 +       cpu_ptr->txd_info3.OWN_bit = 0;
19950 +       sysRegWrite(QTX_CTX_PTR, ei_local->tx_cpu_ptr);
19951 +
19952 +#if 0
19953 +       printk("----------------------------------------------\n");
19954 +       printk("txd_info1:%08X \n",*(int *)&cpu_ptr->txd_info1);
19955 +       printk("txd_info2:%08X \n",*(int *)&cpu_ptr->txd_info2);
19956 +       printk("txd_info3:%08X \n",*(int *)&cpu_ptr->txd_info3);
19957 +       printk("txd_info4:%08X \n",*(int *)&cpu_ptr->txd_info4);
19958 +#endif
19959 +
19960 +#else //#if !defined (CONFIG_RAETH_TSO)
19961 +        cpu_ptr->txd_info1.SDP = virt_to_phys(skb->data);
19962 +       cpu_ptr->txd_info3.SDL = (length - skb->data_len);
19963 +       cpu_ptr->txd_info3.LS_bit = nr_frags ? 0:1;
19964 +       if (gmac_no == 1) {
19965 +               cpu_ptr->txd_info4.FPORT = 1;
19966 +       }else {
19967 +               cpu_ptr->txd_info4.FPORT = 2;
19968 +       }
19969 +
19970 +       cpu_ptr->txd_info4.TSO = 0;
19971 +        cpu_ptr->txd_info3.QID = M2Q_table[skb->mark];
19972 +#if defined (CONFIG_RAETH_CHECKSUM_OFFLOAD) && ! defined(CONFIG_RALINK_RT5350) && !defined (CONFIG_RALINK_MT7628)
19973 +       if (skb->ip_summed == CHECKSUM_PARTIAL){
19974 +           cpu_ptr->txd_info4.TUI_CO = 7;
19975 +       }else {
19976 +           cpu_ptr->txd_info4.TUI_CO = 0;
19977 +       }
19978 +#endif
19979 +
19980 +#ifdef CONFIG_RAETH_HW_VLAN_TX
19981 +       if(vlan_tx_tag_present(skb)) {
19982 +           cpu_ptr->txd_info4.VLAN_TAG = 0x10000 | vlan_tx_tag_get(skb);
19983 +       }else {
19984 +           cpu_ptr->txd_info4.VLAN_TAG = 0;
19985 +       }
19986 +#endif
19987 +
19988 +#if defined (CONFIG_RA_HW_NAT) || defined (CONFIG_RA_HW_NAT_MODULE)
19989 +       if(FOE_MAGIC_TAG(skb) == FOE_MAGIC_PPE) {
19990 +           if(ra_sw_nat_hook_rx!= NULL){
19991 +                   cpu_ptr->txd_info4.FPORT = 4; /* PPE */
19992 +                   FOE_MAGIC_TAG(skb) = 0;
19993 +           }
19994 +       }
19995 +#endif
19996 +
19997 +        cpu_ptr->txd_info3.SWC_bit = 1;
19998 +
19999 +        ctx_offset = get_free_txd(&free_txd);
20000 +        if(ctx_offset == NUM_TX_DESC) {
20001 +            printk("get_free_txd fail\n");
20002 +        return 0;
20003 +       }
20004 +        //cpu_ptr->txd_info2.NDP = virt_to_phys(free_txd);
20005 +        //ei_local->tx_cpu_ptr = virt_to_phys(free_txd);
20006 +        cpu_ptr->txd_info2.NDP = free_txd;
20007 +        ei_local->tx_cpu_ptr = free_txd;
20008 +
20009 +       if(nr_frags > 0) {
20010 +               for(i=0;i<nr_frags;i++) {
20011 +                       // 1. set or get init value for current fragment
20012 +                       offset = 0;
20013 +                       frag = &skb_shinfo(skb)->frags[i];
20014 +                       len = frag->size;
20015 +                       frag_txd_num = cal_frag_txd_num(len); // calculate the needed TXD numbers for this fragment
20016 +                       for(frag_txd_num = frag_txd_num;frag_txd_num > 0; frag_txd_num --){
20017 +                               // 2. size will be assigned to SDL and can't be larger than MAX_TXD_LEN
20018 +                               if(len < MAX_TXD_LEN)
20019 +                                       size = len;
20020 +                               else
20021 +                                       size = MAX_TXD_LEN;
20022 +
20023 +                               //3. Update TXD info
20024 +                               cpu_ptr = (ei_local->txd_pool + (ctx_offset));
20025 +                               cpu_ptr->txd_info3.QID = M2Q_table[skb->mark];
20026 +#if LINUX_VERSION_CODE < KERNEL_VERSION(3,2,0)
20027 +                               cpu_ptr->txd_info1.SDP = pci_map_page(NULL, frag->page, frag->page_offset, frag->size, PCI_DMA_TODEVICE);
20028 +#else
20029 +                               cpu_ptr->txd_info1.SDP = pci_map_page(NULL, frag->page.p, frag->page_offset + offset, size, PCI_DMA_TODEVICE);
20030 +//                             printk(" frag->page = %08x. frag->page_offset = %08x. frag->size = % 08x.\n", frag->page, (frag->page_offset+offset), size);
20031 +#endif
20032 +                               cpu_ptr->txd_info3.SDL = size;
20033 +                               if( (i==(nr_frags-1)) && (frag_txd_num == 1))
20034 +                                       cpu_ptr->txd_info3.LS_bit = 1;
20035 +                               else
20036 +                                       cpu_ptr->txd_info3.LS_bit = 0;
20037 +                               cpu_ptr->txd_info3.OWN_bit = 0;
20038 +                               cpu_ptr->txd_info3.SWC_bit = 1;
20039 +                               //4. Update skb_free for housekeeping
20040 +                               ei_local->skb_free[ctx_offset] = (cpu_ptr->txd_info3.LS_bit == 1)?skb:(struct  sk_buff *)0xFFFFFFFF; //MAGIC ID
20041 +
20042 +                               //5. Get next TXD
20043 +                               ctx_offset = get_free_txd(&free_txd);
20044 +                               //cpu_ptr->txd_info2.NDP = virt_to_phys(free_txd);
20045 +                               //ei_local->tx_cpu_ptr = virt_to_phys(free_txd);
20046 +                               cpu_ptr->txd_info2.NDP = free_txd;
20047 +                               ei_local->tx_cpu_ptr = free_txd;
20048 +                               //6. Update offset and len.
20049 +                               offset += size;
20050 +                               len -= size;
20051 +                       }
20052 +               }
20053 +               ei_local->skb_free[init_txd_idx]= (struct  sk_buff *)0xFFFFFFFF; //MAGIC ID
20054 +       }
20055 +
20056 +       if(skb_shinfo(skb)->gso_segs > 1) {
20057 +
20058 +//             TsoLenUpdate(skb->len);
20059 +
20060 +               /* TCP over IPv4 */
20061 +               iph = (struct iphdr *)skb_network_header(skb);
20062 +#if defined (CONFIG_RAETH_TSOV6)
20063 +               /* TCP over IPv6 */
20064 +               ip6h = (struct ipv6hdr *)skb_network_header(skb);
20065 +#endif
20066 +               if((iph->version == 4) && (iph->protocol == IPPROTO_TCP)) {
20067 +                       th = (struct tcphdr *)skb_transport_header(skb);
20068 +
20069 +                       init_cpu_ptr->txd_info4.TSO = 1;
20070 +
20071 +                       th->check = htons(skb_shinfo(skb)->gso_size);
20072 +#if defined (CONFIG_MIPS)
20073 +                       dma_cache_sync(NULL, th, sizeof(struct tcphdr), DMA_TO_DEVICE);
20074 +#else
20075 +                       dma_sync_single_for_device(NULL, virt_to_phys(th), sizeof(struct tcphdr), DMA_TO_DEVICE);
20076 +#endif
20077 +               }
20078 +
20079 +#if defined (CONFIG_RAETH_TSOV6)
20080 +               /* TCP over IPv6 */
20081 +               //ip6h = (struct ipv6hdr *)skb_network_header(skb);
20082 +               else if ((ip6h->version == 6) && (ip6h->nexthdr == NEXTHDR_TCP)) {
20083 +                       th = (struct tcphdr *)skb_transport_header(skb);
20084 +#ifdef CONFIG_RAETH_RW_PDMAPTR_FROM_VAR
20085 +                       init_cpu_ptr->txd_info4.TSO = 1;
20086 +#else
20087 +                       init_cpu_ptr->txd_info4.TSO = 1;
20088 +#endif
20089 +                       th->check = htons(skb_shinfo(skb)->gso_size);
20090 +#if defined (CONFIG_MIPS)
20091 +                       dma_cache_sync(NULL, th, sizeof(struct tcphdr), DMA_TO_DEVICE);
20092 +#else
20093 +                       dma_sync_single_for_device(NULL, virt_to_phys(th), sizeof(struct tcphdr), DMA_TO_DEVICE);
20094 +#endif
20095 +               }
20096 +#endif
20097 +       }
20098 +
20099 +
20100 +//     dma_cache_sync(NULL, skb->data, skb->len, DMA_TO_DEVICE);
20101 +
20102 +       init_cpu_ptr->txd_info3.OWN_bit = 0;
20103 +#endif // CONFIG_RAETH_TSO //
20104 +
20105 +       sysRegWrite(QTX_CTX_PTR, ei_local->tx_cpu_ptr);
20106 +
20107 +#ifdef CONFIG_PSEUDO_SUPPORT
20108 +       if (gmac_no == 2) {
20109 +               if (ei_local->PseudoDev != NULL) {
20110 +                               pAd = netdev_priv(ei_local->PseudoDev);
20111 +                               pAd->stat.tx_packets++;
20112 +                               pAd->stat.tx_bytes += length;
20113 +                       }
20114 +               } else
20115 +
20116 +#endif
20117 +        {
20118 +       ei_local->stat.tx_packets++;
20119 +       ei_local->stat.tx_bytes += skb->len;
20120 +       }
20121 +#ifdef CONFIG_RAETH_NAPI
20122 +       if ( ei_local->tx_full == 1) {
20123 +               ei_local->tx_full = 0;
20124 +               netif_wake_queue(dev);
20125 +       }
20126 +#endif
20127 +
20128 +       return length;
20129 +}
20130 +
20131 +int ei_start_xmit(struct sk_buff* skb, struct net_device *dev, int gmac_no)
20132 +{
20133 +       END_DEVICE *ei_local = netdev_priv(dev);
20134 +       unsigned long flags;
20135 +       unsigned int num_of_txd = 0;
20136 +#if defined (CONFIG_RAETH_TSO)
20137 +       unsigned int nr_frags = skb_shinfo(skb)->nr_frags, i;
20138 +       struct skb_frag_struct *frag;
20139 +#endif
20140 +#ifdef CONFIG_PSEUDO_SUPPORT
20141 +       PSEUDO_ADAPTER *pAd;
20142 +#endif
20143 +
20144 +#if !defined(CONFIG_RA_NAT_NONE)
20145 +         if(ra_sw_nat_hook_tx!= NULL)
20146 +         {
20147 +//        spin_lock_irqsave(&ei_local->page_lock, flags);
20148 +           if(ra_sw_nat_hook_tx(skb, gmac_no)==1){
20149 +//             spin_unlock_irqrestore(&ei_local->page_lock, flags);
20150 +          }else{
20151 +               kfree_skb(skb);
20152 +//             spin_unlock_irqrestore(&ei_local->page_lock, flags);
20153 +               return 0;
20154 +          }
20155 +         }
20156 +#endif
20157 +
20158 +#if defined(CONFIG_RALINK_MT7621) || defined(CONFIG_ARCH_MT7623)
20159 +#define MIN_PKT_LEN  64
20160 +        if (skb->len < MIN_PKT_LEN) {
20161 +                if (skb_padto(skb, MIN_PKT_LEN)) {
20162 +                        printk("raeth: skb_padto failed\n");
20163 +                        return 0;
20164 +                }
20165 +                skb_put(skb, MIN_PKT_LEN - skb->len);
20166 +        }
20167 +#endif
20168 +
20169 +
20170 +       dev->trans_start = jiffies;     /* save the timestamp */
20171 +       spin_lock_irqsave(&ei_local->page_lock, flags);
20172 +#if defined (CONFIG_MIPS)
20173 +       dma_cache_sync(NULL, skb->data, skb->len, DMA_TO_DEVICE);
20174 +#else
20175 +       dma_sync_single_for_device(NULL, virt_to_phys(skb->data), skb->len, DMA_TO_DEVICE);
20176 +#endif
20177 +
20178 +
20179 +//check free_txd_num before calling rt288_eth_send()
20180 +
20181 +#if defined (CONFIG_RAETH_TSO)
20182 +       //      num_of_txd = (nr_frags==0) ? 1 : (nr_frags + 1);
20183 +       if(nr_frags != 0){
20184 +               for(i=0;i<nr_frags;i++) {
20185 +                       frag = &skb_shinfo(skb)->frags[i];
20186 +                       num_of_txd  += cal_frag_txd_num(frag->size);
20187 +               }
20188 +       }else
20189 +               num_of_txd = 1;
20190 +#else
20191 +       num_of_txd = 1;
20192 +#endif
20193 +
20194 +#if defined(CONFIG_RALINK_MT7621)
20195 +    if((sysRegRead(0xbe00000c)&0xFFFF) == 0x0101) {
20196 +           ei_xmit_housekeeping(0);
20197 +    }
20198 +#endif
20199 +
20200 +    ei_xmit_housekeeping(0);
20201 +
20202 +    //if ((ei_local->free_txd_num > num_of_txd + 1) && (ei_local->free_txd_num != NUM_TX_DESC))
20203 +    if ((ei_local->free_txd_num > num_of_txd + 5) && (ei_local->free_txd_num != NUM_TX_DESC))
20204 +    {
20205 +        rt2880_eth_send(dev, skb, gmac_no); // need to modify rt2880_eth_send() for QDMA
20206 +               if (ei_local->free_txd_num < 3)
20207 +               {
20208 +#if defined (CONFIG_RAETH_STOP_RX_WHEN_TX_FULL)
20209 +                   netif_stop_queue(dev);
20210 +#ifdef CONFIG_PSEUDO_SUPPORT
20211 +                   netif_stop_queue(ei_local->PseudoDev);
20212 +#endif
20213 +                   tx_ring_full = 1;
20214 +#endif
20215 +               }
20216 +    } else {
20217 +#ifdef CONFIG_PSEUDO_SUPPORT
20218 +               if (gmac_no == 2)
20219 +               {
20220 +                       if (ei_local->PseudoDev != NULL)
20221 +                       {
20222 +                           pAd = netdev_priv(ei_local->PseudoDev);
20223 +                           pAd->stat.tx_dropped++;
20224 +                   }
20225 +               } else
20226 +#endif
20227 +               ei_local->stat.tx_dropped++;
20228 +               kfree_skb(skb);
20229 +                spin_unlock_irqrestore(&ei_local->page_lock, flags);
20230 +               return 0;
20231 +     }
20232 +       spin_unlock_irqrestore(&ei_local->page_lock, flags);
20233 +       return 0;
20234 +}
20235 +
20236 +void ei_xmit_housekeeping(unsigned long unused)
20237 +{
20238 +    struct net_device *dev = dev_raether;
20239 +    END_DEVICE *ei_local = netdev_priv(dev);
20240 +#ifndef CONFIG_RAETH_NAPI
20241 +    unsigned long reg_int_mask=0;
20242 +#endif
20243 +    struct QDMA_txdesc *dma_ptr = NULL;
20244 +    struct QDMA_txdesc *cpu_ptr = NULL;
20245 +    struct QDMA_txdesc *tmp_ptr = NULL;
20246 +    unsigned int htx_offset = 0;
20247 +    unsigned int ctx_offset = 0;
20248 +    unsigned int dtx_offset = 0;
20249 +
20250 +    //dma_ptr = phys_to_virt(sysRegRead(QTX_DRX_PTR));
20251 +    //cpu_ptr = phys_to_virt(sysRegRead(QTX_CRX_PTR));
20252 +    //printk("kurtis:housekeeping  QTX_DRX_PTR = 0x%x!!!\n", sysRegRead(QTX_DRX_PTR));
20253 +    //printk("kurtis:housekeeping  DMA_PTR = 0x%x!!!\n", dma_ptr);
20254 +
20255 +    cpu_ptr = sysRegRead(QTX_CRX_PTR);
20256 +    dma_ptr = sysRegRead(QTX_DRX_PTR);
20257 +
20258 +    //printk("kurtis:housekeeping  QTX_CRX_PTR = 0x%x!!!\n", cpu_ptr);
20259 +    //printk("kurtis:housekeeping  QTX_DRX_PTR = 0x%x!!!\n", dma_ptr);
20260 +    ctx_offset = GET_TXD_OFFSET(&cpu_ptr);
20261 +    dtx_offset = GET_TXD_OFFSET(&dma_ptr);
20262 +    htx_offset = ctx_offset;
20263 +    cpu_ptr    = (ei_local->txd_pool + (ctx_offset));
20264 +    dma_ptr    = (ei_local->txd_pool + (dtx_offset));
20265 +
20266 +
20267 +    //printk("kurtis:housekeeping  CPU_PTR = 0x%x!!!\n", cpu_ptr);
20268 +    //printk("kurtis:housekeeping  DMA_PTR = 0x%x!!!\n", dma_ptr);
20269 +
20270 +/*temp mark*/
20271 +#if 1
20272 +
20273 +
20274 +    if(cpu_ptr != dma_ptr && (cpu_ptr->txd_info3.OWN_bit == 1)) {
20275 +       while(cpu_ptr != dma_ptr && (cpu_ptr->txd_info3.OWN_bit == 1)) {
20276 +
20277 +           //1. keep cpu next TXD
20278 +           //tmp_ptr = phys_to_virt(cpu_ptr->txd_info2.NDP);
20279 +           tmp_ptr = cpu_ptr->txd_info2.NDP;
20280 +            htx_offset = GET_TXD_OFFSET(&tmp_ptr);
20281 +       //printk("kurtis:housekeeping  cpu_ptr->txd_info2.NDP = 0x%x!!!\n", cpu_ptr->txd_info2.NDP);
20282 +       //printk("kurtis:housekeeping  tmp_ptr = 0x%x!!!\n", tmp_ptr);
20283 +       //printk("kurtis:housekeeping  htx_offset = 0x%x!!!\n", htx_offset);
20284 +            //2. free skb meomry
20285 +#if defined (CONFIG_RAETH_TSO)
20286 +           if(ei_local->skb_free[htx_offset]!=(struct  sk_buff *)0xFFFFFFFF) {
20287 +                   dev_kfree_skb_any(ei_local->skb_free[htx_offset]);
20288 +           }
20289 +#else
20290 +           dev_kfree_skb_any(ei_local->skb_free[htx_offset]);
20291 +#endif
20292 +
20293 +           //3. release TXD
20294 +           //htx_offset = GET_TXD_OFFSET(&cpu_ptr);
20295 +           //put_free_txd(htx_offset);
20296 +           put_free_txd(ctx_offset);
20297 +
20298 +
20299 +
20300 +            netif_wake_queue(dev);
20301 +#ifdef CONFIG_PSEUDO_SUPPORT
20302 +           netif_wake_queue(ei_local->PseudoDev);
20303 +#endif
20304 +           tx_ring_full=0;
20305 +
20306 +           //4. update cpu_ptr to next ptr
20307 +           //cpu_ptr = tmp_ptr;
20308 +           cpu_ptr = (ei_local->txd_pool + htx_offset);
20309 +           ctx_offset = htx_offset;
20310 +           //cpu_ptr = (cpu_ptr + (htx_offset));
20311 +           //printk("kurtis:housekeeping 4. update  cpu_ptr = 0x%x!!!\n", cpu_ptr);
20312 +       }
20313 +    }
20314 +    //sysRegWrite(QTX_CRX_PTR, virt_to_phys(cpu_ptr));
20315 +    //sysRegWrite(QTX_CRX_PTR, cpu_ptr);
20316 +    tmp_ptr = (ei_local->phy_txd_pool + (htx_offset << 4));
20317 +    //printk("kurtis:housekeeping 5. update  QTX_CRX_PTR = 0x%x!!!\n", tmp_ptr);
20318 +    sysRegWrite(QTX_CRX_PTR, tmp_ptr);
20319 +
20320 +#endif
20321 +
20322 +#ifndef CONFIG_RAETH_NAPI
20323 +    reg_int_mask=sysRegRead(QFE_INT_ENABLE);
20324 +#if defined (DELAY_INT)
20325 +    sysRegWrite(FE_INT_ENABLE, reg_int_mask| RLS_DLY_INT);
20326 +#else
20327 +
20328 +    sysRegWrite(FE_INT_ENABLE, reg_int_mask | RLS_DONE_INT);
20329 +#endif
20330 +#endif //CONFIG_RAETH_NAPI//
20331 +}
20332 +
20333 +EXPORT_SYMBOL(ei_start_xmit);
20334 +EXPORT_SYMBOL(ei_xmit_housekeeping);
20335 +EXPORT_SYMBOL(fe_dma_init);
20336 +EXPORT_SYMBOL(rt2880_eth_send);
20337 diff --git a/drivers/net/ethernet/raeth/smb_hook.c b/drivers/net/ethernet/raeth/smb_hook.c
20338 new file mode 100644
20339 index 0000000..617139c
20340 --- /dev/null
20341 +++ b/drivers/net/ethernet/raeth/smb_hook.c
20342 @@ -0,0 +1,17 @@
20343 +#include <linux/version.h>
20344 +#include <linux/module.h>
20345 +#include <linux/kernel.h>
20346 +#include <linux/types.h>
20347 +#include <linux/skbuff.h>
20348 +
20349 +
20350 +int (*smb_nf_local_in_hook)(struct sk_buff *skb) = NULL;
20351 +int (*smb_nf_pre_routing_hook)(struct sk_buff *skb) = NULL;
20352 +int (*smb_nf_local_out_hook)(struct sk_buff *skb) = NULL;
20353 +int (*smb_nf_post_routing_hook)(struct sk_buff *skb) = NULL;
20354 +EXPORT_SYMBOL(smb_nf_local_in_hook);
20355 +EXPORT_SYMBOL(smb_nf_pre_routing_hook);
20356 +EXPORT_SYMBOL(smb_nf_local_out_hook);
20357 +EXPORT_SYMBOL(smb_nf_post_routing_hook);
20358 +
20359 +
20360 diff --git a/drivers/net/ethernet/raeth/smb_nf.c b/drivers/net/ethernet/raeth/smb_nf.c
20361 new file mode 100644
20362 index 0000000..86250eb
20363 --- /dev/null
20364 +++ b/drivers/net/ethernet/raeth/smb_nf.c
20365 @@ -0,0 +1,177 @@
20366 +#include <linux/module.h>
20367 +#include <linux/version.h>
20368 +#include <linux/kernel.h>
20369 +#include <linux/types.h>
20370 +
20371 +#include <linux/inetdevice.h>
20372 +#include <linux/tcp.h>
20373 +#include <linux/ip.h>
20374 +#include <net/tcp.h>
20375 +#include <net/ip.h>
20376 +
20377 +extern int (*smb_nf_local_in_hook)(struct sk_buff *skb);
20378 +extern int (*smb_nf_pre_routing_hook)(struct sk_buff *skb);
20379 +extern int (*smb_nf_local_out_hook)(struct sk_buff *skb);
20380 +extern int (*smb_nf_post_routing_hook)(struct sk_buff *skb);
20381 +
20382 +struct net_device *lan_int = NULL;
20383 +struct in_ifaddr *lan_ifa = NULL;
20384 +
20385 +
20386 +int mtk_smb_nf_local_in_hook(struct sk_buff *skb)
20387 +{
20388 +       struct iphdr *iph = ip_hdr(skb);
20389 +
20390 +       if (skb->protocol == htons(ETH_P_IP)) {
20391 +               struct iphdr *iph = ip_hdr(skb);
20392 +
20393 +               if (iph->protocol == IPPROTO_TCP) {
20394 +                       struct tcphdr *th = tcp_hdr(skb);
20395 +                       unsigned short sport, dport;
20396 +
20397 +                       th = tcp_hdr(skb);
20398 +                       th = (struct tcphdr *)(((unsigned char *)iph) + iph->ihl*4);
20399 +
20400 +                       if ((iph->daddr == lan_ifa->ifa_local)
20401 +                               && ((th->dest == 0xbd01) || (th->dest == 0x8900)
20402 +                               || (th->dest == 0x8a00) || (th->dest == 0x8b00)))
20403 +                               return 1;
20404 +                       else
20405 +                               return 0;
20406 +               }
20407 +
20408 +       }
20409 +
20410 +       return 0;
20411 +}
20412 +
20413 +int mtk_smb_nf_pre_routing_hook(struct sk_buff *skb)
20414 +{
20415 +       struct iphdr *iph = ip_hdr(skb);
20416 +
20417 +       if (skb->protocol == htons(ETH_P_IP)) {
20418 +               struct iphdr *iph = ip_hdr(skb);
20419 +
20420 +               if (iph->protocol == IPPROTO_TCP) {
20421 +                       struct tcphdr *th = tcp_hdr(skb);
20422 +                       unsigned short sport, dport;
20423 +
20424 +                       th = tcp_hdr(skb);
20425 +                       th = (struct tcphdr *)(((unsigned char *)iph) + iph->ihl*4);
20426 +                       if ((iph->daddr == lan_ifa->ifa_local)
20427 +                               && ((th->dest == 0xbd01) || (th->dest == 0x8900)
20428 +                               || (th->dest == 0x8a00) || (th->dest == 0x8b00)))
20429 +                               return 1;
20430 +                       else
20431 +                               return 0;
20432 +               }
20433 +
20434 +       }
20435 +
20436 +       return 0;
20437 +}
20438 +
20439 +int mtk_smb_nf_local_out_hook(struct sk_buff *skb)
20440 +{
20441 +       struct iphdr *iph = ip_hdr(skb);
20442 +
20443 +       if (iph->protocol == IPPROTO_TCP) {
20444 +               struct tcphdr *th = tcp_hdr(skb);
20445 +
20446 +               th = tcp_hdr(skb);
20447 +               th = (struct tcphdr *)(((unsigned char *)iph) + iph->ihl*4);
20448 +
20449 +               if ((iph->saddr == lan_ifa->ifa_local)
20450 +                       && ((th->source == 0xbd01) || (th->source == 0x8900)
20451 +                       || (th->source == 0x8a00) || (th->source == 0x8b00)))
20452 +                       return 1;
20453 +               else
20454 +                       return 0;
20455 +       }
20456 +
20457 +       return 0;
20458 +}
20459 +
20460 +int mtk_smb_nf_post_routing_hook(struct sk_buff *skb)
20461 +{
20462 +       struct iphdr *iph = ip_hdr(skb);
20463 +
20464 +       if (skb->protocol == htons(ETH_P_IP)) {
20465 +               struct iphdr *iph = ip_hdr(skb);
20466 +
20467 +               if (iph->protocol == IPPROTO_TCP) {
20468 +                       struct tcphdr *th = tcp_hdr(skb);
20469 +
20470 +                       th = tcp_hdr(skb);
20471 +                       th = (struct tcphdr *)(((unsigned char *)iph) + iph->ihl*4);
20472 +
20473 +                       if ((iph->saddr == lan_ifa->ifa_local)
20474 +                               && ((th->source == 0xbd01) || (th->source == 0x8900)
20475 +                               || (th->source == 0x8a00) || (th->source == 0x8b00)))
20476 +                               return 1;
20477 +                       else
20478 +                               return 0;
20479 +               }
20480 +
20481 +       }
20482 +
20483 +       return 0;
20484 +}
20485 +
20486 +int __init mtk_smb_hook_init(void)
20487 +{
20488 +       struct in_device *in_dev;
20489 +       struct in_ifaddr **ifap = NULL;
20490 +       struct in_ifaddr *ifa = NULL;
20491 +
20492 +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,35)
20493 +       lan_int = dev_get_by_name(&init_net, "br0");
20494 +#else
20495 +       lan_int = dev_get_by_name("br0");
20496 +#endif
20497 +       if (lan_int)
20498 +               in_dev = __in_dev_get_rtnl(lan_int);
20499 +       else
20500 +               return 0;
20501 +
20502 +       if (in_dev) {
20503 +               for (ifap = &in_dev->ifa_list; (ifa = *ifap) != NULL;
20504 +                    ifap = &ifa->ifa_next) {
20505 +                       if (!strcmp("br0", ifa->ifa_label))
20506 +                       {
20507 +                               lan_ifa = ifa;
20508 +                               break; /* found */
20509 +                       }
20510 +               }
20511 +       }
20512 +       else
20513 +               return 0;
20514 +
20515 +       if (lan_ifa) {
20516 +               smb_nf_local_in_hook = mtk_smb_nf_local_in_hook;
20517 +               smb_nf_pre_routing_hook = mtk_smb_nf_pre_routing_hook;
20518 +               smb_nf_local_out_hook = mtk_smb_nf_local_out_hook;
20519 +               smb_nf_post_routing_hook = mtk_smb_nf_post_routing_hook;
20520 +       }
20521 +
20522 +       printk("Samba Netfilter Hook Enabled\n");
20523 +
20524 +       return 0;
20525 +}
20526 +
20527 +void mtk_smb_hook_cleanup(void)
20528 +{
20529 +       lan_int = NULL;
20530 +       lan_ifa = NULL;
20531 +       smb_nf_local_in_hook = NULL;
20532 +       smb_nf_pre_routing_hook = NULL;
20533 +       smb_nf_local_out_hook = NULL;
20534 +       smb_nf_post_routing_hook = NULL;
20535 +
20536 +       return;
20537 +}
20538 +
20539 +module_init(mtk_smb_hook_init);
20540 +module_exit(mtk_smb_hook_cleanup);
20541 +
20542 +MODULE_LICENSE("GPL");
20543 diff --git a/drivers/net/ethernet/raeth/sync_write.h b/drivers/net/ethernet/raeth/sync_write.h
20544 new file mode 100644
20545 index 0000000..8b800e6
20546 --- /dev/null
20547 +++ b/drivers/net/ethernet/raeth/sync_write.h
20548 @@ -0,0 +1,103 @@
20549 +#ifndef _MT_SYNC_WRITE_H
20550 +#define _MT_SYNC_WRITE_H
20551 +
20552 +#if defined(__KERNEL__)
20553 +
20554 +#include <linux/io.h>
20555 +#include <asm/cacheflush.h>
20556 +//#include <asm/system.h>
20557 +
20558 +/*
20559 + * Define macros.
20560 + */
20561 +
20562 +#define mt65xx_reg_sync_writel(v, a) \
20563 +        do {    \
20564 +            __raw_writel((v), IOMEM((a)));   \
20565 +            dsb();  \
20566 +        } while (0)
20567 +
20568 +#define mt65xx_reg_sync_writew(v, a) \
20569 +        do {    \
20570 +            __raw_writew((v), IOMEM((a)));   \
20571 +            dsb();  \
20572 +        } while (0)
20573 +
20574 +#define mt65xx_reg_sync_writeb(v, a) \
20575 +        do {    \
20576 +            __raw_writeb((v), IOMEM((a)));   \
20577 +            dsb();  \
20578 +        } while (0)
20579 +
20580 +#define mt_reg_sync_writel(v, a) \
20581 +        do {    \
20582 +            __raw_writel((v), IOMEM((a)));   \
20583 +            dsb();  \
20584 +        } while (0)
20585 +
20586 +#define mt_reg_sync_writew(v, a) \
20587 +        do {    \
20588 +            __raw_writew((v), IOMEM((a)));   \
20589 +            dsb();  \
20590 +        } while (0)
20591 +
20592 +#define mt_reg_sync_writeb(v, a) \
20593 +        do {    \
20594 +            __raw_writeb((v), IOMEM((a)));   \
20595 +            dsb();  \
20596 +        } while (0)
20597 +
20598 +
20599 +#else   /* __KERNEL__ */
20600 +
20601 +#include <sys/types.h>
20602 +#include <sys/stat.h>
20603 +#include <fcntl.h>
20604 +#include <unistd.h>
20605 +#include <string.h>
20606 +
20607 +#define dsb()   \
20608 +        do {    \
20609 +            __asm__ __volatile__ ("dsb" : : : "memory"); \
20610 +        } while (0)
20611 +
20612 +#define mt65xx_reg_sync_writel(v, a) \
20613 +        do {    \
20614 +            *(volatile unsigned int *)(a) = (v);    \
20615 +            dsb(); \
20616 +        } while (0)
20617 +
20618 +#define mt65xx_reg_sync_writew(v, a) \
20619 +        do {    \
20620 +            *(volatile unsigned short *)(a) = (v);    \
20621 +            dsb(); \
20622 +        } while (0)
20623 +
20624 +#define mt65xx_reg_sync_writeb(v, a) \
20625 +        do {    \
20626 +            *(volatile unsigned char *)(a) = (v);    \
20627 +            dsb(); \
20628 +        } while (0)
20629 +
20630 +#define mt_reg_sync_writel(v, a) \
20631 +        do {    \
20632 +            *(volatile unsigned int *)(a) = (v);    \
20633 +            dsb(); \
20634 +        } while (0)
20635 +
20636 +#define mt_reg_sync_writew(v, a) \
20637 +        do {    \
20638 +            *(volatile unsigned short *)(a) = (v);    \
20639 +            dsb(); \
20640 +        } while (0)
20641 +
20642 +#define mt_reg_sync_writeb(v, a) \
20643 +        do {    \
20644 +            *(volatile unsigned char *)(a) = (v);    \
20645 +            dsb(); \
20646 +        } while (0)
20647 +
20648 +
20649 +#endif  /* __KERNEL__ */
20650 +
20651 +#endif  /* !_MT_SYNC_WRITE_H */
20652 --
20653 1.7.10.4
20654