1 From 32ea3b91046bea40cd1a7a4f16a24d75f53ca92a Mon Sep 17 00:00:00 2001
2 From: Hongzhou Yang <hongzhou.yang@mediatek.com>
3 Date: Mon, 18 May 2015 23:11:16 -0700
4 Subject: [PATCH 52/76] pinctrl: mediatek: add ies/smt control to common code.
6 Input enable and smt setting have different register,
9 Several mediatek soc use similar input enable/smt setting
10 procedure as mt8173, some soc use generic input enable/smt
11 setting, some soc has no input enable/smt setting. Adding
12 common code to handle all those cases, so future soc driver
15 Signed-off-by: Hongzhou Yang <hongzhou.yang@mediatek.com>
17 drivers/pinctrl/mediatek/pinctrl-mt8173.c | 201 +++++++++++++------------
18 drivers/pinctrl/mediatek/pinctrl-mtk-common.c | 82 +++++++---
19 drivers/pinctrl/mediatek/pinctrl-mtk-common.h | 31 +++-
20 3 files changed, 198 insertions(+), 116 deletions(-)
22 --- a/drivers/pinctrl/mediatek/pinctrl-mt8173.c
23 +++ b/drivers/pinctrl/mediatek/pinctrl-mt8173.c
25 #include <linux/of_device.h>
26 #include <linux/pinctrl/pinctrl.h>
27 #include <linux/regmap.h>
28 +#include <linux/pinctrl/pinconf-generic.h>
29 #include <dt-bindings/pinctrl/mt65xx.h>
31 #include "pinctrl-mtk-common.h"
34 #define DRV_BASE 0xb00
37 - * struct mtk_pin_ies_smt_set - For special pins' ies and smt setting.
38 - * @start: The start pin number of those special pins.
39 - * @end: The end pin number of those special pins.
40 - * @offset: The offset of special setting register.
41 - * @bit: The bit of special setting register.
43 -struct mtk_pin_ies_smt_set {
46 - unsigned int offset;
50 -#define MTK_PIN_IES_SMT_SET(_start, _end, _offset, _bit) \
55 - .offset = _offset, \
58 static const struct mtk_pin_spec_pupd_set_samereg mt8173_spec_pupd[] = {
59 MTK_PIN_PUPD_SPEC_SR(119, 0xe00, 2, 1, 0), /* KROW0 */
60 MTK_PIN_PUPD_SPEC_SR(120, 0xe00, 6, 5, 4), /* KROW1 */
61 @@ -97,80 +76,114 @@ static int mt8173_spec_pull_set(struct r
62 ARRAY_SIZE(mt8173_spec_pupd), pin, align, isup, r1r0);
65 -static const struct mtk_pin_ies_smt_set mt8173_ies_smt_set[] = {
66 - MTK_PIN_IES_SMT_SET(0, 4, 0x930, 1),
67 - MTK_PIN_IES_SMT_SET(5, 9, 0x930, 2),
68 - MTK_PIN_IES_SMT_SET(10, 13, 0x930, 10),
69 - MTK_PIN_IES_SMT_SET(14, 15, 0x940, 10),
70 - MTK_PIN_IES_SMT_SET(16, 16, 0x930, 0),
71 - MTK_PIN_IES_SMT_SET(17, 17, 0x950, 2),
72 - MTK_PIN_IES_SMT_SET(18, 21, 0x940, 3),
73 - MTK_PIN_IES_SMT_SET(29, 32, 0x930, 3),
74 - MTK_PIN_IES_SMT_SET(33, 33, 0x930, 4),
75 - MTK_PIN_IES_SMT_SET(34, 36, 0x930, 5),
76 - MTK_PIN_IES_SMT_SET(37, 38, 0x930, 6),
77 - MTK_PIN_IES_SMT_SET(39, 39, 0x930, 7),
78 - MTK_PIN_IES_SMT_SET(40, 41, 0x930, 9),
79 - MTK_PIN_IES_SMT_SET(42, 42, 0x940, 0),
80 - MTK_PIN_IES_SMT_SET(43, 44, 0x930, 11),
81 - MTK_PIN_IES_SMT_SET(45, 46, 0x930, 12),
82 - MTK_PIN_IES_SMT_SET(57, 64, 0xc20, 13),
83 - MTK_PIN_IES_SMT_SET(65, 65, 0xc10, 13),
84 - MTK_PIN_IES_SMT_SET(66, 66, 0xc00, 13),
85 - MTK_PIN_IES_SMT_SET(67, 67, 0xd10, 13),
86 - MTK_PIN_IES_SMT_SET(68, 68, 0xd00, 13),
87 - MTK_PIN_IES_SMT_SET(69, 72, 0x940, 14),
88 - MTK_PIN_IES_SMT_SET(73, 76, 0xc60, 13),
89 - MTK_PIN_IES_SMT_SET(77, 77, 0xc40, 13),
90 - MTK_PIN_IES_SMT_SET(78, 78, 0xc50, 13),
91 - MTK_PIN_IES_SMT_SET(79, 82, 0x940, 15),
92 - MTK_PIN_IES_SMT_SET(83, 83, 0x950, 0),
93 - MTK_PIN_IES_SMT_SET(84, 85, 0x950, 1),
94 - MTK_PIN_IES_SMT_SET(86, 91, 0x950, 2),
95 - MTK_PIN_IES_SMT_SET(92, 92, 0x930, 13),
96 - MTK_PIN_IES_SMT_SET(93, 95, 0x930, 14),
97 - MTK_PIN_IES_SMT_SET(96, 99, 0x930, 15),
98 - MTK_PIN_IES_SMT_SET(100, 103, 0xca0, 13),
99 - MTK_PIN_IES_SMT_SET(104, 104, 0xc80, 13),
100 - MTK_PIN_IES_SMT_SET(105, 105, 0xc90, 13),
101 - MTK_PIN_IES_SMT_SET(106, 107, 0x940, 4),
102 - MTK_PIN_IES_SMT_SET(108, 112, 0x940, 1),
103 - MTK_PIN_IES_SMT_SET(113, 116, 0x940, 2),
104 - MTK_PIN_IES_SMT_SET(117, 118, 0x940, 5),
105 - MTK_PIN_IES_SMT_SET(119, 124, 0x940, 6),
106 - MTK_PIN_IES_SMT_SET(125, 126, 0x940, 7),
107 - MTK_PIN_IES_SMT_SET(127, 127, 0x940, 0),
108 - MTK_PIN_IES_SMT_SET(128, 128, 0x950, 8),
109 - MTK_PIN_IES_SMT_SET(129, 130, 0x950, 9),
110 - MTK_PIN_IES_SMT_SET(131, 132, 0x950, 8),
111 - MTK_PIN_IES_SMT_SET(133, 134, 0x910, 8)
112 +static const struct mtk_pin_ies_smt_set mt8173_smt_set[] = {
113 + MTK_PIN_IES_SMT_SPEC(0, 4, 0x930, 1),
114 + MTK_PIN_IES_SMT_SPEC(5, 9, 0x930, 2),
115 + MTK_PIN_IES_SMT_SPEC(10, 13, 0x930, 10),
116 + MTK_PIN_IES_SMT_SPEC(14, 15, 0x940, 10),
117 + MTK_PIN_IES_SMT_SPEC(16, 16, 0x930, 0),
118 + MTK_PIN_IES_SMT_SPEC(17, 17, 0x950, 2),
119 + MTK_PIN_IES_SMT_SPEC(18, 21, 0x940, 3),
120 + MTK_PIN_IES_SMT_SPEC(29, 32, 0x930, 3),
121 + MTK_PIN_IES_SMT_SPEC(33, 33, 0x930, 4),
122 + MTK_PIN_IES_SMT_SPEC(34, 36, 0x930, 5),
123 + MTK_PIN_IES_SMT_SPEC(37, 38, 0x930, 6),
124 + MTK_PIN_IES_SMT_SPEC(39, 39, 0x930, 7),
125 + MTK_PIN_IES_SMT_SPEC(40, 41, 0x930, 9),
126 + MTK_PIN_IES_SMT_SPEC(42, 42, 0x940, 0),
127 + MTK_PIN_IES_SMT_SPEC(43, 44, 0x930, 11),
128 + MTK_PIN_IES_SMT_SPEC(45, 46, 0x930, 12),
129 + MTK_PIN_IES_SMT_SPEC(57, 64, 0xc20, 13),
130 + MTK_PIN_IES_SMT_SPEC(65, 65, 0xc10, 13),
131 + MTK_PIN_IES_SMT_SPEC(66, 66, 0xc00, 13),
132 + MTK_PIN_IES_SMT_SPEC(67, 67, 0xd10, 13),
133 + MTK_PIN_IES_SMT_SPEC(68, 68, 0xd00, 13),
134 + MTK_PIN_IES_SMT_SPEC(69, 72, 0x940, 14),
135 + MTK_PIN_IES_SMT_SPEC(73, 76, 0xc60, 13),
136 + MTK_PIN_IES_SMT_SPEC(77, 77, 0xc40, 13),
137 + MTK_PIN_IES_SMT_SPEC(78, 78, 0xc50, 13),
138 + MTK_PIN_IES_SMT_SPEC(79, 82, 0x940, 15),
139 + MTK_PIN_IES_SMT_SPEC(83, 83, 0x950, 0),
140 + MTK_PIN_IES_SMT_SPEC(84, 85, 0x950, 1),
141 + MTK_PIN_IES_SMT_SPEC(86, 91, 0x950, 2),
142 + MTK_PIN_IES_SMT_SPEC(92, 92, 0x930, 13),
143 + MTK_PIN_IES_SMT_SPEC(93, 95, 0x930, 14),
144 + MTK_PIN_IES_SMT_SPEC(96, 99, 0x930, 15),
145 + MTK_PIN_IES_SMT_SPEC(100, 103, 0xca0, 13),
146 + MTK_PIN_IES_SMT_SPEC(104, 104, 0xc80, 13),
147 + MTK_PIN_IES_SMT_SPEC(105, 105, 0xc90, 13),
148 + MTK_PIN_IES_SMT_SPEC(106, 107, 0x940, 4),
149 + MTK_PIN_IES_SMT_SPEC(108, 112, 0x940, 1),
150 + MTK_PIN_IES_SMT_SPEC(113, 116, 0x940, 2),
151 + MTK_PIN_IES_SMT_SPEC(117, 118, 0x940, 5),
152 + MTK_PIN_IES_SMT_SPEC(119, 124, 0x940, 6),
153 + MTK_PIN_IES_SMT_SPEC(125, 126, 0x940, 7),
154 + MTK_PIN_IES_SMT_SPEC(127, 127, 0x940, 0),
155 + MTK_PIN_IES_SMT_SPEC(128, 128, 0x950, 8),
156 + MTK_PIN_IES_SMT_SPEC(129, 130, 0x950, 9),
157 + MTK_PIN_IES_SMT_SPEC(131, 132, 0x950, 8),
158 + MTK_PIN_IES_SMT_SPEC(133, 134, 0x910, 8)
161 -static int spec_ies_smt_set(struct regmap *regmap, unsigned int pin,
162 - unsigned char align, int value)
164 - unsigned int i, reg_addr, bit;
166 +static const struct mtk_pin_ies_smt_set mt8173_ies_set[] = {
167 + MTK_PIN_IES_SMT_SPEC(0, 4, 0x900, 1),
168 + MTK_PIN_IES_SMT_SPEC(5, 9, 0x900, 2),
169 + MTK_PIN_IES_SMT_SPEC(10, 13, 0x900, 10),
170 + MTK_PIN_IES_SMT_SPEC(14, 15, 0x910, 10),
171 + MTK_PIN_IES_SMT_SPEC(16, 16, 0x900, 0),
172 + MTK_PIN_IES_SMT_SPEC(17, 17, 0x920, 2),
173 + MTK_PIN_IES_SMT_SPEC(18, 21, 0x910, 3),
174 + MTK_PIN_IES_SMT_SPEC(29, 32, 0x900, 3),
175 + MTK_PIN_IES_SMT_SPEC(33, 33, 0x900, 4),
176 + MTK_PIN_IES_SMT_SPEC(34, 36, 0x900, 5),
177 + MTK_PIN_IES_SMT_SPEC(37, 38, 0x900, 6),
178 + MTK_PIN_IES_SMT_SPEC(39, 39, 0x900, 7),
179 + MTK_PIN_IES_SMT_SPEC(40, 41, 0x900, 9),
180 + MTK_PIN_IES_SMT_SPEC(42, 42, 0x910, 0),
181 + MTK_PIN_IES_SMT_SPEC(43, 44, 0x900, 11),
182 + MTK_PIN_IES_SMT_SPEC(45, 46, 0x900, 12),
183 + MTK_PIN_IES_SMT_SPEC(57, 64, 0xc20, 14),
184 + MTK_PIN_IES_SMT_SPEC(65, 65, 0xc10, 14),
185 + MTK_PIN_IES_SMT_SPEC(66, 66, 0xc00, 14),
186 + MTK_PIN_IES_SMT_SPEC(67, 67, 0xd10, 14),
187 + MTK_PIN_IES_SMT_SPEC(68, 68, 0xd00, 14),
188 + MTK_PIN_IES_SMT_SPEC(69, 72, 0x910, 14),
189 + MTK_PIN_IES_SMT_SPEC(73, 76, 0xc60, 14),
190 + MTK_PIN_IES_SMT_SPEC(77, 77, 0xc40, 14),
191 + MTK_PIN_IES_SMT_SPEC(78, 78, 0xc50, 14),
192 + MTK_PIN_IES_SMT_SPEC(79, 82, 0x910, 15),
193 + MTK_PIN_IES_SMT_SPEC(83, 83, 0x920, 0),
194 + MTK_PIN_IES_SMT_SPEC(84, 85, 0x920, 1),
195 + MTK_PIN_IES_SMT_SPEC(86, 91, 0x920, 2),
196 + MTK_PIN_IES_SMT_SPEC(92, 92, 0x900, 13),
197 + MTK_PIN_IES_SMT_SPEC(93, 95, 0x900, 14),
198 + MTK_PIN_IES_SMT_SPEC(96, 99, 0x900, 15),
199 + MTK_PIN_IES_SMT_SPEC(100, 103, 0xca0, 14),
200 + MTK_PIN_IES_SMT_SPEC(104, 104, 0xc80, 14),
201 + MTK_PIN_IES_SMT_SPEC(105, 105, 0xc90, 14),
202 + MTK_PIN_IES_SMT_SPEC(106, 107, 0x91, 4),
203 + MTK_PIN_IES_SMT_SPEC(108, 112, 0x910, 1),
204 + MTK_PIN_IES_SMT_SPEC(113, 116, 0x910, 2),
205 + MTK_PIN_IES_SMT_SPEC(117, 118, 0x910, 5),
206 + MTK_PIN_IES_SMT_SPEC(119, 124, 0x910, 6),
207 + MTK_PIN_IES_SMT_SPEC(125, 126, 0x910, 7),
208 + MTK_PIN_IES_SMT_SPEC(127, 127, 0x910, 0),
209 + MTK_PIN_IES_SMT_SPEC(128, 128, 0x920, 8),
210 + MTK_PIN_IES_SMT_SPEC(129, 130, 0x920, 9),
211 + MTK_PIN_IES_SMT_SPEC(131, 132, 0x920, 8),
212 + MTK_PIN_IES_SMT_SPEC(133, 134, 0x910, 8)
215 - for (i = 0; i < ARRAY_SIZE(mt8173_ies_smt_set); i++) {
216 - if (pin >= mt8173_ies_smt_set[i].start &&
217 - pin <= mt8173_ies_smt_set[i].end) {
227 - reg_addr = mt8173_ies_smt_set[i].offset + align;
229 - reg_addr = mt8173_ies_smt_set[i].offset + (align << 1);
231 - bit = BIT(mt8173_ies_smt_set[i].bit);
232 - regmap_write(regmap, reg_addr, bit);
234 +static int mt8173_ies_smt_set(struct regmap *regmap, unsigned int pin,
235 + unsigned char align, int value, enum pin_config_param arg)
237 + if (arg == PIN_CONFIG_INPUT_ENABLE)
238 + return mtk_pconf_spec_set_ies_smt_range(regmap, mt8173_ies_set,
239 + ARRAY_SIZE(mt8173_ies_set), pin, align, value);
240 + else if (arg == PIN_CONFIG_INPUT_SCHMITT_ENABLE)
241 + return mtk_pconf_spec_set_ies_smt_range(regmap, mt8173_smt_set,
242 + ARRAY_SIZE(mt8173_smt_set), pin, align, value);
246 static const struct mtk_drv_group_desc mt8173_drv_grp[] = {
247 @@ -307,7 +320,7 @@ static const struct mtk_pinctrl_devdata
248 .pin_drv_grp = mt8173_pin_drv,
249 .n_pin_drv_grps = ARRAY_SIZE(mt8173_pin_drv),
250 .spec_pull_set = mt8173_spec_pull_set,
251 - .spec_ies_smt_set = spec_ies_smt_set,
252 + .spec_ies_smt_set = mt8173_ies_smt_set,
253 .dir_offset = 0x0000,
254 .pullen_offset = 0x0100,
255 .pullsel_offset = 0x0200,
256 --- a/drivers/pinctrl/mediatek/pinctrl-mtk-common.c
257 +++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common.c
258 @@ -107,28 +107,38 @@ static void mtk_gpio_set(struct gpio_chi
259 regmap_write(mtk_get_regmap(pctl, offset), reg_addr, bit);
262 -static void mtk_pconf_set_ies_smt(struct mtk_pinctrl *pctl, unsigned pin,
263 - int value, enum pin_config_param param)
264 +static int mtk_pconf_set_ies_smt(struct mtk_pinctrl *pctl, unsigned pin,
265 + int value, enum pin_config_param arg)
267 unsigned int reg_addr, offset;
272 + * Due to some soc are not support ies/smt config, add this special
273 + * control to handle it.
275 + if (!pctl->devdata->spec_ies_smt_set &&
276 + pctl->devdata->ies_offset == MTK_PINCTRL_NOT_SUPPORT &&
277 + arg == PIN_CONFIG_INPUT_ENABLE)
280 + if (!pctl->devdata->spec_ies_smt_set &&
281 + pctl->devdata->smt_offset == MTK_PINCTRL_NOT_SUPPORT &&
282 + arg == PIN_CONFIG_INPUT_SCHMITT_ENABLE)
286 * Due to some pins are irregular, their input enable and smt
287 - * control register are discontinuous, but they are mapping together.
288 - * So we need this special handle.
289 + * control register are discontinuous, so we need this special handle.
291 if (pctl->devdata->spec_ies_smt_set) {
292 - ret = pctl->devdata->spec_ies_smt_set(mtk_get_regmap(pctl, pin),
293 - pin, pctl->devdata->port_align, value);
296 + return pctl->devdata->spec_ies_smt_set(mtk_get_regmap(pctl, pin),
297 + pin, pctl->devdata->port_align, value, arg);
300 bit = BIT(pin & 0xf);
302 - if (param == PIN_CONFIG_INPUT_ENABLE)
303 + if (arg == PIN_CONFIG_INPUT_ENABLE)
304 offset = pctl->devdata->ies_offset;
306 offset = pctl->devdata->smt_offset;
307 @@ -139,6 +149,33 @@ static void mtk_pconf_set_ies_smt(struct
308 reg_addr = CLR_ADDR(mtk_get_port(pctl, pin) + offset, pctl);
310 regmap_write(mtk_get_regmap(pctl, pin), reg_addr, bit);
314 +int mtk_pconf_spec_set_ies_smt_range(struct regmap *regmap,
315 + const struct mtk_pin_ies_smt_set *ies_smt_infos, unsigned int info_num,
316 + unsigned int pin, unsigned char align, int value)
318 + unsigned int i, reg_addr, bit;
320 + for (i = 0; i < info_num; i++) {
321 + if (pin >= ies_smt_infos[i].start &&
322 + pin <= ies_smt_infos[i].end) {
331 + reg_addr = ies_smt_infos[i].offset + align;
333 + reg_addr = ies_smt_infos[i].offset + (align << 1);
335 + bit = BIT(ies_smt_infos[i].bit);
336 + regmap_write(regmap, reg_addr, bit);
340 static const struct mtk_pin_drv_grp *mtk_find_pin_drv_grp_by_pin(
341 @@ -295,36 +332,37 @@ static int mtk_pconf_parse_conf(struct p
342 unsigned int pin, enum pin_config_param param,
343 enum pin_config_param arg)
346 struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
349 case PIN_CONFIG_BIAS_DISABLE:
350 - mtk_pconf_set_pull_select(pctl, pin, false, false, arg);
351 + ret = mtk_pconf_set_pull_select(pctl, pin, false, false, arg);
353 case PIN_CONFIG_BIAS_PULL_UP:
354 - mtk_pconf_set_pull_select(pctl, pin, true, true, arg);
355 + ret = mtk_pconf_set_pull_select(pctl, pin, true, true, arg);
357 case PIN_CONFIG_BIAS_PULL_DOWN:
358 - mtk_pconf_set_pull_select(pctl, pin, true, false, arg);
359 + ret = mtk_pconf_set_pull_select(pctl, pin, true, false, arg);
361 case PIN_CONFIG_INPUT_ENABLE:
362 - mtk_pconf_set_ies_smt(pctl, pin, arg, param);
363 + ret = mtk_pconf_set_ies_smt(pctl, pin, arg, param);
365 case PIN_CONFIG_OUTPUT:
366 mtk_gpio_set(pctl->chip, pin, arg);
367 - mtk_pmx_gpio_set_direction(pctldev, NULL, pin, false);
368 + ret = mtk_pmx_gpio_set_direction(pctldev, NULL, pin, false);
370 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
371 - mtk_pconf_set_ies_smt(pctl, pin, arg, param);
372 + ret = mtk_pconf_set_ies_smt(pctl, pin, arg, param);
374 case PIN_CONFIG_DRIVE_STRENGTH:
375 - mtk_pconf_set_driving(pctl, pin, arg);
376 + ret = mtk_pconf_set_driving(pctl, pin, arg);
387 static int mtk_pconf_group_get(struct pinctrl_dev *pctldev,
388 @@ -343,12 +381,14 @@ static int mtk_pconf_group_set(struct pi
390 struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
391 struct mtk_pinctrl_group *g = &pctl->groups[group];
395 for (i = 0; i < num_configs; i++) {
396 - mtk_pconf_parse_conf(pctldev, g->pin,
397 + ret = mtk_pconf_parse_conf(pctldev, g->pin,
398 pinconf_to_config_param(configs[i]),
399 pinconf_to_config_argument(configs[i]));
403 g->config = configs[i];
405 --- a/drivers/pinctrl/mediatek/pinctrl-mtk-common.h
406 +++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common.h
409 #include <linux/pinctrl/pinctrl.h>
410 #include <linux/regmap.h>
411 +#include <linux/pinctrl/pinconf-generic.h>
413 #define NO_EINT_SUPPORT 255
414 #define MT_EDGE_SENSITIVE 0
416 #define EINT_DBNC_RST_BIT (0x1 << 1)
417 #define EINT_DBNC_SET_EN (0x1 << 0)
419 +#define MTK_PINCTRL_NOT_SUPPORT (0xffff)
421 struct mtk_desc_function {
423 unsigned char muxval;
424 @@ -143,6 +146,28 @@ struct mtk_pin_spec_pupd_set_samereg {
429 + * struct mtk_pin_ies_set - For special pins' ies and smt setting.
430 + * @start: The start pin number of those special pins.
431 + * @end: The end pin number of those special pins.
432 + * @offset: The offset of special setting register.
433 + * @bit: The bit of special setting register.
435 +struct mtk_pin_ies_smt_set {
436 + unsigned short start;
437 + unsigned short end;
438 + unsigned short offset;
442 +#define MTK_PIN_IES_SMT_SPEC(_start, _end, _offset, _bit) \
447 + .offset = _offset, \
450 struct mtk_eint_offsets {
453 @@ -208,7 +233,7 @@ struct mtk_pinctrl_devdata {
454 int (*spec_pull_set)(struct regmap *reg, unsigned int pin,
455 unsigned char align, bool isup, unsigned int arg);
456 int (*spec_ies_smt_set)(struct regmap *reg, unsigned int pin,
457 - unsigned char align, int value);
458 + unsigned char align, int value, enum pin_config_param arg);
459 unsigned int dir_offset;
460 unsigned int ies_offset;
461 unsigned int smt_offset;
462 @@ -251,4 +276,8 @@ int mtk_pctrl_spec_pull_set_samereg(stru
463 unsigned int info_num, unsigned int pin,
464 unsigned char align, bool isup, unsigned int r1r0);
466 +int mtk_pconf_spec_set_ies_smt_range(struct regmap *regmap,
467 + const struct mtk_pin_ies_smt_set *ies_smt_infos, unsigned int info_num,
468 + unsigned int pin, unsigned char align, int value);
470 #endif /* __PINCTRL_MTK_COMMON_H */