target/linux/mediatek/patches/0031-I2C-mediatek-Add-driver-for-MediaTek-MT8173-I2C-cont.patch

   1 From 5f33206ebe4fb4a2cc8634f29c3e3c9bc01e3416 Mon Sep 17 00:00:00 2001
   2 From: Eddie Huang <eddie.huang@mediatek.com>
   3 Date: Wed, 6 May 2015 16:37:07 +0800
   4 Subject: [PATCH 31/76] I2C: mediatek: Add driver for MediaTek MT8173 I2C
   5  controller
   6
   7 Add mediatek MT8173 I2C controller driver. Compare to I2C controller
   8 of earlier mediatek SoC, MT8173 fix write-then-read limitation, and
   9 also increase message size to 64kb.
  10
  11 Signed-off-by: Xudong Chen <xudong.chen@mediatek.com>
  12 Signed-off-by: Liguo Zhang <liguo.zhang@mediatek.com>
  13 Signed-off-by: Eddie Huang <eddie.huang@mediatek.com>
  14 ---
  15  drivers/i2c/busses/i2c-mt65xx.c |  104 ++++++++++++++++++++++++++++-----------
  16  1 file changed, 76 insertions(+), 28 deletions(-)
  17
  18 diff --git a/drivers/i2c/busses/i2c-mt65xx.c b/drivers/i2c/busses/i2c-mt65xx.c
  19 index faecf7e..c501421 100644
  20 --- a/drivers/i2c/busses/i2c-mt65xx.c
  21 +++ b/drivers/i2c/busses/i2c-mt65xx.c
  22 @@ -33,10 +33,13 @@
  23  #include <linux/clk.h>
  24  #include <linux/completion.h>
  25
  26 +#define I2C_RS_TRANSFER                        (1 << 4)
  27  #define I2C_HS_NACKERR                 (1 << 2)
  28  #define I2C_ACKERR                     (1 << 1)
  29  #define I2C_TRANSAC_COMP               (1 << 0)
  30  #define I2C_TRANSAC_START              (1 << 0)
  31 +#define I2C_RS_MUL_CNFG                        (1 << 15)
  32 +#define I2C_RS_MUL_TRIG                        (1 << 14)
  33  #define I2C_TIMING_STEP_DIV_MASK       (0x3f << 0)
  34  #define I2C_TIMING_SAMPLE_COUNT_MASK   (0x7 << 0)
  35  #define I2C_TIMING_SAMPLE_DIV_MASK     (0x7 << 8)
  36 @@ -67,6 +70,9 @@
  37  #define MAX_MSG_NUM_MT6577             1
  38  #define MAX_DMA_TRANS_SIZE_MT6577      255
  39  #define MAX_WRRD_TRANS_SIZE_MT6577     31
  40 +#define MAX_MSG_NUM_MT8173             65535
  41 +#define MAX_DMA_TRANS_SIZE_MT8173      65535
  42 +#define MAX_WRRD_TRANS_SIZE_MT8173     65535
  43  #define MAX_SAMPLE_CNT_DIV             8
  44  #define MAX_STEP_CNT_DIV               64
  45  #define MAX_HS_STEP_CNT_DIV            8
  46 @@ -139,6 +145,7 @@ struct mtk_i2c_compatible {
  47         const struct i2c_adapter_quirks *quirks;
  48         unsigned char pmic_i2c;
  49         unsigned char dcm;
  50 +       unsigned char auto_restart;
  51  };
  52
  53  struct mtk_i2c {
  54 @@ -172,21 +179,39 @@ static const struct i2c_adapter_quirks mt6577_i2c_quirks = {
  55         .max_comb_2nd_msg_len = MAX_WRRD_TRANS_SIZE_MT6577,
  56  };
  57
  58 +static const struct i2c_adapter_quirks mt8173_i2c_quirks = {
  59 +       .max_num_msgs = MAX_MSG_NUM_MT8173,
  60 +       .max_write_len = MAX_DMA_TRANS_SIZE_MT8173,
  61 +       .max_read_len = MAX_DMA_TRANS_SIZE_MT8173,
  62 +       .max_comb_1st_msg_len = MAX_DMA_TRANS_SIZE_MT8173,
  63 +       .max_comb_2nd_msg_len = MAX_WRRD_TRANS_SIZE_MT8173,
  64 +};
  65 +
  66  static const struct mtk_i2c_compatible mt6577_compat = {
  67         .quirks = &mt6577_i2c_quirks,
  68         .pmic_i2c = 0,
  69         .dcm = 1,
  70 +       .auto_restart = 0,
  71  };
  72
  73  static const struct mtk_i2c_compatible mt6589_compat = {
  74         .quirks = &mt6577_i2c_quirks,
  75         .pmic_i2c = 1,
  76         .dcm = 0,
  77 +       .auto_restart = 0,
  78 +};
  79 +
  80 +static const struct mtk_i2c_compatible mt8173_compat = {
  81 +       .quirks = &mt8173_i2c_quirks,
  82 +       .pmic_i2c = 0,
  83 +       .dcm = 1,
  84 +       .auto_restart = 1,
  85  };
  86
  87  static const struct of_device_id mtk_i2c_of_match[] = {
  88         { .compatible = "mediatek,mt6577-i2c", .data = (void *)&mt6577_compat },
  89         { .compatible = "mediatek,mt6589-i2c", .data = (void *)&mt6589_compat },
  90 +       { .compatible = "mediatek,mt8173-i2c", .data = (void *)&mt8173_compat },
  91         {}
  92  };
  93  MODULE_DEVICE_TABLE(of, mtk_i2c_of_match);
  94 @@ -343,9 +368,11 @@ static int mtk_i2c_set_speed(struct mtk_i2c *i2c, unsigned int clk_src_in_hz)
  95         return 0;
  96  }
  97
  98 -static int mtk_i2c_do_transfer(struct mtk_i2c *i2c, struct i2c_msg *msgs)
  99 +static int mtk_i2c_do_transfer(struct mtk_i2c *i2c, struct i2c_msg *msgs,
 100 +                                       int num, int left_num)
 101  {
 102         u16 addr_reg;
 103 +       u16 start_reg;
 104         u16 control_reg;
 105         dma_addr_t rpaddr = 0;
 106         dma_addr_t wpaddr = 0;
 107 @@ -361,6 +388,8 @@ static int mtk_i2c_do_transfer(struct mtk_i2c *i2c, struct i2c_msg *msgs)
 108                 control_reg |= I2C_CONTROL_RS;
 109         if (i2c->op == I2C_MASTER_WRRD)
 110                 control_reg |= I2C_CONTROL_DIR_CHANGE | I2C_CONTROL_RS;
 111 +       if (left_num >= 1)
 112 +               control_reg |= I2C_CONTROL_RS;
 113         mtk_i2c_writew(control_reg, i2c, OFFSET_CONTROL);
 114
 115         /* set start condition */
 116 @@ -375,13 +404,13 @@ static int mtk_i2c_do_transfer(struct mtk_i2c *i2c, struct i2c_msg *msgs)
 117         mtk_i2c_writew(addr_reg, i2c, OFFSET_SLAVE_ADDR);
 118
 119         /* Clear interrupt status */
 120 -       mtk_i2c_writew(I2C_HS_NACKERR | I2C_ACKERR | I2C_TRANSAC_COMP,
 121 -               i2c, OFFSET_INTR_STAT);
 122 +       mtk_i2c_writew(I2C_RS_TRANSFER | I2C_HS_NACKERR | I2C_ACKERR
 123 +                       | I2C_TRANSAC_COMP, i2c, OFFSET_INTR_STAT);
 124         mtk_i2c_writew(I2C_FIFO_ADDR_CLR, i2c, OFFSET_FIFO_ADDR_CLR);
 125
 126         /* Enable interrupt */
 127 -       mtk_i2c_writew(I2C_HS_NACKERR | I2C_ACKERR | I2C_TRANSAC_COMP,
 128 -               i2c, OFFSET_INTR_MASK);
 129 +       mtk_i2c_writew(I2C_RS_TRANSFER | I2C_HS_NACKERR | I2C_ACKERR
 130 +                       | I2C_TRANSAC_COMP, i2c, OFFSET_INTR_MASK);
 131
 132         /* Set transfer and transaction len */
 133         if (i2c->op == I2C_MASTER_WRRD) {
 134 @@ -390,7 +419,7 @@ static int mtk_i2c_do_transfer(struct mtk_i2c *i2c, struct i2c_msg *msgs)
 135                 mtk_i2c_writew(I2C_WRRD_TRANAC_VALUE, i2c, OFFSET_TRANSAC_LEN);
 136         } else {
 137                 mtk_i2c_writew(msgs->len, i2c, OFFSET_TRANSFER_LEN);
 138 -               mtk_i2c_writew(I2C_RD_TRANAC_VALUE, i2c, OFFSET_TRANSAC_LEN);
 139 +               mtk_i2c_writew(num, i2c, OFFSET_TRANSAC_LEN);
 140         }
 141
 142         /* Prepare buffer data to start transfer */
 143 @@ -436,13 +465,23 @@ static int mtk_i2c_do_transfer(struct mtk_i2c *i2c, struct i2c_msg *msgs)
 144         /* flush before sending start */
 145         mb();
 146         mtk_i2c_writel_dma(I2C_DMA_START_EN, i2c, OFFSET_EN);
 147 -       mtk_i2c_writew(I2C_TRANSAC_START, i2c, OFFSET_START);
 148 +
 149 +       if (!i2c->dev_comp->auto_restart) {
 150 +               start_reg = I2C_TRANSAC_START;
 151 +       } else {
 152 +               if (left_num >= 1)
 153 +                       start_reg = I2C_TRANSAC_START | I2C_RS_MUL_CNFG
 154 +                                       | I2C_RS_MUL_TRIG;
 155 +               else
 156 +                       start_reg = I2C_TRANSAC_START | I2C_RS_MUL_TRIG;
 157 +       }
 158 +       mtk_i2c_writew(start_reg, i2c, OFFSET_START);
 159
 160         ret = wait_for_completion_timeout(&i2c->msg_complete,
 161                                 i2c->adap.timeout);
 162
 163         /* Clear interrupt mask */
 164 -       mtk_i2c_writew(~(I2C_HS_NACKERR | I2C_ACKERR
 165 +       mtk_i2c_writew(~(I2C_RS_TRANSFER | I2C_HS_NACKERR | I2C_ACKERR
 166                         | I2C_TRANSAC_COMP), i2c, OFFSET_INTR_MASK);
 167
 168         if (i2c->op == I2C_MASTER_WR) {
 169 @@ -472,6 +511,10 @@ static int mtk_i2c_do_transfer(struct mtk_i2c *i2c, struct i2c_msg *msgs)
 170                 return -EREMOTEIO;
 171         }
 172
 173 +       if (i2c->irq_stat & I2C_RS_TRANSFER)
 174 +               dev_dbg(i2c->dev, "addr: %x, restart transfer interrupt.\n",
 175 +                               msgs->addr);
 176 +
 177         return 0;
 178  }
 179
 180 @@ -486,28 +529,33 @@ static int mtk_i2c_transfer(struct i2c_adapter *adap,
 181         if (ret)
 182                 return ret;
 183
 184 -       if (msgs->buf == NULL) {
 185 -               dev_dbg(i2c->dev, "data buffer is NULL.\n");
 186 -               ret = -EINVAL;
 187 -               goto err_exit;
 188 -       }
 189 -
 190 -       if (msgs->flags & I2C_M_RD)
 191 -               i2c->op = I2C_MASTER_RD;
 192 -       else
 193 -               i2c->op = I2C_MASTER_WR;
 194 +       while (left_num--) {
 195 +               if (msgs->buf == NULL) {
 196 +                       dev_dbg(i2c->dev, "data buffer is NULL.\n");
 197 +                       ret = -EINVAL;
 198 +                       goto err_exit;
 199 +               }
 200
 201 -       if (num > 1) {
 202 -               /* combined two messages into one transaction */
 203 -               i2c->op = I2C_MASTER_WRRD;
 204 -               left_num--;
 205 -       }
 206 +               if (msgs->flags & I2C_M_RD)
 207 +                       i2c->op = I2C_MASTER_RD;
 208 +               else
 209 +                       i2c->op = I2C_MASTER_WR;
 210 +
 211 +               if (!i2c->dev_comp->auto_restart) {
 212 +                       if (num > 1) {
 213 +                               /* combined two messages into one transaction */
 214 +                               i2c->op = I2C_MASTER_WRRD;
 215 +                               left_num--;
 216 +                       }
 217 +               }
 218
 219 -       /* always use DMA mode. */
 220 -       ret = mtk_i2c_do_transfer(i2c, msgs);
 221 -       if (ret < 0)
 222 -               goto err_exit;
 223 +               /* always use DMA mode. */
 224 +               ret = mtk_i2c_do_transfer(i2c, msgs, num, left_num);
 225 +               if (ret < 0)
 226 +                       goto err_exit;
 227
 228 +               msgs++;
 229 +       }
 230         /* the return value is number of executed messages */
 231         ret = num;
 232
 233 @@ -521,7 +569,7 @@ static irqreturn_t mtk_i2c_irq(int irqno, void *dev_id)
 234         struct mtk_i2c *i2c = dev_id;
 235
 236         i2c->irq_stat = mtk_i2c_readw(i2c, OFFSET_INTR_STAT);
 237 -       mtk_i2c_writew(I2C_HS_NACKERR | I2C_ACKERR
 238 +       mtk_i2c_writew(I2C_RS_TRANSFER | I2C_HS_NACKERR | I2C_ACKERR
 239                         | I2C_TRANSAC_COMP, i2c, OFFSET_INTR_STAT);
 240
 241         complete(&i2c->msg_complete);
 242 --
 243 1.7.10.4
 244