1 From 047222cfefe97ef8706f03117bc8deada4cb4ddd Mon Sep 17 00:00:00 2001
2 From: Leilk Liu <leilk.liu@mediatek.com>
3 Date: Fri, 8 May 2015 16:55:42 +0800
4 Subject: [PATCH 26/76] spi: mediatek: Add spi bus for Mediatek MT8173
6 This patch adds basic spi bus for MT8173.
8 Signed-off-by: Leilk Liu <leilk.liu@mediatek.com>
10 drivers/spi/Kconfig | 10 +
11 drivers/spi/Makefile | 1 +
12 drivers/spi/spi-mt65xx.c | 622 ++++++++++++++++++++++++++++++++++++++++++++++
13 3 files changed, 633 insertions(+)
14 create mode 100644 drivers/spi/spi-mt65xx.c
16 --- a/drivers/spi/Kconfig
17 +++ b/drivers/spi/Kconfig
18 @@ -334,6 +334,16 @@ config SPI_MESON_SPIFC
19 This enables master mode support for the SPIFC (SPI flash
20 controller) available in Amlogic Meson SoCs.
23 + tristate "MediaTek SPI controller"
24 + depends on ARCH_MEDIATEK || COMPILE_TEST
27 + This selects the MediaTek(R) SPI bus driver.
28 + If you want to use MediaTek(R) SPI interface,
29 + say Y or M here.If you are not sure, say N.
30 + SPI drivers for Mediatek mt65XX series ARM SoCs.
33 tristate "OpenCores tiny SPI"
35 --- a/drivers/spi/Makefile
36 +++ b/drivers/spi/Makefile
37 @@ -49,6 +49,7 @@ obj-$(CONFIG_SPI_MESON_SPIFC) += spi-me
38 obj-$(CONFIG_SPI_MPC512x_PSC) += spi-mpc512x-psc.o
39 obj-$(CONFIG_SPI_MPC52xx_PSC) += spi-mpc52xx-psc.o
40 obj-$(CONFIG_SPI_MPC52xx) += spi-mpc52xx.o
41 +obj-$(CONFIG_SPI_MT65XX) += spi-mt65xx.o
42 obj-$(CONFIG_SPI_MXS) += spi-mxs.o
43 obj-$(CONFIG_SPI_NUC900) += spi-nuc900.o
44 obj-$(CONFIG_SPI_OC_TINY) += spi-oc-tiny.o
46 +++ b/drivers/spi/spi-mt65xx.c
49 + * Copyright (c) 2015 MediaTek Inc.
50 + * Author: Leilk Liu <leilk.liu@mediatek.com>
52 + * This program is free software; you can redistribute it and/or modify
53 + * it under the terms of the GNU General Public License version 2 as
54 + * published by the Free Software Foundation.
56 + * This program is distributed in the hope that it will be useful,
57 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
58 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
59 + * GNU General Public License for more details.
62 +#include <linux/init.h>
63 +#include <linux/module.h>
64 +#include <linux/device.h>
65 +#include <linux/ioport.h>
66 +#include <linux/errno.h>
67 +#include <linux/spi/spi.h>
68 +#include <linux/workqueue.h>
69 +#include <linux/dma-mapping.h>
70 +#include <linux/platform_device.h>
71 +#include <linux/interrupt.h>
72 +#include <linux/irqreturn.h>
73 +#include <linux/types.h>
74 +#include <linux/delay.h>
75 +#include <linux/clk.h>
76 +#include <linux/err.h>
77 +#include <linux/io.h>
78 +#include <linux/sched.h>
79 +#include <linux/of.h>
80 +#include <linux/of_irq.h>
81 +#include <linux/of_address.h>
82 +#include <linux/kernel.h>
83 +#include <linux/spi/spi_bitbang.h>
84 +#include <linux/gpio.h>
85 +#include <linux/module.h>
86 +#include <linux/of_gpio.h>
88 +#define SPI_CFG0_REG 0x0000
89 +#define SPI_CFG1_REG 0x0004
90 +#define SPI_TX_SRC_REG 0x0008
91 +#define SPI_RX_DST_REG 0x000c
92 +#define SPI_CMD_REG 0x0018
93 +#define SPI_STATUS0_REG 0x001c
94 +#define SPI_PAD_SEL_REG 0x0024
96 +#define SPI_CFG0_SCK_HIGH_OFFSET 0
97 +#define SPI_CFG0_SCK_LOW_OFFSET 8
98 +#define SPI_CFG0_CS_HOLD_OFFSET 16
99 +#define SPI_CFG0_CS_SETUP_OFFSET 24
101 +#define SPI_CFG0_SCK_HIGH_MASK 0xff
102 +#define SPI_CFG0_SCK_LOW_MASK 0xff00
103 +#define SPI_CFG0_CS_HOLD_MASK 0xff0000
104 +#define SPI_CFG0_CS_SETUP_MASK 0xff000000
106 +#define SPI_CFG1_CS_IDLE_OFFSET 0
107 +#define SPI_CFG1_PACKET_LOOP_OFFSET 8
108 +#define SPI_CFG1_PACKET_LENGTH_OFFSET 16
109 +#define SPI_CFG1_GET_TICK_DLY_OFFSET 30
111 +#define SPI_CFG1_CS_IDLE_MASK 0xff
112 +#define SPI_CFG1_PACKET_LOOP_MASK 0xff00
113 +#define SPI_CFG1_PACKET_LENGTH_MASK 0x3ff0000
114 +#define SPI_CFG1_GET_TICK_DLY_MASK 0xc0000000
116 +#define SPI_CMD_ACT_OFFSET 0
117 +#define SPI_CMD_RESUME_OFFSET 1
118 +#define SPI_CMD_RST_OFFSET 2
119 +#define SPI_CMD_PAUSE_EN_OFFSET 4
120 +#define SPI_CMD_DEASSERT_OFFSET 5
121 +#define SPI_CMD_CPHA_OFFSET 8
122 +#define SPI_CMD_CPOL_OFFSET 9
123 +#define SPI_CMD_RX_DMA_OFFSET 10
124 +#define SPI_CMD_TX_DMA_OFFSET 11
125 +#define SPI_CMD_TXMSBF_OFFSET 12
126 +#define SPI_CMD_RXMSBF_OFFSET 13
127 +#define SPI_CMD_RX_ENDIAN_OFFSET 14
128 +#define SPI_CMD_TX_ENDIAN_OFFSET 15
129 +#define SPI_CMD_FINISH_IE_OFFSET 16
130 +#define SPI_CMD_PAUSE_IE_OFFSET 17
132 +#define SPI_CMD_RESUME_MASK 0x2
133 +#define SPI_CMD_RST_MASK 0x4
134 +#define SPI_CMD_PAUSE_EN_MASK 0x10
135 +#define SPI_CMD_DEASSERT_MASK 0x20
136 +#define SPI_CMD_CPHA_MASK 0x100
137 +#define SPI_CMD_CPOL_MASK 0x200
138 +#define SPI_CMD_RX_DMA_MASK 0x400
139 +#define SPI_CMD_TX_DMA_MASK 0x800
140 +#define SPI_CMD_TXMSBF_MASK 0x1000
141 +#define SPI_CMD_RXMSBF_MASK 0x2000
142 +#define SPI_CMD_RX_ENDIAN_MASK 0x4000
143 +#define SPI_CMD_TX_ENDIAN_MASK 0x8000
144 +#define SPI_CMD_FINISH_IE_MASK 0x10000
146 +#define COMPAT_MT6589 (0x1 << 0)
147 +#define COMPAT_MT8173 (0x1 << 1)
149 +#define MT8173_MAX_PAD_SEL 3
152 +#define INPROGRESS 1
155 +#define PACKET_SIZE 1024
157 +struct mtk_chip_config {
173 +struct mtk_spi_ddata {
174 + struct spi_bitbang bitbang;
175 + void __iomem *base;
178 + u32 platform_compat;
184 + u32 tx_len, rx_len;
185 + struct completion done;
189 + * A piece of default chip info unless the platform
192 +static const struct mtk_chip_config mtk_default_chip_info = {
208 +static const struct of_device_id mtk_spi_of_match[] = {
209 + { .compatible = "mediatek,mt6589-spi", .data = (void *)COMPAT_MT6589},
210 + { .compatible = "mediatek,mt8173-spi", .data = (void *)COMPAT_MT8173},
213 +MODULE_DEVICE_TABLE(of, mtk_spi_of_match);
215 +static void mtk_spi_reset(struct mtk_spi_ddata *mdata)
219 + /*set the software reset bit in SPI_CMD_REG.*/
220 + reg_val = readl(mdata->base + SPI_CMD_REG);
221 + reg_val &= ~SPI_CMD_RST_MASK;
222 + reg_val |= 1 << SPI_CMD_RST_OFFSET;
223 + writel(reg_val, mdata->base + SPI_CMD_REG);
224 + reg_val = readl(mdata->base + SPI_CMD_REG);
225 + reg_val &= ~SPI_CMD_RST_MASK;
226 + writel(reg_val, mdata->base + SPI_CMD_REG);
229 +static void mtk_set_pause_bit(struct mtk_spi_ddata *mdata)
233 + reg_val = readl(mdata->base + SPI_CMD_REG);
234 + reg_val |= 1 << SPI_CMD_PAUSE_EN_OFFSET;
235 + reg_val |= 1 << SPI_CMD_PAUSE_IE_OFFSET;
236 + writel(reg_val, mdata->base + SPI_CMD_REG);
239 +static void mtk_clear_pause_bit(struct mtk_spi_ddata *mdata)
243 + reg_val = readl(mdata->base + SPI_CMD_REG);
244 + reg_val &= ~SPI_CMD_PAUSE_EN_MASK;
245 + writel(reg_val, mdata->base + SPI_CMD_REG);
248 +static int mtk_spi_config(struct mtk_spi_ddata *mdata,
249 + struct mtk_chip_config *chip_config)
253 + /* set the timing */
254 + reg_val = readl(mdata->base + SPI_CFG0_REG);
255 + reg_val &= ~(SPI_CFG0_SCK_HIGH_MASK | SPI_CFG0_SCK_LOW_MASK);
256 + reg_val &= ~(SPI_CFG0_CS_HOLD_MASK | SPI_CFG0_CS_SETUP_MASK);
257 + reg_val |= ((chip_config->high_time - 1) << SPI_CFG0_SCK_HIGH_OFFSET);
258 + reg_val |= ((chip_config->low_time - 1) << SPI_CFG0_SCK_LOW_OFFSET);
259 + reg_val |= ((chip_config->holdtime - 1) << SPI_CFG0_CS_HOLD_OFFSET);
260 + reg_val |= ((chip_config->setuptime - 1) << SPI_CFG0_CS_SETUP_OFFSET);
261 + writel(reg_val, mdata->base + SPI_CFG0_REG);
263 + reg_val = readl(mdata->base + SPI_CFG1_REG);
264 + reg_val &= ~SPI_CFG1_CS_IDLE_MASK;
265 + reg_val |= ((chip_config->cs_idletime - 1) << SPI_CFG1_CS_IDLE_OFFSET);
266 + reg_val &= ~SPI_CFG1_GET_TICK_DLY_MASK;
267 + reg_val |= ((chip_config->tckdly) << SPI_CFG1_GET_TICK_DLY_OFFSET);
268 + writel(reg_val, mdata->base + SPI_CFG1_REG);
270 + /* set the mlsbx and mlsbtx */
271 + reg_val = readl(mdata->base + SPI_CMD_REG);
272 + reg_val &= ~(SPI_CMD_TX_ENDIAN_MASK | SPI_CMD_RX_ENDIAN_MASK);
273 + reg_val &= ~(SPI_CMD_TXMSBF_MASK | SPI_CMD_RXMSBF_MASK);
274 + reg_val |= (chip_config->tx_mlsb << SPI_CMD_TXMSBF_OFFSET);
275 + reg_val |= (chip_config->rx_mlsb << SPI_CMD_RXMSBF_OFFSET);
276 + reg_val |= (chip_config->tx_endian << SPI_CMD_TX_ENDIAN_OFFSET);
277 + reg_val |= (chip_config->rx_endian << SPI_CMD_RX_ENDIAN_OFFSET);
278 + writel(reg_val, mdata->base + SPI_CMD_REG);
280 + /* set finish and pause interrupt always enable */
281 + reg_val = readl(mdata->base + SPI_CMD_REG);
282 + reg_val &= ~SPI_CMD_FINISH_IE_MASK;
283 + reg_val |= (chip_config->finish_intr << SPI_CMD_FINISH_IE_OFFSET);
284 + writel(reg_val, mdata->base + SPI_CMD_REG);
286 + reg_val = readl(mdata->base + SPI_CMD_REG);
287 + reg_val |= 1 << SPI_CMD_TX_DMA_OFFSET;
288 + reg_val |= 1 << SPI_CMD_RX_DMA_OFFSET;
289 + writel(reg_val, mdata->base + SPI_CMD_REG);
291 + /* set deassert mode */
292 + reg_val = readl(mdata->base + SPI_CMD_REG);
293 + reg_val &= ~SPI_CMD_DEASSERT_MASK;
294 + reg_val |= (chip_config->deassert << SPI_CMD_DEASSERT_OFFSET);
295 + writel(reg_val, mdata->base + SPI_CMD_REG);
298 + if (mdata->platform_compat & COMPAT_MT8173)
299 + writel(mdata->pad_sel, mdata->base + SPI_PAD_SEL_REG);
304 +static int mtk_spi_setup_transfer(struct spi_device *spi,
305 + struct spi_transfer *t)
308 + struct spi_master *master = spi->master;
309 + struct mtk_spi_ddata *mdata = spi_master_get_devdata(master);
310 + struct spi_message *m = master->cur_msg;
311 + struct mtk_chip_config *chip_config;
313 + u8 cpha = spi->mode & SPI_CPHA ? 1 : 0;
314 + u8 cpol = spi->mode & SPI_CPOL ? 1 : 0;
316 + reg_val = readl(mdata->base + SPI_CMD_REG);
317 + reg_val &= ~(SPI_CMD_CPHA_MASK | SPI_CMD_CPOL_MASK);
318 + reg_val |= (cpha << SPI_CMD_CPHA_OFFSET);
319 + reg_val |= (cpol << SPI_CMD_CPOL_OFFSET);
320 + writel(reg_val, mdata->base + SPI_CMD_REG);
322 + if (t->cs_change) {
323 + if (!(list_is_last(&t->transfer_list, &m->transfers)))
324 + mdata->state = IDLE;
326 + mdata->state = IDLE;
327 + mtk_spi_reset(mdata);
330 + chip_config = (struct mtk_chip_config *)spi->controller_data;
331 + if (!chip_config) {
332 + chip_config = (void *)&mtk_default_chip_info;
333 + spi->controller_data = chip_config;
334 + mdata->state = IDLE;
337 + mtk_spi_config(mdata, chip_config);
342 +static void mtk_spi_chipselect(struct spi_device *spi, int is_on)
344 + struct mtk_spi_ddata *mdata = spi_master_get_devdata(spi->master);
347 + case BITBANG_CS_ACTIVE:
348 + mtk_set_pause_bit(mdata);
350 + case BITBANG_CS_INACTIVE:
351 + mtk_clear_pause_bit(mdata);
356 +static void mtk_spi_start_transfer(struct mtk_spi_ddata *mdata)
360 + reg_val = readl(mdata->base + SPI_CMD_REG);
361 + reg_val |= 1 << SPI_CMD_ACT_OFFSET;
362 + writel(reg_val, mdata->base + SPI_CMD_REG);
365 +static void mtk_spi_resume_transfer(struct mtk_spi_ddata *mdata)
369 + reg_val = readl(mdata->base + SPI_CMD_REG);
370 + reg_val &= ~SPI_CMD_RESUME_MASK;
371 + reg_val |= 1 << SPI_CMD_RESUME_OFFSET;
372 + writel(reg_val, mdata->base + SPI_CMD_REG);
375 +static int mtk_spi_setup_packet(struct mtk_spi_ddata *mdata,
376 + struct spi_transfer *xfer)
378 + struct device *dev = &mdata->bitbang.master->dev;
379 + u32 packet_size, packet_loop, reg_val;
381 + packet_size = min_t(unsigned, xfer->len, PACKET_SIZE);
383 + /* mtk hw has the restriction that xfer len must be a multiple of 1024,
384 + * when it is greater than 1024bytes.
386 + if (xfer->len % packet_size) {
387 + dev_err(dev, "ERROR!The lens must be a multiple of %d, your len %d\n",
388 + PACKET_SIZE, xfer->len);
392 + packet_loop = xfer->len / packet_size;
394 + reg_val = readl(mdata->base + SPI_CFG1_REG);
395 + reg_val &= ~(SPI_CFG1_PACKET_LENGTH_MASK + SPI_CFG1_PACKET_LOOP_MASK);
396 + reg_val |= (packet_size - 1) << SPI_CFG1_PACKET_LENGTH_OFFSET;
397 + reg_val |= (packet_loop - 1) << SPI_CFG1_PACKET_LOOP_OFFSET;
398 + writel(reg_val, mdata->base + SPI_CFG1_REG);
403 +static int mtk_spi_txrx_bufs(struct spi_device *spi, struct spi_transfer *xfer)
405 + struct spi_master *master = spi->master;
406 + struct mtk_spi_ddata *mdata = spi_master_get_devdata(master);
407 + struct device *dev = &mdata->bitbang.master->dev;
410 + /* mtk spi hw tx/rx have 4bytes aligned restriction,
411 + * so kmalloc tx/rx buffer to workaround here.
413 + mdata->tx_buf = NULL;
414 + mdata->rx_buf = NULL;
415 + if (xfer->tx_buf) {
416 + mdata->tx_buf = kmalloc(xfer->len, GFP_KERNEL);
417 + if (!mdata->tx_buf) {
418 + dev_err(dev, "malloc tx_buf failed.\n");
422 + memcpy((void *)mdata->tx_buf, xfer->tx_buf, xfer->len);
424 + if (xfer->rx_buf) {
425 + mdata->rx_buf = kmalloc(xfer->len, GFP_KERNEL);
426 + if (!mdata->rx_buf) {
427 + dev_err(dev, "malloc rx_buf failed.\n");
433 + reinit_completion(&mdata->done);
435 + xfer->tx_dma = DMA_ERROR_CODE;
436 + xfer->rx_dma = DMA_ERROR_CODE;
437 + if (xfer->tx_buf) {
438 + xfer->tx_dma = dma_map_single(dev, (void *)mdata->tx_buf,
439 + xfer->len, DMA_TO_DEVICE);
440 + if (dma_mapping_error(dev, xfer->tx_dma)) {
441 + dev_err(dev, "dma mapping tx_buf error.\n");
446 + if (xfer->rx_buf) {
447 + xfer->rx_dma = dma_map_single(dev, mdata->rx_buf,
448 + xfer->len, DMA_FROM_DEVICE);
449 + if (dma_mapping_error(dev, xfer->rx_dma)) {
451 + dma_unmap_single(dev, xfer->tx_dma,
452 + xfer->len, DMA_TO_DEVICE);
453 + dev_err(dev, "dma mapping rx_buf error.\n");
459 + ret = mtk_spi_setup_packet(mdata, xfer);
463 + /* Here is mt8173 HW issue: RX must enable TX, then TX transfer
464 + * dummy data; TX don't need to enable RX. so enable TX dma for
465 + * RX to workaround.
467 + cmd = readl(mdata->base + SPI_CMD_REG);
468 + if (xfer->tx_buf || (mdata->platform_compat & COMPAT_MT8173))
469 + cmd |= 1 << SPI_CMD_TX_DMA_OFFSET;
471 + cmd |= 1 << SPI_CMD_RX_DMA_OFFSET;
472 + writel(cmd, mdata->base + SPI_CMD_REG);
474 + /* set up the DMA bus address */
475 + if (xfer->tx_dma != DMA_ERROR_CODE)
476 + writel(cpu_to_le32(xfer->tx_dma), mdata->base + SPI_TX_SRC_REG);
477 + if (xfer->rx_dma != DMA_ERROR_CODE)
478 + writel(cpu_to_le32(xfer->rx_dma), mdata->base + SPI_RX_DST_REG);
480 + if (mdata->state == IDLE)
481 + mtk_spi_start_transfer(mdata);
482 + else if (mdata->state == PAUSED)
483 + mtk_spi_resume_transfer(mdata);
485 + mdata->state = INPROGRESS;
487 + wait_for_completion(&mdata->done);
489 + if (xfer->tx_dma != DMA_ERROR_CODE) {
490 + dma_unmap_single(dev, xfer->tx_dma, xfer->len, DMA_TO_DEVICE);
491 + xfer->tx_dma = DMA_ERROR_CODE;
493 + if (xfer->rx_dma != DMA_ERROR_CODE) {
494 + dma_unmap_single(dev, xfer->rx_dma, xfer->len, DMA_FROM_DEVICE);
495 + xfer->rx_dma = DMA_ERROR_CODE;
498 + /* spi disable dma */
499 + cmd = readl(mdata->base + SPI_CMD_REG);
500 + cmd &= ~SPI_CMD_TX_DMA_MASK;
501 + cmd &= ~SPI_CMD_RX_DMA_MASK;
502 + writel(cmd, mdata->base + SPI_CMD_REG);
505 + memcpy(xfer->rx_buf, mdata->rx_buf, xfer->len);
510 + kfree(mdata->tx_buf);
511 + kfree(mdata->rx_buf);
515 +static irqreturn_t mtk_spi_interrupt(int irq, void *dev_id)
517 + struct mtk_spi_ddata *mdata = dev_id;
520 + reg_val = readl(mdata->base + SPI_STATUS0_REG);
522 + mdata->state = PAUSED;
524 + mdata->state = IDLE;
525 + complete(&mdata->done);
527 + return IRQ_HANDLED;
530 +static unsigned long mtk_get_device_prop(struct platform_device *pdev)
532 + const struct of_device_id *match;
534 + match = of_match_node(mtk_spi_of_match, pdev->dev.of_node);
535 + return (unsigned long)match->data;
538 +static int mtk_spi_probe(struct platform_device *pdev)
540 + struct spi_master *master;
541 + struct mtk_spi_ddata *mdata;
542 + struct resource *res;
545 + master = spi_alloc_master(&pdev->dev, sizeof(struct mtk_spi_ddata));
547 + dev_err(&pdev->dev, "failed to alloc spi master\n");
551 + platform_set_drvdata(pdev, master);
553 + master->dev.of_node = pdev->dev.of_node;
554 + master->bus_num = pdev->id;
555 + master->num_chipselect = 1;
556 + master->mode_bits = SPI_CPOL | SPI_CPHA;
558 + mdata = spi_master_get_devdata(master);
560 + mdata->bitbang.master = master;
561 + mdata->bitbang.chipselect = mtk_spi_chipselect;
562 + mdata->bitbang.setup_transfer = mtk_spi_setup_transfer;
563 + mdata->bitbang.txrx_bufs = mtk_spi_txrx_bufs;
564 + mdata->platform_compat = mtk_get_device_prop(pdev);
566 + if (mdata->platform_compat & COMPAT_MT8173) {
567 + ret = of_property_read_u32(pdev->dev.of_node, "pad-select",
570 + dev_err(&pdev->dev, "failed to read pad select: %d\n",
575 + if (mdata->pad_sel > MT8173_MAX_PAD_SEL) {
576 + dev_err(&pdev->dev, "wrong pad-select: %u\n",
582 + init_completion(&mdata->done);
584 + mdata->clk = devm_clk_get(&pdev->dev, "main");
585 + if (IS_ERR(mdata->clk)) {
586 + ret = PTR_ERR(mdata->clk);
587 + dev_err(&pdev->dev, "failed to get clock: %d\n", ret);
591 + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
594 + dev_err(&pdev->dev, "failed to determine base address\n");
598 + mdata->base = devm_ioremap_resource(&pdev->dev, res);
599 + if (IS_ERR(mdata->base)) {
600 + ret = PTR_ERR(mdata->base);
604 + ret = platform_get_irq(pdev, 0);
606 + dev_err(&pdev->dev, "failed to get irq (%d)\n", ret);
612 + if (!pdev->dev.dma_mask)
613 + pdev->dev.dma_mask = &pdev->dev.coherent_dma_mask;
615 + mdata->bitbang.master->dev.dma_mask = pdev->dev.dma_mask;
617 + ret = clk_prepare_enable(mdata->clk);
619 + dev_err(&pdev->dev, "failed to enable clock (%d)\n", ret);
623 + ret = devm_request_irq(&pdev->dev, mdata->irq, mtk_spi_interrupt,
624 + IRQF_TRIGGER_NONE, dev_name(&pdev->dev), mdata);
626 + dev_err(&pdev->dev, "failed to register irq (%d)\n", ret);
627 + goto err_disable_clk;
630 + ret = spi_bitbang_start(&mdata->bitbang);
632 + dev_err(&pdev->dev, "spi_bitbang_start failed (%d)\n", ret);
634 + clk_disable_unprepare(mdata->clk);
636 + spi_master_put(master);
642 +static int mtk_spi_remove(struct platform_device *pdev)
644 + struct spi_master *master = platform_get_drvdata(pdev);
645 + struct mtk_spi_ddata *mdata = spi_master_get_devdata(master);
647 + spi_bitbang_stop(&mdata->bitbang);
648 + mtk_spi_reset(mdata);
649 + clk_disable_unprepare(mdata->clk);
650 + spi_master_put(master);
655 +struct platform_driver mtk_spi_driver = {
658 + .of_match_table = mtk_spi_of_match,
660 + .probe = mtk_spi_probe,
661 + .remove = mtk_spi_remove,
664 +module_platform_driver(mtk_spi_driver);
666 +MODULE_DESCRIPTION("MTK SPI Controller driver");
667 +MODULE_AUTHOR("Leilk Liu <leilk.liu@mediatek.com>");
668 +MODULE_LICENSE("GPL v2");
669 +MODULE_ALIAS("platform: mtk_spi");