1 From d6d7a7dc1b7db2e3d496bf67b30abc894edbc4bd Mon Sep 17 00:00:00 2001
2 From: Sascha Hauer <s.hauer@pengutronix.de>
3 Date: Tue, 9 Jun 2015 10:46:59 +0200
4 Subject: [PATCH 06/76] soc: mediatek: Add infracfg misc driver support
6 This adds support for some miscellaneous bits of the infracfg controller.
7 The mtk_infracfg_set/clear_bus_protection functions are necessary for
8 the scpsys power domain driver to handle the bus protection bits which
9 are contained in the infacfg register space.
11 Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
13 drivers/soc/mediatek/Kconfig | 9 ++++
14 drivers/soc/mediatek/Makefile | 1 +
15 drivers/soc/mediatek/mtk-infracfg.c | 91 +++++++++++++++++++++++++++++++++
16 include/linux/soc/mediatek/infracfg.h | 26 ++++++++++
17 4 files changed, 127 insertions(+)
18 create mode 100644 drivers/soc/mediatek/mtk-infracfg.c
19 create mode 100644 include/linux/soc/mediatek/infracfg.h
21 --- a/drivers/soc/mediatek/Kconfig
22 +++ b/drivers/soc/mediatek/Kconfig
25 # MediaTek SoC drivers
28 + bool "MediaTek INFRACFG Support"
29 + depends on ARCH_MEDIATEK
32 + Say yes here to add support for the MediaTek INFRACFG controller. The
33 + INFRACFG controller contains various infrastructure registers not
34 + directly associated to any device.
37 tristate "MediaTek PMIC Wrapper Support"
38 depends on ARCH_MEDIATEK
39 --- a/drivers/soc/mediatek/Makefile
40 +++ b/drivers/soc/mediatek/Makefile
42 +obj-$(CONFIG_MTK_INFRACFG) += mtk-infracfg.o
43 obj-$(CONFIG_MTK_PMIC_WRAP) += mtk-pmic-wrap.o
45 +++ b/drivers/soc/mediatek/mtk-infracfg.c
48 + * Copyright (c) 2015 Pengutronix, Sascha Hauer <kernel@pengutronix.de>
50 + * This program is free software; you can redistribute it and/or modify
51 + * it under the terms of the GNU General Public License version 2 as
52 + * published by the Free Software Foundation.
54 + * This program is distributed in the hope that it will be useful,
55 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
56 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
57 + * GNU General Public License for more details.
60 +#include <linux/export.h>
61 +#include <linux/jiffies.h>
62 +#include <linux/regmap.h>
63 +#include <linux/soc/mediatek/infracfg.h>
64 +#include <asm/processor.h>
66 +#define INFRA_TOPAXI_PROTECTEN 0x0220
67 +#define INFRA_TOPAXI_PROTECTSTA1 0x0228
70 + * mtk_infracfg_set_bus_protection - enable bus protection
71 + * @regmap: The infracfg regmap
72 + * @mask: The mask containing the protection bits to be enabled.
74 + * This function enables the bus protection bits for disabled power
75 + * domains so that the system does not hanf when some unit accesses the
76 + * bus while in power down.
78 +int mtk_infracfg_set_bus_protection(struct regmap *infracfg, u32 mask)
80 + unsigned long expired;
84 + regmap_update_bits(infracfg, INFRA_TOPAXI_PROTECTEN, mask, mask);
86 + expired = jiffies + HZ;
89 + ret = regmap_read(infracfg, INFRA_TOPAXI_PROTECTSTA1, &val);
93 + if ((val & mask) == mask)
97 + if (time_after(jiffies, expired))
105 + * mtk_infracfg_clear_bus_protection - disable bus protection
106 + * @regmap: The infracfg regmap
107 + * @mask: The mask containing the protection bits to be disabled.
109 + * This function disables the bus protection bits previously enabled with
110 + * mtk_infracfg_set_bus_protection.
112 +int mtk_infracfg_clear_bus_protection(struct regmap *infracfg, u32 mask)
114 + unsigned long expired;
117 + regmap_update_bits(infracfg, INFRA_TOPAXI_PROTECTEN, mask, 0);
119 + expired = jiffies + HZ;
124 + ret = regmap_read(infracfg, INFRA_TOPAXI_PROTECTSTA1, &val);
132 + if (time_after(jiffies, expired))
139 +++ b/include/linux/soc/mediatek/infracfg.h
141 +#ifndef __SOC_MEDIATEK_INFRACFG_H
142 +#define __SOC_MEDIATEK_INFRACFG_H
144 +#define MT8173_TOP_AXI_PROT_EN_MCI_M2 BIT(0)
145 +#define MT8173_TOP_AXI_PROT_EN_MM_M0 BIT(1)
146 +#define MT8173_TOP_AXI_PROT_EN_MM_M1 BIT(2)
147 +#define MT8173_TOP_AXI_PROT_EN_MMAPB_S BIT(6)
148 +#define MT8173_TOP_AXI_PROT_EN_L2C_M2 BIT(9)
149 +#define MT8173_TOP_AXI_PROT_EN_L2SS_SMI BIT(11)
150 +#define MT8173_TOP_AXI_PROT_EN_L2SS_ADD BIT(12)
151 +#define MT8173_TOP_AXI_PROT_EN_CCI_M2 BIT(13)
152 +#define MT8173_TOP_AXI_PROT_EN_MFG_S BIT(14)
153 +#define MT8173_TOP_AXI_PROT_EN_PERI_M0 BIT(15)
154 +#define MT8173_TOP_AXI_PROT_EN_PERI_M1 BIT(16)
155 +#define MT8173_TOP_AXI_PROT_EN_DEBUGSYS BIT(17)
156 +#define MT8173_TOP_AXI_PROT_EN_CQ_DMA BIT(18)
157 +#define MT8173_TOP_AXI_PROT_EN_GCPU BIT(19)
158 +#define MT8173_TOP_AXI_PROT_EN_IOMMU BIT(20)
159 +#define MT8173_TOP_AXI_PROT_EN_MFG_M0 BIT(21)
160 +#define MT8173_TOP_AXI_PROT_EN_MFG_M1 BIT(22)
161 +#define MT8173_TOP_AXI_PROT_EN_MFG_SNOOP_OUT BIT(23)
163 +int mtk_infracfg_set_bus_protection(struct regmap *infracfg, u32 mask);
164 +int mtk_infracfg_clear_bus_protection(struct regmap *infracfg, u32 mask);
166 +#endif /* __SOC_MEDIATEK_INFRACFG_H */