target/linux/linux-2.4/patches/ar7/000-ar7_support.patch

   1 diff -urN kernel-base/arch/mips/ar7/ar7/ar7_jump.S kernel-tmp2/arch/mips/ar7/ar7/ar7_jump.S
   2 --- kernel-base/arch/mips/ar7/ar7/ar7_jump.S    1970-01-01 01:00:00.000000000 +0100
   3 +++ kernel-tmp2/arch/mips/ar7/ar7/ar7_jump.S    2005-07-10 06:40:39.582267168 +0200
   4 @@ -0,0 +1,89 @@
   5 +/*
   6 + * $Id$
   7 + * Copyright (C) $Date$  $Author$
   8 + *
   9 + * This program is free software; you can redistribute it and/or modify
  10 + * it under the terms of the GNU General Public License as published by
  11 + * the Free Software Foundation; either version 2 of the License, or
  12 + * (at your option) any later version.
  13 + *
  14 + * This program is distributed in the hope that it will be useful,
  15 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17 + * GNU General Public License for more details.
  18 + *
  19 + * You should have received a copy of the GNU General Public License
  20 + * along with this program; if not, write to the Free Software
  21 + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
  22 + *
  23 + */
  24 +
  25 +#include <linux/config.h>
  26 +#include <linux/threads.h>
  27 +
  28 +#include <asm/asm.h>
  29 +#include <asm/cacheops.h>
  30 +#include <asm/current.h>
  31 +#include <asm/offset.h>
  32 +#include <asm/processor.h>
  33 +#include <asm/regdef.h>
  34 +#include <asm/cachectl.h>
  35 +#include <asm/mipsregs.h>
  36 +#include <asm/stackframe.h>
  37 +
  38 +.text
  39 +
  40 +.set noreorder
  41 +.set noat
  42 +
  43 +/* TLB Miss Vector */
  44 +
  45 +LEAF(jump_tlb_miss)
  46 +       .set mips2
  47 +       lui     k0,0x9400
  48 +       ori     k0,0
  49 +       jr      k0
  50 +       nop
  51 +END(jump_tlb_miss)
  52 +
  53 +       /* Unused TLB Miss Vector */
  54 +
  55 +LEAF(jump_tlb_miss_unused)
  56 +       .set mips2
  57 +       lui     k0,0x9400
  58 +       ori     k0,0x80
  59 +       jr      k0
  60 +       nop
  61 +END(jump_tlb_miss_unused)
  62 +
  63 +       /* Cache Error Vector */
  64 +
  65 +LEAF(jump_cache_error)
  66 +       .set mips2
  67 +       lui     k0,0x9400
  68 +       ori     k0,0x100
  69 +       jr      k0
  70 +       nop
  71 +END(jump_cache_error)
  72 +
  73 +       /* General Exception */
  74 +
  75 +LEAF(jump_general_exception)
  76 +       .set mips2
  77 +       lui     k0,0x9400
  78 +       ori     k0,0x180
  79 +       jr      k0
  80 +       nop
  81 +END(jump_general_exception)
  82 +
  83 +       /* Dedicated Interrupt */
  84 +
  85 +LEAF(jump_dedicated_interrupt)
  86 +       .set mips2
  87 +       lui     k0,0x9400
  88 +       ori     k0,0x200
  89 +       jr      k0
  90 +       nop
  91 +END(jump_dedicated_interrupt)
  92 +
  93 +       .set at
  94 diff -urN kernel-base/arch/mips/ar7/ar7/ar7_paging.c kernel-tmp2/arch/mips/ar7/ar7/ar7_paging.c
  95 --- kernel-base/arch/mips/ar7/ar7/ar7_paging.c  1970-01-01 01:00:00.000000000 +0100
  96 +++ kernel-tmp2/arch/mips/ar7/ar7/ar7_paging.c  2005-07-10 07:08:33.725758672 +0200
  97 @@ -0,0 +1,314 @@
  98 +/*
  99 + *  -*- linux-c -*-
 100 + * This file is subject to the terms and conditions of the GNU General Public
 101 + * License.  See the file "COPYING" in the main directory of this archive
 102 + * for more details.
 103 + *
 104 + * Copyright (C) 2002 by Jeff Harrell (jharrell@ti.com)
 105 + * Copyright (C) 2002 Texas Instruments, Inc.
 106 + *
 107 + */
 108 +
 109 +/*
 110 + * This file takes care of the "memory hole" issue that exists with the standard
 111 + * linux kernel and the TI Avalanche ASIC.  The Avalanche ASIC requires an offset
 112 + * of 0x14000000 due to the ASIC's memory map constraints.  This file corrects the
 113 + * paging tables so that the only reflect valid memory (i.e. > 0x14000000)
 114 + *
 115 + *  -JAH
 116 + */
 117 +#include <linux/config.h>
 118 +#include <linux/signal.h>
 119 +#include <linux/sched.h>
 120 +#include <linux/kernel.h>
 121 +#include <linux/errno.h>
 122 +#include <linux/string.h>
 123 +#include <linux/types.h>
 124 +#include <linux/ptrace.h>
 125 +#include <linux/mman.h>
 126 +#include <linux/mm.h>
 127 +#include <linux/swap.h>
 128 +#include <linux/smp.h>
 129 +#include <linux/init.h>
 130 +#ifdef CONFIG_BLK_DEV_INITRD
 131 +#include <linux/blk.h>
 132 +#endif /* CONFIG_BLK_DEV_INITRD */
 133 +#include <linux/highmem.h>
 134 +#include <linux/bootmem.h>
 135 +
 136 +#include <asm/processor.h>
 137 +#include <asm/system.h>
 138 +#include <asm/uaccess.h>
 139 +#include <asm/pgtable.h>
 140 +#include <asm/pgalloc.h>
 141 +#include <asm/mmu_context.h>
 142 +#include <asm/io.h>
 143 +#include <asm/tlb.h>
 144 +#include <asm/cpu.h>
 145 +
 146 +#define __MEMORY_START CONFIG_AR7_MEMORY
 147 +
 148 +#ifdef CONFIG_DISCONTIGMEM
 149 +pg_data_t discontig_page_data[NR_NODES];
 150 +bootmem_data_t discontig_node_bdata[NR_NODES];
 151 +#endif
 152 +
 153 +static unsigned long totalram_pages;
 154 +/* static unsigned long totalhigh_pages; */
 155 +
 156 +#define START_PFN (NODE_DATA(0)->bdata->node_boot_start >> PAGE_SHIFT)
 157 +#define MAX_LOW_PFN (NODE_DATA(0)->bdata->node_low_pfn)
 158 +
 159 +#define PFN_UP(x)  (((x) + PAGE_SIZE - 1) >> PAGE_SHIFT)
 160 +#define PFN_DOWN(x)        ((x) >> PAGE_SHIFT)
 161 +#define PFN_PHYS(x)        ((x) << PAGE_SHIFT)
 162 +
 163 +unsigned long bootmap_size;
 164 +
 165 +extern char *prom_getenv(char *envname);
 166 +
 167 +/*
 168 + * We have upto 8 empty zeroed pages so we can map one of the right colour
 169 + * when needed.  This is necessary only on R4000 / R4400 SC and MC versions
 170 + * where we have to avoid VCED / VECI exceptions for good performance at
 171 + * any price.  Since page is never written to after the initialization we
 172 + * don't have to care about aliases on other CPUs.
 173 + */
 174 +
 175 +static inline unsigned long setup_zero_pages(void)
 176 +{
 177 +       unsigned long order, size;
 178 +       struct page *page;
 179 +       if(current_cpu_data.options & MIPS_CPU_VCE)
 180 +               order = 3;
 181 +       else
 182 +               order = 0;
 183 +
 184 +       empty_zero_page = __get_free_pages(GFP_KERNEL, order);
 185 +
 186 +       if (!empty_zero_page)
 187 +               panic("Oh boy, that early out of memory?");
 188 +
 189 +       page = virt_to_page(empty_zero_page);
 190 +
 191 +       while (page < virt_to_page(empty_zero_page + (PAGE_SIZE << order))) {
 192 +               set_bit(PG_reserved, &page->flags);
 193 +               set_page_count(page, 0);
 194 +               page++;
 195 +       }
 196 +
 197 +       size = PAGE_SIZE << order;
 198 +       zero_page_mask = (size - 1) & PAGE_MASK;
 199 +       memset((void *)empty_zero_page, 0, size);
 200 +
 201 +       return 1UL << order;
 202 +}
 203 +
 204 +/*
 205 + * paging_init() sets up the page tables
 206 + *
 207 + * This routines also unmaps the page at virtual kernel address 0, so
 208 + * that we can trap those pesky NULL-reference errors in the kernel.
 209 + */
 210 +void __init paging_init(void)
 211 +{
 212 +       unsigned long zones_size[MAX_NR_ZONES] = {0, 0, 0};
 213 +       unsigned long low, start_pfn;
 214 +
 215 +       /* Initialize the entire pgd.  */
 216 +       pgd_init((unsigned long)swapper_pg_dir);
 217 +       pgd_init((unsigned long)swapper_pg_dir + PAGE_SIZE / 2);
 218 +
 219 +
 220 +       start_pfn = START_PFN;
 221 +       // max_dma = virt_to_phys((char *)MAX_DMA_ADDRESS) >> PAGE_SHIFT;
 222 +       low = MAX_LOW_PFN;
 223 +
 224 +       /* Avalanche DMA-able memory 0x14000000+memsize */
 225 +
 226 +       zones_size[ZONE_DMA] = low - start_pfn;
 227 +
 228 +       free_area_init_node(0, NODE_DATA(0), 0, zones_size, __MEMORY_START, 0);
 229 +
 230 +#ifdef CONFIG_DISCONTIGMEM
 231 +       zones_size[ZONE_DMA] = __MEMORY_SIZE_2ND >> PAGE_SHIFT;
 232 +       zones_size[ZONE_NORMAL] = 0;
 233 +       free_area_init_node(1, NODE_DATA(1), 0, zones_size, __MEMORY_START_2ND, 0);
 234 +#endif /* CONFIG_DISCONTIGMEM */
 235 +
 236 +}
 237 +
 238 +extern char _ftext, _etext, _fdata, _edata, _end;
 239 +extern char __init_begin, __init_end;
 240 +
 241 +void __init mem_init(void)
 242 +{
 243 +       int codesize, reservedpages, datasize, initsize;
 244 +       int tmp;
 245 +
 246 +       max_mapnr = num_physpages = MAX_LOW_PFN - START_PFN;
 247 +       high_memory = (void *)__va(MAX_LOW_PFN * PAGE_SIZE);
 248 +
 249 +       /* free up the memory associated with Adam2 -
 250 +        * that is the, after the first page that is
 251 +        * reserved all the way up to the start of the kernel
 252 +        */
 253 +       free_bootmem_node(NODE_DATA(0), (__MEMORY_START+PAGE_SIZE),
 254 +                       (__pa(&_ftext))-(__MEMORY_START+PAGE_SIZE) );
 255 +
 256 +       /* this will put all low memory onto the freelists */
 257 +       totalram_pages += free_all_bootmem_node(NODE_DATA(0));
 258 +
 259 +       /* Setup zeroed pages */
 260 +       totalram_pages -= setup_zero_pages();
 261 +
 262 +
 263 +#ifdef CONFIG_DISCONTIGMEM
 264 +       totalram_pages += free_all_bootmem_node(NODE_DATA(1));
 265 +#endif
 266 +       reservedpages = 0;
 267 +       for (tmp = 0; tmp < num_physpages; tmp++)
 268 +               /*
 269 +                * Only count reserved RAM pages
 270 +                */
 271 +               if (PageReserved(mem_map+tmp))
 272 +                       reservedpages++;
 273 +
 274 +       codesize =  (unsigned long) &_etext - (unsigned long) &_ftext;
 275 +       datasize =  (unsigned long) &_edata - (unsigned long) &_fdata;
 276 +       initsize =  (unsigned long) &__init_end - (unsigned long) &__init_begin;
 277 +
 278 +       printk("Memory: %luk/%luk available (%dk kernel code, %dk reserved, %dk data, %dk init)\n",
 279 +                       (unsigned long) nr_free_pages() << (PAGE_SHIFT-10),
 280 +                       max_mapnr << (PAGE_SHIFT-10),
 281 +                       codesize >> 10,
 282 +                       reservedpages << (PAGE_SHIFT-10),
 283 +                       datasize >> 10,
 284 +                       initsize >> 10);
 285 +
 286 +}
 287 +
 288 +/* fixes paging routines for avalanche  (utilized in /arch/mips/kernel/setup.c) */
 289 +
 290 +void avalanche_bootmem_init(void)
 291 +{
 292 +       unsigned long start_pfn, max_pfn;
 293 +       unsigned long max_low_pfn;
 294 +       unsigned int memsize,memory_end,memory_start;
 295 +       char *memsize_str;
 296 +
 297 +       memsize_str = prom_getenv("memsize");
 298 +       if (!memsize_str) {
 299 +               memsize = 0x02000000;
 300 +       } else {
 301 +               memsize = simple_strtol(memsize_str, NULL, 0);
 302 +       }
 303 +
 304 +
 305 +       memory_start = (unsigned long)PAGE_OFFSET+__MEMORY_START;
 306 +       memory_end = memory_start + memsize;
 307 +
 308 +       /*
 309 +        * Find the highest memory page fram number we have available
 310 +        */
 311 +
 312 +       max_pfn = PFN_DOWN(__pa(memory_end));
 313 +
 314 +       /*
 315 +        * Determine the low and high memory ranges
 316 +        */
 317 +
 318 +       max_low_pfn = max_pfn;
 319 +
 320 +       /*
 321 +        * Partially used pages are not usable - thus we are
 322 +        * rounding upwards:
 323 +        */
 324 +
 325 +       start_pfn = PFN_UP(__pa(&_end));
 326 +
 327 +       /*
 328 +        * Find a proper area for the bootmem bitmap. After this
 329 +        * bootstrap step all allocations (until the page allocator is
 330 +        * intact)  must be done via bootmem_alloc().
 331 +        */
 332 +
 333 +       bootmap_size = init_bootmem_node(NODE_DATA(0), start_pfn,
 334 +                       __MEMORY_START>>PAGE_SHIFT, max_low_pfn);
 335 +
 336 +
 337 +       /*
 338 +        * Register fully available low RAM pages with the bootmem allocator.
 339 +        */
 340 +
 341 +       {
 342 +               unsigned long curr_pfn, last_pfn, pages;
 343 +
 344 +               /*
 345 +                * We are rounding up the start address of usable memory:
 346 +                */
 347 +               curr_pfn = PFN_UP(__MEMORY_START);
 348 +
 349 +               /*
 350 +                * ... and at the end of the usable range downwards:
 351 +                */
 352 +               last_pfn = PFN_DOWN(__pa(memory_end));
 353 +
 354 +               if (last_pfn > max_low_pfn)
 355 +                       last_pfn = max_low_pfn;
 356 +
 357 +               pages = last_pfn - curr_pfn;
 358 +
 359 +
 360 +               free_bootmem_node(NODE_DATA(0), PFN_PHYS(curr_pfn),
 361 +                               PFN_PHYS(pages));
 362 +       }
 363 +
 364 +       /*
 365 +        * Reserve the kernel text and
 366 +        * Reserve the bootmem bitmap. We do this in two steps (first step
 367 +        * was init_bootmem()), because this catches the (definitely buggy)
 368 +        * case of us accidentally initializing the bootmem allocator with
 369 +        * an invalid RAM area.
 370 +        */
 371 +       reserve_bootmem_node(NODE_DATA(0), __MEMORY_START+PAGE_SIZE,
 372 +                       (PFN_PHYS(start_pfn)+bootmap_size+PAGE_SIZE-1)-__MEMORY_START);
 373 +
 374 +       /*
 375 +        * reserve physical page 0 - it's a special BIOS page on many boxes,
 376 +        * enabling clean reboots, SMP operation, laptop functions.
 377 +        */
 378 +       reserve_bootmem_node(NODE_DATA(0), __MEMORY_START, PAGE_SIZE);
 379 +}
 380 +
 381 +extern char __init_begin, __init_end;
 382 +
 383 +void free_initmem(void)
 384 +{
 385 +       unsigned long addr;
 386 +       //      prom_free_prom_memory ();
 387 +
 388 +       addr = (unsigned long) &__init_begin;
 389 +       while (addr < (unsigned long) &__init_end) {
 390 +               ClearPageReserved(virt_to_page(addr));
 391 +               set_page_count(virt_to_page(addr), 1);
 392 +               free_page(addr);
 393 +               totalram_pages++;
 394 +               addr += PAGE_SIZE;
 395 +       }
 396 +       printk("Freeing unused kernel memory: %dk freed\n",
 397 +                       (&__init_end - &__init_begin) >> 10);
 398 +}
 399 +
 400 +void si_meminfo(struct sysinfo *val)
 401 +{
 402 +       val->totalram = totalram_pages;
 403 +       val->sharedram = 0;
 404 +       val->freeram = nr_free_pages();
 405 +       val->bufferram = atomic_read(&buffermem_pages);
 406 +       val->totalhigh = 0;
 407 +       val->freehigh = nr_free_highpages();
 408 +       val->mem_unit = PAGE_SIZE;
 409 +
 410 +       return;
 411 +}
 412 diff -urN kernel-base/arch/mips/ar7/ar7/Makefile kernel-tmp2/arch/mips/ar7/ar7/Makefile
 413 --- kernel-base/arch/mips/ar7/ar7/Makefile      1970-01-01 01:00:00.000000000 +0100
 414 +++ kernel-tmp2/arch/mips/ar7/ar7/Makefile      2005-07-10 06:40:39.583267016 +0200
 415 @@ -0,0 +1,30 @@
 416 +# $Id$
 417 +# Copyright (C) $Date$  $Author$
 418 +#
 419 +# This program is free software; you can redistribute it and/or modify
 420 +# it under the terms of the GNU General Public License as published by
 421 +# the Free Software Foundation; either version 2 of the License, or
 422 +# (at your option) any later version.
 423 +#
 424 +# This program is distributed in the hope that it will be useful,
 425 +# but WITHOUT ANY WARRANTY; without even the implied warranty of
 426 +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 427 +# GNU General Public License for more details.
 428 +#
 429 +# You should have received a copy of the GNU General Public License
 430 +# along with this program; if not, write to the Free Software
 431 +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
 432 +
 433 +.S.s:
 434 +       $(CPP) $(AFLAGS) $< -o $*.s
 435 +
 436 +.S.o:
 437 +       $(CC) $(AFLAGS) -c $< -o $*.o
 438 +
 439 +EXTRA_CFLAGS := -DLITTLE_ENDIAN -D_LINK_KSEG0_
 440 +
 441 +O_TARGET := ar7.o
 442 +
 443 +obj-y += ar7_paging.o ar7_jump.o
 444 +
 445 +include $(TOPDIR)/Rules.make
 446 diff -urN kernel-base/arch/mips/ar7/cmdline.c kernel-tmp2/arch/mips/ar7/cmdline.c
 447 --- kernel-base/arch/mips/ar7/cmdline.c 1970-01-01 01:00:00.000000000 +0100
 448 +++ kernel-tmp2/arch/mips/ar7/cmdline.c 2005-07-10 06:40:39.584266864 +0200
 449 @@ -0,0 +1,64 @@
 450 +/*
 451 + * Carsten Langgaard, carstenl@mips.com
 452 + * Copyright (C) 1999,2000 MIPS Technologies, Inc.  All rights reserved.
 453 + *
 454 + * This program is free software; you can distribute it and/or modify it
 455 + * under the terms of the GNU General Public License (Version 2) as
 456 + * published by the Free Software Foundation.
 457 + *
 458 + * This program is distributed in the hope it will be useful, but WITHOUT
 459 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 460 + * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
 461 + * for more details.
 462 + *
 463 + * You should have received a copy of the GNU General Public License along
 464 + * with this program; if not, write to the Free Software Foundation, Inc.,
 465 + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
 466 + *
 467 + * Kernel command line creation using the prom monitor (YAMON) argc/argv.
 468 + */
 469 +#include <linux/init.h>
 470 +#include <linux/string.h>
 471 +
 472 +#include <asm/bootinfo.h>
 473 +
 474 +extern int prom_argc;
 475 +extern int *_prom_argv;
 476 +
 477 +/*
 478 + * YAMON (32-bit PROM) pass arguments and environment as 32-bit pointer.
 479 + * This macro take care of sign extension.
 480 + */
 481 +#define prom_argv(index) ((char *)(((int *)(int)_prom_argv)[(index)]))
 482 +
 483 +char arcs_cmdline[CL_SIZE];
 484 +
 485 +char * __init prom_getcmdline(void)
 486 +{
 487 +       return &(arcs_cmdline[0]);
 488 +}
 489 +
 490 +
 491 +void  __init prom_init_cmdline(void)
 492 +{
 493 +       char *cp;
 494 +       int actr;
 495 +
 496 +       actr = 1; /* Always ignore argv[0] */
 497 +
 498 +       cp = &(arcs_cmdline[0]);
 499 +#ifdef CONFIG_CMDLINE_BOOL
 500 +       strcpy(cp, CONFIG_CMDLINE);
 501 +       cp += strlen(CONFIG_CMDLINE);
 502 +       *cp++ = ' ';
 503 +#endif
 504 +       while(actr < prom_argc) {
 505 +               strcpy(cp, prom_argv(actr));
 506 +               cp += strlen(prom_argv(actr));
 507 +               *cp++ = ' ';
 508 +               actr++;
 509 +       }
 510 +       if (cp != &(arcs_cmdline[0])) /* get rid of trailing space */
 511 +               --cp;
 512 +       *cp = '\0';
 513 +}
 514 diff -urN kernel-base/arch/mips/ar7/init.c kernel-tmp2/arch/mips/ar7/init.c
 515 --- kernel-base/arch/mips/ar7/init.c    1970-01-01 01:00:00.000000000 +0100
 516 +++ kernel-tmp2/arch/mips/ar7/init.c    2005-07-10 06:40:39.584266864 +0200
 517 @@ -0,0 +1,146 @@
 518 +/*
 519 + * Carsten Langgaard, carstenl@mips.com
 520 + * Copyright (C) 1999,2000 MIPS Technologies, Inc.  All rights reserved.
 521 + *
 522 + *  This program is free software; you can distribute it and/or modify it
 523 + *  under the terms of the GNU General Public License (Version 2) as
 524 + *  published by the Free Software Foundation.
 525 + *
 526 + *  This program is distributed in the hope it will be useful, but WITHOUT
 527 + *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 528 + *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
 529 + *  for more details.
 530 + *
 531 + *  You should have received a copy of the GNU General Public License along
 532 + *  with this program; if not, write to the Free Software Foundation, Inc.,
 533 + *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
 534 + *
 535 + * PROM library initialisation code.
 536 + */
 537 +#include <linux/config.h>
 538 +#include <linux/init.h>
 539 +#include <linux/string.h>
 540 +#include <linux/kernel.h>
 541 +#include <linux/module.h>
 542 +
 543 +#include <asm/io.h>
 544 +#include <asm/mips-boards/prom.h>
 545 +#include <asm/mips-boards/generic.h>
 546 +
 547 +/* Environment variable */
 548 +typedef struct {
 549 +       char *name;
 550 +       char *val;
 551 +} t_env_var;
 552 +
 553 +int prom_argc;
 554 +int *_prom_argv, *_prom_envp;
 555 +
 556 +/* max # of Adam2 environment variables */
 557 +#define MAX_ENV_ENTRY 80
 558 +
 559 +static t_env_var local_envp[MAX_ENV_ENTRY];
 560 +int init_debug = 0;
 561 +
 562 +char *prom_getenv(char *envname)
 563 +{
 564 +       /*
 565 +        * Return a pointer to the given environment variable.
 566 +        * In 64-bit mode: we're using 64-bit pointers, but all pointers
 567 +        * in the PROM structures are only 32-bit, so we need some
 568 +        * workarounds, if we are running in 64-bit mode.
 569 +        */
 570 +       int i, index=0;
 571 +       t_env_var *env = (t_env_var *) local_envp;
 572 +
 573 +       i = strlen(envname);
 574 +       while (env->name) {
 575 +               if(strncmp(envname, env->name, i) == 0) {
 576 +                       return(env->val);
 577 +               }
 578 +               env++;
 579 +       }
 580 +
 581 +       return NULL;
 582 +}
 583 +
 584 +static inline unsigned char str2hexnum(unsigned char c)
 585 +{
 586 +       if (c >= '0' && c <= '9')
 587 +               return c - '0';
 588 +       if (c >= 'a' && c <= 'f')
 589 +               return c - 'a' + 10;
 590 +       return 0; /* foo */
 591 +}
 592 +
 593 +static inline void str2eaddr(unsigned char *ea, unsigned char *str)
 594 +{
 595 +       int i;
 596 +
 597 +       for (i = 0; i < 6; i++) {
 598 +               unsigned char num;
 599 +
 600 +               if((*str == '.') || (*str == ':'))
 601 +                       str++;
 602 +               num = str2hexnum(*str++) << 4;
 603 +               num |= (str2hexnum(*str++));
 604 +               ea[i] = num;
 605 +       }
 606 +}
 607 +
 608 +int get_ethernet_addr(char *ethernet_addr)
 609 +{
 610 +       char *ethaddr_str;
 611 +
 612 +       ethaddr_str = prom_getenv("ethaddr");
 613 +       if (!ethaddr_str) {
 614 +               printk("ethaddr not set in boot prom\n");
 615 +               return -1;
 616 +       }
 617 +       str2eaddr(ethernet_addr, ethaddr_str);
 618 +
 619 +       if (init_debug > 1) {
 620 +               int i;
 621 +               printk("get_ethernet_addr: ");
 622 +               for (i=0; i<5; i++)
 623 +                       printk("%02x:", (unsigned char)*(ethernet_addr+i));
 624 +               printk("%02x\n", *(ethernet_addr+i));
 625 +       }
 626 +
 627 +       return 0;
 628 +}
 629 +
 630 +int __init prom_init(int argc, char **argv, char **envp)
 631 +{
 632 +       int i;
 633 +       t_env_var *env = (t_env_var *) envp;
 634 +
 635 +       prom_argc = argc;
 636 +       _prom_argv = (int *)argv;
 637 +       _prom_envp = (int *)envp;
 638 +
 639 +       /* Copy what we need locally so we are not dependent on
 640 +        * bootloader RAM.  In Adam2, the environment parameters
 641 +        * are in flash but the table that references them is in
 642 +        * RAM
 643 +        */
 644 +       for(i=0; i < MAX_ENV_ENTRY; i++, env++) {
 645 +               if (env->name) {
 646 +                       local_envp[i].name = env->name;
 647 +                       local_envp[i].val = env->val;
 648 +               } else {
 649 +                       local_envp[i].name = NULL;
 650 +                       local_envp[i].val = NULL;
 651 +               }
 652 +       }
 653 +
 654 +       set_io_port_base(0);
 655 +
 656 +       prom_printf("\nLINUX started...\n");
 657 +       prom_init_cmdline();
 658 +       prom_meminit();
 659 +
 660 +       return 0;
 661 +}
 662 +
 663 +EXPORT_SYMBOL(prom_getenv);
 664 diff -urN kernel-base/arch/mips/ar7/irq.c kernel-tmp2/arch/mips/ar7/irq.c
 665 --- kernel-base/arch/mips/ar7/irq.c     1970-01-01 01:00:00.000000000 +0100
 666 +++ kernel-tmp2/arch/mips/ar7/irq.c     2005-07-10 06:40:39.585266712 +0200
 667 @@ -0,0 +1,664 @@
 668 +/*
 669 + * Nitin Dhingra, iamnd@ti.com
 670 + * Copyright (C) 2002 Texas Instruments, Inc.  All rights reserved.
 671 + *
 672 + * ########################################################################
 673 + *
 674 + *  This program is free software; you can distribute it and/or modify it
 675 + *  under the terms of the GNU General Public License (Version 2) as
 676 + *  published by the Free Software Foundation.
 677 + *
 678 + *  This program is distributed in the hope it will be useful, but WITHOUT
 679 + *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 680 + *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
 681 + *  for more details.
 682 + *
 683 + *  You should have received a copy of the GNU General Public License along
 684 + *  with this program; if not, write to the Free Software Foundation, Inc.,
 685 + *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
 686 + *
 687 + * ########################################################################
 688 + *
 689 + * Routines for generic manipulation of the interrupts found on the Texas
 690 + * Instruments avalanche board
 691 + *
 692 + */
 693 +
 694 +#include <linux/config.h>
 695 +#include <linux/init.h>
 696 +#include <linux/sched.h>
 697 +#include <linux/slab.h>
 698 +#include <linux/interrupt.h>
 699 +#include <linux/kernel_stat.h>
 700 +#include <linux/proc_fs.h>
 701 +#include <asm/irq.h>
 702 +#include <asm/mips-boards/prom.h>
 703 +#include <asm/ar7/ar7.h>
 704 +#include <asm/ar7/avalanche_intc.h>
 705 +#include <asm/gdb-stub.h>
 706 +
 707 +
 708 +#define shutdown_avalanche_irq disable_avalanche_irq
 709 +#define mask_and_ack_avalanche_irq   disable_avalanche_irq
 710 +
 711 +static unsigned int startup_avalanche_irq(unsigned int irq);
 712 +static void end_avalanche_irq(unsigned int irq);
 713 +void enable_avalanche_irq(unsigned int irq_nr);
 714 +void disable_avalanche_irq(unsigned int irq_nr);
 715 +
 716 +static struct hw_interrupt_type avalanche_irq_type = {
 717 +       "TI AVALANCHE",
 718 +       startup_avalanche_irq,
 719 +       shutdown_avalanche_irq,
 720 +       enable_avalanche_irq,
 721 +       disable_avalanche_irq,
 722 +       mask_and_ack_avalanche_irq,
 723 +       end_avalanche_irq,
 724 +       NULL
 725 +};
 726 +
 727 +irq_desc_t irq_desc_ti[AVALANCHE_INT_END+1] __cacheline_aligned =
 728 +{ [0 ... AVALANCHE_INT_END] = { 0, &avalanche_irq_type, NULL, 0, SPIN_LOCK_UNLOCKED}};
 729 +
 730 +
 731 +unsigned long spurious_count = 0;
 732 +
 733 +struct avalanche_ictrl_regs         *avalanche_hw0_icregs;  /* Interrupt control regs (primary)   */
 734 +struct avalanche_exctrl_regs        *avalanche_hw0_ecregs;  /* Exception control regs (secondary) */
 735 +struct avalanche_ipace_regs         *avalanche_hw0_ipaceregs;
 736 +struct avalanche_channel_int_number *avalanche_hw0_chregs;  /* Channel control registers          */
 737 +
 738 +extern asmlinkage void mipsIRQ(void);
 739 +
 740 +
 741 +/*
 742 + *   The avalanche/MIPS interrupt line numbers are used to represent the
 743 + *   interrupts within the irqaction arrays.  The index notation is
 744 + *   is as follows:
 745 + *
 746 + *           0-7    MIPS CPU Exceptions  (HW/SW)
 747 + *           8-47   Primary Interrupts   (Avalanche)
 748 + *           48-79  Secondary Interrupts (Avalanche)
 749 + *
 750 + */
 751 +
 752 +
 753 +static struct irqaction *hw0_irq_action_primary[AVINTNUM(AVALANCHE_INT_END_PRIMARY)] =
 754 +{
 755 +       NULL, NULL, NULL, NULL,
 756 +       NULL, NULL, NULL, NULL,
 757 +       NULL, NULL, NULL, NULL,
 758 +       NULL, NULL, NULL, NULL,
 759 +       NULL, NULL, NULL, NULL,
 760 +       NULL, NULL, NULL, NULL,
 761 +       NULL, NULL, NULL, NULL,
 762 +       NULL, NULL, NULL, NULL,
 763 +       NULL, NULL, NULL, NULL,
 764 +       NULL, NULL, NULL, NULL
 765 +};
 766 +
 767 +static struct irqaction *hw0_irq_action_secondary[AVINTNUM(AVALANCHE_INT_END_SECONDARY)] =
 768 +{
 769 +       NULL, NULL, NULL, NULL,
 770 +       NULL, NULL, NULL, NULL,
 771 +       NULL, NULL, NULL, NULL,
 772 +       NULL, NULL, NULL, NULL,
 773 +       NULL, NULL, NULL, NULL,
 774 +       NULL, NULL, NULL, NULL,
 775 +       NULL, NULL, NULL, NULL,
 776 +       NULL, NULL, NULL, NULL
 777 +};
 778 +
 779 +/*
 780 +   This remaps interrupts to exist on other channels than the default
 781 +   channels.  essentially we can use the line # as the index for this
 782 +   array
 783 + */
 784 +
 785 +
 786 +static unsigned long line_to_channel[AVINTNUM(AVALANCHE_INT_END_PRIMARY)];
 787 +unsigned long uni_secondary_interrupt = 0;
 788 +
 789 +static struct irqaction r4ktimer_action = {
 790 +       NULL, 0, 0, "R4000 timer/counter", NULL, NULL,
 791 +};
 792 +
 793 +static struct irqaction *irq_action[8] = {
 794 +       NULL,              /* SW int 0 */
 795 +       NULL,              /* SW int 1 */
 796 +       NULL,              /* HW int 0 */
 797 +       NULL,
 798 +       NULL,
 799 +       NULL,              /* HW int 3 */
 800 +       NULL,              /* HW int 4 */
 801 +       &r4ktimer_action   /* HW int 5 */
 802 +};
 803 +
 804 +static void end_avalanche_irq(unsigned int irq)
 805 +{
 806 +       if (!(irq_desc_ti[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
 807 +               enable_avalanche_irq(irq);
 808 +}
 809 +
 810 +void disable_avalanche_irq(unsigned int irq_nr)
 811 +{
 812 +       unsigned long flags;
 813 +       unsigned long chan_nr=0;
 814 +       unsigned long int_bit=0;
 815 +
 816 +       if(irq_nr >= AVALANCHE_INT_END)
 817 +       {
 818 +               printk("whee, invalid irq_nr %d\n", irq_nr);
 819 +               panic("IRQ, you lose...");
 820 +       }
 821 +
 822 +       save_and_cli(flags);
 823 +
 824 +
 825 +       if(irq_nr <  MIPS_EXCEPTION_OFFSET)
 826 +       {
 827 +               /* disable mips exception */
 828 +
 829 +               int_bit = read_c0_status() & ~(1 << (8+irq_nr));
 830 +               change_c0_status(ST0_IM,int_bit);
 831 +               restore_flags(flags);
 832 +               return;
 833 +       }
 834 +
 835 +       /* irq_nr represents the line number for the interrupt.  We must
 836 +        *  disable the channel number associated with that line number.
 837 +        */
 838 +
 839 +       if(irq_nr > AVALANCHE_INT_END_PRIMARY_REG2)
 840 +               chan_nr = AVINTNUM(irq_nr);                 /*CHECK THIS ALSO*/
 841 +       else
 842 +               chan_nr = line_to_channel[AVINTNUM(irq_nr)];/* WE NEED A LINE TO CHANNEL MAPPING FUNCTION HERE*/
 843 +
 844 +       /* disable the interrupt channel bit */
 845 +
 846 +       /* primary interrupt #'s 0-31 */
 847 +
 848 +       if(chan_nr <= AVINTNUM(AVALANCHE_INT_END_PRIMARY_REG1))
 849 +               avalanche_hw0_icregs->intecr1 = (1 << chan_nr);
 850 +
 851 +       /* primary interrupt #'s 32-39 */
 852 +
 853 +       else if ((chan_nr <= AVINTNUM(AVALANCHE_INT_END_PRIMARY_REG2)) &&
 854 +                       (chan_nr > AVINTNUM(AVALANCHE_INT_END_PRIMARY_REG1)))
 855 +               avalanche_hw0_icregs->intecr2 = (1 << (chan_nr - AVINTNUM(AVALANCHE_INT_END_SECONDARY)));
 856 +
 857 +       else  /* secondary interrupt #'s 0-31 */
 858 +               avalanche_hw0_ecregs->exiecr = (1 << (chan_nr - AVINTNUM(AVALANCHE_INT_END_PRIMARY)));
 859 +
 860 +       restore_flags(flags);
 861 +}
 862 +
 863 +void enable_avalanche_irq(unsigned int irq_nr)
 864 +{
 865 +       unsigned long flags;
 866 +       unsigned long chan_nr=0;
 867 +       unsigned long int_bit=0;
 868 +
 869 +       if(irq_nr > AVALANCHE_INT_END) {
 870 +               printk("whee, invalid irq_nr %d\n", irq_nr);
 871 +               panic("IRQ, you lose...");
 872 +       }
 873 +
 874 +       save_and_cli(flags);
 875 +
 876 +
 877 +       if(irq_nr <  MIPS_EXCEPTION_OFFSET)
 878 +       {
 879 +               /* Enable MIPS exceptions */
 880 +               int_bit = read_c0_status();
 881 +               change_c0_status(ST0_IM,int_bit | (1<<(8+irq_nr)));
 882 +               restore_flags(flags);
 883 +               return;
 884 +       }
 885 +
 886 +       /* irq_nr represents the line number for the interrupt.  We must
 887 +        *  disable the channel number associated with that line number.
 888 +        */
 889 +
 890 +       if(irq_nr > AVALANCHE_INT_END_PRIMARY_REG2)
 891 +               chan_nr = AVINTNUM(irq_nr);
 892 +       else
 893 +               chan_nr = line_to_channel[AVINTNUM(irq_nr)];
 894 +
 895 +       /* enable the interrupt channel  bit */
 896 +
 897 +       /* primary interrupt #'s 0-31 */
 898 +       if(chan_nr <= AVINTNUM(AVALANCHE_INT_END_PRIMARY_REG1))
 899 +               avalanche_hw0_icregs->intesr1 = (1 << chan_nr);
 900 +
 901 +       /* primary interrupt #'s 32 throuth 39 */
 902 +       else if ((chan_nr <= AVINTNUM(AVALANCHE_INT_END_PRIMARY_REG2)) &&
 903 +                       (chan_nr > AVINTNUM(AVALANCHE_INT_END_PRIMARY_REG1)))
 904 +               avalanche_hw0_icregs->intesr2 = (1 << (chan_nr - AVINTNUM(AVALANCHE_INT_END_SECONDARY)));
 905 +
 906 +       else    /* secondary interrupt #'s 0-31 */
 907 +               avalanche_hw0_ecregs->exiesr = (1 << (chan_nr - AVINTNUM(AVALANCHE_INT_END_PRIMARY)));
 908 +
 909 +       restore_flags(flags);
 910 +}
 911 +
 912 +static unsigned int startup_avalanche_irq(unsigned int irq)
 913 +{
 914 +       enable_avalanche_irq(irq);
 915 +       return 0; /* never anything pending */
 916 +}
 917 +
 918 +
 919 +int get_irq_list(char *buf)
 920 +{
 921 +       int i, len = 0;
 922 +       int num = 0;
 923 +       struct irqaction *action;
 924 +
 925 +       for (i = 0; i < MIPS_EXCEPTION_OFFSET; i++, num++)
 926 +       {
 927 +               action = irq_action[i];
 928 +               if (!action)
 929 +                       continue;
 930 +               len += sprintf(buf+len, "%2d: %8d %c %s",
 931 +                               num, kstat.irqs[0][num],
 932 +                               (action->flags & SA_INTERRUPT) ? '+' : ' ',
 933 +                               action->name);
 934 +               for (action=action->next; action; action = action->next) {
 935 +                       len += sprintf(buf+len, ",%s %s",
 936 +                                       (action->flags & SA_INTERRUPT) ? " +" : "",
 937 +                                       action->name);
 938 +               }
 939 +               len += sprintf(buf+len, " [MIPS interrupt]\n");
 940 +       }
 941 +
 942 +
 943 +       for (i = 0; i < AVINTNUM(AVALANCHE_INT_END); i++,num++)
 944 +       {
 945 +               if(i < AVINTNUM(AVALANCHE_INT_END_PRIMARY))
 946 +                       action = hw0_irq_action_primary[i];
 947 +               else
 948 +                       action = hw0_irq_action_secondary[i-AVINTNUM(AVALANCHE_INT_END_PRIMARY)];
 949 +               if (!action)
 950 +                       continue;
 951 +               len += sprintf(buf+len, "%2d: %8d %c %s",
 952 +                               num, kstat.irqs[0][ LNXINTNUM(i) ],
 953 +                               (action->flags & SA_INTERRUPT) ? '+' : ' ',
 954 +                               action->name);
 955 +
 956 +               for (action=action->next; action; action = action->next)
 957 +               {
 958 +                       len += sprintf(buf+len, ",%s %s",
 959 +                                       (action->flags & SA_INTERRUPT) ? " +" : "",
 960 +                                       action->name);
 961 +               }
 962 +
 963 +               if(i < AVINTNUM(AVALANCHE_INT_END_PRIMARY))
 964 +                       len += sprintf(buf+len, " [hw0 (Avalanche Primary)]\n");
 965 +               else
 966 +                       len += sprintf(buf+len, " [hw0 (Avalanche Secondary)]\n");
 967 +
 968 +       }
 969 +
 970 +       return len;
 971 +}
 972 +
 973 +int request_irq(unsigned int irq,
 974 +               void (*handler)(int, void *, struct pt_regs *),
 975 +               unsigned long irqflags,
 976 +               const char * devname,
 977 +               void *dev_id)
 978 +{
 979 +       struct irqaction *action;
 980 +
 981 +       if (irq >  AVALANCHE_INT_END)
 982 +               return -EINVAL;
 983 +       if (!handler)
 984 +               return -EINVAL;
 985 +
 986 +       action = (struct irqaction *)kmalloc(sizeof(struct irqaction), GFP_KERNEL);
 987 +       if(!action)
 988 +               return -ENOMEM;
 989 +
 990 +       action->handler = handler;
 991 +       action->flags = irqflags;
 992 +       action->mask = 0;
 993 +       action->name = devname;
 994 +       irq_desc_ti[irq].action = action;
 995 +       action->dev_id = dev_id;
 996 +
 997 +       action->next = 0;
 998 +
 999 +       if(irq <  MIPS_EXCEPTION_OFFSET)
1000 +       {
1001 +               irq_action[irq] = action;
1002 +               enable_avalanche_irq(irq);
1003 +               return 0;
1004 +       }
1005 +
1006 +       if(irq < AVALANCHE_INT_END_PRIMARY)
1007 +               hw0_irq_action_primary[line_to_channel[AVINTNUM(irq)]] = action;
1008 +       else
1009 +               hw0_irq_action_secondary[irq - AVALANCHE_INT_END_PRIMARY] = action;
1010 +
1011 +       enable_avalanche_irq(irq);
1012 +
1013 +       return 0;
1014 +}
1015 +
1016 +void free_irq(unsigned int irq, void *dev_id)
1017 +{
1018 +       struct irqaction *action;
1019 +
1020 +       if (irq > AVALANCHE_INT_END) {
1021 +               printk("Trying to free IRQ%d\n",irq);
1022 +               return;
1023 +       }
1024 +
1025 +       if(irq <  MIPS_EXCEPTION_OFFSET)
1026 +       {
1027 +               action = irq_action[irq];
1028 +               irq_action[irq] = NULL;
1029 +               irq_desc_ti[irq].action = NULL;
1030 +               disable_avalanche_irq(irq);
1031 +               kfree(action);
1032 +               return;
1033 +       }
1034 +
1035 +       if(irq < AVALANCHE_INT_END_PRIMARY) {
1036 +               action = hw0_irq_action_primary[line_to_channel[AVINTNUM(irq)]];
1037 +               hw0_irq_action_primary[line_to_channel[AVINTNUM(irq)]] = NULL;
1038 +               irq_desc_ti[irq].action = NULL;
1039 +       }
1040 +       else {
1041 +               action = hw0_irq_action_secondary[irq - AVALANCHE_INT_END_PRIMARY];
1042 +               hw0_irq_action_secondary[irq - AVALANCHE_INT_END_PRIMARY] = NULL;
1043 +               irq_desc_ti[irq].action = NULL;
1044 +       }
1045 +
1046 +       disable_avalanche_irq(irq);
1047 +       kfree(action);
1048 +}
1049 +
1050 +#ifdef CONFIG_KGDB
1051 +extern void breakpoint(void);
1052 +extern int remote_debug;
1053 +#endif
1054 +
1055 +//void init_IRQ(void) __init;
1056 +void __init init_IRQ(void)
1057 +{
1058 +       int i;
1059 +
1060 +       avalanche_hw0_icregs = (struct avalanche_ictrl_regs *)AVALANCHE_ICTRL_REGS_BASE;
1061 +       avalanche_hw0_ecregs = (struct avalanche_exctrl_regs *)AVALANCHE_ECTRL_REGS_BASE;
1062 +       avalanche_hw0_ipaceregs = (struct avalanche_ipace_regs *)AVALANCHE_IPACE_REGS_BASE;
1063 +       avalanche_hw0_chregs = (struct avalanche_channel_int_number *)AVALANCHE_CHCTRL_REGS_BASE;
1064 +
1065 +       /*  Disable interrupts and clear pending
1066 +        */
1067 +
1068 +       avalanche_hw0_icregs->intecr1 = 0xffffffff;    /* disable interrupts 0:31  */
1069 +       avalanche_hw0_icregs->intcr1 = 0xffffffff;     /* clear interrupts 0:31    */
1070 +       avalanche_hw0_icregs->intecr2 = 0xff;          /* disable interrupts 32:39 */
1071 +       avalanche_hw0_icregs->intcr2 = 0xff;           /* clear interrupts 32:39   */
1072 +       avalanche_hw0_ecregs->exiecr = 0xffffffff;     /* disable secondary interrupts 0:31 */
1073 +       avalanche_hw0_ecregs->excr = 0xffffffff;       /* clear secondary interrupts 0:31 */
1074 +
1075 +
1076 +       /* Channel to line mapping, Line to Channel mapping */
1077 +
1078 +       for(i = 0; i < 40; i++)
1079 +               avalanche_int_set(i,i);
1080 +
1081 +       /* Now safe to set the exception vector. */
1082 +       set_except_vector(0, mipsIRQ);
1083 +
1084 +       /* Setup the IRQ description array.  These will be mapped
1085 +        *  as flat interrupts numbers.  The mapping is as follows
1086 +        *
1087 +        *           0-7    MIPS CPU Exceptions  (HW/SW)
1088 +        *           8-46   Primary Interrupts   (Avalanche)
1089 +        *           47-78  Secondary Interrupts (Avalanche)
1090 +        */
1091 +
1092 +       for (i = 0; i <= AVALANCHE_INT_END; i++)
1093 +       {
1094 +               irq_desc_ti[i].status   = IRQ_DISABLED;
1095 +               irq_desc_ti[i].action   = 0;
1096 +               irq_desc_ti[i].depth    = 1;
1097 +               irq_desc_ti[i].handler  = &avalanche_irq_type;
1098 +       }
1099 +
1100 +#ifdef CONFIG_KGDB
1101 +       if (remote_debug)
1102 +       {
1103 +               set_debug_traps();
1104 +               breakpoint();
1105 +       }
1106 +#endif
1107 +}
1108 +
1109 +
1110 +void avalanche_hw0_irqdispatch(struct pt_regs *regs)
1111 +{
1112 +       struct irqaction *action;
1113 +       int irq, cpu = smp_processor_id();
1114 +       unsigned long int_line_number,status;
1115 +       int i,secondary = 0;
1116 +       int chan_nr=0;
1117 +
1118 +       int_line_number = ((avalanche_hw0_icregs->pintir >> 16) & 0x3F);
1119 +       chan_nr = ((avalanche_hw0_icregs->pintir) & 0x3F);
1120 +
1121 +
1122 +       if(chan_nr < 32)
1123 +       {
1124 +               if( chan_nr != uni_secondary_interrupt)
1125 +                       avalanche_hw0_icregs->intcr1 = (1<<chan_nr);
1126 +
1127 +       }
1128 +
1129 +       if((chan_nr < 40) && (chan_nr > 31))
1130 +       {
1131 +               avalanche_hw0_icregs->intcr2 = (1<<(chan_nr-AVINTNUM(AVALANCHE_INT_END_SECONDARY)));
1132 +       }
1133 +
1134 +
1135 +       /* If the Priority Interrupt Index Register returns 40  then no
1136 +        * interrupts are pending
1137 +        */
1138 +
1139 +       if(chan_nr == 40)
1140 +               return;
1141 +
1142 +       if(chan_nr == uni_secondary_interrupt)
1143 +       {
1144 +               status = avalanche_hw0_ecregs->exsr;
1145 +               for(i=0; i < AVINTNUM(AVALANCHE_INT_END_SECONDARY); i++)
1146 +               {
1147 +                       if (status & 1<<i)
1148 +                       {
1149 +                               /* clear secondary interrupt */
1150 +                               avalanche_hw0_ecregs->excr = 1 << i;
1151 +                               break;
1152 +                       }
1153 +               }
1154 +               irq = i;
1155 +               secondary = 1;
1156 +
1157 +               /* clear the universal secondary interrupt */
1158 +               avalanche_hw0_icregs->intcr1 = 1 << uni_secondary_interrupt;
1159 +
1160 +       }
1161 +       else
1162 +               irq = chan_nr;
1163 +
1164 +       /* Suraj Add code to clear secondary interrupt */
1165 +
1166 +       if(secondary)
1167 +               action = hw0_irq_action_secondary[irq];
1168 +       else
1169 +               action = hw0_irq_action_primary[irq];
1170 +
1171 +       /* if action == NULL, then we don't have a handler for the irq */
1172 +
1173 +       if ( action == NULL ) {
1174 +               printk("No handler for hw0 irq: %i\n", irq);
1175 +               return;
1176 +       }
1177 +
1178 +       irq_enter(cpu,irq);
1179 +       if(secondary)
1180 +       {
1181 +               kstat.irqs[0][(irq + AVINTNUM(AVALANCHE_INT_END_PRIMARY)) + 8]++;
1182 +               action->handler((irq + AVALANCHE_INT_END_PRIMARY), action->dev_id, regs);
1183 +       }
1184 +       else
1185 +       {
1186 +               kstat.irqs[0][irq + 8]++;
1187 +               action->handler(LNXINTNUM(irq), action->dev_id, regs);
1188 +       }
1189 +
1190 +       irq_exit(cpu,irq);
1191 +
1192 +       if(softirq_pending(cpu))
1193 +               do_softirq();
1194 +
1195 +       return;
1196 +}
1197 +
1198 +void avalanche_int_set(int channel, int line)
1199 +{
1200 +       switch(channel)
1201 +       {
1202 +               case(0):
1203 +                       avalanche_hw0_chregs->cintnr0 =  line;
1204 +                       break;
1205 +               case(1):
1206 +                       avalanche_hw0_chregs->cintnr1 =  line;
1207 +                       break;
1208 +               case(2):
1209 +                       avalanche_hw0_chregs->cintnr2 =  line;
1210 +                       break;
1211 +               case(3):
1212 +                       avalanche_hw0_chregs->cintnr3 =  line;
1213 +                       break;
1214 +               case(4):
1215 +                       avalanche_hw0_chregs->cintnr4 =  line;
1216 +                       break;
1217 +               case(5):
1218 +                       avalanche_hw0_chregs->cintnr5 =  line;
1219 +                       break;
1220 +               case(6):
1221 +                       avalanche_hw0_chregs->cintnr6 =  line;
1222 +                       break;
1223 +               case(7):
1224 +                       avalanche_hw0_chregs->cintnr7 =  line;
1225 +                       break;
1226 +               case(8):
1227 +                       avalanche_hw0_chregs->cintnr8 =  line;
1228 +                       break;
1229 +               case(9):
1230 +                       avalanche_hw0_chregs->cintnr9 =  line;
1231 +                       break;
1232 +               case(10):
1233 +                       avalanche_hw0_chregs->cintnr10 = line;
1234 +                       break;
1235 +               case(11):
1236 +                       avalanche_hw0_chregs->cintnr11 = line;
1237 +                       break;
1238 +               case(12):
1239 +                       avalanche_hw0_chregs->cintnr12 = line;
1240 +                       break;
1241 +               case(13):
1242 +                       avalanche_hw0_chregs->cintnr13 = line;
1243 +                       break;
1244 +               case(14):
1245 +                       avalanche_hw0_chregs->cintnr14 = line;
1246 +                       break;
1247 +               case(15):
1248 +                       avalanche_hw0_chregs->cintnr15 = line;
1249 +                       break;
1250 +               case(16):
1251 +                       avalanche_hw0_chregs->cintnr16 = line;
1252 +                       break;
1253 +               case(17):
1254 +                       avalanche_hw0_chregs->cintnr17 = line;
1255 +                       break;
1256 +               case(18):
1257 +                       avalanche_hw0_chregs->cintnr18 = line;
1258 +                       break;
1259 +               case(19):
1260 +                       avalanche_hw0_chregs->cintnr19 = line;
1261 +                       break;
1262 +               case(20):
1263 +                       avalanche_hw0_chregs->cintnr20 = line;
1264 +                       break;
1265 +               case(21):
1266 +                       avalanche_hw0_chregs->cintnr21 = line;
1267 +                       break;
1268 +               case(22):
1269 +                       avalanche_hw0_chregs->cintnr22 = line;
1270 +                       break;
1271 +               case(23):
1272 +                       avalanche_hw0_chregs->cintnr23 = line;
1273 +                       break;
1274 +               case(24):
1275 +                       avalanche_hw0_chregs->cintnr24 = line;
1276 +                       break;
1277 +               case(25):
1278 +                       avalanche_hw0_chregs->cintnr25 = line;
1279 +                       break;
1280 +               case(26):
1281 +                       avalanche_hw0_chregs->cintnr26 = line;
1282 +                       break;
1283 +               case(27):
1284 +                       avalanche_hw0_chregs->cintnr27 = line;
1285 +                       break;
1286 +               case(28):
1287 +                       avalanche_hw0_chregs->cintnr28 = line;
1288 +                       break;
1289 +               case(29):
1290 +                       avalanche_hw0_chregs->cintnr29 = line;
1291 +                       break;
1292 +               case(30):
1293 +                       avalanche_hw0_chregs->cintnr30 = line;
1294 +                       break;
1295 +               case(31):
1296 +                       avalanche_hw0_chregs->cintnr31 = line;
1297 +                       break;
1298 +               case(32):
1299 +                       avalanche_hw0_chregs->cintnr32 = line;
1300 +                       break;
1301 +               case(33):
1302 +                       avalanche_hw0_chregs->cintnr33 = line;
1303 +                       break;
1304 +               case(34):
1305 +                       avalanche_hw0_chregs->cintnr34 = line;
1306 +                       break;
1307 +               case(35):
1308 +                       avalanche_hw0_chregs->cintnr35 = line;
1309 +                       break;
1310 +               case(36):
1311 +                       avalanche_hw0_chregs->cintnr36 = line;
1312 +                       break;
1313 +               case(37):
1314 +                       avalanche_hw0_chregs->cintnr37 = line;
1315 +                       break;
1316 +               case(38):
1317 +                       avalanche_hw0_chregs->cintnr38 = line;
1318 +                       break;
1319 +               case(39):
1320 +                       avalanche_hw0_chregs->cintnr39 = line;
1321 +                       break;
1322 +               default:
1323 +                       printk("Error: Unknown Avalanche interrupt channel\n");
1324 +       }
1325 +
1326 +       line_to_channel[line] = channel; /* Suraj check */
1327 +
1328 +       if (channel == UNIFIED_SECONDARY_INTERRUPT)
1329 +               uni_secondary_interrupt = line;
1330 +
1331 +}
1332 diff -urN kernel-base/arch/mips/ar7/Makefile kernel-tmp2/arch/mips/ar7/Makefile
1333 --- kernel-base/arch/mips/ar7/Makefile  1970-01-01 01:00:00.000000000 +0100
1334 +++ kernel-tmp2/arch/mips/ar7/Makefile  2005-07-10 06:40:39.586266560 +0200
1335 @@ -0,0 +1,29 @@
1336 +# $Id$
1337 +# Copyright (C) $Date$  $Author$
1338 +#
1339 +# This program is free software; you can redistribute it and/or modify
1340 +# it under the terms of the GNU General Public License as published by
1341 +# the Free Software Foundation; either version 2 of the License, or
1342 +# (at your option) any later version.
1343 +#
1344 +# This program is distributed in the hope that it will be useful,
1345 +# but WITHOUT ANY WARRANTY; without even the implied warranty of
1346 +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
1347 +# GNU General Public License for more details.
1348 +#
1349 +# You should have received a copy of the GNU General Public License
1350 +# along with this program; if not, write to the Free Software
1351 +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
1352 +
1353 +.S.s:
1354 +       $(CPP) $(AFLAGS) $< -o $*.s
1355 +
1356 +.S.o:
1357 +       $(CC) $(AFLAGS) -c $< -o $*.o
1358 +
1359 +O_TARGET := ar7.o
1360 +
1361 +export-objs := init.o
1362 +obj-y := setup.o irq.o mipsIRQ.o reset.o init.o memory.o printf.o cmdline.o time.o
1363 +
1364 +include $(TOPDIR)/Rules.make
1365 diff -urN kernel-base/arch/mips/ar7/memory.c kernel-tmp2/arch/mips/ar7/memory.c
1366 --- kernel-base/arch/mips/ar7/memory.c  1970-01-01 01:00:00.000000000 +0100
1367 +++ kernel-tmp2/arch/mips/ar7/memory.c  2005-07-10 06:40:39.586266560 +0200
1368 @@ -0,0 +1,130 @@
1369 +/*
1370 + * Carsten Langgaard, carstenl@mips.com
1371 + * Copyright (C) 1999,2000 MIPS Technologies, Inc.  All rights reserved.
1372 + *
1373 + * ########################################################################
1374 + *
1375 + *  This program is free software; you can distribute it and/or modify it
1376 + *  under the terms of the GNU General Public License (Version 2) as
1377 + *  published by the Free Software Foundation.
1378 + *
1379 + *  This program is distributed in the hope it will be useful, but WITHOUT
1380 + *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
1381 + *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
1382 + *  for more details.
1383 + *
1384 + *  You should have received a copy of the GNU General Public License along
1385 + *  with this program; if not, write to the Free Software Foundation, Inc.,
1386 + *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
1387 + *
1388 + * ########################################################################
1389 + *
1390 + * PROM library functions for acquiring/using memory descriptors given to
1391 + * us from the YAMON.
1392 + *
1393 + */
1394 +#include <linux/config.h>
1395 +#include <linux/init.h>
1396 +#include <linux/mm.h>
1397 +#include <linux/bootmem.h>
1398 +
1399 +#include <asm/bootinfo.h>
1400 +#include <asm/page.h>
1401 +#include <asm/mips-boards/prom.h>
1402 +#include <asm/ar7/ar7.h>
1403 +
1404 +enum yamon_memtypes {
1405 +       yamon_dontuse,
1406 +       yamon_prom,
1407 +       yamon_free,
1408 +};
1409 +struct prom_pmemblock mdesc[PROM_MAX_PMEMBLOCKS];
1410 +
1411 +/* References to section boundaries */
1412 +extern char _end;
1413 +
1414 +#define PFN_ALIGN(x)    (((unsigned long)(x) + (PAGE_SIZE - 1)) & PAGE_MASK)
1415 +
1416 +
1417 +struct prom_pmemblock * __init prom_getmdesc(void)
1418 +{
1419 +       char *memsize_str;
1420 +       unsigned int memsize;
1421 +
1422 +       memsize_str = prom_getenv("memsize");
1423 +       if (!memsize_str) {
1424 +               memsize = 0x02000000;
1425 +       } else {
1426 +               memsize = simple_strtol(memsize_str, NULL, 0);
1427 +       }
1428 +
1429 +       memset(mdesc, 0, sizeof(mdesc));
1430 +
1431 +       mdesc[0].type = yamon_dontuse;
1432 +       mdesc[0].base = 0x00000000;
1433 +       mdesc[0].size = CONFIG_AR7_MEMORY;
1434 +
1435 +       mdesc[1].type = yamon_prom;
1436 +       mdesc[1].base = CONFIG_AR7_MEMORY;
1437 +       mdesc[1].size = 0x00020000;
1438 +
1439 +       mdesc[2].type = yamon_free;
1440 +       mdesc[2].base = CONFIG_AR7_MEMORY + 0x00020000;
1441 +       mdesc[2].size = (memsize + CONFIG_AR7_MEMORY) - mdesc[2].base;
1442 +
1443 +       return &mdesc[0];
1444 +}
1445 +
1446 +static int __init prom_memtype_classify (unsigned int type)
1447 +{
1448 +       switch (type) {
1449 +               case yamon_free:
1450 +                       return BOOT_MEM_RAM;
1451 +               case yamon_prom:
1452 +                       return BOOT_MEM_ROM_DATA;
1453 +               default:
1454 +                       return BOOT_MEM_RESERVED;
1455 +       }
1456 +}
1457 +
1458 +void __init prom_meminit(void)
1459 +{
1460 +       struct prom_pmemblock *p;
1461 +
1462 +       p = prom_getmdesc();
1463 +
1464 +       while (p->size) {
1465 +               long type;
1466 +               unsigned long base, size;
1467 +
1468 +               type = prom_memtype_classify (p->type);
1469 +               base = p->base;
1470 +               size = p->size;
1471 +
1472 +               add_memory_region(base, size, type);
1473 +               p++;
1474 +       }
1475 +}
1476 +
1477 +void __init prom_free_prom_memory (void)
1478 +{
1479 +       int i;
1480 +       unsigned long freed = 0;
1481 +       unsigned long addr;
1482 +
1483 +       for (i = 0; i < boot_mem_map.nr_map; i++) {
1484 +               if (boot_mem_map.map[i].type != BOOT_MEM_ROM_DATA)
1485 +                       continue;
1486 +
1487 +               addr = boot_mem_map.map[i].addr;
1488 +               while (addr < boot_mem_map.map[i].addr
1489 +                               + boot_mem_map.map[i].size) {
1490 +                       ClearPageReserved(virt_to_page(__va(addr)));
1491 +                       set_page_count(virt_to_page(__va(addr)), 1);
1492 +                       free_page((unsigned long)__va(addr));
1493 +                       addr += PAGE_SIZE;
1494 +                       freed += PAGE_SIZE;
1495 +               }
1496 +       }
1497 +       printk("Freeing prom memory: %ldkb freed\n", freed >> 10);
1498 +}
1499 diff -urN kernel-base/arch/mips/ar7/mipsIRQ.S kernel-tmp2/arch/mips/ar7/mipsIRQ.S
1500 --- kernel-base/arch/mips/ar7/mipsIRQ.S 1970-01-01 01:00:00.000000000 +0100
1501 +++ kernel-tmp2/arch/mips/ar7/mipsIRQ.S 2005-07-10 06:40:39.587266408 +0200
1502 @@ -0,0 +1,120 @@
1503 +/*
1504 + * Carsten Langgaard, carstenl@mips.com
1505 + * Copyright (C) 1999, 2000 MIPS Technologies, Inc.  All rights reserved.
1506 + *
1507 + * ########################################################################
1508 + *
1509 + *  This program is free software; you can distribute it and/or modify it
1510 + *  under the terms of the GNU General Public License (Version 2) as
1511 + *  published by the Free Software Foundation.
1512 + *
1513 + *  This program is distributed in the hope it will be useful, but WITHOUT
1514 + *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
1515 + *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
1516 + *  for more details.
1517 + *
1518 + *  You should have received a copy of the GNU General Public License along
1519 + *  with this program; if not, write to the Free Software Foundation, Inc.,
1520 + *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
1521 + *
1522 + * ########################################################################
1523 + *
1524 + * Interrupt exception dispatch code.
1525 + *
1526 + */
1527 +#include <linux/config.h>
1528 +
1529 +#include <asm/asm.h>
1530 +#include <asm/mipsregs.h>
1531 +#include <asm/regdef.h>
1532 +#include <asm/stackframe.h>
1533 +
1534 +/* A lot of complication here is taken away because:
1535 + *
1536 + * 1) We handle one interrupt and return, sitting in a loop and moving across
1537 + *    all the pending IRQ bits in the cause register is _NOT_ the answer, the
1538 + *    common case is one pending IRQ so optimize in that direction.
1539 + *
1540 + * 2) We need not check against bits in the status register IRQ mask, that
1541 + *    would make this routine slow as hell.
1542 + *
1543 + * 3) Linux only thinks in terms of all IRQs on or all IRQs off, nothing in
1544 + *    between like BSD spl() brain-damage.
1545 + *
1546 + * Furthermore, the IRQs on the MIPS board look basically (barring software
1547 + * IRQs which we don't use at all and all external interrupt sources are
1548 + * combined together on hardware interrupt 0 (MIPS IRQ 2)) like:
1549 + *
1550 + *     MIPS IRQ        Source
1551 + *      --------        ------
1552 + *             0       Software (ignored)
1553 + *             1        Software (ignored)
1554 + *             2        Combined hardware interrupt (hw0)
1555 + *             3        Hardware (ignored)
1556 + *             4        Hardware (ignored)
1557 + *             5        Hardware (ignored)
1558 + *             6        Hardware (ignored)
1559 + *             7        R4k timer (what we use)
1560 + *
1561 + * Note: On the SEAD board thing are a little bit different.
1562 + *       Here IRQ 2 (hw0) is wired to the UART0 and IRQ 3 (hw1) is wired
1563 + *       wired to UART1.
1564 + *
1565 + * We handle the IRQ according to _our_ priority which is:
1566 + *
1567 + * Highest ----     R4k Timer
1568 + * Lowest  ----     Combined hardware interrupt
1569 + *
1570 + * then we just return, if multiple IRQs are pending then we will just take
1571 + * another exception, big deal.
1572 + */
1573 +
1574 +.text
1575 +.set   noreorder
1576 +.set   noat
1577 +       .align  5
1578 +NESTED(mipsIRQ, PT_SIZE, sp)
1579 +       SAVE_ALL
1580 +       CLI
1581 +       .set    at
1582 +
1583 +       mfc0    s0, CP0_CAUSE           # get irq bits
1584 +
1585 +       /* First we check for r4k counter/timer IRQ. */
1586 +       andi    a0, s0, CAUSEF_IP7
1587 +       beq     a0, zero, 1f
1588 +       andi    a0, s0, CAUSEF_IP2      # delay slot, check hw0 interrupt
1589 +
1590 +       /* Wheee, a timer interrupt. */
1591 +       move    a0, sp
1592 +       jal     ar7_timer_interrupt
1593 +       nop
1594 +
1595 +       j       ret_from_irq
1596 +       nop
1597 +
1598 +       1:
1599 +       beq     a0, zero, 1f            # delay slot, check hw3 interrupt
1600 +       nop
1601 +
1602 +       /* Wheee, combined hardware level zero interrupt. */
1603 +       jal     avalanche_hw0_irqdispatch
1604 +       move    a0, sp                  # delay slot
1605 +
1606 +       j       ret_from_irq
1607 +       nop                             # delay slot
1608 +
1609 +       1:
1610 +       /*
1611 +        * Here by mistake?  This is possible, what can happen is that by the
1612 +        * time we take the exception the IRQ pin goes low, so just leave if
1613 +        * this is the case.
1614 +        */
1615 +       move    a1,s0
1616 +       PRINT("Got interrupt: c0_cause = %08x\n")
1617 +       mfc0    a1, CP0_EPC
1618 +       PRINT("c0_epc = %08x\n")
1619 +
1620 +       j       ret_from_irq
1621 +       nop
1622 +END(mipsIRQ)
1623 diff -urN kernel-base/arch/mips/ar7/printf.c kernel-tmp2/arch/mips/ar7/printf.c
1624 --- kernel-base/arch/mips/ar7/printf.c  1970-01-01 01:00:00.000000000 +0100
1625 +++ kernel-tmp2/arch/mips/ar7/printf.c  2005-07-10 06:40:39.587266408 +0200
1626 @@ -0,0 +1,54 @@
1627 +/*
1628 + * Carsten Langgaard, carstenl@mips.com
1629 + * Copyright (C) 1999,2000 MIPS Technologies, Inc.  All rights reserved.
1630 + *
1631 + *  This program is free software; you can distribute it and/or modify it
1632 + *  under the terms of the GNU General Public License (Version 2) as
1633 + *  published by the Free Software Foundation.
1634 + *
1635 + *  This program is distributed in the hope it will be useful, but WITHOUT
1636 + *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
1637 + *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
1638 + *  for more details.
1639 + *
1640 + *  You should have received a copy of the GNU General Public License along
1641 + *  with this program; if not, write to the Free Software Foundation, Inc.,
1642 + *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
1643 + *
1644 + * Putting things on the screen/serial line using Adam2 facilities.
1645 + */
1646 +
1647 +#include <linux/config.h>
1648 +#include <linux/init.h>
1649 +#include <linux/kernel.h>
1650 +#include <linux/serial_reg.h>
1651 +#include <linux/spinlock.h>
1652 +#include <asm/io.h>
1653 +#include <asm/serial.h>
1654 +#include <asm/addrspace.h>
1655 +#include <asm/ar7/ar7.h>
1656 +
1657 +#define AVALANCHE_YAMON_FUNCTION_BASE             (KSEG1ADDR(0x10000500))
1658 +#define AVALANCHE_YAMON_PROM_PRINT_COUNT_ADDR     (AVALANCHE_YAMON_FUNCTION_BASE + 0x4)  /* print_count function */
1659 +
1660 +static char ppbuf[1024];
1661 +
1662 +void (*prom_print_str)(unsigned int out, char *s, int len);
1663 +
1664 +void prom_printf(char *fmt, ...) __init;
1665 +void prom_printf(char *fmt, ...)
1666 +{
1667 +       va_list args;
1668 +       int len;
1669 +       prom_print_str = (void *)*(unsigned int *)AVALANCHE_YAMON_PROM_PRINT_COUNT_ADDR;
1670 +
1671 +       va_start(args, fmt);
1672 +       vsprintf(ppbuf, fmt, args);
1673 +       len = strlen(ppbuf);
1674 +
1675 +       prom_print_str(1, ppbuf, len);
1676 +
1677 +       va_end(args);
1678 +       return;
1679 +
1680 +}
1681 diff -urN kernel-base/arch/mips/ar7/reset.c kernel-tmp2/arch/mips/ar7/reset.c
1682 --- kernel-base/arch/mips/ar7/reset.c   1970-01-01 01:00:00.000000000 +0100
1683 +++ kernel-tmp2/arch/mips/ar7/reset.c   2005-07-10 06:40:39.587266408 +0200
1684 @@ -0,0 +1,54 @@
1685 +/*
1686 + * Carsten Langgaard, carstenl@mips.com
1687 + * Copyright (C) 1999,2000 MIPS Technologies, Inc.  All rights reserved.
1688 + *
1689 + * ########################################################################
1690 + *
1691 + *  This program is free software; you can distribute it and/or modify it
1692 + *  under the terms of the GNU General Public License (Version 2) as
1693 + *  published by the Free Software Foundation.
1694 + *
1695 + *  This program is distributed in the hope it will be useful, but WITHOUT
1696 + *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
1697 + *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
1698 + *  for more details.
1699 + *
1700 + *  You should have received a copy of the GNU General Public License along
1701 + *  with this program; if not, write to the Free Software Foundation, Inc.,
1702 + *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
1703 + *
1704 + * ########################################################################
1705 + *
1706 + * Reset the MIPS boards.
1707 + *
1708 + */
1709 +#include <linux/config.h>
1710 +
1711 +#include <asm/reboot.h>
1712 +#include <asm/mips-boards/generic.h>
1713 +
1714 +static void ar7_machine_restart(char *command);
1715 +static void ar7_machine_halt(void);
1716 +static void ar7_machine_power_off(void);
1717 +
1718 +static void ar7_machine_restart(char *command)
1719 +{
1720 +
1721 +}
1722 +
1723 +static void ar7_machine_halt(void)
1724 +{
1725 +
1726 +}
1727 +
1728 +static void ar7_machine_power_off(void)
1729 +{
1730 +
1731 +}
1732 +
1733 +void ar7_reboot_setup(void)
1734 +{
1735 +       _machine_restart = ar7_machine_restart;
1736 +       _machine_halt = ar7_machine_halt;
1737 +       _machine_power_off = ar7_machine_power_off;
1738 +}
1739 diff -urN kernel-base/arch/mips/ar7/setup.c kernel-tmp2/arch/mips/ar7/setup.c
1740 --- kernel-base/arch/mips/ar7/setup.c   1970-01-01 01:00:00.000000000 +0100
1741 +++ kernel-tmp2/arch/mips/ar7/setup.c   2005-07-10 06:40:39.588266256 +0200
1742 @@ -0,0 +1,120 @@
1743 +/*
1744 + * Carsten Langgaard, carstenl@mips.com
1745 + * Copyright (C) 2000 MIPS Technologies, Inc.  All rights reserved.
1746 + *
1747 + *  This program is free software; you can distribute it and/or modify it
1748 + *  under the terms of the GNU General Public License (Version 2) as
1749 + *  published by the Free Software Foundation.
1750 + *
1751 + *  This program is distributed in the hope it will be useful, but WITHOUT
1752 + *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
1753 + *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
1754 + *  for more details.
1755 + *
1756 + *  You should have received a copy of the GNU General Public License along
1757 + *  with this program; if not, write to the Free Software Foundation, Inc.,
1758 + *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
1759 + */
1760 +#include <linux/config.h>
1761 +#include <linux/init.h>
1762 +#include <linux/sched.h>
1763 +#include <linux/mc146818rtc.h>
1764 +#include <linux/ioport.h>
1765 +
1766 +#include <asm/cpu.h>
1767 +#include <asm/bootinfo.h>
1768 +#include <asm/irq.h>
1769 +#include <asm/mips-boards/generic.h>
1770 +#include <asm/mips-boards/prom.h>
1771 +
1772 +#include <asm/dma.h>
1773 +#include <asm/time.h>
1774 +#include <asm/traps.h>
1775 +
1776 +#ifdef CONFIG_KGDB
1777 +extern void rs_kgdb_hook(int);
1778 +int remote_debug = 0;
1779 +#endif
1780 +
1781 +extern struct rtc_ops no_rtc_ops;
1782 +
1783 +extern void ar7_reboot_setup(void);
1784 +
1785 +extern void ar7_time_init(void);
1786 +extern void ar7_timer_setup(struct irqaction *irq);
1787 +
1788 +const char *get_system_type(void)
1789 +{
1790 +       return "Texas Instruments AR7";
1791 +}
1792 +
1793 +void __init ar7_setup(void)
1794 +{
1795 +#ifdef CONFIG_KGDB
1796 +       int rs_putDebugChar(char);
1797 +       char rs_getDebugChar(void);
1798 +       extern int (*generic_putDebugChar)(char);
1799 +       extern char (*generic_getDebugChar)(void);
1800 +#endif
1801 +       char *argptr;
1802 +#ifdef CONFIG_SERIAL_CONSOLE
1803 +       argptr = prom_getcmdline();
1804 +       if ((argptr = strstr(argptr, "console=")) == NULL) {
1805 +               char console[20];
1806 +               char *s;
1807 +               int i = 0;
1808 +
1809 +               s = prom_getenv("modetty0");
1810 +               strcpy(console, "38400");
1811 +
1812 +               if (s != NULL) {
1813 +                       while (s[i] >= '0' && s[i] <= '9')
1814 +                               i++;
1815 +
1816 +                       if (i > 0) {
1817 +                               strncpy(console, s, i);
1818 +                               console[i] = 0;
1819 +                       }
1820 +               }
1821 +
1822 +               argptr = prom_getcmdline();
1823 +               strcat(argptr, " console=ttyS0,");
1824 +               strcat(argptr, console);
1825 +       }
1826 +#endif
1827 +
1828 +#ifdef CONFIG_KGDB
1829 +       argptr = prom_getcmdline();
1830 +       if ((argptr = strstr(argptr, "kgdb=ttyS")) != NULL) {
1831 +               int line;
1832 +               argptr += strlen("kgdb=ttyS");
1833 +               if (*argptr != '0' && *argptr != '1')
1834 +                       printk("KGDB: Uknown serial line /dev/ttyS%c, "
1835 +                                       "falling back to /dev/ttyS1\n", *argptr);
1836 +               line = *argptr == '0' ? 0 : 1;
1837 +               printk("KGDB: Using serial line /dev/ttyS%d for session\n",
1838 +                               line ? 1 : 0);
1839 +
1840 +               rs_kgdb_hook(line);
1841 +               generic_putDebugChar = rs_putDebugChar;
1842 +               generic_getDebugChar = rs_getDebugChar;
1843 +
1844 +               prom_printf("KGDB: Using serial line /dev/ttyS%d for session, "
1845 +                               "please connect your debugger\n", line ? 1 : 0);
1846 +
1847 +               remote_debug = 1;
1848 +               /* Breakpoints are in init_IRQ() */
1849 +       }
1850 +#endif
1851 +
1852 +       argptr = prom_getcmdline();
1853 +       if ((argptr = strstr(argptr, "nofpu")) != NULL)
1854 +               cpu_data[0].options &= ~MIPS_CPU_FPU;
1855 +
1856 +       rtc_ops = &no_rtc_ops;
1857 +
1858 +       ar7_reboot_setup();
1859 +
1860 +       board_time_init = ar7_time_init;
1861 +       board_timer_setup = ar7_timer_setup;
1862 +}
1863 diff -urN kernel-base/arch/mips/ar7/time.c kernel-tmp2/arch/mips/ar7/time.c
1864 --- kernel-base/arch/mips/ar7/time.c    1970-01-01 01:00:00.000000000 +0100
1865 +++ kernel-tmp2/arch/mips/ar7/time.c    2005-07-10 06:40:39.588266256 +0200
1866 @@ -0,0 +1,125 @@
1867 +/*
1868 + * Carsten Langgaard, carstenl@mips.com
1869 + * Copyright (C) 1999,2000 MIPS Technologies, Inc.  All rights reserved.
1870 + *
1871 + * ########################################################################
1872 + *
1873 + *  This program is free software; you can distribute it and/or modify it
1874 + *  under the terms of the GNU General Public License (Version 2) as
1875 + *  published by the Free Software Foundation.
1876 + *
1877 + *  This program is distributed in the hope it will be useful, but WITHOUT
1878 + *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
1879 + *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
1880 + *  for more details.
1881 + *
1882 + *  You should have received a copy of the GNU General Public License along
1883 + *  with this program; if not, write to the Free Software Foundation, Inc.,
1884 + *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
1885 + *
1886 + * ########################################################################
1887 + *
1888 + * Setting up the clock on the MIPS boards.
1889 + *
1890 + */
1891 +
1892 +#include <linux/types.h>
1893 +#include <linux/config.h>
1894 +#include <linux/init.h>
1895 +#include <linux/kernel_stat.h>
1896 +#include <linux/sched.h>
1897 +#include <linux/spinlock.h>
1898 +
1899 +#include <asm/mipsregs.h>
1900 +#include <asm/ptrace.h>
1901 +#include <asm/hardirq.h>
1902 +#include <asm/div64.h>
1903 +
1904 +#include <linux/interrupt.h>
1905 +#include <linux/mc146818rtc.h>
1906 +#include <linux/timex.h>
1907 +
1908 +#include <asm/mips-boards/generic.h>
1909 +#include <asm/mips-boards/prom.h>
1910 +#include <asm/ar7/ar7.h>
1911 +
1912 +extern asmlinkage void mipsIRQ(void);
1913 +
1914 +static unsigned long r4k_offset; /* Amount to increment compare reg each time */
1915 +static unsigned long r4k_cur;    /* What counter should be at next timer irq */
1916 +
1917 +#define MIPS_CPU_TIMER_IRQ 7
1918 +#define ALLINTS (IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4 | IE_IRQ5)
1919 +
1920 +static inline void ack_r4ktimer(unsigned long newval)
1921 +{
1922 +       write_c0_compare(newval);
1923 +}
1924 +
1925 +void ar7_timer_interrupt(struct pt_regs *regs)
1926 +{
1927 +       int cpu = smp_processor_id();
1928 +
1929 +       irq_enter(cpu, MIPS_CPU_TIMER_IRQ);
1930 +
1931 +       if (r4k_offset == 0)
1932 +               goto null;
1933 +
1934 +       do {
1935 +               kstat.irqs[cpu][MIPS_CPU_TIMER_IRQ]++;
1936 +               do_timer(regs);
1937 +               r4k_cur += r4k_offset;
1938 +               ack_r4ktimer(r4k_cur);
1939 +
1940 +       } while (((unsigned long)read_c0_count()
1941 +                               - r4k_cur) < 0x7fffffff);
1942 +
1943 +       irq_exit(cpu, MIPS_CPU_TIMER_IRQ);
1944 +
1945 +       if (softirq_pending(cpu))
1946 +               do_softirq();
1947 +
1948 +       return;
1949 +
1950 +null:
1951 +       ack_r4ktimer(0);
1952 +}
1953 +
1954 +/*
1955 + * Figure out the r4k offset, the amount to increment the compare
1956 + * register for each time tick.
1957 + */
1958 +static unsigned long __init cal_r4koff(void)
1959 +{
1960 +       return ((CONFIG_AR7_CPU_FREQUENCY*500000)/HZ);
1961 +}
1962 +
1963 +void __init ar7_time_init(void)
1964 +{
1965 +       unsigned long flags;
1966 +       unsigned int est_freq;
1967 +
1968 +       set_except_vector(0, mipsIRQ);
1969 +       write_c0_count(0);
1970 +
1971 +       printk("calculating r4koff... ");
1972 +       r4k_offset = cal_r4koff();
1973 +       printk("%08lx(%d)\n", r4k_offset, (int) r4k_offset);
1974 +
1975 +       est_freq = 2*r4k_offset*HZ;
1976 +       est_freq += 5000;    /* round */
1977 +       est_freq -= est_freq%10000;
1978 +       printk("CPU frequency %d.%02d MHz\n", est_freq/1000000,
1979 +                       (est_freq%1000000)*100/1000000);
1980 +}
1981 +
1982 +void __init ar7_timer_setup(struct irqaction *irq)
1983 +{
1984 +       /* we are using the cpu counter for timer interrupts */
1985 +       irq->handler = no_action;     /* we use our own handler */
1986 +       setup_irq(MIPS_CPU_TIMER_IRQ, irq);
1987 +
1988 +       r4k_cur = (read_c0_count() + r4k_offset);
1989 +       write_c0_compare(r4k_cur);
1990 +       set_c0_status(ALLINTS);
1991 +}
1992 diff -urN kernel-base/arch/mips/config-shared.in kernel-tmp2/arch/mips/config-shared.in
1993 --- kernel-base/arch/mips/config-shared.in      2005-07-10 03:00:44.784181376 +0200
1994 +++ kernel-tmp2/arch/mips/config-shared.in      2005-07-10 06:40:39.589266104 +0200
1995 @@ -20,6 +20,16 @@
1996  mainmenu_option next_comment
1997  comment 'Machine selection'
1998  dep_bool 'Support for Acer PICA 1 chipset (EXPERIMENTAL)' CONFIG_ACER_PICA_61 $CONFIG_EXPERIMENTAL
1999 +dep_bool 'Support for Texas Instruments AR7 (EXPERIMENTAL)' CONFIG_AR7 $CONFIG_MIPS32 $CONFIG_EXPERIMENTAL
2000 +if [ "$CONFIG_AR7" = "y" ]; then
2001 +   choice 'Texas Instruments Reference Platform' \
2002 +      "AR7DB CONFIG_AR7DB \
2003 +      AR7RD CONFIG_AR7RD \
2004 +      AR7WRD CONFIG_AR7WRD" AR7DB
2005 +   int 'Texas Instruments AR7 CPU Frequency' CONFIG_AR7_CPU_FREQUENCY 150
2006 +   int 'Texas Instruments AR7 System Frequency' CONFIG_AR7_SYS_FREQUENCY 125
2007 +   hex 'Texas Instruments AR7 SDRAM Start' CONFIG_AR7_MEMORY 0x14000000
2008 +fi
2009  dep_bool 'Support for Alchemy Bosporus board' CONFIG_MIPS_BOSPORUS $CONFIG_MIPS32
2010  dep_bool 'Support for FIC Multimedia Player board' CONFIG_MIPS_FICMMP $CONFIG_MIPS32
2011  dep_bool 'Support for Alchemy Mirage board' CONFIG_MIPS_MIRAGE $CONFIG_MIPS32
2012 @@ -239,6 +249,11 @@
2013     define_bool CONFIG_NONCOHERENT_IO y
2014     define_bool CONFIG_PC_KEYB y
2015  fi
2016 +if [ "$CONFIG_AR7" = "y" ]; then
2017 +   define_bool CONFIG_NONCOHERENT_IO y
2018 +   define_bool CONFIG_SWAP_IO_SPACE y
2019 +   define_bool CONFIG_AR7_PAGING y
2020 +fi
2021  if [ "$CONFIG_CASIO_E55" = "y" ]; then
2022     define_bool CONFIG_IRQ_CPU y
2023     define_bool CONFIG_NONCOHERENT_IO y
2024 @@ -736,6 +751,7 @@
2025  mainmenu_option next_comment
2026  comment 'General setup'
2027  if [ "$CONFIG_ACER_PICA_61" = "y" -o \
2028 +     "$CONFIG_AR7" = "y" -o \
2029       "$CONFIG_CASIO_E55" = "y" -o \
2030       "$CONFIG_DDB5074" = "y" -o \
2031       "$CONFIG_DDB5476" = "y" -o \
2032 @@ -797,6 +813,7 @@
2033  bool 'Networking support' CONFIG_NET
2034
2035  if [ "$CONFIG_ACER_PICA_61" = "y" -o \
2036 +     "$CONFIG_AR7" = "y" -o \
2037       "$CONFIG_CASIO_E55" = "y" -o \
2038       "$CONFIG_DECSTATION" = "y" -o \
2039       "$CONFIG_IBM_WORKPAD" = "y" -o \
2040 diff -urN kernel-base/arch/mips/kernel/irq.c kernel-tmp2/arch/mips/kernel/irq.c
2041 --- kernel-base/arch/mips/kernel/irq.c  2005-07-10 03:00:44.784181376 +0200
2042 +++ kernel-tmp2/arch/mips/kernel/irq.c  2005-07-10 06:40:39.589266104 +0200
2043 @@ -76,6 +76,7 @@
2044   * Generic, controller-independent functions:
2045   */
2046
2047 +#ifndef CONFIG_AR7
2048  int get_irq_list(char *buf)
2049  {
2050         int i, j;
2051 @@ -110,6 +111,7 @@
2052         p += sprintf(p, "ERR: %10u\n", atomic_read(&irq_err_count));
2053         return p - buf;
2054  }
2055 +#endif
2056
2057  #ifdef CONFIG_SMP
2058  int global_irq_holder = NO_PROC_ID;
2059 @@ -525,6 +527,7 @@
2060   *
2061   */
2062
2063 +#ifndef CONFIG_AR7
2064  int request_irq(unsigned int irq,
2065                 void (*handler)(int, void *, struct pt_regs *),
2066                 unsigned long irqflags,
2067 @@ -569,6 +572,7 @@
2068                 kfree(action);
2069         return retval;
2070  }
2071 +#endif
2072
2073  /**
2074   *     free_irq - free an interrupt
2075 @@ -588,6 +592,7 @@
2076   *           the machine.
2077   */
2078
2079 +#ifndef CONFIG_AR7
2080  void free_irq(unsigned int irq, void *dev_id)
2081  {
2082         irq_desc_t *desc;
2083 @@ -629,6 +634,7 @@
2084                 return;
2085         }
2086  }
2087 +#endif
2088
2089  /*
2090   * IRQ autodetection code..
2091 diff -urN kernel-base/arch/mips/kernel/setup.c kernel-tmp2/arch/mips/kernel/setup.c
2092 --- kernel-base/arch/mips/kernel/setup.c        2005-07-10 03:00:44.785181224 +0200
2093 +++ kernel-tmp2/arch/mips/kernel/setup.c        2005-07-10 06:40:39.590265952 +0200
2094 @@ -109,6 +109,7 @@
2095  unsigned long isa_slot_offset;
2096  EXPORT_SYMBOL(isa_slot_offset);
2097
2098 +extern void avalanche_bootmem_init(void);
2099  extern void SetUpBootInfo(void);
2100  extern void load_mmu(void);
2101  extern asmlinkage void start_kernel(void);
2102 @@ -267,6 +268,9 @@
2103  #endif /* CONFIG_BLK_DEV_INITRD */
2104
2105         /* Find the highest page frame number we have available.  */
2106 +#ifdef CONFIG_AR7_PAGING
2107 +       avalanche_bootmem_init();
2108 +#else
2109         max_pfn = 0;
2110         first_usable_pfn = -1UL;
2111         for (i = 0; i < boot_mem_map.nr_map; i++) {
2112 @@ -377,6 +381,7 @@
2113         /* Reserve the bootmap memory.  */
2114         reserve_bootmem(PFN_PHYS(first_usable_pfn), bootmap_size);
2115
2116 +#endif
2117  #ifdef CONFIG_BLK_DEV_INITRD
2118         /* Board specific code should have set up initrd_start and initrd_end */
2119         ROOT_DEV = MKDEV(RAMDISK_MAJOR, 0);
2120 @@ -494,6 +499,7 @@
2121         void hp_setup(void);
2122         void au1x00_setup(void);
2123         void frame_info_init(void);
2124 +       void ar7_setup(void);
2125
2126         frame_info_init();
2127  #if defined(CONFIG_BLK_DEV_FD) || defined(CONFIG_BLK_DEV_FD_MODULE)
2128 @@ -691,6 +697,11 @@
2129                  pmc_yosemite_setup();
2130                  break;
2131  #endif
2132 +#ifdef CONFIG_AR7
2133 +       case MACH_GROUP_UNKNOWN:
2134 +               ar7_setup();
2135 +               break;
2136 +#endif
2137         default:
2138                 panic("Unsupported architecture");
2139         }
2140 diff -urN kernel-base/arch/mips/kernel/traps.c kernel-tmp2/arch/mips/kernel/traps.c
2141 --- kernel-base/arch/mips/kernel/traps.c        2005-07-10 03:00:44.786181072 +0200
2142 +++ kernel-tmp2/arch/mips/kernel/traps.c        2005-07-10 06:40:39.591265800 +0200
2143 @@ -40,6 +40,10 @@
2144  #include <asm/uaccess.h>
2145  #include <asm/mmu_context.h>
2146
2147 +#ifdef CONFIG_AR7
2148 +#include <asm/ar7/ar7.h>
2149 +#endif
2150 +
2151  extern asmlinkage void handle_mod(void);
2152  extern asmlinkage void handle_tlbl(void);
2153  extern asmlinkage void handle_tlbs(void);
2154 @@ -869,9 +873,15 @@
2155
2156         exception_handlers[n] = handler;
2157         if (n == 0 && cpu_has_divec) {
2158 +#ifdef CONFIG_AR7
2159 +               *(volatile u32 *)(AVALANCHE_VECS_KSEG0+0x200) = 0x08000000 |
2160 +                       (0x03ffffff & (handler >> 2));
2161 +               flush_icache_range(AVALANCHE_VECS_KSEG0+0x200, AVALANCHE_VECS_KSEG0 + 0x204);
2162 +#else
2163                 *(volatile u32 *)(KSEG0+0x200) = 0x08000000 |
2164                                                  (0x03ffffff & (handler >> 2));
2165                 flush_icache_range(KSEG0+0x200, KSEG0 + 0x204);
2166 +#endif
2167         }
2168         return (void *)old_handler;
2169  }
2170 @@ -920,14 +930,46 @@
2171  void __init trap_init(void)
2172  {
2173         extern char except_vec1_generic;
2174 +       extern char except_vec2_generic;
2175         extern char except_vec3_generic, except_vec3_r4000;
2176         extern char except_vec_ejtag_debug;
2177         extern char except_vec4;
2178         unsigned long i;
2179
2180 +#ifdef CONFIG_AR7
2181 +       extern char jump_tlb_miss, jump_tlb_miss_unused;
2182 +       extern char jump_cache_error,jump_general_exception;
2183 +       extern char jump_dedicated_interrupt;
2184 +       clear_c0_status(ST0_BEV);
2185 +#endif
2186 +
2187         /* Copy the generic exception handler code to it's final destination. */
2188         memcpy((void *)(KSEG0 + 0x80), &except_vec1_generic, 0x80);
2189 +       memcpy((void *)(KSEG0 + 0x100), &except_vec2_generic, 0x80);
2190 +       memcpy((void *)(KSEG0 + 0x180), &except_vec3_generic, 0x80);
2191
2192 +       memcpy((void *)(KSEG0 + 0x0),   &jump_tlb_miss, 0x80);
2193 +       memcpy((void *)(KSEG0 + 0x80),  &jump_tlb_miss_unused, 0x80);
2194 +       memcpy((void *)(KSEG0 + 0x100), &jump_cache_error, 0x80);
2195 +       memcpy((void *)(KSEG0 + 0x180), &jump_general_exception, 0x80);
2196 +       memcpy((void *)(KSEG0 + 0x200), &jump_dedicated_interrupt, 0x80);
2197 +
2198 +#ifdef CONFIG_AR7
2199 +       memcpy((void *)(AVALANCHE_VECS_KSEG0 + 0x80), &except_vec1_generic, 0x80);
2200 +       memcpy((void *)(AVALANCHE_VECS_KSEG0 + 0x100), &except_vec2_generic, 0x80);
2201 +       memcpy((void *)(AVALANCHE_VECS_KSEG0 + 0x180), &except_vec3_generic, 0x80);
2202 +       flush_icache_range(AVALANCHE_VECS_KSEG0, AVALANCHE_VECS_KSEG0 + 0x200);
2203 +
2204 +       memcpy((void *)(KSEG0 + 0x0),   &jump_tlb_miss, 0x80);
2205 +       memcpy((void *)(KSEG0 + 0x80),  &jump_tlb_miss_unused, 0x80);
2206 +       memcpy((void *)(KSEG0 + 0x100), &jump_cache_error, 0x80);
2207 +       memcpy((void *)(KSEG0 + 0x180), &jump_general_exception, 0x80);
2208 +       memcpy((void *)(KSEG0 + 0x200), &jump_dedicated_interrupt, 0x80);
2209 +#else
2210 +       memcpy((void *)(KSEG0 + 0x80), &except_vec1_generic, 0x80);
2211 +#endif
2212 +       flush_icache_range(KSEG0 + 0x80, KSEG0 + 0x200);
2213 +
2214         /*
2215          * Setup default vectors
2216          */
2217 @@ -951,8 +993,12 @@
2218          * Some MIPS CPUs have a dedicated interrupt vector which reduces the
2219          * interrupt processing overhead.  Use it where available.
2220          */
2221 +#ifdef CONFIG_AR7
2222 +       memcpy((void *)(AVALANCHE_VECS_KSEG0 + 0x200), &except_vec4, 8);
2223 +#else
2224         if (cpu_has_divec)
2225                 memcpy((void *)(KSEG0 + 0x200), &except_vec4, 8);
2226 +#endif
2227
2228         /*
2229          * Some CPUs can enable/disable for cache parity detection, but does
2230 @@ -991,12 +1037,17 @@
2231         if (cpu_has_mcheck)
2232                 set_except_vector(24, handle_mcheck);
2233
2234 +memcpy((void *)(KSEG0 + 0x180), &except_vec3_generic, 0x80);
2235 +#ifdef CONFIG_AR7
2236 +       memcpy((void *)(AVALANCHE_VECS_KSEG0 + 0x180), &except_vec3_generic, 0x80);
2237 +#else
2238         if (cpu_has_vce)
2239                 memcpy((void *)(KSEG0 + 0x180), &except_vec3_r4000, 0x80);
2240         else if (cpu_has_4kex)
2241                 memcpy((void *)(KSEG0 + 0x180), &except_vec3_generic, 0x80);
2242         else
2243                 memcpy((void *)(KSEG0 + 0x080), &except_vec3_generic, 0x80);
2244 +#endif
2245
2246         if (current_cpu_data.cputype == CPU_R6000 ||
2247             current_cpu_data.cputype == CPU_R6000A) {
2248 @@ -1023,7 +1074,11 @@
2249         if (board_nmi_handler_setup)
2250                 board_nmi_handler_setup();
2251
2252 +#ifdef CONFIG_AR7
2253 +       flush_icache_range(AVALANCHE_VECS_KSEG0, AVALANCHE_VECS_KSEG0 + 0x200);
2254 +#else
2255         flush_icache_range(KSEG0, KSEG0 + 0x400);
2256 +#endif
2257
2258         per_cpu_trap_init();
2259  }
2260 diff -urN kernel-base/arch/mips/lib/promlib.c kernel-tmp2/arch/mips/lib/promlib.c
2261 --- kernel-base/arch/mips/lib/promlib.c 2005-07-10 03:00:44.786181072 +0200
2262 +++ kernel-tmp2/arch/mips/lib/promlib.c 2005-07-10 06:40:39.591265800 +0200
2263 @@ -1,3 +1,4 @@
2264 +#ifndef CONFIG_AR7
2265  #include <stdarg.h>
2266  #include <linux/kernel.h>
2267
2268 @@ -22,3 +23,4 @@
2269         }
2270         va_end(args);
2271  }
2272 +#endif
2273 diff -urN kernel-base/arch/mips/Makefile kernel-tmp2/arch/mips/Makefile
2274 --- kernel-base/arch/mips/Makefile      2005-07-10 03:00:44.786181072 +0200
2275 +++ kernel-tmp2/arch/mips/Makefile      2005-07-10 06:40:39.591265800 +0200
2276 @@ -369,6 +369,16 @@
2277  endif
2278
2279  #
2280 +# Texas Instruments AR7
2281 +#
2282 +
2283 +ifdef CONFIG_AR7
2284 +LIBS           += arch/mips/ar7/ar7.o arch/mips/ar7/ar7/ar7.o
2285 +SUBDIRS                += arch/mips/ar7 arch/mips/ar7/ar7
2286 +LOADADDR       += 0x94020000
2287 +endif
2288 +
2289 +#
2290  # DECstation family
2291  #
2292  ifdef CONFIG_DECSTATION
2293 diff -urN kernel-base/arch/mips/mm/init.c kernel-tmp2/arch/mips/mm/init.c
2294 --- kernel-base/arch/mips/mm/init.c     2005-07-10 03:00:44.787180920 +0200
2295 +++ kernel-tmp2/arch/mips/mm/init.c     2005-07-10 07:09:29.914216728 +0200
2296 @@ -40,8 +40,10 @@
2297
2298  mmu_gather_t mmu_gathers[NR_CPUS];
2299  unsigned long highstart_pfn, highend_pfn;
2300 +#ifndef CONFIG_AR7_PAGING
2301  static unsigned long totalram_pages;
2302  static unsigned long totalhigh_pages;
2303 +#endif
2304
2305  void pgd_init(unsigned long page)
2306  {
2307 @@ -235,6 +237,7 @@
2308  #endif
2309  }
2310
2311 +#ifndef CONFIG_AR7_PAGING
2312  void __init paging_init(void)
2313  {
2314         unsigned long zones_size[MAX_NR_ZONES] = {0, 0, 0};
2315 @@ -272,6 +275,7 @@
2316
2317         free_area_init(zones_size);
2318  }
2319 +#endif
2320
2321  #define PFN_UP(x)      (((x) + PAGE_SIZE - 1) >> PAGE_SHIFT)
2322  #define PFN_DOWN(x)    ((x) >> PAGE_SHIFT)
2323 @@ -298,6 +302,7 @@
2324         return 0;
2325  }
2326
2327 +#ifndef CONFIG_AR7_PAGING
2328  void __init mem_init(void)
2329  {
2330         unsigned long codesize, reservedpages, datasize, initsize;
2331 @@ -359,6 +364,7 @@
2332                initsize >> 10,
2333                (unsigned long) (totalhigh_pages << (PAGE_SHIFT-10)));
2334  }
2335 +#endif
2336
2337  #ifdef CONFIG_BLK_DEV_INITRD
2338  void free_initrd_mem(unsigned long start, unsigned long end)
2339 @@ -376,6 +382,7 @@
2340  }
2341  #endif
2342
2343 +#ifndef CONFIG_AR7_PAGING
2344  extern char __init_begin, __init_end;
2345  extern void prom_free_prom_memory(void) __init;
2346
2347 @@ -383,7 +390,9 @@
2348  {
2349         unsigned long addr;
2350
2351 +#ifndef CONFIG_AR7
2352         prom_free_prom_memory ();
2353 +#endif
2354
2355         addr = (unsigned long) &__init_begin;
2356         while (addr < (unsigned long) &__init_end) {
2357 @@ -409,3 +418,4 @@
2358
2359         return;
2360  }
2361 +#endif
2362 diff -urN kernel-base/arch/mips/mm/tlb-r4k.c kernel-tmp2/arch/mips/mm/tlb-r4k.c
2363 --- kernel-base/arch/mips/mm/tlb-r4k.c  2005-07-10 03:00:44.787180920 +0200
2364 +++ kernel-tmp2/arch/mips/mm/tlb-r4k.c  2005-07-10 06:40:39.592265648 +0200
2365 @@ -20,6 +20,10 @@
2366  #include <asm/pgtable.h>
2367  #include <asm/system.h>
2368
2369 +#ifdef CONFIG_AR7
2370 +#include <asm/ar7/ar7.h>
2371 +#endif
2372 +
2373  extern char except_vec0_nevada, except_vec0_r4000, except_vec0_r4600;
2374
2375  /* CP0 hazard avoidance. */
2376 @@ -375,7 +379,12 @@
2377                 else if (current_cpu_data.cputype == CPU_R4600)
2378                         memcpy((void *)KSEG0, &except_vec0_r4600, 0x80);
2379                 else
2380 +#ifdef CONFIG_AR7
2381 +                       memcpy((void *)AVALANCHE_VECS_KSEG0, &except_vec0_r4000, 0x80);
2382 +               flush_icache_range(AVALANCHE_VECS_KSEG0, AVALANCHE_VECS_KSEG0 + 0x80);
2383 +#else
2384                         memcpy((void *)KSEG0, &except_vec0_r4000, 0x80);
2385                 flush_icache_range(KSEG0, KSEG0 + 0x80);
2386 +#endif
2387         }
2388  }
2389 diff -urN kernel-base/drivers/char/serial.c kernel-tmp2/drivers/char/serial.c
2390 --- kernel-base/drivers/char/serial.c   2005-07-10 03:00:44.789180616 +0200
2391 +++ kernel-tmp2/drivers/char/serial.c   2005-07-10 06:42:02.902600552 +0200
2392 @@ -419,7 +419,40 @@
2393         return 0;
2394  }
2395
2396 -#if defined(CONFIG_MIPS_ATLAS) || defined(CONFIG_MIPS_SEAD)
2397 +#if defined(CONFIG_AR7)
2398 +
2399 +static _INLINE_ unsigned int serial_in(struct async_struct *info, int offset)
2400 +{
2401 +       return (inb(info->port + (offset * 4)) & 0xff);
2402 +}
2403 +
2404 +
2405 +static _INLINE_ unsigned int serial_inp(struct async_struct *info, int offset)
2406 +{
2407 +#ifdef CONFIG_SERIAL_NOPAUSE_IO
2408 +       return (inb(info->port + (offset * 4)) & 0xff);
2409 +#else
2410 +       return (inb_p(info->port + (offset * 4)) & 0xff);
2411 +#endif
2412 +}
2413 +
2414 +static _INLINE_ void serial_out(struct async_struct *info, int offset, int value)
2415 +{
2416 +       outb(value, info->port + (offset * 4));
2417 +}
2418 +
2419 +
2420 +static _INLINE_ void serial_outp(struct async_struct *info, int offset,
2421 +               int value)
2422 +{
2423 +#ifdef CONFIG_SERIAL_NOPAUSE_IO
2424 +       outb(value, info->port + (offset * 4));
2425 +#else
2426 +       outb_p(value, info->port + (offset * 4));
2427 +#endif
2428 +}
2429 +
2430 +#elif defined(CONFIG_MIPS_ATLAS) || defined(CONFIG_MIPS_SEAD)
2431
2432  #include <asm/mips-boards/atlas.h>
2433
2434 @@ -478,8 +511,10 @@
2435   * needed for certain old 386 machines, I've left these #define's
2436   * in....
2437   */
2438 +#ifndef CONFIG_AR7
2439  #define serial_inp(info, offset)               serial_in(info, offset)
2440  #define serial_outp(info, offset, value)       serial_out(info, offset, value)
2441 +#endif
2442
2443
2444  /*
2445 @@ -1728,7 +1763,16 @@
2446                         /* Special case since 134 is really 134.5 */
2447                         quot = (2*baud_base / 269);
2448                 else if (baud)
2449 +#ifdef CONFIG_AR7
2450 +                       quot = (CONFIG_AR7_SYS_FREQUENCY*500000) / baud;
2451 +                       //quot = get_avalanche_vbus_freq() / baud;
2452 +
2453 +               if ((quot%16)>7)
2454 +                       quot += 8;
2455 +               quot /=16;
2456 +#else
2457                         quot = baud_base / baud;
2458 +#endif
2459         }
2460         /* If the quotient is zero refuse the change */
2461         if (!quot && old_termios) {
2462 @@ -5552,8 +5596,10 @@
2463                 state->irq = irq_cannonicalize(state->irq);
2464                 if (state->hub6)
2465                         state->io_type = SERIAL_IO_HUB6;
2466 +#ifndef CONFIG_AR7
2467                 if (state->port && check_region(state->port,8))
2468                         continue;
2469 +#endif
2470  #ifdef CONFIG_MCA
2471                 if ((state->flags & ASYNC_BOOT_ONLYMCA) && !MCA_bus)
2472                         continue;
2473 @@ -6009,7 +6055,16 @@
2474         info->io_type = state->io_type;
2475         info->iomem_base = state->iomem_base;
2476         info->iomem_reg_shift = state->iomem_reg_shift;
2477 +#ifdef CONFIG_AR7
2478 +       //quot = get_avalanche_vbus_freq() / baud;
2479 +       quot = (CONFIG_AR7_SYS_FREQUENCY*500000) / baud;
2480 +
2481 +       if ((quot%16)>7)
2482 +               quot += 8;
2483 +       quot /=16;
2484 +#else
2485         quot = state->baud_base / baud;
2486 +#endif
2487         cval = cflag & (CSIZE | CSTOPB);
2488  #if defined(__powerpc__) || defined(__alpha__)
2489         cval >>= 8;
2490 diff -urN kernel-base/include/asm-mips/ar7/ar7.h kernel-tmp2/include/asm-mips/ar7/ar7.h
2491 --- kernel-base/include/asm-mips/ar7/ar7.h      1970-01-01 01:00:00.000000000 +0100
2492 +++ kernel-tmp2/include/asm-mips/ar7/ar7.h      2005-07-10 06:40:39.622261088 +0200
2493 @@ -0,0 +1,33 @@
2494 +/*
2495 + * $Id$
2496 + * Copyright (C) $Date$  $Author$
2497 + *
2498 + * This program is free software; you can redistribute it and/or modify
2499 + * it under the terms of the GNU General Public License as published by
2500 + * the Free Software Foundation; either version 2 of the License, or
2501 + * (at your option) any later version.
2502 + *
2503 + * This program is distributed in the hope that it will be useful,
2504 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
2505 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
2506 + * GNU General Public License for more details.
2507 + *
2508 + * You should have received a copy of the GNU General Public License
2509 + * along with this program; if not, write to the Free Software
2510 + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
2511 + *
2512 + */
2513 +
2514 +#ifndef _AR7_H
2515 +#define _AR7_H
2516 +
2517 +#include <asm/addrspace.h>
2518 +#include <linux/config.h>
2519 +
2520 +#define AVALANCHE_VECS_KSEG0 (KSEG0ADDR(CONFIG_AR7_MEMORY))
2521 +
2522 +#define AR7_UART0_REGS_BASE (KSEG1ADDR(0x08610E00))
2523 +#define AR7_UART1_REGS_BASE (KSEG1ADDR(0x08610E00))
2524 +#define AR7_BASE_BAUD ( 3686400 / 16 )
2525 +
2526 +#endif
2527 diff -urN kernel-base/include/asm-mips/ar7/avalanche_intc.h kernel-tmp2/include/asm-mips/ar7/avalanche_intc.h
2528 --- kernel-base/include/asm-mips/ar7/avalanche_intc.h   1970-01-01 01:00:00.000000000 +0100
2529 +++ kernel-tmp2/include/asm-mips/ar7/avalanche_intc.h   2005-07-10 06:40:39.622261088 +0200
2530 @@ -0,0 +1,278 @@
2531 + /*
2532 + * Nitin Dhingra, iamnd@ti.com
2533 + * Copyright (C) 2000 Texas Instruments Inc.
2534 + *
2535 + *
2536 + * ########################################################################
2537 + *
2538 + *  This program is free software; you can distribute it and/or modify it
2539 + *  under the terms of the GNU General Public License (Version 2) as
2540 + *  published by the Free Software Foundation.
2541 + *
2542 + *  This program is distributed in the hope it will be useful, but WITHOUT
2543 + *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
2544 + *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
2545 + *  for more details.
2546 + *
2547 + *  You should have received a copy of the GNU General Public License along
2548 + *  with this program; if not, write to the Free Software Foundation, Inc.,
2549 + *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
2550 + *
2551 + * ########################################################################
2552 + *
2553 + * Defines of the Sead board specific address-MAP, registers, etc.
2554 + *
2555 + */
2556 +#ifndef _AVALANCHE_INTC_H
2557 +#define _AVALANCHE_INTC_H
2558 +
2559 +#define MIPS_EXCEPTION_OFFSET 8
2560 +
2561 +/******************************************************************************
2562 + Avalanche Interrupt number
2563 +******************************************************************************/
2564 +#define AVINTNUM(x) ((x) - MIPS_EXCEPTION_OFFSET)
2565 +
2566 +/*******************************************************************************
2567 +*Linux Interrupt number
2568 +*******************************************************************************/
2569 +#define LNXINTNUM(x)((x) + MIPS_EXCEPTION_OFFSET)
2570 +
2571 +
2572 +
2573 +#define AVALANCHE_INT_END_PRIMARY      (40 + MIPS_EXCEPTION_OFFSET)
2574 +#define AVALANCHE_INT_END_SECONDARY    (32 + MIPS_EXCEPTION_OFFSET)
2575 +
2576 +#define AVALANCHE_INT_END_PRIMARY_REG1 (31 + MIPS_EXCEPTION_OFFSET)
2577 +#define AVALANCHE_INT_END_PRIMARY_REG2 (39 + MIPS_EXCEPTION_OFFSET)
2578 +
2579 +
2580 +#define AVALANCHE_INT_END (AVINTNUM(AVALANCHE_INT_END_PRIMARY) + \
2581 +                           AVINTNUM(AVALANCHE_INT_END_SECONDARY)  \
2582 +                                    + MIPS_EXCEPTION_OFFSET - 1) /* Suraj, check */
2583 +
2584 +
2585 +/*
2586 + * Avalanche interrupt controller register base (primary)
2587 + */
2588 +#define KSEG1_BASE                  0xA0000000
2589 +#define KSEG_INV_MASK               0x1FFFFFFF /* Inverted mask for kseg address */
2590 +#define PHYS_ADDR(addr)             ((addr) & KSEG_INV_MASK)
2591 +#define PHYS_TO_K1(addr)            (PHYS_ADDR(addr)|KSEG1_BASE)
2592 +
2593 +#define AVALANCHE_ICTRL_REGS_BASE   KSEG1ADDR(0x08612400)// AVALANCHE_INTC_BASE
2594 +
2595 +/******************************************************************************
2596 + * Avalanche exception controller register base (secondary)
2597 + ******************************************************************************/
2598 +#define AVALANCHE_ECTRL_REGS_BASE  (AVALANCHE_ICTRL_REGS_BASE + 0x80)
2599 +
2600 +
2601 +/******************************************************************************
2602 + *  Avalanche Interrupt pacing register base (secondary)
2603 + ******************************************************************************/
2604 +#define AVALANCHE_IPACE_REGS_BASE  (AVALANCHE_ICTRL_REGS_BASE + 0xA0)
2605 +
2606 +
2607 +
2608 +/******************************************************************************
2609 + * Avalanche Interrupt Channel Control register base
2610 + *****************************************************************************/
2611 +#define AVALANCHE_CHCTRL_REGS_BASE (AVALANCHE_ICTRL_REGS_BASE + 0x200)
2612 +
2613 +
2614 +struct avalanche_ictrl_regs /* Avalanche Interrupt control registers */
2615 +{
2616 +  volatile unsigned long intsr1;    /* Interrupt Status/Set Register 1   0x00 */
2617 +  volatile unsigned long intsr2;    /* Interrupt Status/Set Register 2   0x04 */
2618 +  volatile unsigned long unused1;                                      /*0x08 */
2619 +  volatile unsigned long unused2;                                      /*0x0C */
2620 +  volatile unsigned long intcr1;    /* Interrupt Clear Register 1        0x10 */
2621 +  volatile unsigned long intcr2;    /* Interrupt Clear Register 2        0x14 */
2622 +  volatile unsigned long unused3;                                      /*0x18 */
2623 +  volatile unsigned long unused4;                                      /*0x1C */
2624 +  volatile unsigned long intesr1;   /* Interrupt Enable (Set) Register 1 0x20 */
2625 +  volatile unsigned long intesr2;   /* Interrupt Enable (Set) Register 2 0x24 */
2626 +  volatile unsigned long unused5;                                      /*0x28 */
2627 +  volatile unsigned long unused6;                                      /*0x2C */
2628 +  volatile unsigned long intecr1;   /* Interrupt Enable Clear Register 1 0x30 */
2629 +  volatile unsigned long intecr2;   /* Interrupt Enable Clear Register 2 0x34 */
2630 +  volatile unsigned long unused7;                                     /* 0x38 */
2631 +  volatile unsigned long unused8;                                     /* 0x3c */
2632 +  volatile unsigned long pintir;    /* Priority Interrupt Index Register 0x40 */
2633 +  volatile unsigned long intmsr;    /* Priority Interrupt Mask Index Reg 0x44 */
2634 +  volatile unsigned long unused9;                                     /* 0x48 */
2635 +  volatile unsigned long unused10;                                    /* 0x4C */
2636 +  volatile unsigned long intpolr1;  /* Interrupt Polarity Mask register 10x50 */
2637 +  volatile unsigned long intpolr2;  /* Interrupt Polarity Mask register 20x54 */
2638 +  volatile unsigned long unused11;                                    /* 0x58 */
2639 +  volatile unsigned long unused12;                                   /*0x5C */
2640 +  volatile unsigned long inttypr1;  /* Interrupt Type     Mask register 10x60 */
2641 +  volatile unsigned long inttypr2;  /* Interrupt Type     Mask register 20x64 */
2642 +};
2643 +
2644 +struct avalanche_exctrl_regs   /* Avalanche Exception control registers */
2645 +{
2646 +  volatile unsigned long exsr;      /* Exceptions Status/Set register    0x80 */
2647 +  volatile unsigned long reserved;                                     /*0x84 */
2648 +  volatile unsigned long excr;      /* Exceptions Clear Register         0x88 */
2649 +  volatile unsigned long reserved1;                                    /*0x8c */
2650 +  volatile unsigned long exiesr;    /* Exceptions Interrupt Enable (set) 0x90 */
2651 +  volatile unsigned long reserved2;                                    /*0x94 */
2652 +  volatile unsigned long exiecr;    /* Exceptions Interrupt Enable(clear)0x98 */
2653 +};
2654 +struct avalanche_ipace_regs
2655 +{
2656 +
2657 +  volatile unsigned long ipacep;    /* Interrupt pacing register         0xa0 */
2658 +  volatile unsigned long ipacemap;  /*Interrupt Pacing Map Register      0xa4 */
2659 +  volatile unsigned long ipacemax;  /*Interrupt Pacing Max Register      0xa8 */
2660 +};
2661 +struct avalanche_channel_int_number
2662 +{
2663 +  volatile unsigned long cintnr0;   /* Channel Interrupt Number Register0x200 */
2664 +  volatile unsigned long cintnr1;   /* Channel Interrupt Number Register0x204 */
2665 +  volatile unsigned long cintnr2;   /* Channel Interrupt Number Register0x208 */
2666 +  volatile unsigned long cintnr3;   /* Channel Interrupt Number Register0x20C */
2667 +  volatile unsigned long cintnr4;   /* Channel Interrupt Number Register0x210 */
2668 +  volatile unsigned long cintnr5;   /* Channel Interrupt Number Register0x214 */
2669 +  volatile unsigned long cintnr6;   /* Channel Interrupt Number Register0x218 */
2670 +  volatile unsigned long cintnr7;   /* Channel Interrupt Number Register0x21C */
2671 +  volatile unsigned long cintnr8;   /* Channel Interrupt Number Register0x220 */
2672 +  volatile unsigned long cintnr9;   /* Channel Interrupt Number Register0x224 */
2673 +  volatile unsigned long cintnr10;  /* Channel Interrupt Number Register0x228 */
2674 +  volatile unsigned long cintnr11;  /* Channel Interrupt Number Register0x22C */
2675 +  volatile unsigned long cintnr12;  /* Channel Interrupt Number Register0x230 */
2676 +  volatile unsigned long cintnr13;  /* Channel Interrupt Number Register0x234 */
2677 +  volatile unsigned long cintnr14;  /* Channel Interrupt Number Register0x238 */
2678 +  volatile unsigned long cintnr15;  /* Channel Interrupt Number Register0x23C */
2679 +  volatile unsigned long cintnr16;  /* Channel Interrupt Number Register0x240 */
2680 +  volatile unsigned long cintnr17;  /* Channel Interrupt Number Register0x244 */
2681 +  volatile unsigned long cintnr18;  /* Channel Interrupt Number Register0x248 */
2682 +  volatile unsigned long cintnr19;  /* Channel Interrupt Number Register0x24C */
2683 +  volatile unsigned long cintnr20;  /* Channel Interrupt Number Register0x250 */
2684 +  volatile unsigned long cintnr21;  /* Channel Interrupt Number Register0x254 */
2685 +  volatile unsigned long cintnr22;  /* Channel Interrupt Number Register0x358 */
2686 +  volatile unsigned long cintnr23;  /* Channel Interrupt Number Register0x35C */
2687 +  volatile unsigned long cintnr24;  /* Channel Interrupt Number Register0x260 */
2688 +  volatile unsigned long cintnr25;  /* Channel Interrupt Number Register0x264 */
2689 +  volatile unsigned long cintnr26;  /* Channel Interrupt Number Register0x268 */
2690 +  volatile unsigned long cintnr27;  /* Channel Interrupt Number Register0x26C */
2691 +  volatile unsigned long cintnr28;  /* Channel Interrupt Number Register0x270 */
2692 +  volatile unsigned long cintnr29;  /* Channel Interrupt Number Register0x274 */
2693 +  volatile unsigned long cintnr30;  /* Channel Interrupt Number Register0x278 */
2694 +  volatile unsigned long cintnr31;  /* Channel Interrupt Number Register0x27C */
2695 +  volatile unsigned long cintnr32;  /* Channel Interrupt Number Register0x280 */
2696 +  volatile unsigned long cintnr33;  /* Channel Interrupt Number Register0x284 */
2697 +  volatile unsigned long cintnr34;  /* Channel Interrupt Number Register0x288 */
2698 +  volatile unsigned long cintnr35;  /* Channel Interrupt Number Register0x28C */
2699 +  volatile unsigned long cintnr36;  /* Channel Interrupt Number Register0x290 */
2700 +  volatile unsigned long cintnr37;  /* Channel Interrupt Number Register0x294 */
2701 +  volatile unsigned long cintnr38;  /* Channel Interrupt Number Register0x298 */
2702 +  volatile unsigned long cintnr39;  /* Channel Interrupt Number Register0x29C */
2703 +};
2704 +
2705 +struct avalanche_interrupt_line_to_channel
2706 +{
2707 +  unsigned long int_line0;    /* Start of primary interrupts */
2708 +  unsigned long int_line1;
2709 +  unsigned long int_line2;
2710 +  unsigned long int_line3;
2711 +  unsigned long int_line4;
2712 +  unsigned long int_line5;
2713 +  unsigned long int_line6;
2714 +  unsigned long int_line7;
2715 +  unsigned long int_line8;
2716 +  unsigned long int_line9;
2717 +  unsigned long int_line10;
2718 +  unsigned long int_line11;
2719 +  unsigned long int_line12;
2720 +  unsigned long int_line13;
2721 +  unsigned long int_line14;
2722 +  unsigned long int_line15;
2723 +  unsigned long int_line16;
2724 +  unsigned long int_line17;
2725 +  unsigned long int_line18;
2726 +  unsigned long int_line19;
2727 +  unsigned long int_line20;
2728 +  unsigned long int_line21;
2729 +  unsigned long int_line22;
2730 +  unsigned long int_line23;
2731 +  unsigned long int_line24;
2732 +  unsigned long int_line25;
2733 +  unsigned long int_line26;
2734 +  unsigned long int_line27;
2735 +  unsigned long int_line28;
2736 +  unsigned long int_line29;
2737 +  unsigned long int_line30;
2738 +  unsigned long int_line31;
2739 +  unsigned long int_line32;
2740 +  unsigned long int_line33;
2741 +  unsigned long int_line34;
2742 +  unsigned long int_line35;
2743 +  unsigned long int_line36;
2744 +  unsigned long int_line37;
2745 +  unsigned long int_line38;
2746 +  unsigned long int_line39;
2747 +};
2748 +
2749 +
2750 +/* Interrupt Line #'s  (Sangam peripherals) */
2751 +
2752 +/*------------------------------*/
2753 +/* Sangam primary interrupts */
2754 +/*------------------------------*/
2755 +
2756 +#define UNIFIED_SECONDARY_INTERRUPT  0
2757 +#define AVALANCHE_EXT_INT_0          1
2758 +#define AVALANCHE_EXT_INT_1          2
2759 +/*  Line #3  Reserved               */
2760 +/*  Line #4  Reserved               */
2761 +#define AVALANCHE_TIMER_0_INT        5
2762 +#define AVALANCHE_TIMER_1_INT        6
2763 +#define AVALANCHE_UART0_INT          7
2764 +#define AVALANCHE_UART1_INT          8
2765 +#define AVALANCHE_PDMA_INT0          9
2766 +#define AVALANCHE_PDMA_INT1          10
2767 +/*  Line #11  Reserved               */
2768 +/*  Line #12  Reserved               */
2769 +/*  Line #13  Reserved               */
2770 +/*  Line #14  Reserved               */
2771 +#define AVALANCHE_ATM_SAR_INT        15
2772 +/*  Line #16  Reserved               */
2773 +/*  Line #17  Reserved               */
2774 +/*  Line #18  Reserved               */
2775 +#define AVALANCHE_MAC0_INT           19
2776 +/*  Line #20  Reserved               */
2777 +#define AVALANCHE_VLYNQ0_INT         21
2778 +#define AVALANCHE_CODEC_WAKE_INT     22
2779 +/*  Line #23  Reserved               */
2780 +#define AVALANCHE_USB_INT            24
2781 +#define AVALANCHE_VLYNQ1_INT         25
2782 +/*  Line #26  Reserved               */
2783 +/*  Line #27  Reserved               */
2784 +#define AVALANCHE_MAC1_INT           28
2785 +#define AVALANCHE_I2CM_INT           29
2786 +#define AVALANCHE_PDMA_INT2          30
2787 +#define AVALANCHE_PDMA_INT3          31
2788 +/*  Line #32  Reserved               */
2789 +/*  Line #33  Reserved               */
2790 +/*  Line #34  Reserved               */
2791 +/*  Line #35  Reserved               */
2792 +/*  Line #36  Reserved               */
2793 +#define AVALANCHE_VDMA_VT_RX_INT     37
2794 +#define AVALANCHE_VDMA_VT_TX_INT     38
2795 +#define AVALANCHE_ADSLSS_INT         39
2796 +
2797 +/*-----------------------------------*/
2798 +/* Sangam Secondary Interrupts    */
2799 +/*-----------------------------------*/
2800 +#define PRIMARY_INTS                 40
2801 +
2802 +#define EMIF_INT                    (7 + PRIMARY_INTS)
2803 +
2804 +
2805 +extern void avalanche_int_set(int channel, int line);
2806 +
2807 +
2808 +#endif /* _AVALANCHE_INTC_H */
2809 diff -urN kernel-base/include/asm-mips/ar7/if_port.h kernel-tmp2/include/asm-mips/ar7/if_port.h
2810 --- kernel-base/include/asm-mips/ar7/if_port.h  1970-01-01 01:00:00.000000000 +0100
2811 +++ kernel-tmp2/include/asm-mips/ar7/if_port.h  2005-07-10 06:40:39.623260936 +0200
2812 @@ -0,0 +1,26 @@
2813 +/*******************************************************************************
2814 + * FILE PURPOSE:    Interface port id Header file
2815 + *******************************************************************************
2816 + * FILE NAME:       if_port.h
2817 + *
2818 + * DESCRIPTION:     Header file carrying information about port ids of interfaces
2819 + *
2820 + *
2821 + * (C) Copyright 2003, Texas Instruments, Inc
2822 + ******************************************************************************/
2823 +#ifndef _IF_PORT_H_
2824 +#define _IF_PORT_H_
2825 +
2826 +#define AVALANCHE_CPMAC_LOW_PORT_ID         0
2827 +#define AVALANCHE_CPMAC_HIGH_PORT_ID        1
2828 +#define AVALANCHE_USB_PORT_ID               2
2829 +#define AVALANCHE_WLAN_PORT_ID              3
2830 +
2831 +
2832 +#define AVALANCHE_MARVELL_BASE_PORT_ID      4
2833 +
2834 +/* The marvell ports occupy port ids from  4 to 8 */
2835 +/* so the next port id number should start at 9   */
2836 +
2837 +
2838 +#endif /* _IF_PORT_H_ */
2839 diff -urN kernel-base/include/asm-mips/ar7/sangam_boards.h kernel-tmp2/include/asm-mips/ar7/sangam_boards.h
2840 --- kernel-base/include/asm-mips/ar7/sangam_boards.h    1970-01-01 01:00:00.000000000 +0100
2841 +++ kernel-tmp2/include/asm-mips/ar7/sangam_boards.h    2005-07-10 06:40:39.623260936 +0200
2842 @@ -0,0 +1,77 @@
2843 +#ifndef _SANGAM_BOARDS_H
2844 +#define _SANGAM_BOARDS_H
2845 +
2846 +// Let us define board specific information here.
2847 +
2848 +
2849 +#if defined(CONFIG_AR7DB)
2850 +
2851 +#define AFECLK_FREQ                                 35328000
2852 +#define REFCLK_FREQ                                 25000000
2853 +#define OSC3_FREQ                                   24000000
2854 +#define AVALANCHE_LOW_CPMAC_PHY_MASK                0x80000000
2855 +#define AVALANCHE_HIGH_CPMAC_PHY_MASK               0x55555555
2856 +#define AVALANCHE_LOW_CPMAC_MDIX_MASK               0x80000000
2857 +
2858 +#endif
2859 +
2860 +
2861 +#if defined(CONFIG_AR7RD)
2862 +#define AFECLK_FREQ                                 35328000
2863 +#define REFCLK_FREQ                                 25000000
2864 +#define OSC3_FREQ                                   24000000
2865 +#define AVALANCHE_LOW_CPMAC_PHY_MASK                0x80000000
2866 +#define AVALANCHE_HIGH_CPMAC_PHY_MASK               0x2
2867 +#define AVALANCHE_LOW_CPMAC_MDIX_MASK               0x80000000
2868 +#endif
2869 +
2870 +
2871 +#if defined(CONFIG_AR7WI)
2872 +#define AFECLK_FREQ                                 35328000
2873 +#define REFCLK_FREQ                                 25000000
2874 +#define OSC3_FREQ                                   24000000
2875 +#define AVALANCHE_LOW_CPMAC_PHY_MASK                0x80000000
2876 +#define AVALANCHE_HIGH_CPMAC_PHY_MASK               0x2
2877 +#define AVALANCHE_LOW_CPMAC_MDIX_MASK               0x80000000
2878 +#endif
2879 +
2880 +
2881 +#if defined(CONFIG_AR7V)
2882 +#define AFECLK_FREQ                                 35328000
2883 +#define REFCLK_FREQ                                 25000000
2884 +#define OSC3_FREQ                                   24000000
2885 +#define AVALANCHE_LOW_CPMAC_PHY_MASK                0x80000000
2886 +#define AVALANCHE_HIGH_CPMAC_PHY_MASK               0x2
2887 +#define AVALANCHE_LOW_CPMAC_MDIX_MASK               0x80000000
2888 +#endif
2889 +
2890 +
2891 +#if defined(CONFIG_AR7WRD)
2892 +#define AFECLK_FREQ                                 35328000
2893 +#define REFCLK_FREQ                                 25000000
2894 +#define OSC3_FREQ                                   24000000
2895 +#define AVALANCHE_LOW_CPMAC_PHY_MASK                0x80000000
2896 +#define AVALANCHE_HIGH_CPMAC_PHY_MASK               0x00010000
2897 +#define AVALANCHE_LOW_CPMAC_MDIX_MASK               0x80000000
2898 +#endif
2899 +
2900 +
2901 +#if defined(CONFIG_AR7VWI)
2902 +#define AFECLK_FREQ                                 35328000
2903 +#define REFCLK_FREQ                                 25000000
2904 +#define OSC3_FREQ                                   24000000
2905 +#define AVALANCHE_LOW_CPMAC_PHY_MASK                0x80000000
2906 +#define AVALANCHE_HIGH_CPMAC_PHY_MASK               0x00010000
2907 +#define AVALANCHE_LOW_CPMAC_MDIX_MASK               0x80000000
2908 +#endif
2909 +
2910 +
2911 +#if defined CONFIG_SEAD2
2912 +#define AVALANCHE_LOW_CPMAC_PHY_MASK                0xAAAAAAAA
2913 +#define AVALANCHE_HIGH_CPMAC_PHY_MASK               0x55555555
2914 +#define AVALANCHE_LOW_CPMAC_MDIX_MASK               0
2915 +#include <asm/mips-boards/sead.h>
2916 +#endif
2917 +
2918 +
2919 +#endif
2920 diff -urN kernel-base/include/asm-mips/ar7/sangam.h kernel-tmp2/include/asm-mips/ar7/sangam.h
2921 --- kernel-base/include/asm-mips/ar7/sangam.h   1970-01-01 01:00:00.000000000 +0100
2922 +++ kernel-tmp2/include/asm-mips/ar7/sangam.h   2005-07-10 06:40:39.624260784 +0200
2923 @@ -0,0 +1,180 @@
2924 +#ifndef _SANGAM_H_
2925 +#define _SANGAM_H_
2926 +
2927 +#include <linux/config.h>
2928 +#include <asm/addrspace.h>
2929 +
2930 +/*----------------------------------------------------
2931 + * Sangam's Module Base Addresses
2932 + *--------------------------------------------------*/
2933 +#define AVALANCHE_ADSL_SUB_SYS_MEM_BASE       (KSEG1ADDR(0x01000000)) /* AVALANCHE ADSL Mem Base */
2934 +#define AVALANCHE_BROADBAND_INTERFACE__BASE   (KSEG1ADDR(0x02000000)) /* AVALANCHE BBIF */
2935 +#define AVALANCHE_ATM_SAR_BASE                (KSEG1ADDR(0x03000000)) /* AVALANCHE ATM SAR */
2936 +#define AVALANCHE_USB_SLAVE_BASE              (KSEG1ADDR(0x03400000)) /* AVALANCHE USB SLAVE */
2937 +#define AVALANCHE_LOW_VLYNQ_MEM_MAP_BASE      (KSEG1ADDR(0x04000000)) /* AVALANCHE VLYNQ 0 Mem map */
2938 +#define AVALANCHE_LOW_CPMAC_BASE              (KSEG1ADDR(0x08610000)) /* AVALANCHE CPMAC 0 */
2939 +#define AVALANCHE_EMIF_CONTROL_BASE           (KSEG1ADDR(0x08610800)) /* AVALANCHE EMIF */
2940 +#define AVALANCHE_GPIO_BASE                   (KSEG1ADDR(0x08610900)) /* AVALANCHE GPIO */
2941 +#define AVALANCHE_CLOCK_CONTROL_BASE          (KSEG1ADDR(0x08610A00)) /* AVALANCHE Clock Control */
2942 +#define AVALANCHE_WATCHDOG_TIMER_BASE         (KSEG1ADDR(0x08610B00)) /* AVALANCHE Watch Dog Timer */
2943 +#define AVALANCHE_TIMER0_BASE                 (KSEG1ADDR(0x08610C00)) /* AVALANCHE Timer 1 */
2944 +#define AVALANCHE_TIMER1_BASE                 (KSEG1ADDR(0x08610D00)) /* AVALANCHE Timer 2 */
2945 +#define AVALANCHE_UART0_REGS_BASE             (KSEG1ADDR(0x08610E00)) /* AVALANCHE UART 0 */
2946 +#define AVALANCHE_UART1_REGS_BASE             (KSEG1ADDR(0x08610F00)) /* AVALANCHE UART 0 */
2947 +#define AVALANCHE_I2C_BASE                    (KSEG1ADDR(0x08611000)) /* AVALANCHE I2C */
2948 +#define AVALANCHE_USB_SLAVE_CONTROL_BASE      (KSEG1ADDR(0x08611200)) /* AVALANCHE USB DMA */
2949 +#define AVALANCHE_MCDMA0_CTRL_BASE            (KSEG1ADDR(0x08611400)) /* AVALANCHE MC DMA 0 (channels 0-3) */
2950 +#define AVALANCHE_RESET_CONTROL_BASE          (KSEG1ADDR(0x08611600)) /* AVALANCHE Reset Control */
2951 +#define AVALANCHE_BIST_CONTROL_BASE           (KSEG1ADDR(0x08611700)) /* AVALANCHE BIST Control */
2952 +#define AVALANCHE_LOW_VLYNQ_CONTROL_BASE      (KSEG1ADDR(0x08611800)) /* AVALANCHE VLYNQ0 Control */
2953 +#define AVALANCHE_DEVICE_CONFIG_LATCH_BASE    (KSEG1ADDR(0x08611A00)) /* AVALANCHE Device Config Latch */
2954 +#define AVALANCHE_HIGH_VLYNQ_CONTROL_BASE     (KSEG1ADDR(0x08611C00)) /* AVALANCHE VLYNQ1 Control */
2955 +#define AVALANCHE_MDIO_BASE                   (KSEG1ADDR(0x08611E00)) /* AVALANCHE MDIO    */
2956 +#define AVALANCHE_FSER_BASE                   (KSEG1ADDR(0x08612000)) /* AVALANCHE FSER base */
2957 +#define AVALANCHE_INTC_BASE                   (KSEG1ADDR(0x08612400)) /* AVALANCHE INTC  */
2958 +#define AVALANCHE_HIGH_CPMAC_BASE             (KSEG1ADDR(0x08612800)) /* AVALANCHE CPMAC 1 */
2959 +#define AVALANCHE_HIGH_VLYNQ_MEM_MAP_BASE     (KSEG1ADDR(0x0C000000)) /* AVALANCHE VLYNQ 1 Mem map */
2960 +
2961 +#define AVALANCHE_SDRAM_BASE                  0x14000000UL
2962 +
2963 +
2964 +/*----------------------------------------------------
2965 + * Sangam Interrupt Map (Primary Interrupts)
2966 + *--------------------------------------------------*/
2967 +
2968 +#define AVALANCHE_UNIFIED_SECONDARY_INT            0
2969 +#define AVALANCHE_EXT_INT_0                        1
2970 +#define AVALANCHE_EXT_INT_1                        2
2971 +/* Line#  3 to 4 are reserved                            */
2972 +#define AVALANCHE_TIMER_0_INT                      5
2973 +#define AVALANCHE_TIMER_1_INT                      6
2974 +#define AVALANCHE_UART0_INT                        7
2975 +#define AVALANCHE_UART1_INT                        8
2976 +#define AVALANCHE_DMA_INT0                         9
2977 +#define AVALANCHE_DMA_INT1                        10
2978 +/* Line# 11 to 14 are reserved                    */
2979 +#define AVALANCHE_ATM_SAR_INT                     15
2980 +/* Line# 16 to 18 are reserved                    */
2981 +#define AVALANCHE_LOW_CPMAC_INT                   19
2982 +/* Line# 20 is reserved                           */
2983 +#define AVALANCHE_LOW_VLYNQ_INT                   21
2984 +#define AVALANCHE_CODEC_WAKEUP_INT                22
2985 +/* Line# 23 is reserved                           */
2986 +#define AVALANCHE_USB_SLAVE_INT                   24
2987 +#define AVALANCHE_HIGH_VLYNQ_INT                  25
2988 +/* Line# 26 to 27 are reserved                    */
2989 +#define AVALANCHE_UNIFIED_PHY_INT                 28
2990 +#define AVALANCHE_I2C_INT                         29
2991 +#define AVALANCHE_DMA_INT2                        30
2992 +#define AVALANCHE_DMA_INT3                        31
2993 +/* Line# 32 is reserved                           */
2994 +#define AVALANCHE_HIGH_CPMAC_INT                  33
2995 +/* Line# 34 to 36 is reserved                     */
2996 +#define AVALANCHE_VDMA_VT_RX_INT                  37
2997 +#define AVALANCHE_VDMA_VT_TX_INT                  38
2998 +#define AVALANCHE_ADSL_SUB_SYSTEM_INT             39
2999 +
3000 +
3001 +#define AVALANCHE_EMIF_INT                        47
3002 +
3003 +
3004 +
3005 +/*-----------------------------------------------------------
3006 + * Sangam's Reset Bits
3007 + *---------------------------------------------------------*/
3008 +
3009 +#define AVALANCHE_UART0_RESET_BIT                  0
3010 +#define AVALANCHE_UART1_RESET_BIT                  1
3011 +#define AVALANCHE_I2C_RESET_BIT                    2
3012 +#define AVALANCHE_TIMER0_RESET_BIT                 3
3013 +#define AVALANCHE_TIMER1_RESET_BIT                 4
3014 +/* Reset bit  5 is reserved.                       */
3015 +#define AVALANCHE_GPIO_RESET_BIT                   6
3016 +#define AVALANCHE_ADSL_SUB_SYS_RESET_BIT           7
3017 +#define AVALANCHE_USB_SLAVE_RESET_BIT              8
3018 +#define AVALANCHE_ATM_SAR_RESET_BIT                9
3019 +/* Reset bit 10 is reserved.                      */
3020 +#define AVALANCHE_VDMA_VT_RESET_BIT               11
3021 +#define AVALANCHE_FSER_RESET_BIT                  12
3022 +/* Reset bit 13 to 15 are reserved                */
3023 +#define AVALANCHE_HIGH_VLYNQ_RESET_BIT            16
3024 +#define AVALANCHE_LOW_CPMAC_RESET_BIT             17
3025 +#define AVALANCHE_MCDMA_RESET_BIT                 18
3026 +#define AVALANCHE_BIST_RESET_BIT                  19
3027 +#define AVALANCHE_LOW_VLYNQ_RESET_BIT             20
3028 +#define AVALANCHE_HIGH_CPMAC_RESET_BIT            21
3029 +#define AVALANCHE_MDIO_RESET_BIT                  22
3030 +#define AVALANCHE_ADSL_SUB_SYS_DSP_RESET_BIT      23
3031 +/* Reset bit 24 to 25 are reserved                */
3032 +#define AVALANCHE_LOW_EPHY_RESET_BIT              26
3033 +/* Reset bit 27 to 31 are reserved                */
3034 +
3035 +
3036 +#define AVALANCHE_POWER_MODULE_USBSP               0
3037 +#define AVALANCHE_POWER_MODULE_WDTP                1
3038 +#define AVALANCHE_POWER_MODULE_UT0P                2
3039 +#define AVALANCHE_POWER_MODULE_UT1P                3
3040 +#define AVALANCHE_POWER_MODULE_IICP                4
3041 +#define AVALANCHE_POWER_MODULE_VDMAP               5
3042 +#define AVALANCHE_POWER_MODULE_GPIOP               6
3043 +#define AVALANCHE_POWER_MODULE_VLYNQ1P             7
3044 +#define AVALANCHE_POWER_MODULE_SARP                8
3045 +#define AVALANCHE_POWER_MODULE_ADSLP               9
3046 +#define AVALANCHE_POWER_MODULE_EMIFP              10
3047 +#define AVALANCHE_POWER_MODULE_ADSPP              12
3048 +#define AVALANCHE_POWER_MODULE_RAMP               13
3049 +#define AVALANCHE_POWER_MODULE_ROMP               14
3050 +#define AVALANCHE_POWER_MODULE_DMAP               15
3051 +#define AVALANCHE_POWER_MODULE_BISTP              16
3052 +#define AVALANCHE_POWER_MODULE_TIMER0P            18
3053 +#define AVALANCHE_POWER_MODULE_TIMER1P            19
3054 +#define AVALANCHE_POWER_MODULE_EMAC0P             20
3055 +#define AVALANCHE_POWER_MODULE_EMAC1P             22
3056 +#define AVALANCHE_POWER_MODULE_EPHYP              24
3057 +#define AVALANCHE_POWER_MODULE_VLYNQ0P            27
3058 +
3059 +
3060 +
3061 +
3062 +
3063 +/*
3064 + * Sangam board vectors
3065 + */
3066 +
3067 +#define AVALANCHE_VECS       (KSEG1ADDR(AVALANCHE_SDRAM_BASE))
3068 +#define AVALANCHE_VECS_KSEG0 (KSEG0ADDR(AVALANCHE_SDRAM_BASE))
3069 +
3070 +/*-----------------------------------------------------------------------------
3071 + * Sangam's system register.
3072 + *
3073 + *---------------------------------------------------------------------------*/
3074 +#define AVALANCHE_DCL_BOOTCR          (KSEG1ADDR(0x08611A00))
3075 +#define AVALANCHE_EMIF_SDRAM_CFG      (AVALANCHE_EMIF_CONTROL_BASE + 0x8)
3076 +#define AVALANCHE_RST_CTRL_PRCR       (KSEG1ADDR(0x08611600))
3077 +#define AVALANCHE_RST_CTRL_SWRCR      (KSEG1ADDR(0x08611604))
3078 +#define AVALANCHE_RST_CTRL_RSR        (KSEG1ADDR(0x08611600))
3079 +
3080 +#define AVALANCHE_POWER_CTRL_PDCR     (KSEG1ADDR(0x08610A00))
3081 +#define AVALANCHE_WAKEUP_CTRL_WKCR    (KSEG1ADDR(0x08610A0C))
3082 +
3083 +#define AVALANCHE_GPIO_DATA_IN        (AVALANCHE_GPIO_BASE +  0x0)
3084 +#define AVALANCHE_GPIO_DATA_OUT       (AVALANCHE_GPIO_BASE +  0x4)
3085 +#define AVALANCHE_GPIO_DIR            (AVALANCHE_GPIO_BASE +  0x8)
3086 +#define AVALANCHE_GPIO_ENBL           (AVALANCHE_GPIO_BASE +  0xC)
3087 +#define AVALANCHE_CVR                 (AVALANCHE_GPIO_BASE +  0x14)
3088 +
3089 +/*
3090 + * Yamon Prom print address.
3091 + */
3092 +#define AVALANCHE_YAMON_FUNCTION_BASE             (KSEG1ADDR(0x10000500))
3093 +#define AVALANCHE_YAMON_PROM_PRINT_COUNT_ADDR     (AVALANCHE_YAMON_FUNCTION_BASE + 0x4)  /* print_count function */
3094 +#define AVALANCHE_YAMON_PROM_PRINT_ADDR           (AVALANCHE_YAMON_FUNCTION_BASE + 0x34)
3095 +
3096 +#define AVALANCHE_BASE_BAUD       ( 3686400 / 16 )
3097 +
3098 +#define  AVALANCHE_GPIO_PIN_COUNT         32
3099 +#define  AVALANCHE_GPIO_OFF_MAP           {0xF34FFFC0}
3100 +
3101 +#include "sangam_boards.h"
3102 +
3103 +#endif /*_SANGAM_H_ */
3104 diff -urN kernel-base/include/asm-mips/io.h kernel-tmp2/include/asm-mips/io.h
3105 --- kernel-base/include/asm-mips/io.h   2005-07-10 03:00:44.797179400 +0200
3106 +++ kernel-tmp2/include/asm-mips/io.h   2005-07-10 06:40:39.624260784 +0200
3107 @@ -63,8 +63,12 @@
3108  #ifdef CONFIG_64BIT_PHYS_ADDR
3109  #define page_to_phys(page)     ((u64)(page - mem_map) << PAGE_SHIFT)
3110  #else
3111 +#ifdef CONFIG_AR7_PAGING
3112 +#define page_to_phys(page)     (((page - mem_map) << PAGE_SHIFT) + CONFIG_AR7_MEMORY)
3113 +#else
3114  #define page_to_phys(page)     ((page - mem_map) << PAGE_SHIFT)
3115  #endif
3116 +#endif
3117
3118  #define IO_SPACE_LIMIT 0xffff
3119
3120 diff -urN kernel-base/include/asm-mips/irq.h kernel-tmp2/include/asm-mips/irq.h
3121 --- kernel-base/include/asm-mips/irq.h  2005-07-10 03:00:44.798179248 +0200
3122 +++ kernel-tmp2/include/asm-mips/irq.h  2005-07-10 06:40:39.624260784 +0200
3123 @@ -14,7 +14,12 @@
3124  #include <linux/config.h>
3125  #include <linux/linkage.h>
3126
3127 +#ifdef CONFIG_AR7
3128 +#include <asm/ar7/avalanche_intc.h>
3129 +#define NR_IRQS AVALANCHE_INT_END + 1
3130 +#else
3131  #define NR_IRQS 128            /* Largest number of ints of all machines.  */
3132 +#endif
3133
3134  #ifdef CONFIG_I8259
3135  static inline int irq_cannonicalize(int irq)
3136 diff -urN kernel-base/include/asm-mips/page.h kernel-tmp2/include/asm-mips/page.h
3137 --- kernel-base/include/asm-mips/page.h 2005-07-10 03:00:44.798179248 +0200
3138 +++ kernel-tmp2/include/asm-mips/page.h 2005-07-10 06:40:39.625260632 +0200
3139 @@ -129,7 +129,11 @@
3140
3141  #define __pa(x)                ((unsigned long) (x) - PAGE_OFFSET)
3142  #define __va(x)                ((void *)((unsigned long) (x) + PAGE_OFFSET))
3143 +#ifdef CONFIG_AR7_PAGING
3144 +#define virt_to_page(kaddr)    phys_to_page(__pa(kaddr))
3145 +#else
3146  #define virt_to_page(kaddr)    (mem_map + (__pa(kaddr) >> PAGE_SHIFT))
3147 +#endif
3148  #define VALID_PAGE(page)       ((page - mem_map) < max_mapnr)
3149
3150  #define VM_DATA_DEFAULT_FLAGS  (VM_READ | VM_WRITE | VM_EXEC | \
3151 diff -urN kernel-base/include/asm-mips/pgtable-32.h kernel-tmp2/include/asm-mips/pgtable-32.h
3152 --- kernel-base/include/asm-mips/pgtable-32.h   2005-07-10 03:00:44.798179248 +0200
3153 +++ kernel-tmp2/include/asm-mips/pgtable-32.h   2005-07-10 06:40:39.625260632 +0200
3154 @@ -108,7 +108,18 @@
3155   * and a page entry and page directory to the page they refer to.
3156   */
3157
3158 -#ifdef CONFIG_CPU_VR41XX
3159 +#if defined(CONFIG_AR7_PAGING)
3160 +#define mk_pte(page, pgprot)                                           \
3161 +({                                                                     \
3162 +       pte_t   __pte;                                                  \
3163 +                                                                       \
3164 +       pte_val(__pte) = ((phys_t)(page - mem_map) << (PAGE_SHIFT) |    \
3165 +               CONFIG_AR7_MEMORY) |                                    \
3166 +       pgprot_val(pgprot);                                             \
3167 +                                                                       \
3168 +       __pte;                                                          \
3169 +})
3170 +#elif defined(CONFIG_CPU_VR41XX)
3171  #define mk_pte(page, pgprot)                                            \
3172  ({                                                                      \
3173          pte_t   __pte;                                                  \
3174 @@ -130,6 +141,7 @@
3175  })
3176  #endif
3177
3178 +
3179  static inline pte_t mk_pte_phys(phys_t physpage, pgprot_t pgprot)
3180  {
3181  #ifdef CONFIG_CPU_VR41XX
3182 @@ -175,7 +187,10 @@
3183                 set_pte(ptep, __pte(0));
3184  }
3185
3186 -#ifdef CONFIG_CPU_VR41XX
3187 +#if defined(CONFIG_AR7_PAGING)
3188 +#define phys_to_page(phys)     (mem_map + (((phys)-CONFIG_AR7_MEMORY) >> PAGE_SHIFT))
3189 +#define pte_page(x)            phys_to_page(pte_val(x))
3190 +#elif defined(CONFIG_CPU_VR41XX)
3191  #define pte_page(x)  (mem_map+((unsigned long)(((x).pte_low >> (PAGE_SHIFT+2)))))
3192  #define __mk_pte(page_nr,pgprot) __pte(((page_nr) << (PAGE_SHIFT+2)) | pgprot_val(pgprot))
3193  #else
3194 diff -urN kernel-base/include/asm-mips/serial.h kernel-tmp2/include/asm-mips/serial.h
3195 --- kernel-base/include/asm-mips/serial.h       2005-07-10 03:00:44.799179096 +0200
3196 +++ kernel-tmp2/include/asm-mips/serial.h       2005-07-10 06:40:39.625260632 +0200
3197 @@ -65,6 +65,15 @@
3198
3199  #define C_P(card,port) (((card)<<6|(port)<<3) + 1)
3200
3201 +#ifdef CONFIG_AR7
3202 +#include <asm/ar7/ar7.h>
3203 +#define AR7_SERIAL_PORT_DEFNS  \
3204 +       { 0, AR7_BASE_BAUD, AR7_UART0_REGS_BASE, LNXINTNUM(AVALANCHE_UART0_INT), STD_COM_FLAGS }, \
3205 +       { 0, AR7_BASE_BAUD, AR7_UART1_REGS_BASE, LNXINTNUM(AVALANCHE_UART1_INT), STD_COM_FLAGS },
3206 +#else
3207 +#define AR7_SERIAL_PORT_DEFNS
3208 +#endif
3209 +
3210  #ifdef CONFIG_MIPS_JAZZ
3211  #define _JAZZ_SERIAL_INIT(int, base)                                   \
3212         { .baud_base = JAZZ_BASE_BAUD, .irq = int, .flags = STD_COM_FLAGS,      \
3213 @@ -468,6 +477,7 @@
3214  #endif
3215
3216  #define SERIAL_PORT_DFNS                       \
3217 +       AR7_SERIAL_PORT_DEFNS                   \
3218         ATLAS_SERIAL_PORT_DEFNS                 \
3219         AU1000_SERIAL_PORT_DEFNS                \
3220         COBALT_SERIAL_PORT_DEFNS                \
3221 diff -urN kernel-base/Makefile kernel-tmp2/Makefile
3222 --- kernel-base/Makefile        2005-07-10 03:00:44.799179096 +0200
3223 +++ kernel-tmp2/Makefile        2005-07-10 06:40:39.626260480 +0200
3224 @@ -91,7 +91,7 @@
3225
3226  CPPFLAGS := -D__KERNEL__ -I$(HPATH)
3227
3228 -CFLAGS := $(CPPFLAGS) -Wall -Wstrict-prototypes -Wno-trigraphs -O2 \
3229 +CFLAGS := $(CPPFLAGS) -Wall -Wstrict-prototypes -Wno-trigraphs -Os \
3230           -fno-strict-aliasing -fno-common
3231  ifndef CONFIG_FRAME_POINTER
3232  CFLAGS += -fomit-frame-pointer