target/linux/linux-2.4/patches/ar7/000-ar7_support.patch

   1 diff -urN linux.old/Makefile linux.dev/Makefile
   2 --- linux.old/Makefile  2005-07-26 18:18:16.286577600 +0200
   3 +++ linux.dev/Makefile  2005-07-26 18:11:03.247409000 +0200
   4 @@ -91,7 +91,7 @@
   5
   6  CPPFLAGS := -D__KERNEL__ -I$(HPATH)
   7
   8 -CFLAGS := $(CPPFLAGS) -Wall -Wstrict-prototypes -Wno-trigraphs -O2 \
   9 +CFLAGS := $(CPPFLAGS) -Wall -Wstrict-prototypes -Wno-trigraphs -Os \
  10           -fno-strict-aliasing -fno-common
  11  ifndef CONFIG_FRAME_POINTER
  12  CFLAGS += -fomit-frame-pointer
  13 diff -urN linux.old/arch/mips/Makefile linux.dev/arch/mips/Makefile
  14 --- linux.old/arch/mips/Makefile        2005-07-26 18:18:16.268580336 +0200
  15 +++ linux.dev/arch/mips/Makefile        2005-07-26 18:11:03.268406000 +0200
  16 @@ -369,6 +369,16 @@
  17  endif
  18
  19  #
  20 +# Texas Instruments AR7
  21 +#
  22 +
  23 +ifdef CONFIG_AR7
  24 +LIBS           += arch/mips/ar7/ar7.o arch/mips/ar7/ar7/ar7.o
  25 +SUBDIRS                += arch/mips/ar7 arch/mips/ar7/ar7
  26 +LOADADDR       += 0x94020000
  27 +endif
  28 +
  29 +#
  30  # DECstation family
  31  #
  32  ifdef CONFIG_DECSTATION
  33 diff -urN linux.old/arch/mips/ar7/Makefile linux.dev/arch/mips/ar7/Makefile
  34 --- linux.old/arch/mips/ar7/Makefile    1970-01-01 01:00:00.000000000 +0100
  35 +++ linux.dev/arch/mips/ar7/Makefile    2005-07-26 18:11:02.626503000 +0200
  36 @@ -0,0 +1,13 @@
  37 +.S.s:
  38 +       $(CPP) $(AFLAGS) $< -o $*.s
  39 +
  40 +.S.o:
  41 +       $(CC) $(AFLAGS) -c $< -o $*.o
  42 +
  43 +EXTRA_CFLAGS := -I$(TOPDIR)/include/asm/ar7 -DLITTLE_ENDIAN -D_LINK_KSEG0_
  44 +O_TARGET := ar7.o
  45 +
  46 +obj-y := tnetd73xx_misc.o
  47 +obj-y += setup.o irq.o mipsIRQ.o reset.o init.o memory.o printf.o cmdline.o time.o
  48 +
  49 +include $(TOPDIR)/Rules.make
  50 diff -urN linux.old/arch/mips/ar7/ar7/Makefile linux.dev/arch/mips/ar7/ar7/Makefile
  51 --- linux.old/arch/mips/ar7/ar7/Makefile        1970-01-01 01:00:00.000000000 +0100
  52 +++ linux.dev/arch/mips/ar7/ar7/Makefile        2005-07-26 18:11:02.621504000 +0200
  53 @@ -0,0 +1,31 @@
  54 +# $Id$
  55 +# Copyright (C) $Date$  $Author$
  56 +#
  57 +# This program is free software; you can redistribute it and/or modify
  58 +# it under the terms of the GNU General Public License as published by
  59 +# the Free Software Foundation; either version 2 of the License, or
  60 +# (at your option) any later version.
  61 +#
  62 +# This program is distributed in the hope that it will be useful,
  63 +# but WITHOUT ANY WARRANTY; without even the implied warranty of
  64 +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  65 +# GNU General Public License for more details.
  66 +#
  67 +# You should have received a copy of the GNU General Public License
  68 +# along with this program; if not, write to the Free Software
  69 +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
  70 +
  71 +.S.s:
  72 +       $(CPP) $(AFLAGS) $< -o $*.s
  73 +
  74 +.S.o:
  75 +       $(CC) $(AFLAGS) -c $< -o $*.o
  76 +
  77 +EXTRA_CFLAGS := -DLITTLE_ENDIAN -D_LINK_KSEG0_
  78 +
  79 +O_TARGET := ar7.o
  80 +
  81 +export-objs := misc.o
  82 +obj-y += paging.o jump.o misc.o
  83 +
  84 +include $(TOPDIR)/Rules.make
  85 diff -urN linux.old/arch/mips/ar7/ar7/jump.S linux.dev/arch/mips/ar7/ar7/jump.S
  86 --- linux.old/arch/mips/ar7/ar7/jump.S  1970-01-01 01:00:00.000000000 +0100
  87 +++ linux.dev/arch/mips/ar7/ar7/jump.S  2005-07-26 18:11:02.621504000 +0200
  88 @@ -0,0 +1,89 @@
  89 +/*
  90 + * $Id$
  91 + * Copyright (C) $Date$  $Author$
  92 + *
  93 + * This program is free software; you can redistribute it and/or modify
  94 + * it under the terms of the GNU General Public License as published by
  95 + * the Free Software Foundation; either version 2 of the License, or
  96 + * (at your option) any later version.
  97 + *
  98 + * This program is distributed in the hope that it will be useful,
  99 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
 100 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 101 + * GNU General Public License for more details.
 102 + *
 103 + * You should have received a copy of the GNU General Public License
 104 + * along with this program; if not, write to the Free Software
 105 + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
 106 + *
 107 + */
 108 +
 109 +#include <linux/config.h>
 110 +#include <linux/threads.h>
 111 +
 112 +#include <asm/asm.h>
 113 +#include <asm/cacheops.h>
 114 +#include <asm/current.h>
 115 +#include <asm/offset.h>
 116 +#include <asm/processor.h>
 117 +#include <asm/regdef.h>
 118 +#include <asm/cachectl.h>
 119 +#include <asm/mipsregs.h>
 120 +#include <asm/stackframe.h>
 121 +
 122 +.text
 123 +
 124 +.set noreorder
 125 +.set noat
 126 +
 127 +/* TLB Miss Vector */
 128 +
 129 +LEAF(jump_tlb_miss)
 130 +       .set mips2
 131 +       lui     k0,0x9400
 132 +       ori     k0,0
 133 +       jr      k0
 134 +       nop
 135 +END(jump_tlb_miss)
 136 +
 137 +       /* Unused TLB Miss Vector */
 138 +
 139 +LEAF(jump_tlb_miss_unused)
 140 +       .set mips2
 141 +       lui     k0,0x9400
 142 +       ori     k0,0x80
 143 +       jr      k0
 144 +       nop
 145 +END(jump_tlb_miss_unused)
 146 +
 147 +       /* Cache Error Vector */
 148 +
 149 +LEAF(jump_cache_error)
 150 +       .set mips2
 151 +       lui     k0,0x9400
 152 +       ori     k0,0x100
 153 +       jr      k0
 154 +       nop
 155 +END(jump_cache_error)
 156 +
 157 +       /* General Exception */
 158 +
 159 +LEAF(jump_general_exception)
 160 +       .set mips2
 161 +       lui     k0,0x9400
 162 +       ori     k0,0x180
 163 +       jr      k0
 164 +       nop
 165 +END(jump_general_exception)
 166 +
 167 +       /* Dedicated Interrupt */
 168 +
 169 +LEAF(jump_dedicated_interrupt)
 170 +       .set mips2
 171 +       lui     k0,0x9400
 172 +       ori     k0,0x200
 173 +       jr      k0
 174 +       nop
 175 +END(jump_dedicated_interrupt)
 176 +
 177 +       .set at
 178 diff -urN linux.old/arch/mips/ar7/ar7/misc.c linux.dev/arch/mips/ar7/ar7/misc.c
 179 --- linux.old/arch/mips/ar7/ar7/misc.c  1970-01-01 01:00:00.000000000 +0100
 180 +++ linux.dev/arch/mips/ar7/ar7/misc.c  2005-07-26 18:11:02.622504000 +0200
 181 @@ -0,0 +1,319 @@
 182 +#include <asm/ar7/sangam.h>
 183 +#include <asm/ar7/avalanche_misc.h>
 184 +#include <linux/module.h>
 185 +#include <linux/spinlock.h>
 186 +
 187 +#define TRUE 1
 188 +
 189 +static unsigned int avalanche_vbus_freq;
 190 +
 191 +REMOTE_VLYNQ_DEV_RESET_CTRL_FN p_remote_vlynq_dev_reset_ctrl = NULL;
 192 +
 193 +/*****************************************************************************
 194 + * Reset Control Module.
 195 + *****************************************************************************/
 196 +void avalanche_reset_ctrl(unsigned int module_reset_bit,
 197 +                          AVALANCHE_RESET_CTRL_T reset_ctrl)
 198 +{
 199 +    volatile unsigned int *reset_reg = (unsigned int*) AVALANCHE_RST_CTRL_PRCR;
 200 +
 201 +    if(module_reset_bit >= 32 && module_reset_bit < 64)
 202 +        return;
 203 +
 204 +    if(module_reset_bit >= 64)
 205 +    {
 206 +        if(p_remote_vlynq_dev_reset_ctrl)
 207 +            return(p_remote_vlynq_dev_reset_ctrl(module_reset_bit - 64, reset_ctrl));
 208 +        else
 209 +            return;
 210 +    }
 211 +
 212 +    if(reset_ctrl == OUT_OF_RESET)
 213 +        *reset_reg |= 1 << module_reset_bit;
 214 +    else
 215 +        *reset_reg &= ~(1 << module_reset_bit);
 216 +}
 217 +
 218 +AVALANCHE_RESET_CTRL_T avalanche_get_reset_status(unsigned int module_reset_bit)
 219 +{
 220 +    volatile unsigned int *reset_reg = (unsigned int*) AVALANCHE_RST_CTRL_PRCR;
 221 +
 222 +    return (((*reset_reg) & (1 << module_reset_bit)) ? OUT_OF_RESET : IN_RESET );
 223 +}
 224 +
 225 +void avalanche_sys_reset(AVALANCHE_SYS_RST_MODE_T mode)
 226 +{
 227 +    volatile unsigned int *sw_reset_reg = (unsigned int*) AVALANCHE_RST_CTRL_SWRCR;
 228 +    *sw_reset_reg =  mode;
 229 +}
 230 +
 231 +#define AVALANCHE_RST_CTRL_RSR_MASK 0x3
 232 +
 233 +AVALANCHE_SYS_RESET_STATUS_T avalanche_get_sys_last_reset_status()
 234 +{
 235 +    volatile unsigned int *sys_reset_status = (unsigned int*) AVALANCHE_RST_CTRL_RSR;
 236 +
 237 +    return ( (AVALANCHE_SYS_RESET_STATUS_T) (*sys_reset_status & AVALANCHE_RST_CTRL_RSR_MASK) );
 238 +}
 239 +
 240 +
 241 +/*****************************************************************************
 242 + * Power Control Module
 243 + *****************************************************************************/
 244 +#define AVALANCHE_GLOBAL_POWER_DOWN_MASK    0x3FFFFFFF      /* bit 31, 30 masked */
 245 +#define AVALANCHE_GLOBAL_POWER_DOWN_BIT     30              /* shift to bit 30, 31 */
 246 +
 247 +
 248 +void avalanche_power_ctrl(unsigned int module_power_bit, AVALANCHE_POWER_CTRL_T power_ctrl)
 249 +{
 250 +    volatile unsigned int *power_reg = (unsigned int*)AVALANCHE_POWER_CTRL_PDCR;
 251 +
 252 +    if (power_ctrl == POWER_CTRL_POWER_DOWN)
 253 +        /* power down the module */
 254 +        *power_reg |= (1 << module_power_bit);
 255 +    else
 256 +        /* power on the module */
 257 +        *power_reg &= (~(1 << module_power_bit));
 258 +}
 259 +
 260 +AVALANCHE_POWER_CTRL_T avalanche_get_power_status(unsigned int module_power_bit)
 261 +{
 262 +    volatile unsigned int *power_status_reg = (unsigned int*)AVALANCHE_POWER_CTRL_PDCR;
 263 +
 264 +    return (((*power_status_reg) & (1 << module_power_bit)) ? POWER_CTRL_POWER_DOWN : POWER_CTRL_POWER_UP);
 265 +}
 266 +
 267 +void avalanche_set_global_power_mode(AVALANCHE_SYS_POWER_MODE_T power_mode)
 268 +{
 269 +    volatile unsigned int *power_status_reg = (unsigned int*)AVALANCHE_POWER_CTRL_PDCR;
 270 +
 271 +    *power_status_reg &= AVALANCHE_GLOBAL_POWER_DOWN_MASK;
 272 +    *power_status_reg |= ( power_mode << AVALANCHE_GLOBAL_POWER_DOWN_BIT);
 273 +}
 274 +
 275 +AVALANCHE_SYS_POWER_MODE_T avalanche_get_global_power_mode(void)
 276 +{
 277 +    volatile unsigned int *power_status_reg = (unsigned int*)AVALANCHE_POWER_CTRL_PDCR;
 278 +
 279 +    return((AVALANCHE_SYS_POWER_MODE_T) (((*power_status_reg) & (~AVALANCHE_GLOBAL_POWER_DOWN_MASK))
 280 +                                           >> AVALANCHE_GLOBAL_POWER_DOWN_BIT));
 281 +}
 282 +
 283 +/*****************************************************************************
 284 + * GPIO  Control
 285 + *****************************************************************************/
 286 +
 287 +/****************************************************************************
 288 + * FUNCTION: avalanche_gpio_init
 289 + ***************************************************************************/
 290 +void avalanche_gpio_init(void)
 291 +{
 292 +    spinlock_t closeLock;
 293 +    unsigned int closeFlag;
 294 +    volatile unsigned int *reset_reg = (unsigned int*) AVALANCHE_RST_CTRL_PRCR;
 295 +    spin_lock_irqsave(&closeLock, closeFlag);
 296 +    *reset_reg |= (1 << AVALANCHE_GPIO_RESET_BIT);
 297 +    spin_unlock_irqrestore(&closeLock, closeFlag);
 298 +}
 299 +
 300 +/****************************************************************************
 301 + * FUNCTION: avalanche_gpio_ctrl
 302 + ***************************************************************************/
 303 +int avalanche_gpio_ctrl(unsigned int gpio_pin,
 304 +                        AVALANCHE_GPIO_PIN_MODE_T pin_mode,
 305 +                        AVALANCHE_GPIO_PIN_DIRECTION_T pin_direction)
 306 +{
 307 +    spinlock_t closeLock;
 308 +    unsigned int closeFlag;
 309 +    volatile unsigned int *gpio_ctrl = (unsigned int*)AVALANCHE_GPIO_ENBL;
 310 +
 311 +    if(gpio_pin >= 32)
 312 +        return(-1);
 313 +
 314 +    spin_lock_irqsave(&closeLock, closeFlag);
 315 +
 316 +    if(pin_mode == GPIO_PIN)
 317 +    {
 318 +        *gpio_ctrl |= (1 << gpio_pin);
 319 +
 320 +       gpio_ctrl = (unsigned int*)AVALANCHE_GPIO_DIR;
 321 +
 322 +        if(pin_direction == GPIO_INPUT_PIN)
 323 +            *gpio_ctrl |=  (1 << gpio_pin);
 324 +        else
 325 +            *gpio_ctrl &= ~(1 << gpio_pin);
 326 +    }
 327 +    else /* FUNCTIONAL PIN */
 328 +    {
 329 +        *gpio_ctrl &= ~(1 << gpio_pin);
 330 +    }
 331 +
 332 +    spin_unlock_irqrestore(&closeLock, closeFlag);
 333 +
 334 +    return (0);
 335 +}
 336 +
 337 +/****************************************************************************
 338 + * FUNCTION: avalanche_gpio_out
 339 + ***************************************************************************/
 340 +int avalanche_gpio_out_bit(unsigned int gpio_pin, int value)
 341 +{
 342 +    spinlock_t closeLock;
 343 +    unsigned int closeFlag;
 344 +    volatile unsigned int *gpio_out = (unsigned int*) AVALANCHE_GPIO_DATA_OUT;
 345 +
 346 +    if(gpio_pin >= 32)
 347 +        return(-1);
 348 +
 349 +    spin_lock_irqsave(&closeLock, closeFlag);
 350 +    if(value == TRUE)
 351 +        *gpio_out |= 1 << gpio_pin;
 352 +    else
 353 +       *gpio_out &= ~(1 << gpio_pin);
 354 +    spin_unlock_irqrestore(&closeLock, closeFlag);
 355 +
 356 +    return(0);
 357 +}
 358 +
 359 +/****************************************************************************
 360 + * FUNCTION: avalanche_gpio_in
 361 + ***************************************************************************/
 362 +int avalanche_gpio_in_bit(unsigned int gpio_pin)
 363 +{
 364 +    spinlock_t closeLock;
 365 +    unsigned int closeFlag;
 366 +    volatile unsigned int *gpio_in = (unsigned int*) AVALANCHE_GPIO_DATA_IN;
 367 +    int ret_val = 0;
 368 +
 369 +    if(gpio_pin >= 32)
 370 +        return(-1);
 371 +
 372 +    spin_lock_irqsave(&closeLock, closeFlag);
 373 +    ret_val = ((*gpio_in) & (1 << gpio_pin));
 374 +    spin_unlock_irqrestore(&closeLock, closeFlag);
 375 +
 376 +    return (ret_val);
 377 +}
 378 +
 379 +/****************************************************************************
 380 + * FUNCTION: avalanche_gpio_out_val
 381 + ***************************************************************************/
 382 +int avalanche_gpio_out_value(unsigned int out_val, unsigned int out_mask,
 383 +                           unsigned int reg_index)
 384 +{
 385 +    spinlock_t closeLock;
 386 +    unsigned int closeFlag;
 387 +    volatile unsigned int *gpio_out = (unsigned int*) AVALANCHE_GPIO_DATA_OUT;
 388 +
 389 +    if(reg_index > 0)
 390 +        return(-1);
 391 +
 392 +    spin_lock_irqsave(&closeLock, closeFlag);
 393 +    *gpio_out &= ~out_mask;
 394 +    *gpio_out |= out_val;
 395 +    spin_unlock_irqrestore(&closeLock, closeFlag);
 396 +
 397 +    return(0);
 398 +}
 399 +
 400 +/****************************************************************************
 401 + * FUNCTION: avalanche_gpio_in_value
 402 + ***************************************************************************/
 403 +int avalanche_gpio_in_value(unsigned int* in_val, unsigned int reg_index)
 404 +{
 405 +    spinlock_t closeLock;
 406 +    unsigned int closeFlag;
 407 +    volatile unsigned int *gpio_in = (unsigned int*) AVALANCHE_GPIO_DATA_IN;
 408 +
 409 +    if(reg_index > 0)
 410 +        return(-1);
 411 +
 412 +    spin_lock_irqsave(&closeLock, closeFlag);
 413 +    *in_val = *gpio_in;
 414 +    spin_unlock_irqrestore(&closeLock, closeFlag);
 415 +
 416 +    return (0);
 417 +}
 418 +
 419 +/***********************************************************************
 420 + *
 421 + *    Wakeup Control Module for TNETV1050 Communication Processor
 422 + *
 423 + ***********************************************************************/
 424 +
 425 +#define AVALANCHE_WAKEUP_POLARITY_BIT   16
 426 +
 427 +void avalanche_wakeup_ctrl(AVALANCHE_WAKEUP_INTERRUPT_T wakeup_int,
 428 +                           AVALANCHE_WAKEUP_CTRL_T      wakeup_ctrl,
 429 +                           AVALANCHE_WAKEUP_POLARITY_T  wakeup_polarity)
 430 +{
 431 +    volatile unsigned int *wakeup_status_reg = (unsigned int*) AVALANCHE_WAKEUP_CTRL_WKCR;
 432 +
 433 +    /* enable/disable */
 434 +    if (wakeup_ctrl == WAKEUP_ENABLED)
 435 +        /* enable wakeup */
 436 +        *wakeup_status_reg |= wakeup_int;
 437 +    else
 438 +        /* disable wakeup */
 439 +        *wakeup_status_reg &= (~wakeup_int);
 440 +
 441 +    /* set polarity */
 442 +    if (wakeup_polarity == WAKEUP_ACTIVE_LOW)
 443 +        *wakeup_status_reg |=  (wakeup_int << AVALANCHE_WAKEUP_POLARITY_BIT);
 444 +    else
 445 +        *wakeup_status_reg &= ~(wakeup_int << AVALANCHE_WAKEUP_POLARITY_BIT);
 446 +}
 447 +
 448 +void avalanche_set_vbus_freq(unsigned int new_vbus_freq)
 449 +{
 450 +    avalanche_vbus_freq = new_vbus_freq;
 451 +}
 452 +
 453 +unsigned int avalanche_get_vbus_freq()
 454 +{
 455 +    return(avalanche_vbus_freq);
 456 +}
 457 +
 458 +unsigned int avalanche_get_chip_version_info()
 459 +{
 460 +    return(*(volatile unsigned int*)AVALANCHE_CVR);
 461 +}
 462 +
 463 +SET_MDIX_ON_CHIP_FN_T p_set_mdix_on_chip_fn = NULL;
 464 +
 465 +int avalanche_set_mdix_on_chip(unsigned int base_addr, unsigned int operation)
 466 +{
 467 +    if(p_set_mdix_on_chip_fn)
 468 +        return (p_set_mdix_on_chip_fn(base_addr, operation));
 469 +    else
 470 +        return(-1);
 471 +}
 472 +
 473 +unsigned int avalanche_is_mdix_on_chip(void)
 474 +{
 475 +    return(p_set_mdix_on_chip_fn ? 1:0);
 476 +}
 477 +
 478 +EXPORT_SYMBOL(avalanche_reset_ctrl);
 479 +EXPORT_SYMBOL(avalanche_get_reset_status);
 480 +EXPORT_SYMBOL(avalanche_sys_reset);
 481 +EXPORT_SYMBOL(avalanche_get_sys_last_reset_status);
 482 +EXPORT_SYMBOL(avalanche_power_ctrl);
 483 +EXPORT_SYMBOL(avalanche_get_power_status);
 484 +EXPORT_SYMBOL(avalanche_set_global_power_mode);
 485 +EXPORT_SYMBOL(avalanche_get_global_power_mode);
 486 +EXPORT_SYMBOL(avalanche_set_mdix_on_chip);
 487 +EXPORT_SYMBOL(avalanche_is_mdix_on_chip);
 488 +
 489 +EXPORT_SYMBOL(avalanche_gpio_init);
 490 +EXPORT_SYMBOL(avalanche_gpio_ctrl);
 491 +EXPORT_SYMBOL(avalanche_gpio_out_bit);
 492 +EXPORT_SYMBOL(avalanche_gpio_in_bit);
 493 +EXPORT_SYMBOL(avalanche_gpio_out_value);
 494 +EXPORT_SYMBOL(avalanche_gpio_in_value);
 495 +
 496 +EXPORT_SYMBOL(avalanche_set_vbus_freq);
 497 +EXPORT_SYMBOL(avalanche_get_vbus_freq);
 498 +
 499 +EXPORT_SYMBOL(avalanche_get_chip_version_info);
 500 +
 501 diff -urN linux.old/arch/mips/ar7/ar7/paging.c linux.dev/arch/mips/ar7/ar7/paging.c
 502 --- linux.old/arch/mips/ar7/ar7/paging.c        1970-01-01 01:00:00.000000000 +0100
 503 +++ linux.dev/arch/mips/ar7/ar7/paging.c        2005-07-26 18:38:00.086612640 +0200
 504 @@ -0,0 +1,265 @@
 505 +/*
 506 + *  -*- linux-c -*-
 507 + * This file is subject to the terms and conditions of the GNU General Public
 508 + * License.  See the file "COPYING" in the main directory of this archive
 509 + * for more details.
 510 + *
 511 + * Copyright (C) 2002 by Jeff Harrell (jharrell@ti.com)
 512 + * Copyright (C) 2002 Texas Instruments, Inc.
 513 + *
 514 + */
 515 +
 516 +/*
 517 + * This file takes care of the "memory hole" issue that exists with the standard
 518 + * linux kernel and the TI Avalanche ASIC.  The Avalanche ASIC requires an offset
 519 + * of 0x14000000 due to the ASIC's memory map constraints.  This file corrects the
 520 + * paging tables so that the only reflect valid memory (i.e. > 0x14000000)
 521 + *
 522 + *  -JAH
 523 + */
 524 +#include <linux/config.h>
 525 +#include <linux/signal.h>
 526 +#include <linux/sched.h>
 527 +#include <linux/kernel.h>
 528 +#include <linux/errno.h>
 529 +#include <linux/string.h>
 530 +#include <linux/types.h>
 531 +#include <linux/ptrace.h>
 532 +#include <linux/mman.h>
 533 +#include <linux/mm.h>
 534 +#include <linux/swap.h>
 535 +#include <linux/smp.h>
 536 +#include <linux/init.h>
 537 +#ifdef CONFIG_BLK_DEV_INITRD
 538 +#include <linux/blk.h>
 539 +#endif /* CONFIG_BLK_DEV_INITRD */
 540 +#include <linux/highmem.h>
 541 +#include <linux/bootmem.h>
 542 +
 543 +#include <asm/processor.h>
 544 +#include <asm/system.h>
 545 +#include <asm/uaccess.h>
 546 +#include <asm/pgtable.h>
 547 +#include <asm/pgalloc.h>
 548 +#include <asm/mmu_context.h>
 549 +#include <asm/io.h>
 550 +#include <asm/tlb.h>
 551 +#include <asm/cpu.h>
 552 +
 553 +static unsigned long totalram_pages;
 554 +/* static unsigned long totalhigh_pages; */
 555 +
 556 +#define START_PFN (NODE_DATA(0)->bdata->node_boot_start >> PAGE_SHIFT)
 557 +#define MAX_LOW_PFN (NODE_DATA(0)->bdata->node_low_pfn)
 558 +
 559 +#define PFN_UP(x)  (((x) + PAGE_SIZE - 1) >> PAGE_SHIFT)
 560 +#define PFN_DOWN(x)        ((x) >> PAGE_SHIFT)
 561 +#define PFN_PHYS(x)        ((x) << PAGE_SHIFT)
 562 +
 563 +/*
 564 + * We have upto 8 empty zeroed pages so we can map one of the right colour
 565 + * when needed.  This is necessary only on R4000 / R4400 SC and MC versions
 566 + * where we have to avoid VCED / VECI exceptions for good performance at
 567 + * any price.  Since page is never written to after the initialization we
 568 + * don't have to care about aliases on other CPUs.
 569 + */
 570 +
 571 +static inline unsigned long setup_zero_pages(void)
 572 +{
 573 +       unsigned long order, size;
 574 +       struct page *page;
 575 +       if(current_cpu_data.options & MIPS_CPU_VCE)
 576 +               order = 3;
 577 +       else
 578 +               order = 0;
 579 +
 580 +       empty_zero_page = __get_free_pages(GFP_KERNEL, order);
 581 +
 582 +       if (!empty_zero_page)
 583 +               panic("Oh boy, that early out of memory?");
 584 +
 585 +       page = virt_to_page(empty_zero_page);
 586 +
 587 +       while (page < virt_to_page(empty_zero_page + (PAGE_SIZE << order))) {
 588 +               set_bit(PG_reserved, &page->flags);
 589 +               set_page_count(page, 0);
 590 +               page++;
 591 +       }
 592 +
 593 +       size = PAGE_SIZE << order;
 594 +       zero_page_mask = (size - 1) & PAGE_MASK;
 595 +       memset((void *)empty_zero_page, 0, size);
 596 +
 597 +       return 1UL << order;
 598 +}
 599 +
 600 +/*
 601 + * paging_init() sets up the page tables
 602 + *
 603 + * This routines also unmaps the page at virtual kernel address 0, so
 604 + * that we can trap those pesky NULL-reference errors in the kernel.
 605 + */
 606 +void __init paging_init(void)
 607 +{
 608 +       unsigned long zones_size[MAX_NR_ZONES] = {0, 0, 0};
 609 +       unsigned long low, start_pfn;
 610 +
 611 +       /* Initialize the entire pgd.  */
 612 +       pgd_init((unsigned long)swapper_pg_dir);
 613 +       pgd_init((unsigned long)swapper_pg_dir + PAGE_SIZE / 2);
 614 +
 615 +
 616 +       start_pfn = START_PFN;
 617 +       // max_dma = virt_to_phys((char *)MAX_DMA_ADDRESS) >> PAGE_SHIFT;
 618 +       low = MAX_LOW_PFN;
 619 +
 620 +       /* Avalanche DMA-able memory 0x14000000+memsize */
 621 +
 622 +       zones_size[ZONE_DMA] = low - start_pfn;
 623 +
 624 +       free_area_init_node(0, NODE_DATA(0), 0, zones_size, CONFIG_AR7_MEMORY, 0);
 625 +}
 626 +
 627 +extern char _ftext, _etext, _fdata, _edata, _end;
 628 +extern char __init_begin, __init_end;
 629 +
 630 +void __init mem_init(void)
 631 +{
 632 +       int codesize, reservedpages, datasize, initsize;
 633 +       int tmp;
 634 +
 635 +       max_mapnr = num_physpages = MAX_LOW_PFN - START_PFN;
 636 +       high_memory = (void *)__va(MAX_LOW_PFN * PAGE_SIZE);
 637 +
 638 +       /* free up the memory associated with Adam2 -
 639 +        * that is the, after the first page that is
 640 +        * reserved all the way up to the start of the kernel
 641 +        */
 642 +       free_bootmem_node(NODE_DATA(0), (CONFIG_AR7_MEMORY+PAGE_SIZE),
 643 +                       (__pa(&_ftext))-(CONFIG_AR7_MEMORY+PAGE_SIZE) );
 644 +
 645 +       /* this will put all low memory onto the freelists */
 646 +       totalram_pages += free_all_bootmem_node(NODE_DATA(0));
 647 +
 648 +       /* Setup zeroed pages */
 649 +       totalram_pages -= setup_zero_pages();
 650 +
 651 +       reservedpages = 0;
 652 +       for (tmp = 0; tmp < num_physpages; tmp++)
 653 +               /*
 654 +                * Only count reserved RAM pages
 655 +                */
 656 +               if (PageReserved(mem_map+tmp))
 657 +                       reservedpages++;
 658 +
 659 +       codesize =  (unsigned long) &_etext - (unsigned long) &_ftext;
 660 +       datasize =  (unsigned long) &_edata - (unsigned long) &_fdata;
 661 +       initsize =  (unsigned long) &__init_end - (unsigned long) &__init_begin;
 662 +
 663 +       printk("Memory: %luk/%luk available (%dk kernel code, %dk reserved, %dk data, %dk init)\n",
 664 +                       (unsigned long) nr_free_pages() << (PAGE_SHIFT-10),
 665 +                       max_mapnr << (PAGE_SHIFT-10),
 666 +                       codesize >> 10,
 667 +                       reservedpages << (PAGE_SHIFT-10),
 668 +                       datasize >> 10,
 669 +                       initsize >> 10);
 670 +
 671 +}
 672 +
 673 +/* fixes paging routines for avalanche  (utilized in /arch/mips/kernel/setup.c) */
 674 +
 675 +void avalanche_bootmem_init(void)
 676 +{
 677 +       unsigned long start_pfn, max_pfn;
 678 +       unsigned long max_low_pfn;
 679 +       unsigned int memory_end,memory_start;
 680 +       unsigned long bootmap_size;
 681 +
 682 +       memory_start = (unsigned long)PAGE_OFFSET+CONFIG_AR7_MEMORY;
 683 +       memory_end = memory_start + 0x02000000;
 684 +
 685 +       /*
 686 +        * Find the highest memory page fram number we have available
 687 +        */
 688 +
 689 +       max_pfn = PFN_DOWN(__pa(memory_end));
 690 +
 691 +       /*
 692 +        * Determine the low and high memory ranges
 693 +        */
 694 +
 695 +       max_low_pfn = max_pfn;
 696 +
 697 +       /*
 698 +        * Partially used pages are not usable - thus we are
 699 +        * rounding upwards:
 700 +        */
 701 +
 702 +       start_pfn = PFN_UP(__pa(&_end));
 703 +
 704 +       /*
 705 +        * Find a proper area for the bootmem bitmap. After this
 706 +        * bootstrap step all allocations (until the page allocator is
 707 +        * intact)  must be done via bootmem_alloc().
 708 +        */
 709 +
 710 +       bootmap_size = init_bootmem_node(NODE_DATA(0), start_pfn,
 711 +                       CONFIG_AR7_MEMORY>>PAGE_SHIFT, max_low_pfn);
 712 +
 713 +
 714 +       /*
 715 +        * Register fully available low RAM pages with the bootmem allocator.
 716 +        */
 717 +
 718 +       {
 719 +               unsigned long curr_pfn, last_pfn, pages;
 720 +
 721 +               /*
 722 +                * We are rounding up the start address of usable memory:
 723 +                */
 724 +               curr_pfn = PFN_UP(CONFIG_AR7_MEMORY);
 725 +
 726 +               /*
 727 +                * ... and at the end of the usable range downwards:
 728 +                */
 729 +               last_pfn = PFN_DOWN(__pa(memory_end));
 730 +
 731 +               if (last_pfn > max_low_pfn)
 732 +                       last_pfn = max_low_pfn;
 733 +
 734 +               pages = last_pfn - curr_pfn;
 735 +
 736 +
 737 +               free_bootmem_node(NODE_DATA(0), PFN_PHYS(curr_pfn),
 738 +                               PFN_PHYS(pages));
 739 +       }
 740 +
 741 +       /*
 742 +        * Reserve the kernel text and
 743 +        * Reserve the bootmem bitmap. We do this in two steps (first step
 744 +        * was init_bootmem()), because this catches the (definitely buggy)
 745 +        * case of us accidentally initializing the bootmem allocator with
 746 +        * an invalid RAM area.
 747 +        */
 748 +       reserve_bootmem_node(NODE_DATA(0), CONFIG_AR7_MEMORY+PAGE_SIZE,
 749 +                       (PFN_PHYS(start_pfn)+bootmap_size+PAGE_SIZE-1)-CONFIG_AR7_MEMORY);
 750 +
 751 +       /*
 752 +        * reserve physical page 0 - it's a special BIOS page on many boxes,
 753 +        * enabling clean reboots, SMP operation, laptop functions.
 754 +        */
 755 +       reserve_bootmem_node(NODE_DATA(0), CONFIG_AR7_MEMORY, PAGE_SIZE);
 756 +}
 757 +
 758 +void si_meminfo(struct sysinfo *val)
 759 +{
 760 +       val->totalram = totalram_pages;
 761 +       val->sharedram = 0;
 762 +       val->freeram = nr_free_pages();
 763 +       val->bufferram = atomic_read(&buffermem_pages);
 764 +       val->totalhigh = 0;
 765 +       val->freehigh = nr_free_highpages();
 766 +       val->mem_unit = PAGE_SIZE;
 767 +
 768 +       return;
 769 +}
 770 diff -urN linux.old/arch/mips/ar7/cmdline.c linux.dev/arch/mips/ar7/cmdline.c
 771 --- linux.old/arch/mips/ar7/cmdline.c   1970-01-01 01:00:00.000000000 +0100
 772 +++ linux.dev/arch/mips/ar7/cmdline.c   2005-07-26 18:11:02.623504000 +0200
 773 @@ -0,0 +1,64 @@
 774 +/*
 775 + * Carsten Langgaard, carstenl@mips.com
 776 + * Copyright (C) 1999,2000 MIPS Technologies, Inc.  All rights reserved.
 777 + *
 778 + * This program is free software; you can distribute it and/or modify it
 779 + * under the terms of the GNU General Public License (Version 2) as
 780 + * published by the Free Software Foundation.
 781 + *
 782 + * This program is distributed in the hope it will be useful, but WITHOUT
 783 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 784 + * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
 785 + * for more details.
 786 + *
 787 + * You should have received a copy of the GNU General Public License along
 788 + * with this program; if not, write to the Free Software Foundation, Inc.,
 789 + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
 790 + *
 791 + * Kernel command line creation using the prom monitor (YAMON) argc/argv.
 792 + */
 793 +#include <linux/init.h>
 794 +#include <linux/string.h>
 795 +
 796 +#include <asm/bootinfo.h>
 797 +
 798 +extern int prom_argc;
 799 +extern int *_prom_argv;
 800 +
 801 +/*
 802 + * YAMON (32-bit PROM) pass arguments and environment as 32-bit pointer.
 803 + * This macro take care of sign extension.
 804 + */
 805 +#define prom_argv(index) ((char *)(((int *)(int)_prom_argv)[(index)]))
 806 +
 807 +char arcs_cmdline[CL_SIZE];
 808 +
 809 +char * __init prom_getcmdline(void)
 810 +{
 811 +       return &(arcs_cmdline[0]);
 812 +}
 813 +
 814 +
 815 +void  __init prom_init_cmdline(void)
 816 +{
 817 +       char *cp;
 818 +       int actr;
 819 +
 820 +       actr = 1; /* Always ignore argv[0] */
 821 +
 822 +       cp = &(arcs_cmdline[0]);
 823 +#ifdef CONFIG_CMDLINE_BOOL
 824 +       strcpy(cp, CONFIG_CMDLINE);
 825 +       cp += strlen(CONFIG_CMDLINE);
 826 +       *cp++ = ' ';
 827 +#endif
 828 +       while(actr < prom_argc) {
 829 +               strcpy(cp, prom_argv(actr));
 830 +               cp += strlen(prom_argv(actr));
 831 +               *cp++ = ' ';
 832 +               actr++;
 833 +       }
 834 +       if (cp != &(arcs_cmdline[0])) /* get rid of trailing space */
 835 +               --cp;
 836 +       *cp = '\0';
 837 +}
 838 diff -urN linux.old/arch/mips/ar7/init.c linux.dev/arch/mips/ar7/init.c
 839 --- linux.old/arch/mips/ar7/init.c      1970-01-01 01:00:00.000000000 +0100
 840 +++ linux.dev/arch/mips/ar7/init.c      2005-07-26 18:11:02.624504000 +0200
 841 @@ -0,0 +1,144 @@
 842 +/*
 843 + * Carsten Langgaard, carstenl@mips.com
 844 + * Copyright (C) 1999,2000 MIPS Technologies, Inc.  All rights reserved.
 845 + *
 846 + *  This program is free software; you can distribute it and/or modify it
 847 + *  under the terms of the GNU General Public License (Version 2) as
 848 + *  published by the Free Software Foundation.
 849 + *
 850 + *  This program is distributed in the hope it will be useful, but WITHOUT
 851 + *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 852 + *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
 853 + *  for more details.
 854 + *
 855 + *  You should have received a copy of the GNU General Public License along
 856 + *  with this program; if not, write to the Free Software Foundation, Inc.,
 857 + *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
 858 + *
 859 + * PROM library initialisation code.
 860 + */
 861 +#include <linux/config.h>
 862 +#include <linux/init.h>
 863 +#include <linux/string.h>
 864 +#include <linux/kernel.h>
 865 +#include <linux/module.h>
 866 +
 867 +#include <asm/io.h>
 868 +#include <asm/mips-boards/prom.h>
 869 +#include <asm/mips-boards/generic.h>
 870 +
 871 +/* Environment variable */
 872 +typedef struct {
 873 +       char *name;
 874 +       char *val;
 875 +} t_env_var;
 876 +
 877 +int prom_argc;
 878 +int *_prom_argv, *_prom_envp;
 879 +
 880 +/* max # of Adam2 environment variables */
 881 +#define MAX_ENV_ENTRY 80
 882 +
 883 +static t_env_var local_envp[MAX_ENV_ENTRY];
 884 +int init_debug = 0;
 885 +
 886 +char *prom_getenv(char *envname)
 887 +{
 888 +       /*
 889 +        * Return a pointer to the given environment variable.
 890 +        * In 64-bit mode: we're using 64-bit pointers, but all pointers
 891 +        * in the PROM structures are only 32-bit, so we need some
 892 +        * workarounds, if we are running in 64-bit mode.
 893 +        */
 894 +       int i, index=0;
 895 +       t_env_var *env = (t_env_var *) local_envp;
 896 +
 897 +       i = strlen(envname);
 898 +       while (env->name) {
 899 +               if(strncmp(envname, env->name, i) == 0) {
 900 +                       return(env->val);
 901 +               }
 902 +               env++;
 903 +       }
 904 +
 905 +       return NULL;
 906 +}
 907 +
 908 +static inline unsigned char str2hexnum(unsigned char c)
 909 +{
 910 +       if (c >= '0' && c <= '9')
 911 +               return c - '0';
 912 +       if (c >= 'a' && c <= 'f')
 913 +               return c - 'a' + 10;
 914 +       return 0; /* foo */
 915 +}
 916 +
 917 +static inline void str2eaddr(unsigned char *ea, unsigned char *str)
 918 +{
 919 +       int i;
 920 +
 921 +       for (i = 0; i < 6; i++) {
 922 +               unsigned char num;
 923 +
 924 +               if((*str == '.') || (*str == ':'))
 925 +                       str++;
 926 +               num = str2hexnum(*str++) << 4;
 927 +               num |= (str2hexnum(*str++));
 928 +               ea[i] = num;
 929 +       }
 930 +}
 931 +
 932 +int get_ethernet_addr(char *ethernet_addr)
 933 +{
 934 +       char *ethaddr_str;
 935 +
 936 +       ethaddr_str = prom_getenv("ethaddr");
 937 +       if (!ethaddr_str) {
 938 +               printk("ethaddr not set in boot prom\n");
 939 +               return -1;
 940 +       }
 941 +       str2eaddr(ethernet_addr, ethaddr_str);
 942 +
 943 +       if (init_debug > 1) {
 944 +               int i;
 945 +               printk("get_ethernet_addr: ");
 946 +               for (i=0; i<5; i++)
 947 +                       printk("%02x:", (unsigned char)*(ethernet_addr+i));
 948 +               printk("%02x\n", *(ethernet_addr+i));
 949 +       }
 950 +
 951 +       return 0;
 952 +}
 953 +
 954 +int __init prom_init(int argc, char **argv, char **envp)
 955 +{
 956 +       int i;
 957 +       t_env_var *env = (t_env_var *) envp;
 958 +
 959 +       prom_argc = argc;
 960 +       _prom_argv = (int *)argv;
 961 +       _prom_envp = (int *)envp;
 962 +
 963 +       /* Copy what we need locally so we are not dependent on
 964 +        * bootloader RAM.  In Adam2, the environment parameters
 965 +        * are in flash but the table that references them is in
 966 +        * RAM
 967 +        */
 968 +       for(i=0; i < MAX_ENV_ENTRY; i++, env++) {
 969 +               if (env->name) {
 970 +                       local_envp[i].name = env->name;
 971 +                       local_envp[i].val = env->val;
 972 +               } else {
 973 +                       local_envp[i].name = NULL;
 974 +                       local_envp[i].val = NULL;
 975 +               }
 976 +       }
 977 +
 978 +       set_io_port_base(0);
 979 +
 980 +       prom_printf("\nLINUX started...\n");
 981 +       prom_init_cmdline();
 982 +       prom_meminit();
 983 +
 984 +       return 0;
 985 +}
 986 diff -urN linux.old/arch/mips/ar7/irq.c linux.dev/arch/mips/ar7/irq.c
 987 --- linux.old/arch/mips/ar7/irq.c       1970-01-01 01:00:00.000000000 +0100
 988 +++ linux.dev/arch/mips/ar7/irq.c       2005-07-26 18:38:00.087612488 +0200
 989 @@ -0,0 +1,709 @@
 990 +/*
 991 + * Nitin Dhingra, iamnd@ti.com
 992 + * Copyright (C) 2002 Texas Instruments, Inc.  All rights reserved.
 993 + *
 994 + * ########################################################################
 995 + *
 996 + *  This program is free software; you can distribute it and/or modify it
 997 + *  under the terms of the GNU General Public License (Version 2) as
 998 + *  published by the Free Software Foundation.
 999 + *
1000 + *  This program is distributed in the hope it will be useful, but WITHOUT
1001 + *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
1002 + *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
1003 + *  for more details.
1004 + *
1005 + *  You should have received a copy of the GNU General Public License along
1006 + *  with this program; if not, write to the Free Software Foundation, Inc.,
1007 + *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
1008 + *
1009 + * ########################################################################
1010 + *
1011 + * Routines for generic manipulation of the interrupts found on the Texas
1012 + * Instruments avalanche board
1013 + *
1014 + */
1015 +
1016 +#include <linux/config.h>
1017 +#include <linux/init.h>
1018 +#include <linux/sched.h>
1019 +#include <linux/slab.h>
1020 +#include <linux/interrupt.h>
1021 +#include <linux/kernel_stat.h>
1022 +#include <linux/proc_fs.h>
1023 +#include <asm/irq.h>
1024 +#include <asm/mips-boards/prom.h>
1025 +#include <asm/ar7/ar7.h>
1026 +#include <asm/ar7/avalanche_intc.h>
1027 +#include <asm/gdb-stub.h>
1028 +
1029 +
1030 +#define shutdown_avalanche_irq disable_avalanche_irq
1031 +#define mask_and_ack_avalanche_irq   disable_avalanche_irq
1032 +
1033 +static unsigned int startup_avalanche_irq(unsigned int irq);
1034 +static void end_avalanche_irq(unsigned int irq);
1035 +void enable_avalanche_irq(unsigned int irq_nr);
1036 +void disable_avalanche_irq(unsigned int irq_nr);
1037 +
1038 +static struct hw_interrupt_type avalanche_irq_type = {
1039 +       "TI AVALANCHE",
1040 +       startup_avalanche_irq,
1041 +       shutdown_avalanche_irq,
1042 +       enable_avalanche_irq,
1043 +       disable_avalanche_irq,
1044 +       mask_and_ack_avalanche_irq,
1045 +       end_avalanche_irq,
1046 +       NULL
1047 +};
1048 +
1049 +irq_desc_t irq_desc_ti[AVALANCHE_INT_END+1] __cacheline_aligned =
1050 +{ [0 ... AVALANCHE_INT_END] = { 0, &avalanche_irq_type, NULL, 0, SPIN_LOCK_UNLOCKED}};
1051 +
1052 +
1053 +unsigned long spurious_count = 0;
1054 +
1055 +struct avalanche_ictrl_regs         *avalanche_hw0_icregs;  /* Interrupt control regs (primary)   */
1056 +struct avalanche_exctrl_regs        *avalanche_hw0_ecregs;  /* Exception control regs (secondary) */
1057 +struct avalanche_ipace_regs         *avalanche_hw0_ipaceregs;
1058 +struct avalanche_channel_int_number *avalanche_hw0_chregs;  /* Channel control registers          */
1059 +
1060 +extern asmlinkage void mipsIRQ(void);
1061 +
1062 +
1063 +/*
1064 + *   The avalanche/MIPS interrupt line numbers are used to represent the
1065 + *   interrupts within the irqaction arrays.  The index notation is
1066 + *   is as follows:
1067 + *
1068 + *           0-7    MIPS CPU Exceptions  (HW/SW)
1069 + *           8-47   Primary Interrupts   (Avalanche)
1070 + *           48-79  Secondary Interrupts (Avalanche)
1071 + *
1072 + */
1073 +
1074 +
1075 +static struct irqaction *hw0_irq_action_primary[AVINTNUM(AVALANCHE_INT_END_PRIMARY)] =
1076 +{
1077 +       NULL, NULL, NULL, NULL,
1078 +       NULL, NULL, NULL, NULL,
1079 +       NULL, NULL, NULL, NULL,
1080 +       NULL, NULL, NULL, NULL,
1081 +       NULL, NULL, NULL, NULL,
1082 +       NULL, NULL, NULL, NULL,
1083 +       NULL, NULL, NULL, NULL,
1084 +       NULL, NULL, NULL, NULL,
1085 +       NULL, NULL, NULL, NULL,
1086 +       NULL, NULL, NULL, NULL
1087 +};
1088 +
1089 +static struct irqaction *hw0_irq_action_secondary[AVINTNUM(AVALANCHE_INT_END_SECONDARY)] =
1090 +{
1091 +       NULL, NULL, NULL, NULL,
1092 +       NULL, NULL, NULL, NULL,
1093 +       NULL, NULL, NULL, NULL,
1094 +       NULL, NULL, NULL, NULL,
1095 +       NULL, NULL, NULL, NULL,
1096 +       NULL, NULL, NULL, NULL,
1097 +       NULL, NULL, NULL, NULL,
1098 +       NULL, NULL, NULL, NULL
1099 +};
1100 +
1101 +/*
1102 +   This remaps interrupts to exist on other channels than the default
1103 +   channels.  essentially we can use the line # as the index for this
1104 +   array
1105 + */
1106 +
1107 +
1108 +static unsigned long line_to_channel[AVINTNUM(AVALANCHE_INT_END_PRIMARY)];
1109 +unsigned long uni_secondary_interrupt = 0;
1110 +
1111 +static struct irqaction r4ktimer_action = {
1112 +       NULL, 0, 0, "R4000 timer/counter", NULL, NULL,
1113 +};
1114 +
1115 +static struct irqaction *irq_action[8] = {
1116 +       NULL,              /* SW int 0 */
1117 +       NULL,              /* SW int 1 */
1118 +       NULL,              /* HW int 0 */
1119 +       NULL,
1120 +       NULL,
1121 +       NULL,              /* HW int 3 */
1122 +       NULL,              /* HW int 4 */
1123 +       &r4ktimer_action   /* HW int 5 */
1124 +};
1125 +
1126 +static void end_avalanche_irq(unsigned int irq)
1127 +{
1128 +       if (!(irq_desc_ti[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
1129 +               enable_avalanche_irq(irq);
1130 +}
1131 +
1132 +void disable_avalanche_irq(unsigned int irq_nr)
1133 +{
1134 +       unsigned long flags;
1135 +       unsigned long chan_nr=0;
1136 +       unsigned long int_bit=0;
1137 +
1138 +       if(irq_nr >= AVALANCHE_INT_END)
1139 +       {
1140 +               printk("whee, invalid irq_nr %d\n", irq_nr);
1141 +               panic("IRQ, you lose...");
1142 +       }
1143 +
1144 +       save_and_cli(flags);
1145 +
1146 +
1147 +       if(irq_nr <  MIPS_EXCEPTION_OFFSET)
1148 +       {
1149 +               /* disable mips exception */
1150 +
1151 +               int_bit = read_c0_status() & ~(1 << (8+irq_nr));
1152 +               change_c0_status(ST0_IM,int_bit);
1153 +               restore_flags(flags);
1154 +               return;
1155 +       }
1156 +
1157 +       /* irq_nr represents the line number for the interrupt.  We must
1158 +        *  disable the channel number associated with that line number.
1159 +        */
1160 +
1161 +       if(irq_nr > AVALANCHE_INT_END_PRIMARY_REG2)
1162 +               chan_nr = AVINTNUM(irq_nr);                 /*CHECK THIS ALSO*/
1163 +       else
1164 +               chan_nr = line_to_channel[AVINTNUM(irq_nr)];/* WE NEED A LINE TO CHANNEL MAPPING FUNCTION HERE*/
1165 +
1166 +       /* disable the interrupt channel bit */
1167 +
1168 +       /* primary interrupt #'s 0-31 */
1169 +
1170 +       if(chan_nr <= AVINTNUM(AVALANCHE_INT_END_PRIMARY_REG1))
1171 +               avalanche_hw0_icregs->intecr1 = (1 << chan_nr);
1172 +
1173 +       /* primary interrupt #'s 32-39 */
1174 +
1175 +       else if ((chan_nr <= AVINTNUM(AVALANCHE_INT_END_PRIMARY_REG2)) &&
1176 +                       (chan_nr > AVINTNUM(AVALANCHE_INT_END_PRIMARY_REG1)))
1177 +               avalanche_hw0_icregs->intecr2 = (1 << (chan_nr - AVINTNUM(AVALANCHE_INT_END_SECONDARY)));
1178 +
1179 +       else  /* secondary interrupt #'s 0-31 */
1180 +               avalanche_hw0_ecregs->exiecr = (1 << (chan_nr - AVINTNUM(AVALANCHE_INT_END_PRIMARY)));
1181 +
1182 +       restore_flags(flags);
1183 +}
1184 +
1185 +void enable_avalanche_irq(unsigned int irq_nr)
1186 +{
1187 +       unsigned long flags;
1188 +       unsigned long chan_nr=0;
1189 +       unsigned long int_bit=0;
1190 +
1191 +       if(irq_nr > AVALANCHE_INT_END) {
1192 +               printk("whee, invalid irq_nr %d\n", irq_nr);
1193 +               panic("IRQ, you lose...");
1194 +       }
1195 +
1196 +       save_and_cli(flags);
1197 +
1198 +
1199 +       if(irq_nr <  MIPS_EXCEPTION_OFFSET)
1200 +       {
1201 +               /* Enable MIPS exceptions */
1202 +               int_bit = read_c0_status();
1203 +               change_c0_status(ST0_IM,int_bit | (1<<(8+irq_nr)));
1204 +               restore_flags(flags);
1205 +               return;
1206 +       }
1207 +
1208 +       /* irq_nr represents the line number for the interrupt.  We must
1209 +        *  disable the channel number associated with that line number.
1210 +        */
1211 +
1212 +       if(irq_nr > AVALANCHE_INT_END_PRIMARY_REG2)
1213 +               chan_nr = AVINTNUM(irq_nr);
1214 +       else
1215 +               chan_nr = line_to_channel[AVINTNUM(irq_nr)];
1216 +
1217 +       /* enable the interrupt channel  bit */
1218 +
1219 +       /* primary interrupt #'s 0-31 */
1220 +       if(chan_nr <= AVINTNUM(AVALANCHE_INT_END_PRIMARY_REG1))
1221 +               avalanche_hw0_icregs->intesr1 = (1 << chan_nr);
1222 +
1223 +       /* primary interrupt #'s 32 throuth 39 */
1224 +       else if ((chan_nr <= AVINTNUM(AVALANCHE_INT_END_PRIMARY_REG2)) &&
1225 +                       (chan_nr > AVINTNUM(AVALANCHE_INT_END_PRIMARY_REG1)))
1226 +               avalanche_hw0_icregs->intesr2 = (1 << (chan_nr - AVINTNUM(AVALANCHE_INT_END_SECONDARY)));
1227 +
1228 +       else    /* secondary interrupt #'s 0-31 */
1229 +               avalanche_hw0_ecregs->exiesr = (1 << (chan_nr - AVINTNUM(AVALANCHE_INT_END_PRIMARY)));
1230 +
1231 +       restore_flags(flags);
1232 +}
1233 +
1234 +static unsigned int startup_avalanche_irq(unsigned int irq)
1235 +{
1236 +       enable_avalanche_irq(irq);
1237 +       return 0; /* never anything pending */
1238 +}
1239 +
1240 +
1241 +int get_irq_list(char *buf)
1242 +{
1243 +       int i, len = 0;
1244 +       int num = 0;
1245 +       struct irqaction *action;
1246 +
1247 +       for (i = 0; i < MIPS_EXCEPTION_OFFSET; i++, num++)
1248 +       {
1249 +               action = irq_action[i];
1250 +               if (!action)
1251 +                       continue;
1252 +               len += sprintf(buf+len, "%2d: %8d %c %s",
1253 +                               num, kstat.irqs[0][num],
1254 +                               (action->flags & SA_INTERRUPT) ? '+' : ' ',
1255 +                               action->name);
1256 +               for (action=action->next; action; action = action->next) {
1257 +                       len += sprintf(buf+len, ",%s %s",
1258 +                                       (action->flags & SA_INTERRUPT) ? " +" : "",
1259 +                                       action->name);
1260 +               }
1261 +               len += sprintf(buf+len, " [MIPS interrupt]\n");
1262 +       }
1263 +
1264 +
1265 +       for (i = 0; i < AVINTNUM(AVALANCHE_INT_END); i++,num++)
1266 +       {
1267 +               if(i < AVINTNUM(AVALANCHE_INT_END_PRIMARY))
1268 +                       action = hw0_irq_action_primary[i];
1269 +               else
1270 +                       action = hw0_irq_action_secondary[i-AVINTNUM(AVALANCHE_INT_END_PRIMARY)];
1271 +               if (!action)
1272 +                       continue;
1273 +               len += sprintf(buf+len, "%2d: %8d %c %s",
1274 +                               num, kstat.irqs[0][ LNXINTNUM(i) ],
1275 +                               (action->flags & SA_INTERRUPT) ? '+' : ' ',
1276 +                               action->name);
1277 +
1278 +               for (action=action->next; action; action = action->next)
1279 +               {
1280 +                       len += sprintf(buf+len, ",%s %s",
1281 +                                       (action->flags & SA_INTERRUPT) ? " +" : "",
1282 +                                       action->name);
1283 +               }
1284 +
1285 +               if(i < AVINTNUM(AVALANCHE_INT_END_PRIMARY))
1286 +                       len += sprintf(buf+len, " [hw0 (Avalanche Primary)]\n");
1287 +               else
1288 +                       len += sprintf(buf+len, " [hw0 (Avalanche Secondary)]\n");
1289 +
1290 +       }
1291 +
1292 +       return len;
1293 +}
1294 +
1295 +int request_irq(unsigned int irq,
1296 +               void (*handler)(int, void *, struct pt_regs *),
1297 +               unsigned long irqflags,
1298 +               const char * devname,
1299 +               void *dev_id)
1300 +{
1301 +       struct irqaction *action;
1302 +
1303 +       if (irq >  AVALANCHE_INT_END)
1304 +               return -EINVAL;
1305 +       if (!handler)
1306 +               return -EINVAL;
1307 +
1308 +       action = (struct irqaction *)kmalloc(sizeof(struct irqaction), GFP_KERNEL);
1309 +       if(!action)
1310 +               return -ENOMEM;
1311 +
1312 +       action->handler = handler;
1313 +       action->flags = irqflags;
1314 +       action->mask = 0;
1315 +       action->name = devname;
1316 +       irq_desc_ti[irq].action = action;
1317 +       action->dev_id = dev_id;
1318 +
1319 +       action->next = 0;
1320 +
1321 +       if(irq <  MIPS_EXCEPTION_OFFSET)
1322 +       {
1323 +               irq_action[irq] = action;
1324 +               enable_avalanche_irq(irq);
1325 +               return 0;
1326 +       }
1327 +
1328 +       if(irq < AVALANCHE_INT_END_PRIMARY)
1329 +               hw0_irq_action_primary[line_to_channel[AVINTNUM(irq)]] = action;
1330 +       else
1331 +               hw0_irq_action_secondary[irq - AVALANCHE_INT_END_PRIMARY] = action;
1332 +
1333 +       enable_avalanche_irq(irq);
1334 +
1335 +       return 0;
1336 +}
1337 +
1338 +void free_irq(unsigned int irq, void *dev_id)
1339 +{
1340 +       struct irqaction *action;
1341 +
1342 +       if (irq > AVALANCHE_INT_END) {
1343 +               printk("Trying to free IRQ%d\n",irq);
1344 +               return;
1345 +       }
1346 +
1347 +       if(irq <  MIPS_EXCEPTION_OFFSET)
1348 +       {
1349 +               action = irq_action[irq];
1350 +               irq_action[irq] = NULL;
1351 +               irq_desc_ti[irq].action = NULL;
1352 +               disable_avalanche_irq(irq);
1353 +               kfree(action);
1354 +               return;
1355 +       }
1356 +
1357 +       if(irq < AVALANCHE_INT_END_PRIMARY) {
1358 +               action = hw0_irq_action_primary[line_to_channel[AVINTNUM(irq)]];
1359 +               hw0_irq_action_primary[line_to_channel[AVINTNUM(irq)]] = NULL;
1360 +               irq_desc_ti[irq].action = NULL;
1361 +       }
1362 +       else {
1363 +               action = hw0_irq_action_secondary[irq - AVALANCHE_INT_END_PRIMARY];
1364 +               hw0_irq_action_secondary[irq - AVALANCHE_INT_END_PRIMARY] = NULL;
1365 +               irq_desc_ti[irq].action = NULL;
1366 +       }
1367 +
1368 +       disable_avalanche_irq(irq);
1369 +       kfree(action);
1370 +}
1371 +
1372 +#ifdef CONFIG_KGDB
1373 +extern void breakpoint(void);
1374 +extern int remote_debug;
1375 +#endif
1376 +
1377 +//void init_IRQ(void) __init;
1378 +void __init init_IRQ(void)
1379 +{
1380 +       int i;
1381 +
1382 +       avalanche_hw0_icregs = (struct avalanche_ictrl_regs *)AVALANCHE_ICTRL_REGS_BASE;
1383 +       avalanche_hw0_ecregs = (struct avalanche_exctrl_regs *)AVALANCHE_ECTRL_REGS_BASE;
1384 +       avalanche_hw0_ipaceregs = (struct avalanche_ipace_regs *)AVALANCHE_IPACE_REGS_BASE;
1385 +       avalanche_hw0_chregs = (struct avalanche_channel_int_number *)AVALANCHE_CHCTRL_REGS_BASE;
1386 +
1387 +       /*  Disable interrupts and clear pending
1388 +        */
1389 +
1390 +       avalanche_hw0_icregs->intecr1 = 0xffffffff;    /* disable interrupts 0:31  */
1391 +       avalanche_hw0_icregs->intcr1 = 0xffffffff;     /* clear interrupts 0:31    */
1392 +       avalanche_hw0_icregs->intecr2 = 0xff;          /* disable interrupts 32:39 */
1393 +       avalanche_hw0_icregs->intcr2 = 0xff;           /* clear interrupts 32:39   */
1394 +       avalanche_hw0_ecregs->exiecr = 0xffffffff;     /* disable secondary interrupts 0:31 */
1395 +       avalanche_hw0_ecregs->excr = 0xffffffff;       /* clear secondary interrupts 0:31 */
1396 +
1397 +
1398 +       // avalanche_hw0_ipaceregs->ipacep = (2*get_avalanche_vbus_freq()/1000000)*4;
1399 +       /* hack for speeding up the pacing. */
1400 +       printk("the pacing pre-scalar has been set as 600.\n");
1401 +       avalanche_hw0_ipaceregs->ipacep = 600;
1402 +       /* Channel to line mapping, Line to Channel mapping */
1403 +
1404 +       for(i = 0; i < 40; i++)
1405 +               avalanche_int_set(i,i);
1406 +
1407 +       /* Now safe to set the exception vector. */
1408 +       set_except_vector(0, mipsIRQ);
1409 +
1410 +       /* Setup the IRQ description array.  These will be mapped
1411 +        *  as flat interrupts numbers.  The mapping is as follows
1412 +        *
1413 +        *           0-7    MIPS CPU Exceptions  (HW/SW)
1414 +        *           8-46   Primary Interrupts   (Avalanche)
1415 +        *           47-78  Secondary Interrupts (Avalanche)
1416 +        */
1417 +
1418 +       for (i = 0; i <= AVALANCHE_INT_END; i++)
1419 +       {
1420 +               irq_desc_ti[i].status   = IRQ_DISABLED;
1421 +               irq_desc_ti[i].action   = 0;
1422 +               irq_desc_ti[i].depth    = 1;
1423 +               irq_desc_ti[i].handler  = &avalanche_irq_type;
1424 +       }
1425 +
1426 +#ifdef CONFIG_KGDB
1427 +       if (remote_debug)
1428 +       {
1429 +               set_debug_traps();
1430 +               breakpoint();
1431 +       }
1432 +#endif
1433 +}
1434 +
1435 +
1436 +void avalanche_hw0_irqdispatch(struct pt_regs *regs)
1437 +{
1438 +       struct irqaction *action;
1439 +       int irq, cpu = smp_processor_id();
1440 +       unsigned long int_line_number,status;
1441 +       int i,secondary = 0;
1442 +       int chan_nr=0;
1443 +
1444 +       int_line_number = ((avalanche_hw0_icregs->pintir >> 16) & 0x3F);
1445 +       chan_nr = ((avalanche_hw0_icregs->pintir) & 0x3F);
1446 +
1447 +
1448 +       if(chan_nr < 32)
1449 +       {
1450 +               if( chan_nr != uni_secondary_interrupt)
1451 +                       avalanche_hw0_icregs->intcr1 = (1<<chan_nr);
1452 +
1453 +       }
1454 +
1455 +       if((chan_nr < 40) && (chan_nr > 31))
1456 +       {
1457 +               avalanche_hw0_icregs->intcr2 = (1<<(chan_nr-AVINTNUM(AVALANCHE_INT_END_SECONDARY)));
1458 +       }
1459 +
1460 +
1461 +       /* If the Priority Interrupt Index Register returns 40  then no
1462 +        * interrupts are pending
1463 +        */
1464 +
1465 +       if(chan_nr == 40)
1466 +               return;
1467 +
1468 +       if(chan_nr == uni_secondary_interrupt)
1469 +       {
1470 +               status = avalanche_hw0_ecregs->exsr;
1471 +               for(i=0; i < AVINTNUM(AVALANCHE_INT_END_SECONDARY); i++)
1472 +               {
1473 +                       if (status & 1<<i)
1474 +                       {
1475 +                               /* clear secondary interrupt */
1476 +                               avalanche_hw0_ecregs->excr = 1 << i;
1477 +                               break;
1478 +                       }
1479 +               }
1480 +               irq = i;
1481 +               secondary = 1;
1482 +
1483 +               /* clear the universal secondary interrupt */
1484 +               avalanche_hw0_icregs->intcr1 = 1 << uni_secondary_interrupt;
1485 +
1486 +       }
1487 +       else
1488 +               irq = chan_nr;
1489 +
1490 +       /* Suraj Add code to clear secondary interrupt */
1491 +
1492 +       if(secondary)
1493 +               action = hw0_irq_action_secondary[irq];
1494 +       else
1495 +               action = hw0_irq_action_primary[irq];
1496 +
1497 +       /* if action == NULL, then we don't have a handler for the irq */
1498 +
1499 +       if ( action == NULL ) {
1500 +               printk("No handler for hw0 irq: %i\n", irq);
1501 +               return;
1502 +       }
1503 +
1504 +       irq_enter(cpu,irq);
1505 +       if(secondary)
1506 +       {
1507 +               kstat.irqs[0][(irq + AVINTNUM(AVALANCHE_INT_END_PRIMARY)) + 8]++;
1508 +               action->handler((irq + AVALANCHE_INT_END_PRIMARY), action->dev_id, regs);
1509 +       }
1510 +       else
1511 +       {
1512 +               kstat.irqs[0][irq + 8]++;
1513 +               action->handler(LNXINTNUM(irq), action->dev_id, regs);
1514 +       }
1515 +
1516 +       irq_exit(cpu,irq);
1517 +
1518 +       if(softirq_pending(cpu))
1519 +               do_softirq();
1520 +
1521 +       return;
1522 +}
1523 +
1524 +void avalanche_int_set(int channel, int line)
1525 +{
1526 +       switch(channel)
1527 +       {
1528 +               case(0):
1529 +                       avalanche_hw0_chregs->cintnr0 =  line;
1530 +                       break;
1531 +               case(1):
1532 +                       avalanche_hw0_chregs->cintnr1 =  line;
1533 +                       break;
1534 +               case(2):
1535 +                       avalanche_hw0_chregs->cintnr2 =  line;
1536 +                       break;
1537 +               case(3):
1538 +                       avalanche_hw0_chregs->cintnr3 =  line;
1539 +                       break;
1540 +               case(4):
1541 +                       avalanche_hw0_chregs->cintnr4 =  line;
1542 +                       break;
1543 +               case(5):
1544 +                       avalanche_hw0_chregs->cintnr5 =  line;
1545 +                       break;
1546 +               case(6):
1547 +                       avalanche_hw0_chregs->cintnr6 =  line;
1548 +                       break;
1549 +               case(7):
1550 +                       avalanche_hw0_chregs->cintnr7 =  line;
1551 +                       break;
1552 +               case(8):
1553 +                       avalanche_hw0_chregs->cintnr8 =  line;
1554 +                       break;
1555 +               case(9):
1556 +                       avalanche_hw0_chregs->cintnr9 =  line;
1557 +                       break;
1558 +               case(10):
1559 +                       avalanche_hw0_chregs->cintnr10 = line;
1560 +                       break;
1561 +               case(11):
1562 +                       avalanche_hw0_chregs->cintnr11 = line;
1563 +                       break;
1564 +               case(12):
1565 +                       avalanche_hw0_chregs->cintnr12 = line;
1566 +                       break;
1567 +               case(13):
1568 +                       avalanche_hw0_chregs->cintnr13 = line;
1569 +                       break;
1570 +               case(14):
1571 +                       avalanche_hw0_chregs->cintnr14 = line;
1572 +                       break;
1573 +               case(15):
1574 +                       avalanche_hw0_chregs->cintnr15 = line;
1575 +                       break;
1576 +               case(16):
1577 +                       avalanche_hw0_chregs->cintnr16 = line;
1578 +                       break;
1579 +               case(17):
1580 +                       avalanche_hw0_chregs->cintnr17 = line;
1581 +                       break;
1582 +               case(18):
1583 +                       avalanche_hw0_chregs->cintnr18 = line;
1584 +                       break;
1585 +               case(19):
1586 +                       avalanche_hw0_chregs->cintnr19 = line;
1587 +                       break;
1588 +               case(20):
1589 +                       avalanche_hw0_chregs->cintnr20 = line;
1590 +                       break;
1591 +               case(21):
1592 +                       avalanche_hw0_chregs->cintnr21 = line;
1593 +                       break;
1594 +               case(22):
1595 +                       avalanche_hw0_chregs->cintnr22 = line;
1596 +                       break;
1597 +               case(23):
1598 +                       avalanche_hw0_chregs->cintnr23 = line;
1599 +                       break;
1600 +               case(24):
1601 +                       avalanche_hw0_chregs->cintnr24 = line;
1602 +                       break;
1603 +               case(25):
1604 +                       avalanche_hw0_chregs->cintnr25 = line;
1605 +                       break;
1606 +               case(26):
1607 +                       avalanche_hw0_chregs->cintnr26 = line;
1608 +                       break;
1609 +               case(27):
1610 +                       avalanche_hw0_chregs->cintnr27 = line;
1611 +                       break;
1612 +               case(28):
1613 +                       avalanche_hw0_chregs->cintnr28 = line;
1614 +                       break;
1615 +               case(29):
1616 +                       avalanche_hw0_chregs->cintnr29 = line;
1617 +                       break;
1618 +               case(30):
1619 +                       avalanche_hw0_chregs->cintnr30 = line;
1620 +                       break;
1621 +               case(31):
1622 +                       avalanche_hw0_chregs->cintnr31 = line;
1623 +                       break;
1624 +               case(32):
1625 +                       avalanche_hw0_chregs->cintnr32 = line;
1626 +                       break;
1627 +               case(33):
1628 +                       avalanche_hw0_chregs->cintnr33 = line;
1629 +                       break;
1630 +               case(34):
1631 +                       avalanche_hw0_chregs->cintnr34 = line;
1632 +                       break;
1633 +               case(35):
1634 +                       avalanche_hw0_chregs->cintnr35 = line;
1635 +                       break;
1636 +               case(36):
1637 +                       avalanche_hw0_chregs->cintnr36 = line;
1638 +                       break;
1639 +               case(37):
1640 +                       avalanche_hw0_chregs->cintnr37 = line;
1641 +                       break;
1642 +               case(38):
1643 +                       avalanche_hw0_chregs->cintnr38 = line;
1644 +                       break;
1645 +               case(39):
1646 +                       avalanche_hw0_chregs->cintnr39 = line;
1647 +                       break;
1648 +               default:
1649 +                       printk("Error: Unknown Avalanche interrupt channel\n");
1650 +       }
1651 +
1652 +       line_to_channel[line] = channel; /* Suraj check */
1653 +
1654 +       if (channel == UNIFIED_SECONDARY_INTERRUPT)
1655 +               uni_secondary_interrupt = line;
1656 +
1657 +}
1658 +
1659 +
1660 +#define AVALANCHE_MAX_PACING_BLK   3
1661 +#define AVALANCHE_PACING_LOW_VAL   2
1662 +#define AVALANCHE_PACING_HIGH_VAL 63
1663 +
1664 +int avalanche_request_pacing(int irq_nr, unsigned int blk_num,
1665 +                            unsigned int pace_value)
1666 +{
1667 +    unsigned int  blk_offset;
1668 +    unsigned long flags;
1669 +
1670 +    if(irq_nr < MIPS_EXCEPTION_OFFSET &&
1671 +       irq_nr >= AVALANCHE_INT_END_PRIMARY)
1672 +        return (0);
1673 +
1674 +    if(blk_num > AVALANCHE_MAX_PACING_BLK)
1675 +        return(-1);
1676 +
1677 +    if(pace_value > AVALANCHE_PACING_HIGH_VAL &&
1678 +       pace_value < AVALANCHE_PACING_LOW_VAL)
1679 +       return(-1);
1680 +
1681 +    blk_offset = blk_num*8;
1682 +
1683 +    save_and_cli(flags);
1684 +
1685 +    /* disable the interrupt pacing, if enabled previously */
1686 +    avalanche_hw0_ipaceregs->ipacemax &= ~(0xff << blk_offset);
1687 +
1688 +    /* clear the pacing map */
1689 +    avalanche_hw0_ipaceregs->ipacemap &= ~(0xff << blk_offset);
1690 +
1691 +    /* setup the new values */
1692 +    avalanche_hw0_ipaceregs->ipacemap |= ((AVINTNUM(irq_nr))   << blk_offset);
1693 +    avalanche_hw0_ipaceregs->ipacemax |= ((0x80 | pace_value)  << blk_offset);
1694 +
1695 +    restore_flags(flags);
1696 +
1697 +    return(0);
1698 +}
1699 diff -urN linux.old/arch/mips/ar7/memory.c linux.dev/arch/mips/ar7/memory.c
1700 --- linux.old/arch/mips/ar7/memory.c    1970-01-01 01:00:00.000000000 +0100
1701 +++ linux.dev/arch/mips/ar7/memory.c    2005-07-26 18:38:00.087612488 +0200
1702 @@ -0,0 +1,131 @@
1703 +/*
1704 + * Carsten Langgaard, carstenl@mips.com
1705 + * Copyright (C) 1999,2000 MIPS Technologies, Inc.  All rights reserved.
1706 + *
1707 + * ########################################################################
1708 + *
1709 + *  This program is free software; you can distribute it and/or modify it
1710 + *  under the terms of the GNU General Public License (Version 2) as
1711 + *  published by the Free Software Foundation.
1712 + *
1713 + *  This program is distributed in the hope it will be useful, but WITHOUT
1714 + *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
1715 + *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
1716 + *  for more details.
1717 + *
1718 + *  You should have received a copy of the GNU General Public License along
1719 + *  with this program; if not, write to the Free Software Foundation, Inc.,
1720 + *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
1721 + *
1722 + * ########################################################################
1723 + *
1724 + * PROM library functions for acquiring/using memory descriptors given to
1725 + * us from the YAMON.
1726 + *
1727 + */
1728 +#include <linux/config.h>
1729 +#include <linux/init.h>
1730 +#include <linux/mm.h>
1731 +#include <linux/bootmem.h>
1732 +
1733 +#include <asm/bootinfo.h>
1734 +#include <asm/page.h>
1735 +#include <asm/mips-boards/prom.h>
1736 +
1737 +enum yamon_memtypes {
1738 +       yamon_dontuse,
1739 +       yamon_prom,
1740 +       yamon_free,
1741 +};
1742 +struct prom_pmemblock mdesc[PROM_MAX_PMEMBLOCKS];
1743 +
1744 +/* References to section boundaries */
1745 +extern char _end;
1746 +
1747 +#define PFN_ALIGN(x)    (((unsigned long)(x) + (PAGE_SIZE - 1)) & PAGE_MASK)
1748 +
1749 +
1750 +struct prom_pmemblock * __init prom_getmdesc(void)
1751 +{
1752 +       char *memsize_str;
1753 +       unsigned int memsize;
1754 +
1755 +       memsize_str = prom_getenv("memsize");
1756 +       if (!memsize_str) {
1757 +               memsize = 0x02000000;
1758 +       } else {
1759 +               memsize = simple_strtol(memsize_str, NULL, 0);
1760 +       }
1761 +
1762 +       memset(mdesc, 0, sizeof(mdesc));
1763 +
1764 +       mdesc[0].type = yamon_dontuse;
1765 +       mdesc[0].base = 0x00000000;
1766 +       mdesc[0].size = CONFIG_AR7_MEMORY;
1767 +
1768 +       mdesc[1].type = yamon_prom;
1769 +       mdesc[1].base = CONFIG_AR7_MEMORY;
1770 +       mdesc[1].size = 0x00020000;
1771 +
1772 +       mdesc[2].type = yamon_free;
1773 +       mdesc[2].base = CONFIG_AR7_MEMORY + 0x00020000;
1774 +       mdesc[2].size = (memsize + CONFIG_AR7_MEMORY) - mdesc[2].base;
1775 +
1776 +       return &mdesc[0];
1777 +}
1778 +
1779 +static int __init prom_memtype_classify (unsigned int type)
1780 +{
1781 +       switch (type) {
1782 +               case yamon_free:
1783 +                       return BOOT_MEM_RAM;
1784 +               case yamon_prom:
1785 +                       return BOOT_MEM_ROM_DATA;
1786 +               default:
1787 +                       return BOOT_MEM_RESERVED;
1788 +       }
1789 +}
1790 +
1791 +void __init prom_meminit(void)
1792 +{
1793 +       struct prom_pmemblock *p;
1794 +
1795 +       p = prom_getmdesc();
1796 +
1797 +       while (p->size) {
1798 +               long type;
1799 +               unsigned long base, size;
1800 +
1801 +               type = prom_memtype_classify (p->type);
1802 +               base = p->base;
1803 +               size = p->size;
1804 +
1805 +               add_memory_region(base, size, type);
1806 +               p++;
1807 +       }
1808 +}
1809 +
1810 +void __init prom_free_prom_memory (void)
1811 +{
1812 +#if 0
1813 +       int i;
1814 +       unsigned long freed = 0;
1815 +       unsigned long addr;
1816 +
1817 +       for (i = 0; i < boot_mem_map.nr_map; i++) {
1818 +               if (boot_mem_map.map[i].type != BOOT_MEM_ROM_DATA)
1819 +                       continue;
1820 +
1821 +               addr = boot_mem_map.map[i].addr;
1822 +               while (addr < boot_mem_map.map[i].addr
1823 +                               + boot_mem_map.map[i].size) {
1824 +                       ClearPageReserved(virt_to_page(__va(addr)));
1825 +                       set_page_count(virt_to_page(__va(addr)), 1);
1826 +                       free_page((unsigned long)__va(addr));
1827 +                       addr += PAGE_SIZE;
1828 +                       freed += PAGE_SIZE;
1829 +               }
1830 +       }
1831 +       printk("Freeing prom memory: %ldkb freed\n", freed >> 10);
1832 +#endif
1833 +}
1834 diff -urN linux.old/arch/mips/ar7/mipsIRQ.S linux.dev/arch/mips/ar7/mipsIRQ.S
1835 --- linux.old/arch/mips/ar7/mipsIRQ.S   1970-01-01 01:00:00.000000000 +0100
1836 +++ linux.dev/arch/mips/ar7/mipsIRQ.S   2005-07-26 18:11:02.627503000 +0200
1837 @@ -0,0 +1,120 @@
1838 +/*
1839 + * Carsten Langgaard, carstenl@mips.com
1840 + * Copyright (C) 1999, 2000 MIPS Technologies, Inc.  All rights reserved.
1841 + *
1842 + * ########################################################################
1843 + *
1844 + *  This program is free software; you can distribute it and/or modify it
1845 + *  under the terms of the GNU General Public License (Version 2) as
1846 + *  published by the Free Software Foundation.
1847 + *
1848 + *  This program is distributed in the hope it will be useful, but WITHOUT
1849 + *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
1850 + *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
1851 + *  for more details.
1852 + *
1853 + *  You should have received a copy of the GNU General Public License along
1854 + *  with this program; if not, write to the Free Software Foundation, Inc.,
1855 + *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
1856 + *
1857 + * ########################################################################
1858 + *
1859 + * Interrupt exception dispatch code.
1860 + *
1861 + */
1862 +#include <linux/config.h>
1863 +
1864 +#include <asm/asm.h>
1865 +#include <asm/mipsregs.h>
1866 +#include <asm/regdef.h>
1867 +#include <asm/stackframe.h>
1868 +
1869 +/* A lot of complication here is taken away because:
1870 + *
1871 + * 1) We handle one interrupt and return, sitting in a loop and moving across
1872 + *    all the pending IRQ bits in the cause register is _NOT_ the answer, the
1873 + *    common case is one pending IRQ so optimize in that direction.
1874 + *
1875 + * 2) We need not check against bits in the status register IRQ mask, that
1876 + *    would make this routine slow as hell.
1877 + *
1878 + * 3) Linux only thinks in terms of all IRQs on or all IRQs off, nothing in
1879 + *    between like BSD spl() brain-damage.
1880 + *
1881 + * Furthermore, the IRQs on the MIPS board look basically (barring software
1882 + * IRQs which we don't use at all and all external interrupt sources are
1883 + * combined together on hardware interrupt 0 (MIPS IRQ 2)) like:
1884 + *
1885 + *     MIPS IRQ        Source
1886 + *      --------        ------
1887 + *             0       Software (ignored)
1888 + *             1        Software (ignored)
1889 + *             2        Combined hardware interrupt (hw0)
1890 + *             3        Hardware (ignored)
1891 + *             4        Hardware (ignored)
1892 + *             5        Hardware (ignored)
1893 + *             6        Hardware (ignored)
1894 + *             7        R4k timer (what we use)
1895 + *
1896 + * Note: On the SEAD board thing are a little bit different.
1897 + *       Here IRQ 2 (hw0) is wired to the UART0 and IRQ 3 (hw1) is wired
1898 + *       wired to UART1.
1899 + *
1900 + * We handle the IRQ according to _our_ priority which is:
1901 + *
1902 + * Highest ----     R4k Timer
1903 + * Lowest  ----     Combined hardware interrupt
1904 + *
1905 + * then we just return, if multiple IRQs are pending then we will just take
1906 + * another exception, big deal.
1907 + */
1908 +
1909 +.text
1910 +.set   noreorder
1911 +.set   noat
1912 +       .align  5
1913 +NESTED(mipsIRQ, PT_SIZE, sp)
1914 +       SAVE_ALL
1915 +       CLI
1916 +       .set    at
1917 +
1918 +       mfc0    s0, CP0_CAUSE           # get irq bits
1919 +
1920 +       /* First we check for r4k counter/timer IRQ. */
1921 +       andi    a0, s0, CAUSEF_IP7
1922 +       beq     a0, zero, 1f
1923 +       andi    a0, s0, CAUSEF_IP2      # delay slot, check hw0 interrupt
1924 +
1925 +       /* Wheee, a timer interrupt. */
1926 +       move    a0, sp
1927 +       jal     ar7_timer_interrupt
1928 +       nop
1929 +
1930 +       j       ret_from_irq
1931 +       nop
1932 +
1933 +       1:
1934 +       beq     a0, zero, 1f            # delay slot, check hw3 interrupt
1935 +       nop
1936 +
1937 +       /* Wheee, combined hardware level zero interrupt. */
1938 +       jal     avalanche_hw0_irqdispatch
1939 +       move    a0, sp                  # delay slot
1940 +
1941 +       j       ret_from_irq
1942 +       nop                             # delay slot
1943 +
1944 +       1:
1945 +       /*
1946 +        * Here by mistake?  This is possible, what can happen is that by the
1947 +        * time we take the exception the IRQ pin goes low, so just leave if
1948 +        * this is the case.
1949 +        */
1950 +       move    a1,s0
1951 +       PRINT("Got interrupt: c0_cause = %08x\n")
1952 +       mfc0    a1, CP0_EPC
1953 +       PRINT("c0_epc = %08x\n")
1954 +
1955 +       j       ret_from_irq
1956 +       nop
1957 +END(mipsIRQ)
1958 diff -urN linux.old/arch/mips/ar7/printf.c linux.dev/arch/mips/ar7/printf.c
1959 --- linux.old/arch/mips/ar7/printf.c    1970-01-01 01:00:00.000000000 +0100
1960 +++ linux.dev/arch/mips/ar7/printf.c    2005-07-26 18:38:00.087612488 +0200
1961 @@ -0,0 +1,53 @@
1962 +/*
1963 + * Carsten Langgaard, carstenl@mips.com
1964 + * Copyright (C) 1999,2000 MIPS Technologies, Inc.  All rights reserved.
1965 + *
1966 + *  This program is free software; you can distribute it and/or modify it
1967 + *  under the terms of the GNU General Public License (Version 2) as
1968 + *  published by the Free Software Foundation.
1969 + *
1970 + *  This program is distributed in the hope it will be useful, but WITHOUT
1971 + *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
1972 + *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
1973 + *  for more details.
1974 + *
1975 + *  You should have received a copy of the GNU General Public License along
1976 + *  with this program; if not, write to the Free Software Foundation, Inc.,
1977 + *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
1978 + *
1979 + * Putting things on the screen/serial line using Adam2 facilities.
1980 + */
1981 +
1982 +#include <linux/config.h>
1983 +#include <linux/init.h>
1984 +#include <linux/kernel.h>
1985 +#include <linux/serial_reg.h>
1986 +#include <linux/spinlock.h>
1987 +#include <asm/io.h>
1988 +#include <asm/serial.h>
1989 +#include <asm/addrspace.h>
1990 +
1991 +#define AVALANCHE_YAMON_FUNCTION_BASE (KSEG1ADDR(0x10000500))
1992 +#define AVALANCHE_YAMON_PROM_PRINT_COUNT_ADDR (AVALANCHE_YAMON_FUNCTION_BASE + 0x4)
1993 +
1994 +static char ppbuf[1024];
1995 +
1996 +void (*prom_print_str)(unsigned int out, char *s, int len);
1997 +
1998 +void prom_printf(char *fmt, ...) __init;
1999 +void prom_printf(char *fmt, ...)
2000 +{
2001 +       va_list args;
2002 +       int len;
2003 +       prom_print_str = (void *)*(unsigned int *)AVALANCHE_YAMON_PROM_PRINT_COUNT_ADDR;
2004 +
2005 +       va_start(args, fmt);
2006 +       vsprintf(ppbuf, fmt, args);
2007 +       len = strlen(ppbuf);
2008 +
2009 +       prom_print_str(1, ppbuf, len);
2010 +
2011 +       va_end(args);
2012 +       return;
2013 +
2014 +}
2015 diff -urN linux.old/arch/mips/ar7/reset.c linux.dev/arch/mips/ar7/reset.c
2016 --- linux.old/arch/mips/ar7/reset.c     1970-01-01 01:00:00.000000000 +0100
2017 +++ linux.dev/arch/mips/ar7/reset.c     2005-07-26 18:38:00.088612336 +0200
2018 @@ -0,0 +1,56 @@
2019 +/*
2020 + * Carsten Langgaard, carstenl@mips.com
2021 + * Copyright (C) 1999,2000 MIPS Technologies, Inc.  All rights reserved.
2022 + *
2023 + * ########################################################################
2024 + *
2025 + *  This program is free software; you can distribute it and/or modify it
2026 + *  under the terms of the GNU General Public License (Version 2) as
2027 + *  published by the Free Software Foundation.
2028 + *
2029 + *  This program is distributed in the hope it will be useful, but WITHOUT
2030 + *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
2031 + *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
2032 + *  for more details.
2033 + *
2034 + *  You should have received a copy of the GNU General Public License along
2035 + *  with this program; if not, write to the Free Software Foundation, Inc.,
2036 + *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
2037 + *
2038 + * ########################################################################
2039 + *
2040 + * Reset the MIPS boards.
2041 + *
2042 + */
2043 +#include <linux/config.h>
2044 +
2045 +#include <asm/reboot.h>
2046 +#include <asm/mips-boards/generic.h>
2047 +
2048 +static void ar7_machine_restart(char *command);
2049 +static void ar7_machine_halt(void);
2050 +static void ar7_machine_power_off(void);
2051 +
2052 +static void ar7_machine_restart(char *command)
2053 +{
2054 +       volatile unsigned int *softres_reg = (void *)(KSEG1ADDR(0x08611600 + 0x4));
2055 +
2056 +       *softres_reg = 1;
2057 +}
2058 +
2059 +static void ar7_machine_halt(void)
2060 +{
2061 +
2062 +}
2063 +
2064 +static void ar7_machine_power_off(void)
2065 +{
2066 +
2067 +}
2068 +
2069 +void ar7_reboot_setup(void)
2070 +{
2071 +       _machine_restart = ar7_machine_restart;
2072 +       _machine_halt = ar7_machine_halt;
2073 +       _machine_power_off = ar7_machine_power_off;
2074 +}
2075 diff -urN linux.old/arch/mips/ar7/setup.c linux.dev/arch/mips/ar7/setup.c
2076 --- linux.old/arch/mips/ar7/setup.c     1970-01-01 01:00:00.000000000 +0100
2077 +++ linux.dev/arch/mips/ar7/setup.c     2005-07-26 18:11:02.628503000 +0200
2078 @@ -0,0 +1,120 @@
2079 +/*
2080 + * Carsten Langgaard, carstenl@mips.com
2081 + * Copyright (C) 2000 MIPS Technologies, Inc.  All rights reserved.
2082 + *
2083 + *  This program is free software; you can distribute it and/or modify it
2084 + *  under the terms of the GNU General Public License (Version 2) as
2085 + *  published by the Free Software Foundation.
2086 + *
2087 + *  This program is distributed in the hope it will be useful, but WITHOUT
2088 + *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
2089 + *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
2090 + *  for more details.
2091 + *
2092 + *  You should have received a copy of the GNU General Public License along
2093 + *  with this program; if not, write to the Free Software Foundation, Inc.,
2094 + *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
2095 + */
2096 +#include <linux/config.h>
2097 +#include <linux/init.h>
2098 +#include <linux/sched.h>
2099 +#include <linux/mc146818rtc.h>
2100 +#include <linux/ioport.h>
2101 +
2102 +#include <asm/cpu.h>
2103 +#include <asm/bootinfo.h>
2104 +#include <asm/irq.h>
2105 +#include <asm/mips-boards/generic.h>
2106 +#include <asm/mips-boards/prom.h>
2107 +
2108 +#include <asm/dma.h>
2109 +#include <asm/time.h>
2110 +#include <asm/traps.h>
2111 +
2112 +#ifdef CONFIG_KGDB
2113 +extern void rs_kgdb_hook(int);
2114 +int remote_debug = 0;
2115 +#endif
2116 +
2117 +extern struct rtc_ops no_rtc_ops;
2118 +
2119 +extern void ar7_reboot_setup(void);
2120 +
2121 +extern void ar7_time_init(void);
2122 +extern void ar7_timer_setup(struct irqaction *irq);
2123 +
2124 +const char *get_system_type(void)
2125 +{
2126 +       return "Texas Instruments AR7";
2127 +}
2128 +
2129 +void __init ar7_setup(void)
2130 +{
2131 +#ifdef CONFIG_KGDB
2132 +       int rs_putDebugChar(char);
2133 +       char rs_getDebugChar(void);
2134 +       extern int (*generic_putDebugChar)(char);
2135 +       extern char (*generic_getDebugChar)(void);
2136 +#endif
2137 +       char *argptr;
2138 +#ifdef CONFIG_SERIAL_CONSOLE
2139 +       argptr = prom_getcmdline();
2140 +       if ((argptr = strstr(argptr, "console=")) == NULL) {
2141 +               char console[20];
2142 +               char *s;
2143 +               int i = 0;
2144 +
2145 +               s = prom_getenv("modetty0");
2146 +               strcpy(console, "38400");
2147 +
2148 +               if (s != NULL) {
2149 +                       while (s[i] >= '0' && s[i] <= '9')
2150 +                               i++;
2151 +
2152 +                       if (i > 0) {
2153 +                               strncpy(console, s, i);
2154 +                               console[i] = 0;
2155 +                       }
2156 +               }
2157 +
2158 +               argptr = prom_getcmdline();
2159 +               strcat(argptr, " console=ttyS0,");
2160 +               strcat(argptr, console);
2161 +       }
2162 +#endif
2163 +
2164 +#ifdef CONFIG_KGDB
2165 +       argptr = prom_getcmdline();
2166 +       if ((argptr = strstr(argptr, "kgdb=ttyS")) != NULL) {
2167 +               int line;
2168 +               argptr += strlen("kgdb=ttyS");
2169 +               if (*argptr != '0' && *argptr != '1')
2170 +                       printk("KGDB: Uknown serial line /dev/ttyS%c, "
2171 +                                       "falling back to /dev/ttyS1\n", *argptr);
2172 +               line = *argptr == '0' ? 0 : 1;
2173 +               printk("KGDB: Using serial line /dev/ttyS%d for session\n",
2174 +                               line ? 1 : 0);
2175 +
2176 +               rs_kgdb_hook(line);
2177 +               generic_putDebugChar = rs_putDebugChar;
2178 +               generic_getDebugChar = rs_getDebugChar;
2179 +
2180 +               prom_printf("KGDB: Using serial line /dev/ttyS%d for session, "
2181 +                               "please connect your debugger\n", line ? 1 : 0);
2182 +
2183 +               remote_debug = 1;
2184 +               /* Breakpoints are in init_IRQ() */
2185 +       }
2186 +#endif
2187 +
2188 +       argptr = prom_getcmdline();
2189 +       if ((argptr = strstr(argptr, "nofpu")) != NULL)
2190 +               cpu_data[0].options &= ~MIPS_CPU_FPU;
2191 +
2192 +       rtc_ops = &no_rtc_ops;
2193 +
2194 +       ar7_reboot_setup();
2195 +
2196 +       board_time_init = ar7_time_init;
2197 +       board_timer_setup = ar7_timer_setup;
2198 +}
2199 diff -urN linux.old/arch/mips/ar7/time.c linux.dev/arch/mips/ar7/time.c
2200 --- linux.old/arch/mips/ar7/time.c      1970-01-01 01:00:00.000000000 +0100
2201 +++ linux.dev/arch/mips/ar7/time.c      2005-07-26 18:38:00.088612336 +0200
2202 @@ -0,0 +1,124 @@
2203 +/*
2204 + * Carsten Langgaard, carstenl@mips.com
2205 + * Copyright (C) 1999,2000 MIPS Technologies, Inc.  All rights reserved.
2206 + *
2207 + * ########################################################################
2208 + *
2209 + *  This program is free software; you can distribute it and/or modify it
2210 + *  under the terms of the GNU General Public License (Version 2) as
2211 + *  published by the Free Software Foundation.
2212 + *
2213 + *  This program is distributed in the hope it will be useful, but WITHOUT
2214 + *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
2215 + *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
2216 + *  for more details.
2217 + *
2218 + *  You should have received a copy of the GNU General Public License along
2219 + *  with this program; if not, write to the Free Software Foundation, Inc.,
2220 + *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
2221 + *
2222 + * ########################################################################
2223 + *
2224 + * Setting up the clock on the MIPS boards.
2225 + *
2226 + */
2227 +
2228 +#include <linux/types.h>
2229 +#include <linux/config.h>
2230 +#include <linux/init.h>
2231 +#include <linux/kernel_stat.h>
2232 +#include <linux/sched.h>
2233 +#include <linux/spinlock.h>
2234 +
2235 +#include <asm/mipsregs.h>
2236 +#include <asm/ptrace.h>
2237 +#include <asm/hardirq.h>
2238 +#include <asm/div64.h>
2239 +
2240 +#include <linux/interrupt.h>
2241 +#include <linux/mc146818rtc.h>
2242 +#include <linux/timex.h>
2243 +
2244 +#include <asm/mips-boards/generic.h>
2245 +#include <asm/mips-boards/prom.h>
2246 +
2247 +extern asmlinkage void mipsIRQ(void);
2248 +
2249 +static unsigned long r4k_offset; /* Amount to increment compare reg each time */
2250 +static unsigned long r4k_cur;    /* What counter should be at next timer irq */
2251 +
2252 +#define MIPS_CPU_TIMER_IRQ 7
2253 +#define ALLINTS (IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4 | IE_IRQ5)
2254 +
2255 +static inline void ack_r4ktimer(unsigned long newval)
2256 +{
2257 +       write_c0_compare(newval);
2258 +}
2259 +
2260 +void ar7_timer_interrupt(struct pt_regs *regs)
2261 +{
2262 +       int cpu = smp_processor_id();
2263 +
2264 +       irq_enter(cpu, MIPS_CPU_TIMER_IRQ);
2265 +
2266 +       if (r4k_offset == 0)
2267 +               goto null;
2268 +
2269 +       do {
2270 +               kstat.irqs[cpu][MIPS_CPU_TIMER_IRQ]++;
2271 +               do_timer(regs);
2272 +               r4k_cur += r4k_offset;
2273 +               ack_r4ktimer(r4k_cur);
2274 +
2275 +       } while (((unsigned long)read_c0_count()
2276 +                               - r4k_cur) < 0x7fffffff);
2277 +
2278 +       irq_exit(cpu, MIPS_CPU_TIMER_IRQ);
2279 +
2280 +       if (softirq_pending(cpu))
2281 +               do_softirq();
2282 +
2283 +       return;
2284 +
2285 +null:
2286 +       ack_r4ktimer(0);
2287 +}
2288 +
2289 +/*
2290 + * Figure out the r4k offset, the amount to increment the compare
2291 + * register for each time tick.
2292 + */
2293 +static unsigned long __init cal_r4koff(void)
2294 +{
2295 +       return ((CONFIG_AR7_CPU*500000)/HZ);
2296 +}
2297 +
2298 +void __init ar7_time_init(void)
2299 +{
2300 +       unsigned long flags;
2301 +       unsigned int est_freq;
2302 +
2303 +       set_except_vector(0, mipsIRQ);
2304 +       write_c0_count(0);
2305 +
2306 +       printk("calculating r4koff... ");
2307 +       r4k_offset = cal_r4koff();
2308 +       printk("%08lx(%d)\n", r4k_offset, (int) r4k_offset);
2309 +
2310 +       est_freq = 2*r4k_offset*HZ;
2311 +       est_freq += 5000;    /* round */
2312 +       est_freq -= est_freq%10000;
2313 +       printk("CPU frequency %d.%02d MHz\n", est_freq/1000000,
2314 +                       (est_freq%1000000)*100/1000000);
2315 +}
2316 +
2317 +void __init ar7_timer_setup(struct irqaction *irq)
2318 +{
2319 +       /* we are using the cpu counter for timer interrupts */
2320 +       irq->handler = no_action;     /* we use our own handler */
2321 +       setup_irq(MIPS_CPU_TIMER_IRQ, irq);
2322 +
2323 +       r4k_cur = (read_c0_count() + r4k_offset);
2324 +       write_c0_compare(r4k_cur);
2325 +       set_c0_status(ALLINTS);
2326 +}
2327 diff -urN linux.old/arch/mips/ar7/tnetd73xx_misc.c linux.dev/arch/mips/ar7/tnetd73xx_misc.c
2328 --- linux.old/arch/mips/ar7/tnetd73xx_misc.c    1970-01-01 01:00:00.000000000 +0100
2329 +++ linux.dev/arch/mips/ar7/tnetd73xx_misc.c    2005-07-26 18:11:02.630503000 +0200
2330 @@ -0,0 +1,924 @@
2331 +/******************************************************************************
2332 + * FILE PURPOSE:    TNETD73xx Misc modules API Source
2333 + ******************************************************************************
2334 + * FILE NAME:       tnetd73xx_misc.c
2335 + *
2336 + * DESCRIPTION:     Clock Control, Reset Control, Power Management, GPIO
2337 + *                  FSER Modules API
2338 + *                  As per TNETD73xx specifications
2339 + *
2340 + * REVISION HISTORY:
2341 + * 27 Nov 02 - Sharath Kumar     PSP TII
2342 + * 14 Feb 03 - Anant Gole        PSP TII
2343 + *
2344 + * (C) Copyright 2002, Texas Instruments, Inc
2345 + *******************************************************************************/
2346 +
2347 +#define LITTLE_ENDIAN
2348 +#define _LINK_KSEG0_
2349 +
2350 +#include <linux/types.h>
2351 +#include <asm/ar7/tnetd73xx.h>
2352 +#include <asm/ar7/tnetd73xx_misc.h>
2353 +
2354 +/* TNETD73XX Revision */
2355 +u32 tnetd73xx_get_revision(void)
2356 +{
2357 +       /* Read Chip revision register - This register is from GPIO module */
2358 +       return ( (u32) REG32_DATA(TNETD73XX_CVR));
2359 +}
2360 +
2361 +/*****************************************************************************
2362 + * Reset Control Module
2363 + *****************************************************************************/
2364 +
2365 +
2366 +void tnetd73xx_reset_ctrl(TNETD73XX_RESET_MODULE_T reset_module, TNETD73XX_RESET_CTRL_T reset_ctrl)
2367 +{
2368 +       u32 reset_status;
2369 +
2370 +       /* read current reset register */
2371 +       REG32_READ(TNETD73XX_RST_CTRL_PRCR, reset_status);
2372 +
2373 +       if (reset_ctrl == OUT_OF_RESET)
2374 +       {
2375 +               /* bring module out of reset */
2376 +               reset_status |= (1 << reset_module);
2377 +       }
2378 +       else
2379 +       {
2380 +               /* put module in reset */
2381 +               reset_status &= (~(1 << reset_module));
2382 +       }
2383 +
2384 +       /* write to the reset register */
2385 +       REG32_WRITE(TNETD73XX_RST_CTRL_PRCR, reset_status);
2386 +}
2387 +
2388 +
2389 +TNETD73XX_RESET_CTRL_T tnetd73xx_get_reset_status (TNETD73XX_RESET_MODULE_T reset_module)
2390 +{
2391 +       u32 reset_status;
2392 +
2393 +       REG32_READ(TNETD73XX_RST_CTRL_PRCR, reset_status);
2394 +       return ( (reset_status & (1 << reset_module)) ? OUT_OF_RESET : IN_RESET );
2395 +}
2396 +
2397 +void tnetd73xx_sys_reset(TNETD73XX_SYS_RST_MODE_T mode)
2398 +{
2399 +       REG32_WRITE(TNETD73XX_RST_CTRL_SWRCR, mode);
2400 +}
2401 +
2402 +#define TNETD73XX_RST_CTRL_RSR_MASK 0x3
2403 +
2404 +TNETD73XX_SYS_RESET_STATUS_T tnetd73xx_get_sys_last_reset_status()
2405 +{
2406 +       u32 sys_reset_status;
2407 +
2408 +       REG32_READ(TNETD73XX_RST_CTRL_RSR, sys_reset_status);
2409 +
2410 +       return ( (TNETD73XX_SYS_RESET_STATUS_T) (sys_reset_status & TNETD73XX_RST_CTRL_RSR_MASK) );
2411 +}
2412 +
2413 +
2414 +/*****************************************************************************
2415 + * Power Control Module
2416 + *****************************************************************************/
2417 +#define TNETD73XX_GLOBAL_POWER_DOWN_MASK    0x3FFFFFFF      /* bit 31, 30 masked */
2418 +#define TNETD73XX_GLOBAL_POWER_DOWN_BIT     30              /* shift to bit 30, 31 */
2419 +
2420 +
2421 +void tnetd73xx_power_ctrl(TNETD73XX_POWER_MODULE_T power_module, TNETD73XX_POWER_CTRL_T power_ctrl)
2422 +{
2423 +       u32 power_status;
2424 +
2425 +       /* read current power down control register */
2426 +       REG32_READ(TNETD73XX_POWER_CTRL_PDCR, power_status);
2427 +
2428 +       if (power_ctrl == POWER_CTRL_POWER_DOWN)
2429 +       {
2430 +               /* power down the module */
2431 +               power_status |= (1 << power_module);
2432 +       }
2433 +       else
2434 +       {
2435 +               /* power on the module */
2436 +               power_status &= (~(1 << power_module));
2437 +       }
2438 +
2439 +       /* write to the reset register */
2440 +       REG32_WRITE(TNETD73XX_POWER_CTRL_PDCR, power_status);
2441 +}
2442 +
2443 +TNETD73XX_POWER_CTRL_T tnetd73xx_get_pwr_status(TNETD73XX_POWER_MODULE_T power_module)
2444 +{
2445 +       u32 power_status;
2446 +
2447 +       /* read current power down control register */
2448 +       REG32_READ(TNETD73XX_POWER_CTRL_PDCR, power_status);
2449 +
2450 +       return ( (power_status & (1 << power_module)) ? POWER_CTRL_POWER_DOWN : POWER_CTRL_POWER_UP );
2451 +}
2452 +
2453 +void tnetd73xx_set_global_pwr_mode(TNETD73XX_SYS_POWER_MODE_T power_mode)
2454 +{
2455 +       u32 power_status;
2456 +
2457 +       /* read current power down control register */
2458 +       REG32_READ(TNETD73XX_POWER_CTRL_PDCR, power_status);
2459 +
2460 +       power_status &= TNETD73XX_GLOBAL_POWER_DOWN_MASK;
2461 +       power_status |= ( power_mode << TNETD73XX_GLOBAL_POWER_DOWN_BIT);
2462 +
2463 +       /* write to power down control register */
2464 +       REG32_WRITE(TNETD73XX_POWER_CTRL_PDCR, power_status);
2465 +}
2466 +
2467 +TNETD73XX_SYS_POWER_MODE_T tnetd73xx_get_global_pwr_mode()
2468 +{
2469 +       u32 power_status;
2470 +
2471 +       /* read current power down control register */
2472 +       REG32_READ(TNETD73XX_POWER_CTRL_PDCR, power_status);
2473 +
2474 +       power_status &= (~TNETD73XX_GLOBAL_POWER_DOWN_MASK);
2475 +       power_status = ( power_status >> TNETD73XX_GLOBAL_POWER_DOWN_BIT);
2476 +
2477 +       return ( (TNETD73XX_SYS_POWER_MODE_T) power_status );
2478 +}
2479 +
2480 +
2481 +/*****************************************************************************
2482 + * Wakeup Control
2483 + *****************************************************************************/
2484 +
2485 +#define TNETD73XX_WAKEUP_POLARITY_BIT   16
2486 +
2487 +void tnetd73xx_wakeup_ctrl(TNETD73XX_WAKEUP_INTERRUPT_T wakeup_int,
2488 +               TNETD73XX_WAKEUP_CTRL_T wakeup_ctrl,
2489 +               TNETD73XX_WAKEUP_POLARITY_T wakeup_polarity)
2490 +{
2491 +       u32 wakeup_status;
2492 +
2493 +       /* read the wakeup control register */
2494 +       REG32_READ(TNETD73XX_POWER_CTRL_WKCR, wakeup_status);
2495 +
2496 +       /* enable/disable */
2497 +       if (wakeup_ctrl == WAKEUP_ENABLED)
2498 +       {
2499 +               /* enable wakeup */
2500 +               wakeup_status |= wakeup_int;
2501 +       }
2502 +       else
2503 +       {
2504 +               /* disable wakeup */
2505 +               wakeup_status &= (~wakeup_int);
2506 +       }
2507 +
2508 +       /* set polarity */
2509 +       if (wakeup_polarity == WAKEUP_ACTIVE_LOW)
2510 +       {
2511 +               wakeup_status |= (wakeup_int << TNETD73XX_WAKEUP_POLARITY_BIT);
2512 +       }
2513 +       else
2514 +       {
2515 +               wakeup_status &= ~(wakeup_int << TNETD73XX_WAKEUP_POLARITY_BIT);
2516 +       }
2517 +
2518 +       /* write  the wakeup control register */
2519 +       REG32_WRITE(TNETD73XX_POWER_CTRL_WKCR, wakeup_status);
2520 +}
2521 +
2522 +
2523 +/*****************************************************************************
2524 + * FSER  Control
2525 + *****************************************************************************/
2526 +
2527 +void tnetd73xx_fser_ctrl(TNETD73XX_FSER_MODE_T fser_mode)
2528 +{
2529 +       REG32_WRITE(TNETD73XX_FSER_BASE, fser_mode);
2530 +}
2531 +
2532 +/*****************************************************************************
2533 + * Clock Control
2534 + *****************************************************************************/
2535 +
2536 +#define MIN(x,y)               ( ((x) <  (y)) ? (x) : (y) )
2537 +#define MAX(x,y)               ( ((x) >  (y)) ? (x) : (y) )
2538 +#define ABS(x)                 ( ((signed)(x) > 0) ? (x) : (-(x)) )
2539 +#define CEIL(x,y)              ( ((x) + (y) / 2) / (y) )
2540 +
2541 +#define CLKC_CLKCR(x)          (TNETD73XX_CLOCK_CTRL_BASE + 0x20 + (0x20 * (x)))
2542 +#define CLKC_CLKPLLCR(x)       (TNETD73XX_CLOCK_CTRL_BASE + 0x30 + (0x20 * (x)))
2543 +
2544 +#define CLKC_PRE_DIVIDER        0x0000001F
2545 +#define CLKC_POST_DIVIDER       0x001F0000
2546 +
2547 +#define CLKC_PLL_STATUS         0x1
2548 +#define CLKC_PLL_FACTOR         0x0000F000
2549 +
2550 +#define BOOTCR_PLL_BYPASS       (1 << 5)
2551 +#define BOOTCR_MIPS_ASYNC_MODE  (1 << 25)
2552 +
2553 +#define MIPS_PLL_SELECT         0x00030000
2554 +#define SYSTEM_PLL_SELECT       0x0000C000
2555 +#define USB_PLL_SELECT          0x000C0000
2556 +#define ADSLSS_PLL_SELECT       0x00C00000
2557 +
2558 +#define MIPS_AFECLKI_SELECT     0x00000000
2559 +#define MIPS_REFCLKI_SELECT     0x00010000
2560 +#define MIPS_XTAL3IN_SELECT     0x00020000
2561 +
2562 +#define SYSTEM_AFECLKI_SELECT   0x00000000
2563 +#define SYSTEM_REFCLKI_SELECT   0x00004000
2564 +#define SYSTEM_XTAL3IN_SELECT   0x00008000
2565 +#define SYSTEM_MIPSPLL_SELECT   0x0000C000
2566 +
2567 +#define USB_SYSPLL_SELECT       0x00000000
2568 +#define USB_REFCLKI_SELECT      0x00040000
2569 +#define USB_XTAL3IN_SELECT      0x00080000
2570 +#define USB_MIPSPLL_SELECT      0x000C0000
2571 +
2572 +#define ADSLSS_AFECLKI_SELECT   0x00000000
2573 +#define ADSLSS_REFCLKI_SELECT   0x00400000
2574 +#define ADSLSS_XTAL3IN_SELECT   0x00800000
2575 +#define ADSLSS_MIPSPLL_SELECT   0x00C00000
2576 +
2577 +#define  SYS_MAX                CLK_MHZ(150)
2578 +#define  SYS_MIN                CLK_MHZ(1)
2579 +
2580 +#define  MIPS_SYNC_MAX          SYS_MAX
2581 +#define  MIPS_ASYNC_MAX         CLK_MHZ(160)
2582 +#define  MIPS_MIN               CLK_MHZ(1)
2583 +
2584 +#define  USB_MAX                CLK_MHZ(100)
2585 +#define  USB_MIN                CLK_MHZ(1)
2586 +
2587 +#define  ADSL_MAX               CLK_MHZ(180)
2588 +#define  ADSL_MIN               CLK_MHZ(1)
2589 +
2590 +#define  PLL_MUL_MAXFACTOR      15
2591 +#define  MAX_DIV_VALUE          32
2592 +#define  MIN_DIV_VALUE          1
2593 +
2594 +#define  MIN_PLL_INP_FREQ       CLK_MHZ(8)
2595 +#define  MAX_PLL_INP_FREQ       CLK_MHZ(100)
2596 +
2597 +#define  DIVIDER_LOCK_TIME      10100
2598 +#define  PLL_LOCK_TIME          10100 * 75
2599 +
2600 +
2601 +
2602 +                                                             /****************************************************************************
2603 +                                                              * DATA PURPOSE:    PRIVATE Variables
2604 +                                                              **************************************************************************/
2605 +                                                             static u32 *clk_src[4];
2606 +                                                             static u32 mips_pll_out;
2607 +                                                             static u32 sys_pll_out;
2608 +                                                             static u32 afeclk_inp;
2609 +                                                             static u32 refclk_inp;
2610 +                                                             static u32 xtal_inp;
2611 +                                                             static u32 present_min;
2612 +                                                             static u32 present_max;
2613 +
2614 +                                                             /* Forward References */
2615 +                                                             static u32 find_gcd(u32 min, u32 max);
2616 +                                                             static u32 compute_prediv( u32 divider, u32 min, u32 max);
2617 +                                                             static void get_val(u32 base_freq, u32 output_freq,u32 *multiplier, u32 *divider);
2618 +                                                             static u32 get_base_frequency(TNETD73XX_CLKC_ID_T clk_id);
2619 +                                                             static void find_approx(u32 *,u32 *,u32);
2620 +
2621 +                                                             /****************************************************************************
2622 +                                                              * FUNCTION: tnetd73xx_clkc_init
2623 +                                                              ****************************************************************************
2624 +                                                              * Description: The routine initializes the internal variables depending on
2625 +                                                              *              on the sources selected for different clocks.
2626 +                                                              ***************************************************************************/
2627 +void tnetd73xx_clkc_init(u32 afeclk, u32 refclk, u32 xtal3in)
2628 +{
2629 +
2630 +       u32 choice;
2631 +
2632 +       afeclk_inp = afeclk;
2633 +       refclk_inp = refclk;
2634 +       xtal_inp = xtal3in;
2635 +
2636 +       choice = REG32_DATA(TNETD73XX_DCL_BOOTCR) & MIPS_PLL_SELECT;
2637 +       switch(choice)
2638 +       {
2639 +               case MIPS_AFECLKI_SELECT:
2640 +                       clk_src[CLKC_MIPS] = &afeclk_inp;
2641 +                       break;
2642 +
2643 +               case MIPS_REFCLKI_SELECT:
2644 +                       clk_src[CLKC_MIPS] = &refclk_inp;
2645 +                       break;
2646 +
2647 +               case MIPS_XTAL3IN_SELECT:
2648 +                       clk_src[CLKC_MIPS] = &xtal_inp;
2649 +                       break;
2650 +
2651 +               default :
2652 +                       clk_src[CLKC_MIPS] = 0;
2653 +
2654 +       }
2655 +
2656 +       choice = REG32_DATA(TNETD73XX_DCL_BOOTCR) & SYSTEM_PLL_SELECT;
2657 +       switch(choice)
2658 +       {
2659 +               case SYSTEM_AFECLKI_SELECT:
2660 +                       clk_src[CLKC_SYS] = &afeclk_inp;
2661 +                       break;
2662 +
2663 +               case SYSTEM_REFCLKI_SELECT:
2664 +                       clk_src[CLKC_SYS] = &refclk_inp;
2665 +                       break;
2666 +
2667 +               case SYSTEM_XTAL3IN_SELECT:
2668 +                       clk_src[CLKC_SYS] = &xtal_inp;
2669 +                       break;
2670 +
2671 +               case SYSTEM_MIPSPLL_SELECT:
2672 +                       clk_src[CLKC_SYS] = &mips_pll_out;
2673 +                       break;
2674 +
2675 +               default :
2676 +                       clk_src[CLKC_SYS] = 0;
2677 +
2678 +       }
2679 +
2680 +
2681 +       choice = REG32_DATA(TNETD73XX_DCL_BOOTCR) & ADSLSS_PLL_SELECT;
2682 +       switch(choice)
2683 +       {
2684 +               case ADSLSS_AFECLKI_SELECT:
2685 +                       clk_src[CLKC_ADSLSS] = &afeclk_inp;
2686 +                       break;
2687 +
2688 +               case ADSLSS_REFCLKI_SELECT:
2689 +                       clk_src[CLKC_ADSLSS] = &refclk_inp;
2690 +                       break;
2691 +
2692 +               case ADSLSS_XTAL3IN_SELECT:
2693 +                       clk_src[CLKC_ADSLSS] = &xtal_inp;
2694 +                       break;
2695 +
2696 +               case ADSLSS_MIPSPLL_SELECT:
2697 +                       clk_src[CLKC_ADSLSS] = &mips_pll_out;
2698 +                       break;
2699 +
2700 +               default :
2701 +                       clk_src[CLKC_ADSLSS] = 0;
2702 +
2703 +       }
2704 +
2705 +
2706 +       choice = REG32_DATA(TNETD73XX_DCL_BOOTCR) & USB_PLL_SELECT;
2707 +       switch(choice)
2708 +       {
2709 +               case USB_SYSPLL_SELECT:
2710 +                       clk_src[CLKC_USB] = &sys_pll_out ;
2711 +                       break;
2712 +
2713 +               case USB_REFCLKI_SELECT:
2714 +                       clk_src[CLKC_USB] = &refclk_inp;
2715 +                       break;
2716 +
2717 +               case USB_XTAL3IN_SELECT:
2718 +                       clk_src[CLKC_USB] = &xtal_inp;
2719 +                       break;
2720 +
2721 +               case USB_MIPSPLL_SELECT:
2722 +                       clk_src[CLKC_USB] = &mips_pll_out;
2723 +                       break;
2724 +
2725 +               default :
2726 +                       clk_src[CLKC_USB] = 0;
2727 +
2728 +       }
2729 +}
2730 +
2731 +
2732 +
2733 +/****************************************************************************
2734 + * FUNCTION: tnetd73xx_clkc_set_freq
2735 + ****************************************************************************
2736 + * Description: The above routine is called to set the output_frequency of the
2737 + *              selected clock(using clk_id) to the  required value given
2738 + *              by the variable output_freq.
2739 + ***************************************************************************/
2740 +TNETD73XX_ERR tnetd73xx_clkc_set_freq
2741 +(
2742 + TNETD73XX_CLKC_ID_T clk_id,
2743 + u32              output_freq
2744 + )
2745 +{
2746 +       u32 base_freq;
2747 +       u32 multiplier;
2748 +       u32 divider;
2749 +       u32 min_prediv;
2750 +       u32 max_prediv;
2751 +       u32 prediv;
2752 +       u32 postdiv;
2753 +       u32 temp;
2754 +
2755 +       /* check if PLLs are bypassed*/
2756 +       if(REG32_DATA(TNETD73XX_DCL_BOOTCR) & BOOTCR_PLL_BYPASS)
2757 +       {
2758 +               return TNETD73XX_ERR_ERROR;
2759 +       }
2760 +
2761 +       /*check if the requested output_frequency is in valid range*/
2762 +       switch( clk_id )
2763 +       {
2764 +               case CLKC_SYS:
2765 +                       if( output_freq < SYS_MIN || output_freq > SYS_MAX)
2766 +                       {
2767 +                               return TNETD73XX_ERR_ERROR;
2768 +                       }
2769 +                       present_min = SYS_MIN;
2770 +                       present_max = SYS_MAX;
2771 +                       break;
2772 +
2773 +               case CLKC_MIPS:
2774 +                       if((output_freq < MIPS_MIN) ||
2775 +                                       (output_freq > ((REG32_DATA(TNETD73XX_DCL_BOOTCR) & BOOTCR_MIPS_ASYNC_MODE) ? MIPS_ASYNC_MAX: MIPS_SYNC_MAX)))
2776 +                       {
2777 +                               return TNETD73XX_ERR_ERROR;
2778 +                       }
2779 +                       present_min = MIPS_MIN;
2780 +                       present_max = (REG32_DATA(TNETD73XX_DCL_BOOTCR) & BOOTCR_MIPS_ASYNC_MODE) ? MIPS_ASYNC_MAX: MIPS_SYNC_MAX;
2781 +                       break;
2782 +
2783 +               case CLKC_USB:
2784 +                       if( output_freq < USB_MIN || output_freq > USB_MAX)
2785 +                       {
2786 +                               return TNETD73XX_ERR_ERROR;
2787 +                       }
2788 +                       present_min = USB_MIN;
2789 +                       present_max = USB_MAX;
2790 +                       break;
2791 +
2792 +               case CLKC_ADSLSS:
2793 +                       if( output_freq < ADSL_MIN || output_freq > ADSL_MAX)
2794 +                       {
2795 +                               return TNETD73XX_ERR_ERROR;
2796 +                       }
2797 +                       present_min = ADSL_MIN;
2798 +                       present_max = ADSL_MAX;
2799 +                       break;
2800 +       }
2801 +
2802 +
2803 +       base_freq = get_base_frequency(clk_id);
2804 +
2805 +
2806 +       /* check for minimum base frequency value */
2807 +       if( base_freq < MIN_PLL_INP_FREQ)
2808 +       {
2809 +               return TNETD73XX_ERR_ERROR;
2810 +       }
2811 +
2812 +       get_val(output_freq, base_freq, &multiplier, &divider);
2813 +
2814 +       /* check multiplier range  */
2815 +       if( (multiplier  > PLL_MUL_MAXFACTOR) || (multiplier <= 0) )
2816 +       {
2817 +               return TNETD73XX_ERR_ERROR;
2818 +       }
2819 +
2820 +       /* check divider value */
2821 +       if( divider == 0 )
2822 +       {
2823 +               return TNETD73XX_ERR_ERROR;
2824 +       }
2825 +
2826 +       /*compute minimum and maximum predivider values */
2827 +       min_prediv = MAX(base_freq / MAX_PLL_INP_FREQ + 1, divider / MAX_DIV_VALUE + 1);
2828 +       max_prediv = MIN(base_freq / MIN_PLL_INP_FREQ, MAX_DIV_VALUE);
2829 +
2830 +       /*adjust  the value of divider so that it not less than minimum predivider value*/
2831 +       if (divider < min_prediv)
2832 +       {
2833 +               temp = CEIL(min_prediv, divider);
2834 +               if ((temp * multiplier) > PLL_MUL_MAXFACTOR)
2835 +               {
2836 +                       return TNETD73XX_ERR_ERROR  ;
2837 +               }
2838 +               else
2839 +               {
2840 +                       multiplier = temp * multiplier;
2841 +                       divider = min_prediv;
2842 +               }
2843 +
2844 +       }
2845 +
2846 +       /* compute predivider  and postdivider values */
2847 +       prediv = compute_prediv (divider, min_prediv, max_prediv);
2848 +       postdiv = CEIL(divider,prediv);
2849 +
2850 +       /*return fail if postdivider value falls out of range */
2851 +       if(postdiv > MAX_DIV_VALUE)
2852 +       {
2853 +               return TNETD73XX_ERR_ERROR;
2854 +       }
2855 +
2856 +
2857 +       /*write predivider and postdivider values*/
2858 +       /* pre-Divider and post-divider are 5 bit N+1 dividers */
2859 +       REG32_WRITE(CLKC_CLKCR(clk_id), ((postdiv -1) & 0x1F) << 16 | ((prediv -1) & 0x1F) );
2860 +
2861 +       /*wait for divider output to stabilise*/
2862 +       for(temp =0; temp < DIVIDER_LOCK_TIME; temp++);
2863 +
2864 +       /*write to PLL clock register*/
2865 +
2866 +       if(clk_id == CLKC_SYS)
2867 +       {
2868 +               /* but before writing put DRAM to hold mode */
2869 +               REG32_DATA(TNETD73XX_EMIF_SDRAM_CFG) |= 0x80000000;
2870 +       }
2871 +       /*Bring PLL into div mode */
2872 +       REG32_WRITE(CLKC_CLKPLLCR(clk_id), 0x4);
2873 +
2874 +       /*compute the word to be written to PLLCR
2875 +        *corresponding to multiplier value
2876 +        */
2877 +       multiplier = (((multiplier - 1) & 0xf) << 12)| ((255 <<3) | 0x0e);
2878 +
2879 +       /* wait till PLL enters div mode */
2880 +       while(REG32_DATA(CLKC_CLKPLLCR(clk_id)) & CLKC_PLL_STATUS)
2881 +               /*nothing*/;
2882 +
2883 +       REG32_WRITE(CLKC_CLKPLLCR(clk_id), multiplier);
2884 +
2885 +       while(!REG32_DATA(CLKC_CLKPLLCR(clk_id)) & CLKC_PLL_STATUS)
2886 +               /*nothing*/;
2887 +
2888 +
2889 +       /*wait for External pll to lock*/
2890 +       for(temp =0; temp < PLL_LOCK_TIME; temp++);
2891 +
2892 +       if(clk_id == CLKC_SYS)
2893 +       {
2894 +               /* Bring DRAM out of hold */
2895 +               REG32_DATA(TNETD73XX_EMIF_SDRAM_CFG) &= ~0x80000000;
2896 +       }
2897 +
2898 +       return TNETD73XX_ERR_OK ;
2899 +}
2900 +
2901 +/****************************************************************************
2902 + * FUNCTION: tnetd73xx_clkc_get_freq
2903 + ****************************************************************************
2904 + * Description: The above routine is called to get the output_frequency of the
2905 + *              selected clock( clk_id)
2906 + ***************************************************************************/
2907 +u32 tnetd73xx_clkc_get_freq
2908 +(
2909 + TNETD73XX_CLKC_ID_T clk_id
2910 + )
2911 +{
2912 +
2913 +       u32  clk_ctrl_register;
2914 +       u32  clk_pll_setting;
2915 +       u32  clk_predivider;
2916 +       u32  clk_postdivider;
2917 +       u16  pll_factor;
2918 +       u32  base_freq;
2919 +       u32  divider;
2920 +
2921 +       base_freq = get_base_frequency(clk_id);
2922 +
2923 +       clk_ctrl_register = REG32_DATA(CLKC_CLKCR(clk_id));
2924 +
2925 +       /* pre-Divider and post-divider are 5 bit N+1 dividers */
2926 +       clk_predivider = (CLKC_PRE_DIVIDER & clk_ctrl_register) + 1;
2927 +       clk_postdivider = ((CLKC_POST_DIVIDER & clk_ctrl_register) >> 16) + 1;
2928 +
2929 +       divider =  clk_predivider * clk_postdivider;
2930 +
2931 +
2932 +       if( (REG32_DATA(TNETD73XX_DCL_BOOTCR) & BOOTCR_PLL_BYPASS))
2933 +       {
2934 +               return (CEIL(base_freq, divider));  /* PLLs bypassed.*/
2935 +       }
2936 +
2937 +
2938 +       else
2939 +       {
2940 +               /*  return the current clock speed based upon the PLL setting */
2941 +               clk_pll_setting = REG32_DATA(CLKC_CLKPLLCR(clk_id));
2942 +
2943 +               /* Get the PLL multiplication factor */
2944 +               pll_factor = ((clk_pll_setting & CLKC_PLL_FACTOR) >> 12) + 1;
2945 +
2946 +               /* Check if we're in divide mode or multiply mode */
2947 +               if((clk_pll_setting & 0x1)   == 0)
2948 +               {
2949 +                       /* We're in divide mode */
2950 +                       if(pll_factor <  0x10)
2951 +                               return (CEIL(base_freq >> 1, divider));
2952 +                       else
2953 +                               return (CEIL(base_freq >> 2, divider));
2954 +               }
2955 +
2956 +               else     /* We're in PLL mode */
2957 +               {
2958 +                       /* See if PLLNDIV & PLLDIV are set */
2959 +                       if((clk_pll_setting & 0x0800) && (clk_pll_setting & 0x2))
2960 +                       {
2961 +                               if(clk_pll_setting & 0x1000)
2962 +                               {
2963 +                                       /* clk = base_freq * k/2  */
2964 +                                       return(CEIL((base_freq * pll_factor) >> 1, divider));
2965 +                               }
2966 +                               else
2967 +                               {
2968 +                                       /* clk = base_freq * (k-1) / 4)*/
2969 +                                       return(CEIL((base_freq * (pll_factor - 1)) >>2, divider));
2970 +                               }
2971 +                       }
2972 +                       else
2973 +                       {
2974 +                               if(pll_factor < 0x10)
2975 +                               {
2976 +                                       /* clk = base_freq * k */
2977 +                                       return(CEIL(base_freq * pll_factor, divider));
2978 +                               }
2979 +
2980 +                               else
2981 +                               {
2982 +                                       /* clk = base_freq  */
2983 +                                       return(CEIL(base_freq, divider));
2984 +                               }
2985 +                       }
2986 +               }
2987 +               return(0); /* Should never reach here */
2988 +
2989 +       }
2990 +
2991 +}
2992 +
2993 +
2994 +/* local helper functions */
2995 +
2996 +/****************************************************************************
2997 + * FUNCTION: get_base_frequency
2998 + ****************************************************************************
2999 + * Description: The above routine is called to get base frequency of the clocks.
3000 + ***************************************************************************/
3001 +
3002 +static u32 get_base_frequency(TNETD73XX_CLKC_ID_T clk_id)
3003 +{
3004 +       /* update the current MIPs PLL output value, if the required
3005 +        * source is MIPS PLL
3006 +        */
3007 +       if ( clk_src[clk_id] == &mips_pll_out)
3008 +       {
3009 +               *clk_src[clk_id] = tnetd73xx_clkc_get_freq(CLKC_MIPS);
3010 +       }
3011 +
3012 +
3013 +       /* update the current System PLL output value, if the required
3014 +        * source is system PLL
3015 +        */
3016 +       if ( clk_src[clk_id] == &sys_pll_out)
3017 +       {
3018 +               *clk_src[clk_id] = tnetd73xx_clkc_get_freq(CLKC_SYS);
3019 +       }
3020 +
3021 +       return (*clk_src[clk_id]);
3022 +
3023 +}
3024 +
3025 +
3026 +
3027 +/****************************************************************************
3028 + * FUNCTION: find_gcd
3029 + ****************************************************************************
3030 + * Description: The above routine is called to find gcd of 2 numbers.
3031 + ***************************************************************************/
3032 +static u32 find_gcd
3033 +(
3034 + u32 min,
3035 + u32 max
3036 + )
3037 +{
3038 +       if (max % min == 0)
3039 +       {
3040 +               return min;
3041 +       }
3042 +       else
3043 +       {
3044 +               return find_gcd(max % min, min);
3045 +       }
3046 +}
3047 +
3048 +/****************************************************************************
3049 + * FUNCTION: compute_prediv
3050 + ****************************************************************************
3051 + * Description: The above routine is called to compute predivider value
3052 + ***************************************************************************/
3053 +static u32 compute_prediv(u32 divider, u32 min, u32 max)
3054 +{
3055 +       u16 prediv;
3056 +
3057 +       /* return the divider itself it it falls within the range of predivider*/
3058 +       if (min <= divider && divider <= max)
3059 +       {
3060 +               return divider;
3061 +       }
3062 +
3063 +       /* find a value for prediv such that it is a factor of divider */
3064 +       for (prediv = max; prediv >= min ; prediv--)
3065 +       {
3066 +               if ( (divider % prediv) == 0 )
3067 +               {
3068 +                       return prediv;
3069 +               }
3070 +       }
3071 +
3072 +       /* No such factor exists,  return min as prediv */
3073 +       return min;
3074 +}
3075 +
3076 +/****************************************************************************
3077 + * FUNCTION: get_val
3078 + ****************************************************************************
3079 + * Description: This routine is called to get values of divider and multiplier.
3080 + ***************************************************************************/
3081 +
3082 +static void get_val(u32 output_freq, u32 base_freq,u32 *multiplier, u32 *divider)
3083 +{
3084 +       u32 temp_mul;
3085 +       u32 temp_div;
3086 +       u32 gcd;
3087 +       u32 min_freq;
3088 +       u32 max_freq;
3089 +
3090 +       /* find gcd of base_freq, output_freq */
3091 +       min_freq = (base_freq < output_freq) ? base_freq : output_freq;
3092 +       max_freq = (base_freq > output_freq) ? base_freq : output_freq;
3093 +       gcd = find_gcd(min_freq , max_freq);
3094 +
3095 +       if(gcd == 0)
3096 +               return;  /* ERROR */
3097 +
3098 +       /* compute values of multiplier and divider */
3099 +       temp_mul = output_freq / gcd;
3100 +       temp_div = base_freq / gcd;
3101 +
3102 +
3103 +       /* set multiplier such that 1 <= multiplier <= PLL_MUL_MAXFACTOR */
3104 +       if( temp_mul > PLL_MUL_MAXFACTOR )
3105 +       {
3106 +               if((temp_mul / temp_div) > PLL_MUL_MAXFACTOR)
3107 +                       return;
3108 +
3109 +               find_approx(&temp_mul,&temp_div,base_freq);
3110 +       }
3111 +
3112 +       *multiplier = temp_mul;
3113 +       *divider    = temp_div;
3114 +}
3115 +
3116 +/****************************************************************************
3117 + * FUNCTION: find_approx
3118 + ****************************************************************************
3119 + * Description: This function gets the approx value of num/denom.
3120 + ***************************************************************************/
3121 +
3122 +static void find_approx(u32 *num,u32 *denom,u32 base_freq)
3123 +{
3124 +       u32 num1;
3125 +       u32 denom1;
3126 +       u32 num2;
3127 +       u32 denom2;
3128 +       int32_t closest;
3129 +       int32_t prev_closest;
3130 +       u32 temp_num;
3131 +       u32 temp_denom;
3132 +       u32 normalize;
3133 +       u32 gcd;
3134 +       u32 output_freq;
3135 +
3136 +       num1 = *num;
3137 +       denom1 = *denom;
3138 +
3139 +       prev_closest = 0x7fffffff; /* maximum possible value */
3140 +       num2 = num1;
3141 +       denom2 = denom1;
3142 +
3143 +       /* start with  max */
3144 +       for(temp_num = 15; temp_num >=1; temp_num--)
3145 +       {
3146 +
3147 +               temp_denom = CEIL(temp_num * denom1, num1);
3148 +               output_freq = (temp_num * base_freq) / temp_denom;
3149 +
3150 +               if(temp_denom < 1)
3151 +               {
3152 +                       break;
3153 +               }
3154 +               else
3155 +               {
3156 +                       normalize = CEIL(num1,temp_num);
3157 +                       closest = (ABS((num1 * (temp_denom) ) - (temp_num * denom1)))  * normalize;
3158 +                       if(closest < prev_closest && output_freq > present_min && output_freq <present_max)
3159 +                       {
3160 +                               prev_closest = closest;
3161 +                               num2 = temp_num;
3162 +                               denom2 = temp_denom;
3163 +                       }
3164 +
3165 +               }
3166 +
3167 +       }
3168 +
3169 +       gcd = find_gcd(num2,denom2);
3170 +       num2 = num2 / gcd;
3171 +       denom2 = denom2 /gcd;
3172 +
3173 +       *num      = num2;
3174 +       *denom    = denom2;
3175 +}
3176 +
3177 +
3178 +/*****************************************************************************
3179 + * GPIO  Control
3180 + *****************************************************************************/
3181 +
3182 +/****************************************************************************
3183 + * FUNCTION: tnetd73xx_gpio_init
3184 + ***************************************************************************/
3185 +void tnetd73xx_gpio_init()
3186 +{
3187 +       /* Bring module out of reset */
3188 +       tnetd73xx_reset_ctrl(RESET_MODULE_GPIO, OUT_OF_RESET);
3189 +       REG32_WRITE(TNETD73XX_GPIOENR, 0xFFFFFFFF);
3190 +}
3191 +
3192 +/****************************************************************************
3193 + * FUNCTION: tnetd73xx_gpio_ctrl
3194 + ***************************************************************************/
3195 +void tnetd73xx_gpio_ctrl(TNETD73XX_GPIO_PIN_T gpio_pin,
3196 +               TNETD73XX_GPIO_PIN_MODE_T pin_mode,
3197 +               TNETD73XX_GPIO_PIN_DIRECTION_T pin_direction)
3198 +{
3199 +       u32 pin_status;
3200 +       REG32_READ(TNETD73XX_GPIOENR, pin_status);
3201 +       if (pin_mode == GPIO_PIN)
3202 +       {
3203 +               pin_status |= (1 << gpio_pin);
3204 +               REG32_WRITE(TNETD73XX_GPIOENR, pin_status);
3205 +
3206 +               /* Set pin direction */
3207 +               REG32_READ(TNETD73XX_GPIOPDIRR, pin_status);
3208 +               if (pin_direction == GPIO_INPUT_PIN)
3209 +               {
3210 +                       pin_status |= (1 << gpio_pin);
3211 +               }
3212 +               else /* GPIO_OUTPUT_PIN */
3213 +               {
3214 +                       pin_status &= (~(1 << gpio_pin));
3215 +               }
3216 +               REG32_WRITE(TNETD73XX_GPIOPDIRR, pin_status);
3217 +       }
3218 +       else /* FUNCTIONAL PIN */
3219 +       {
3220 +               pin_status &= (~(1 << gpio_pin));
3221 +               REG32_WRITE(TNETD73XX_GPIOENR, pin_status);
3222 +       }
3223 +
3224 +}
3225 +
3226 +/****************************************************************************
3227 + * FUNCTION: tnetd73xx_gpio_out
3228 + ***************************************************************************/
3229 +void tnetd73xx_gpio_out(TNETD73XX_GPIO_PIN_T gpio_pin, int value)
3230 +{
3231 +       u32 pin_value;
3232 +
3233 +       REG32_READ(TNETD73XX_GPIODOUTR, pin_value);
3234 +       if (value == 1)
3235 +       {
3236 +               pin_value |= (1 << gpio_pin);
3237 +       }
3238 +       else
3239 +       {
3240 +               pin_value &= (~(1 << gpio_pin));
3241 +       }
3242 +       REG32_WRITE(TNETD73XX_GPIODOUTR, pin_value);
3243 +}
3244 +
3245 +/****************************************************************************
3246 + * FUNCTION: tnetd73xx_gpio_in
3247 + ***************************************************************************/
3248 +int tnetd73xx_gpio_in(TNETD73XX_GPIO_PIN_T gpio_pin)
3249 +{
3250 +       u32 pin_value;
3251 +       REG32_READ(TNETD73XX_GPIODINR, pin_value);
3252 +       return ( (pin_value & (1 << gpio_pin)) ? 1 : 0 );
3253 +}
3254 +
3255 diff -urN linux.old/arch/mips/config-shared.in linux.dev/arch/mips/config-shared.in
3256 --- linux.old/arch/mips/config-shared.in        2005-07-26 18:18:16.263581096 +0200
3257 +++ linux.dev/arch/mips/config-shared.in        2005-07-26 18:38:00.089612184 +0200
3258 @@ -20,6 +20,16 @@
3259  mainmenu_option next_comment
3260  comment 'Machine selection'
3261  dep_bool 'Support for Acer PICA 1 chipset (EXPERIMENTAL)' CONFIG_ACER_PICA_61 $CONFIG_EXPERIMENTAL
3262 +dep_bool 'Support for Texas Instruments AR7 (EXPERIMENTAL)' CONFIG_AR7 $CONFIG_MIPS32 $CONFIG_EXPERIMENTAL
3263 +if [ "$CONFIG_AR7" = "y" ]; then
3264 +   choice 'Texas Instruments Reference Platform' \
3265 +      "AR7DB CONFIG_AR7DB \
3266 +      AR7RD CONFIG_AR7RD \
3267 +      AR7WRD CONFIG_AR7WRD" AR7DB
3268 +   int 'Texas Instruments AR7 CPU Frequency' CONFIG_AR7_CPU 150
3269 +   int 'Texas Instruments AR7 System Frequency' CONFIG_AR7_SYS 125
3270 +   hex 'Texas Instruments AR7 SDRAM Start' CONFIG_AR7_MEMORY 0x14000000
3271 +fi
3272  dep_bool 'Support for Alchemy Bosporus board' CONFIG_MIPS_BOSPORUS $CONFIG_MIPS32
3273  dep_bool 'Support for FIC Multimedia Player board' CONFIG_MIPS_FICMMP $CONFIG_MIPS32
3274  dep_bool 'Support for Alchemy Mirage board' CONFIG_MIPS_MIRAGE $CONFIG_MIPS32
3275 @@ -239,6 +249,11 @@
3276     define_bool CONFIG_NONCOHERENT_IO y
3277     define_bool CONFIG_PC_KEYB y
3278  fi
3279 +if [ "$CONFIG_AR7" = "y" ]; then
3280 +   define_bool CONFIG_NONCOHERENT_IO y
3281 +   define_bool CONFIG_SWAP_IO_SPACE y
3282 +   define_bool CONFIG_AR7_PAGING y
3283 +fi
3284  if [ "$CONFIG_CASIO_E55" = "y" ]; then
3285     define_bool CONFIG_IRQ_CPU y
3286     define_bool CONFIG_NONCOHERENT_IO y
3287 @@ -736,6 +751,7 @@
3288  mainmenu_option next_comment
3289  comment 'General setup'
3290  if [ "$CONFIG_ACER_PICA_61" = "y" -o \
3291 +     "$CONFIG_AR7" = "y" -o \
3292       "$CONFIG_CASIO_E55" = "y" -o \
3293       "$CONFIG_DDB5074" = "y" -o \
3294       "$CONFIG_DDB5476" = "y" -o \
3295 @@ -797,6 +813,7 @@
3296  bool 'Networking support' CONFIG_NET
3297
3298  if [ "$CONFIG_ACER_PICA_61" = "y" -o \
3299 +     "$CONFIG_AR7" = "y" -o \
3300       "$CONFIG_CASIO_E55" = "y" -o \
3301       "$CONFIG_DECSTATION" = "y" -o \
3302       "$CONFIG_IBM_WORKPAD" = "y" -o \
3303 diff -urN linux.old/arch/mips/kernel/irq.c linux.dev/arch/mips/kernel/irq.c
3304 --- linux.old/arch/mips/kernel/irq.c    2005-07-26 18:18:16.264580944 +0200
3305 +++ linux.dev/arch/mips/kernel/irq.c    2005-07-26 18:11:02.632503000 +0200
3306 @@ -76,6 +76,7 @@
3307   * Generic, controller-independent functions:
3308   */
3309
3310 +#ifndef CONFIG_AR7
3311  int get_irq_list(char *buf)
3312  {
3313         int i, j;
3314 @@ -110,6 +111,7 @@
3315         p += sprintf(p, "ERR: %10u\n", atomic_read(&irq_err_count));
3316         return p - buf;
3317  }
3318 +#endif
3319
3320  #ifdef CONFIG_SMP
3321  int global_irq_holder = NO_PROC_ID;
3322 @@ -525,6 +527,7 @@
3323   *
3324   */
3325
3326 +#ifndef CONFIG_AR7
3327  int request_irq(unsigned int irq,
3328                 void (*handler)(int, void *, struct pt_regs *),
3329                 unsigned long irqflags,
3330 @@ -569,6 +572,7 @@
3331                 kfree(action);
3332         return retval;
3333  }
3334 +#endif
3335
3336  /**
3337   *     free_irq - free an interrupt
3338 @@ -588,6 +592,7 @@
3339   *           the machine.
3340   */
3341
3342 +#ifndef CONFIG_AR7
3343  void free_irq(unsigned int irq, void *dev_id)
3344  {
3345         irq_desc_t *desc;
3346 @@ -629,6 +634,7 @@
3347                 return;
3348         }
3349  }
3350 +#endif
3351
3352  /*
3353   * IRQ autodetection code..
3354 diff -urN linux.old/arch/mips/kernel/mips_ksyms.c linux.dev/arch/mips/kernel/mips_ksyms.c
3355 --- linux.old/arch/mips/kernel/mips_ksyms.c     2005-07-26 18:18:16.265580792 +0200
3356 +++ linux.dev/arch/mips/kernel/mips_ksyms.c     2005-07-26 18:11:02.633502000 +0200
3357 @@ -40,6 +40,12 @@
3358  extern long __strnlen_user_nocheck_asm(const char *s);
3359  extern long __strnlen_user_asm(const char *s);
3360
3361 +#ifdef CONFIG_AR7
3362 +int avalanche_request_pacing(int irq_nr, unsigned int blk_num, unsigned int pace_value);
3363 +char *prom_getenv(char *envname);
3364 +#endif
3365 +
3366 +
3367  EXPORT_SYMBOL(mips_machtype);
3368  #ifdef CONFIG_EISA
3369  EXPORT_SYMBOL(EISA_bus);
3370 @@ -103,3 +109,9 @@
3371  #endif
3372
3373  EXPORT_SYMBOL(get_wchan);
3374 +
3375 +#ifdef CONFIG_AR7
3376 +EXPORT_SYMBOL_NOVERS(avalanche_request_pacing);
3377 +EXPORT_SYMBOL_NOVERS(prom_getenv);
3378 +#endif
3379 +
3380 diff -urN linux.old/arch/mips/kernel/setup.c linux.dev/arch/mips/kernel/setup.c
3381 --- linux.old/arch/mips/kernel/setup.c  2005-07-26 18:18:16.265580792 +0200
3382 +++ linux.dev/arch/mips/kernel/setup.c  2005-07-26 18:38:00.090612032 +0200
3383 @@ -109,6 +109,7 @@
3384  unsigned long isa_slot_offset;
3385  EXPORT_SYMBOL(isa_slot_offset);
3386
3387 +extern void avalanche_bootmem_init(void);
3388  extern void SetUpBootInfo(void);
3389  extern void load_mmu(void);
3390  extern asmlinkage void start_kernel(void);
3391 @@ -267,6 +268,9 @@
3392  #endif /* CONFIG_BLK_DEV_INITRD */
3393
3394         /* Find the highest page frame number we have available.  */
3395 +#ifdef CONFIG_AR7_PAGING
3396 +       avalanche_bootmem_init();
3397 +#else
3398         max_pfn = 0;
3399         first_usable_pfn = -1UL;
3400         for (i = 0; i < boot_mem_map.nr_map; i++) {
3401 @@ -377,6 +381,7 @@
3402         /* Reserve the bootmap memory.  */
3403         reserve_bootmem(PFN_PHYS(first_usable_pfn), bootmap_size);
3404
3405 +#endif
3406  #ifdef CONFIG_BLK_DEV_INITRD
3407         /* Board specific code should have set up initrd_start and initrd_end */
3408         ROOT_DEV = MKDEV(RAMDISK_MAJOR, 0);
3409 @@ -494,6 +499,7 @@
3410         void hp_setup(void);
3411         void au1x00_setup(void);
3412         void frame_info_init(void);
3413 +       void ar7_setup(void);
3414
3415         frame_info_init();
3416  #if defined(CONFIG_BLK_DEV_FD) || defined(CONFIG_BLK_DEV_FD_MODULE)
3417 @@ -691,6 +697,11 @@
3418                  pmc_yosemite_setup();
3419                  break;
3420  #endif
3421 +#ifdef CONFIG_AR7
3422 +       case MACH_GROUP_UNKNOWN:
3423 +               ar7_setup();
3424 +               break;
3425 +#endif
3426         default:
3427                 panic("Unsupported architecture");
3428         }
3429 diff -urN linux.old/arch/mips/kernel/traps.c linux.dev/arch/mips/kernel/traps.c
3430 --- linux.old/arch/mips/kernel/traps.c  2005-07-26 18:18:16.267580488 +0200
3431 +++ linux.dev/arch/mips/kernel/traps.c  2005-07-26 18:38:00.091611880 +0200
3432 @@ -869,9 +869,15 @@
3433
3434         exception_handlers[n] = handler;
3435         if (n == 0 && cpu_has_divec) {
3436 +#ifdef CONFIG_AR7
3437 +               *(volatile u32 *)((KSEG0+CONFIG_AR7_MEMORY)+0x200) = 0x08000000 |
3438 +                       (0x03ffffff & (handler >> 2));
3439 +               flush_icache_range((KSEG0+CONFIG_AR7_MEMORY)+0x200, (KSEG0+CONFIG_AR7_MEMORY) + 0x204);
3440 +#else
3441                 *(volatile u32 *)(KSEG0+0x200) = 0x08000000 |
3442                                                  (0x03ffffff & (handler >> 2));
3443                 flush_icache_range(KSEG0+0x200, KSEG0 + 0x204);
3444 +#endif
3445         }
3446         return (void *)old_handler;
3447  }
3448 @@ -920,14 +926,46 @@
3449  void __init trap_init(void)
3450  {
3451         extern char except_vec1_generic;
3452 +       extern char except_vec2_generic;
3453         extern char except_vec3_generic, except_vec3_r4000;
3454         extern char except_vec_ejtag_debug;
3455         extern char except_vec4;
3456         unsigned long i;
3457
3458 +#ifdef CONFIG_AR7
3459 +       extern char jump_tlb_miss, jump_tlb_miss_unused;
3460 +       extern char jump_cache_error,jump_general_exception;
3461 +       extern char jump_dedicated_interrupt;
3462 +       clear_c0_status(ST0_BEV);
3463 +#endif
3464 +
3465         /* Copy the generic exception handler code to it's final destination. */
3466         memcpy((void *)(KSEG0 + 0x80), &except_vec1_generic, 0x80);
3467 +       memcpy((void *)(KSEG0 + 0x100), &except_vec2_generic, 0x80);
3468 +       memcpy((void *)(KSEG0 + 0x180), &except_vec3_generic, 0x80);
3469
3470 +       memcpy((void *)(KSEG0 + 0x0),   &jump_tlb_miss, 0x80);
3471 +       memcpy((void *)(KSEG0 + 0x80),  &jump_tlb_miss_unused, 0x80);
3472 +       memcpy((void *)(KSEG0 + 0x100), &jump_cache_error, 0x80);
3473 +       memcpy((void *)(KSEG0 + 0x180), &jump_general_exception, 0x80);
3474 +       memcpy((void *)(KSEG0 + 0x200), &jump_dedicated_interrupt, 0x80);
3475 +
3476 +#ifdef CONFIG_AR7
3477 +       memcpy((void *)((KSEG0+CONFIG_AR7_MEMORY) + 0x80), &except_vec1_generic, 0x80);
3478 +       memcpy((void *)((KSEG0+CONFIG_AR7_MEMORY) + 0x100), &except_vec2_generic, 0x80);
3479 +       memcpy((void *)((KSEG0+CONFIG_AR7_MEMORY) + 0x180), &except_vec3_generic, 0x80);
3480 +       flush_icache_range((KSEG0+CONFIG_AR7_MEMORY), (KSEG0+CONFIG_AR7_MEMORY) + 0x200);
3481 +
3482 +       memcpy((void *)(KSEG0 + 0x0),   &jump_tlb_miss, 0x80);
3483 +       memcpy((void *)(KSEG0 + 0x80),  &jump_tlb_miss_unused, 0x80);
3484 +       memcpy((void *)(KSEG0 + 0x100), &jump_cache_error, 0x80);
3485 +       memcpy((void *)(KSEG0 + 0x180), &jump_general_exception, 0x80);
3486 +       memcpy((void *)(KSEG0 + 0x200), &jump_dedicated_interrupt, 0x80);
3487 +#else
3488 +       memcpy((void *)(KSEG0 + 0x80), &except_vec1_generic, 0x80);
3489 +#endif
3490 +       flush_icache_range(KSEG0 + 0x80, KSEG0 + 0x200);
3491 +
3492         /*
3493          * Setup default vectors
3494          */
3495 @@ -951,8 +989,12 @@
3496          * Some MIPS CPUs have a dedicated interrupt vector which reduces the
3497          * interrupt processing overhead.  Use it where available.
3498          */
3499 +#ifdef CONFIG_AR7
3500 +       memcpy((void *)((KSEG0+CONFIG_AR7_MEMORY) + 0x200), &except_vec4, 8);
3501 +#else
3502         if (cpu_has_divec)
3503                 memcpy((void *)(KSEG0 + 0x200), &except_vec4, 8);
3504 +#endif
3505
3506         /*
3507          * Some CPUs can enable/disable for cache parity detection, but does
3508 @@ -991,12 +1033,17 @@
3509         if (cpu_has_mcheck)
3510                 set_except_vector(24, handle_mcheck);
3511
3512 +memcpy((void *)(KSEG0 + 0x180), &except_vec3_generic, 0x80);
3513 +#ifdef CONFIG_AR7
3514 +       memcpy((void *)((KSEG0+CONFIG_AR7_MEMORY) + 0x180), &except_vec3_generic, 0x80);
3515 +#else
3516         if (cpu_has_vce)
3517                 memcpy((void *)(KSEG0 + 0x180), &except_vec3_r4000, 0x80);
3518         else if (cpu_has_4kex)
3519                 memcpy((void *)(KSEG0 + 0x180), &except_vec3_generic, 0x80);
3520         else
3521                 memcpy((void *)(KSEG0 + 0x080), &except_vec3_generic, 0x80);
3522 +#endif
3523
3524         if (current_cpu_data.cputype == CPU_R6000 ||
3525             current_cpu_data.cputype == CPU_R6000A) {
3526 @@ -1023,7 +1070,11 @@
3527         if (board_nmi_handler_setup)
3528                 board_nmi_handler_setup();
3529
3530 +#ifdef CONFIG_AR7
3531 +       flush_icache_range((KSEG0+CONFIG_AR7_MEMORY), (KSEG0+CONFIG_AR7_MEMORY) + 0x200);
3532 +#else
3533         flush_icache_range(KSEG0, KSEG0 + 0x400);
3534 +#endif
3535
3536         per_cpu_trap_init();
3537  }
3538 diff -urN linux.old/arch/mips/lib/promlib.c linux.dev/arch/mips/lib/promlib.c
3539 --- linux.old/arch/mips/lib/promlib.c   2005-07-26 18:18:16.267580488 +0200
3540 +++ linux.dev/arch/mips/lib/promlib.c   2005-07-26 18:11:02.635502000 +0200
3541 @@ -1,3 +1,4 @@
3542 +#ifndef CONFIG_AR7
3543  #include <stdarg.h>
3544  #include <linux/kernel.h>
3545
3546 @@ -22,3 +23,4 @@
3547         }
3548         va_end(args);
3549  }
3550 +#endif
3551 diff -urN linux.old/arch/mips/mm/init.c linux.dev/arch/mips/mm/init.c
3552 --- linux.old/arch/mips/mm/init.c       2005-07-26 18:18:16.268580336 +0200
3553 +++ linux.dev/arch/mips/mm/init.c       2005-07-26 18:38:00.091611880 +0200
3554 @@ -235,6 +235,7 @@
3555  #endif
3556  }
3557
3558 +#ifndef CONFIG_AR7_PAGING
3559  void __init paging_init(void)
3560  {
3561         unsigned long zones_size[MAX_NR_ZONES] = {0, 0, 0};
3562 @@ -272,6 +273,7 @@
3563
3564         free_area_init(zones_size);
3565  }
3566 +#endif
3567
3568  #define PFN_UP(x)      (((x) + PAGE_SIZE - 1) >> PAGE_SHIFT)
3569  #define PFN_DOWN(x)    ((x) >> PAGE_SHIFT)
3570 @@ -298,6 +300,7 @@
3571         return 0;
3572  }
3573
3574 +#ifndef CONFIG_AR7_PAGING
3575  void __init mem_init(void)
3576  {
3577         unsigned long codesize, reservedpages, datasize, initsize;
3578 @@ -359,6 +362,7 @@
3579                initsize >> 10,
3580                (unsigned long) (totalhigh_pages << (PAGE_SHIFT-10)));
3581  }
3582 +#endif
3583
3584  #ifdef CONFIG_BLK_DEV_INITRD
3585  void free_initrd_mem(unsigned long start, unsigned long end)
3586 @@ -397,6 +401,7 @@
3587                (&__init_end - &__init_begin) >> 10);
3588  }
3589
3590 +#ifndef CONFIG_AR7_PAGING
3591  void si_meminfo(struct sysinfo *val)
3592  {
3593         val->totalram = totalram_pages;
3594 @@ -409,3 +414,4 @@
3595
3596         return;
3597  }
3598 +#endif
3599 diff -urN linux.old/arch/mips/mm/tlb-r4k.c linux.dev/arch/mips/mm/tlb-r4k.c
3600 --- linux.old/arch/mips/mm/tlb-r4k.c    2005-07-26 18:18:16.269580184 +0200
3601 +++ linux.dev/arch/mips/mm/tlb-r4k.c    2005-07-26 18:38:00.092611728 +0200
3602 @@ -375,7 +375,12 @@
3603                 else if (current_cpu_data.cputype == CPU_R4600)
3604                         memcpy((void *)KSEG0, &except_vec0_r4600, 0x80);
3605                 else
3606 +#ifdef CONFIG_AR7
3607 +                       memcpy((void *)(KSEG0+CONFIG_AR7_MEMORY), &except_vec0_r4000, 0x80);
3608 +               flush_icache_range((KSEG0+CONFIG_AR7_MEMORY), (KSEG0+CONFIG_AR7_MEMORY) + 0x80);
3609 +#else
3610                         memcpy((void *)KSEG0, &except_vec0_r4000, 0x80);
3611                 flush_icache_range(KSEG0, KSEG0 + 0x80);
3612 +#endif
3613         }
3614  }
3615 diff -urN linux.old/drivers/char/serial.c linux.dev/drivers/char/serial.c
3616 --- linux.old/drivers/char/serial.c     2005-07-26 18:18:16.274579424 +0200
3617 +++ linux.dev/drivers/char/serial.c     2005-07-26 18:38:00.096611120 +0200
3618 @@ -419,7 +419,40 @@
3619         return 0;
3620  }
3621
3622 -#if defined(CONFIG_MIPS_ATLAS) || defined(CONFIG_MIPS_SEAD)
3623 +#if defined(CONFIG_AR7)
3624 +
3625 +static _INLINE_ unsigned int serial_in(struct async_struct *info, int offset)
3626 +{
3627 +       return (inb(info->port + (offset * 4)) & 0xff);
3628 +}
3629 +
3630 +
3631 +static _INLINE_ unsigned int serial_inp(struct async_struct *info, int offset)
3632 +{
3633 +#ifdef CONFIG_SERIAL_NOPAUSE_IO
3634 +       return (inb(info->port + (offset * 4)) & 0xff);
3635 +#else
3636 +       return (inb_p(info->port + (offset * 4)) & 0xff);
3637 +#endif
3638 +}
3639 +
3640 +static _INLINE_ void serial_out(struct async_struct *info, int offset, int value)
3641 +{
3642 +       outb(value, info->port + (offset * 4));
3643 +}
3644 +
3645 +
3646 +static _INLINE_ void serial_outp(struct async_struct *info, int offset,
3647 +               int value)
3648 +{
3649 +#ifdef CONFIG_SERIAL_NOPAUSE_IO
3650 +       outb(value, info->port + (offset * 4));
3651 +#else
3652 +       outb_p(value, info->port + (offset * 4));
3653 +#endif
3654 +}
3655 +
3656 +#elif defined(CONFIG_MIPS_ATLAS) || defined(CONFIG_MIPS_SEAD)
3657
3658  #include <asm/mips-boards/atlas.h>
3659
3660 @@ -478,8 +511,10 @@
3661   * needed for certain old 386 machines, I've left these #define's
3662   * in....
3663   */
3664 +#ifndef CONFIG_AR7
3665  #define serial_inp(info, offset)               serial_in(info, offset)
3666  #define serial_outp(info, offset, value)       serial_out(info, offset, value)
3667 +#endif
3668
3669
3670  /*
3671 @@ -1728,7 +1763,15 @@
3672                         /* Special case since 134 is really 134.5 */
3673                         quot = (2*baud_base / 269);
3674                 else if (baud)
3675 +#ifdef CONFIG_AR7
3676 +                       quot = (CONFIG_AR7_SYS*500000) / baud;
3677 +
3678 +               if ((quot%16)>7)
3679 +                       quot += 8;
3680 +               quot /=16;
3681 +#else
3682                         quot = baud_base / baud;
3683 +#endif
3684         }
3685         /* If the quotient is zero refuse the change */
3686         if (!quot && old_termios) {
3687 @@ -5552,8 +5595,10 @@
3688                 state->irq = irq_cannonicalize(state->irq);
3689                 if (state->hub6)
3690                         state->io_type = SERIAL_IO_HUB6;
3691 +#ifndef CONFIG_AR7
3692                 if (state->port && check_region(state->port,8))
3693                         continue;
3694 +#endif
3695  #ifdef CONFIG_MCA
3696                 if ((state->flags & ASYNC_BOOT_ONLYMCA) && !MCA_bus)
3697                         continue;
3698 @@ -6009,7 +6054,15 @@
3699         info->io_type = state->io_type;
3700         info->iomem_base = state->iomem_base;
3701         info->iomem_reg_shift = state->iomem_reg_shift;
3702 +#ifdef CONFIG_AR7
3703 +       quot = (CONFIG_AR7_SYS*500000) / baud;
3704 +
3705 +       if ((quot%16)>7)
3706 +               quot += 8;
3707 +       quot /=16;
3708 +#else
3709         quot = state->baud_base / baud;
3710 +#endif
3711         cval = cflag & (CSIZE | CSTOPB);
3712  #if defined(__powerpc__) || defined(__alpha__)
3713         cval >>= 8;
3714 diff -urN linux.old/include/asm-mips/ar7/ar7.h linux.dev/include/asm-mips/ar7/ar7.h
3715 --- linux.old/include/asm-mips/ar7/ar7.h        1970-01-01 01:00:00.000000000 +0100
3716 +++ linux.dev/include/asm-mips/ar7/ar7.h        2005-07-26 18:11:02.643501000 +0200
3717 @@ -0,0 +1,33 @@
3718 +/*
3719 + * $Id$
3720 + * Copyright (C) $Date$  $Author$
3721 + *
3722 + * This program is free software; you can redistribute it and/or modify
3723 + * it under the terms of the GNU General Public License as published by
3724 + * the Free Software Foundation; either version 2 of the License, or
3725 + * (at your option) any later version.
3726 + *
3727 + * This program is distributed in the hope that it will be useful,
3728 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
3729 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
3730 + * GNU General Public License for more details.
3731 + *
3732 + * You should have received a copy of the GNU General Public License
3733 + * along with this program; if not, write to the Free Software
3734 + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
3735 + *
3736 + */
3737 +
3738 +#ifndef _AR7_H
3739 +#define _AR7_H
3740 +
3741 +#include <asm/addrspace.h>
3742 +#include <linux/config.h>
3743 +
3744 +#define AVALANCHE_VECS_KSEG0 (KSEG0ADDR(CONFIG_AR7_MEMORY))
3745 +
3746 +#define AR7_UART0_REGS_BASE (KSEG1ADDR(0x08610E00))
3747 +#define AR7_UART1_REGS_BASE (KSEG1ADDR(0x08610F00))
3748 +#define AR7_BASE_BAUD ( 3686400 / 16 )
3749 +
3750 +#endif
3751 diff -urN linux.old/include/asm-mips/ar7/avalanche_intc.h linux.dev/include/asm-mips/ar7/avalanche_intc.h
3752 --- linux.old/include/asm-mips/ar7/avalanche_intc.h     1970-01-01 01:00:00.000000000 +0100
3753 +++ linux.dev/include/asm-mips/ar7/avalanche_intc.h     2005-07-26 18:38:00.097610968 +0200
3754 @@ -0,0 +1,283 @@
3755 + /*
3756 + * Nitin Dhingra, iamnd@ti.com
3757 + * Copyright (C) 2000 Texas Instruments Inc.
3758 + *
3759 + *
3760 + * ########################################################################
3761 + *
3762 + *  This program is free software; you can distribute it and/or modify it
3763 + *  under the terms of the GNU General Public License (Version 2) as
3764 + *  published by the Free Software Foundation.
3765 + *
3766 + *  This program is distributed in the hope it will be useful, but WITHOUT
3767 + *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
3768 + *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
3769 + *  for more details.
3770 + *
3771 + *  You should have received a copy of the GNU General Public License along
3772 + *  with this program; if not, write to the Free Software Foundation, Inc.,
3773 + *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
3774 + *
3775 + * ########################################################################
3776 + *
3777 + * Defines of the Sead board specific address-MAP, registers, etc.
3778 + *
3779 + */
3780 +#ifndef _AVALANCHE_INTC_H
3781 +#define _AVALANCHE_INTC_H
3782 +
3783 +/* ----- */
3784 +
3785 +#define KSEG1_BASE                  0xA0000000
3786 +#define KSEG_INV_MASK               0x1FFFFFFF /* Inverted mask for kseg address */
3787 +#define PHYS_ADDR(addr)             ((addr) & KSEG_INV_MASK)
3788 +#define PHYS_TO_K1(addr)            (PHYS_ADDR(addr)|KSEG1_BASE)
3789 +#define AVALANCHE_INTC_BASE PHYS_TO_K1(0x08612400)
3790 +
3791 +/* ----- */
3792 +
3793 +#define MIPS_EXCEPTION_OFFSET 8
3794 +
3795 +/******************************************************************************
3796 + Avalanche Interrupt number
3797 +******************************************************************************/
3798 +#define AVINTNUM(x) ((x) - MIPS_EXCEPTION_OFFSET)
3799 +
3800 +/*******************************************************************************
3801 +*Linux Interrupt number
3802 +*******************************************************************************/
3803 +#define LNXINTNUM(x)((x) + MIPS_EXCEPTION_OFFSET)
3804 +
3805 +
3806 +
3807 +#define AVALANCHE_INT_END_PRIMARY      (40 + MIPS_EXCEPTION_OFFSET)
3808 +#define AVALANCHE_INT_END_SECONDARY    (32 + MIPS_EXCEPTION_OFFSET)
3809 +
3810 +#define AVALANCHE_INT_END_PRIMARY_REG1 (31 + MIPS_EXCEPTION_OFFSET)
3811 +#define AVALANCHE_INT_END_PRIMARY_REG2 (39 + MIPS_EXCEPTION_OFFSET)
3812 +
3813 +
3814 +#define AVALANCHE_INT_END (AVINTNUM(AVALANCHE_INT_END_PRIMARY) + \
3815 +                           AVINTNUM(AVALANCHE_INT_END_SECONDARY)  \
3816 +                                    + MIPS_EXCEPTION_OFFSET - 1) /* Suraj, check */
3817 +
3818 +
3819 +/*
3820 + * Avalanche interrupt controller register base (primary)
3821 + */
3822 +#define AVALANCHE_ICTRL_REGS_BASE  AVALANCHE_INTC_BASE
3823 +
3824 +/******************************************************************************
3825 + * Avalanche exception controller register base (secondary)
3826 + ******************************************************************************/
3827 +#define AVALANCHE_ECTRL_REGS_BASE  (AVALANCHE_ICTRL_REGS_BASE + 0x80)
3828 +
3829 +
3830 +/******************************************************************************
3831 + *  Avalanche Interrupt pacing register base (secondary)
3832 + ******************************************************************************/
3833 +#define AVALANCHE_IPACE_REGS_BASE  (AVALANCHE_ICTRL_REGS_BASE + 0xA0)
3834 +
3835 +
3836 +
3837 +/******************************************************************************
3838 + * Avalanche Interrupt Channel Control register base
3839 + *****************************************************************************/
3840 +#define AVALANCHE_CHCTRL_REGS_BASE (AVALANCHE_ICTRL_REGS_BASE + 0x200)
3841 +
3842 +
3843 +struct avalanche_ictrl_regs /* Avalanche Interrupt control registers */
3844 +{
3845 +  volatile unsigned long intsr1;    /* Interrupt Status/Set Register 1   0x00 */
3846 +  volatile unsigned long intsr2;    /* Interrupt Status/Set Register 2   0x04 */
3847 +  volatile unsigned long unused1;                                      /*0x08 */
3848 +  volatile unsigned long unused2;                                      /*0x0C */
3849 +  volatile unsigned long intcr1;    /* Interrupt Clear Register 1        0x10 */
3850 +  volatile unsigned long intcr2;    /* Interrupt Clear Register 2        0x14 */
3851 +  volatile unsigned long unused3;                                      /*0x18 */
3852 +  volatile unsigned long unused4;                                      /*0x1C */
3853 +  volatile unsigned long intesr1;   /* Interrupt Enable (Set) Register 1 0x20 */
3854 +  volatile unsigned long intesr2;   /* Interrupt Enable (Set) Register 2 0x24 */
3855 +  volatile unsigned long unused5;                                      /*0x28 */
3856 +  volatile unsigned long unused6;                                      /*0x2C */
3857 +  volatile unsigned long intecr1;   /* Interrupt Enable Clear Register 1 0x30 */
3858 +  volatile unsigned long intecr2;   /* Interrupt Enable Clear Register 2 0x34 */
3859 +  volatile unsigned long unused7;                                     /* 0x38 */
3860 +  volatile unsigned long unused8;                                     /* 0x3c */
3861 +  volatile unsigned long pintir;    /* Priority Interrupt Index Register 0x40 */
3862 +  volatile unsigned long intmsr;    /* Priority Interrupt Mask Index Reg 0x44 */
3863 +  volatile unsigned long unused9;                                     /* 0x48 */
3864 +  volatile unsigned long unused10;                                    /* 0x4C */
3865 +  volatile unsigned long intpolr1;  /* Interrupt Polarity Mask register 10x50 */
3866 +  volatile unsigned long intpolr2;  /* Interrupt Polarity Mask register 20x54 */
3867 +  volatile unsigned long unused11;                                    /* 0x58 */
3868 +  volatile unsigned long unused12;                                   /*0x5C */
3869 +  volatile unsigned long inttypr1;  /* Interrupt Type     Mask register 10x60 */
3870 +  volatile unsigned long inttypr2;  /* Interrupt Type     Mask register 20x64 */
3871 +};
3872 +
3873 +struct avalanche_exctrl_regs   /* Avalanche Exception control registers */
3874 +{
3875 +  volatile unsigned long exsr;      /* Exceptions Status/Set register    0x80 */
3876 +  volatile unsigned long reserved;                                     /*0x84 */
3877 +  volatile unsigned long excr;      /* Exceptions Clear Register         0x88 */
3878 +  volatile unsigned long reserved1;                                    /*0x8c */
3879 +  volatile unsigned long exiesr;    /* Exceptions Interrupt Enable (set) 0x90 */
3880 +  volatile unsigned long reserved2;                                    /*0x94 */
3881 +  volatile unsigned long exiecr;    /* Exceptions Interrupt Enable(clear)0x98 */
3882 +};
3883 +struct avalanche_ipace_regs
3884 +{
3885 +
3886 +  volatile unsigned long ipacep;    /* Interrupt pacing register         0xa0 */
3887 +  volatile unsigned long ipacemap;  /*Interrupt Pacing Map Register      0xa4 */
3888 +  volatile unsigned long ipacemax;  /*Interrupt Pacing Max Register      0xa8 */
3889 +};
3890 +struct avalanche_channel_int_number
3891 +{
3892 +  volatile unsigned long cintnr0;   /* Channel Interrupt Number Register0x200 */
3893 +  volatile unsigned long cintnr1;   /* Channel Interrupt Number Register0x204 */
3894 +  volatile unsigned long cintnr2;   /* Channel Interrupt Number Register0x208 */
3895 +  volatile unsigned long cintnr3;   /* Channel Interrupt Number Register0x20C */
3896 +  volatile unsigned long cintnr4;   /* Channel Interrupt Number Register0x210 */
3897 +  volatile unsigned long cintnr5;   /* Channel Interrupt Number Register0x214 */
3898 +  volatile unsigned long cintnr6;   /* Channel Interrupt Number Register0x218 */
3899 +  volatile unsigned long cintnr7;   /* Channel Interrupt Number Register0x21C */
3900 +  volatile unsigned long cintnr8;   /* Channel Interrupt Number Register0x220 */
3901 +  volatile unsigned long cintnr9;   /* Channel Interrupt Number Register0x224 */
3902 +  volatile unsigned long cintnr10;  /* Channel Interrupt Number Register0x228 */
3903 +  volatile unsigned long cintnr11;  /* Channel Interrupt Number Register0x22C */
3904 +  volatile unsigned long cintnr12;  /* Channel Interrupt Number Register0x230 */
3905 +  volatile unsigned long cintnr13;  /* Channel Interrupt Number Register0x234 */
3906 +  volatile unsigned long cintnr14;  /* Channel Interrupt Number Register0x238 */
3907 +  volatile unsigned long cintnr15;  /* Channel Interrupt Number Register0x23C */
3908 +  volatile unsigned long cintnr16;  /* Channel Interrupt Number Register0x240 */
3909 +  volatile unsigned long cintnr17;  /* Channel Interrupt Number Register0x244 */
3910 +  volatile unsigned long cintnr18;  /* Channel Interrupt Number Register0x248 */
3911 +  volatile unsigned long cintnr19;  /* Channel Interrupt Number Register0x24C */
3912 +  volatile unsigned long cintnr20;  /* Channel Interrupt Number Register0x250 */
3913 +  volatile unsigned long cintnr21;  /* Channel Interrupt Number Register0x254 */
3914 +  volatile unsigned long cintnr22;  /* Channel Interrupt Number Register0x358 */
3915 +  volatile unsigned long cintnr23;  /* Channel Interrupt Number Register0x35C */
3916 +  volatile unsigned long cintnr24;  /* Channel Interrupt Number Register0x260 */
3917 +  volatile unsigned long cintnr25;  /* Channel Interrupt Number Register0x264 */
3918 +  volatile unsigned long cintnr26;  /* Channel Interrupt Number Register0x268 */
3919 +  volatile unsigned long cintnr27;  /* Channel Interrupt Number Register0x26C */
3920 +  volatile unsigned long cintnr28;  /* Channel Interrupt Number Register0x270 */
3921 +  volatile unsigned long cintnr29;  /* Channel Interrupt Number Register0x274 */
3922 +  volatile unsigned long cintnr30;  /* Channel Interrupt Number Register0x278 */
3923 +  volatile unsigned long cintnr31;  /* Channel Interrupt Number Register0x27C */
3924 +  volatile unsigned long cintnr32;  /* Channel Interrupt Number Register0x280 */
3925 +  volatile unsigned long cintnr33;  /* Channel Interrupt Number Register0x284 */
3926 +  volatile unsigned long cintnr34;  /* Channel Interrupt Number Register0x288 */
3927 +  volatile unsigned long cintnr35;  /* Channel Interrupt Number Register0x28C */
3928 +  volatile unsigned long cintnr36;  /* Channel Interrupt Number Register0x290 */
3929 +  volatile unsigned long cintnr37;  /* Channel Interrupt Number Register0x294 */
3930 +  volatile unsigned long cintnr38;  /* Channel Interrupt Number Register0x298 */
3931 +  volatile unsigned long cintnr39;  /* Channel Interrupt Number Register0x29C */
3932 +};
3933 +
3934 +struct avalanche_interrupt_line_to_channel
3935 +{
3936 +  unsigned long int_line0;    /* Start of primary interrupts */
3937 +  unsigned long int_line1;
3938 +  unsigned long int_line2;
3939 +  unsigned long int_line3;
3940 +  unsigned long int_line4;
3941 +  unsigned long int_line5;
3942 +  unsigned long int_line6;
3943 +  unsigned long int_line7;
3944 +  unsigned long int_line8;
3945 +  unsigned long int_line9;
3946 +  unsigned long int_line10;
3947 +  unsigned long int_line11;
3948 +  unsigned long int_line12;
3949 +  unsigned long int_line13;
3950 +  unsigned long int_line14;
3951 +  unsigned long int_line15;
3952 +  unsigned long int_line16;
3953 +  unsigned long int_line17;
3954 +  unsigned long int_line18;
3955 +  unsigned long int_line19;
3956 +  unsigned long int_line20;
3957 +  unsigned long int_line21;
3958 +  unsigned long int_line22;
3959 +  unsigned long int_line23;
3960 +  unsigned long int_line24;
3961 +  unsigned long int_line25;
3962 +  unsigned long int_line26;
3963 +  unsigned long int_line27;
3964 +  unsigned long int_line28;
3965 +  unsigned long int_line29;
3966 +  unsigned long int_line30;
3967 +  unsigned long int_line31;
3968 +  unsigned long int_line32;
3969 +  unsigned long int_line33;
3970 +  unsigned long int_line34;
3971 +  unsigned long int_line35;
3972 +  unsigned long int_line36;
3973 +  unsigned long int_line37;
3974 +  unsigned long int_line38;
3975 +  unsigned long int_line39;
3976 +};
3977 +
3978 +
3979 +/* Interrupt Line #'s  (Sangam peripherals) */
3980 +
3981 +/*------------------------------*/
3982 +/* Sangam primary interrupts */
3983 +/*------------------------------*/
3984 +
3985 +#define UNIFIED_SECONDARY_INTERRUPT  0
3986 +#define AVALANCHE_EXT_INT_0          1
3987 +#define AVALANCHE_EXT_INT_1          2
3988 +/*  Line #3  Reserved               */
3989 +/*  Line #4  Reserved               */
3990 +#define AVALANCHE_TIMER_0_INT        5
3991 +#define AVALANCHE_TIMER_1_INT        6
3992 +#define AVALANCHE_UART0_INT          7
3993 +#define AVALANCHE_UART1_INT          8
3994 +#define AVALANCHE_PDMA_INT0          9
3995 +#define AVALANCHE_PDMA_INT1          10
3996 +/*  Line #11  Reserved               */
3997 +/*  Line #12  Reserved               */
3998 +/*  Line #13  Reserved               */
3999 +/*  Line #14  Reserved               */
4000 +#define AVALANCHE_ATM_SAR_INT        15
4001 +/*  Line #16  Reserved               */
4002 +/*  Line #17  Reserved               */
4003 +/*  Line #18  Reserved               */
4004 +#define AVALANCHE_MAC0_INT           19
4005 +/*  Line #20  Reserved               */
4006 +#define AVALANCHE_VLYNQ0_INT         21
4007 +#define AVALANCHE_CODEC_WAKE_INT     22
4008 +/*  Line #23  Reserved               */
4009 +#define AVALANCHE_USB_INT            24
4010 +#define AVALANCHE_VLYNQ1_INT         25
4011 +/*  Line #26  Reserved               */
4012 +/*  Line #27  Reserved               */
4013 +#define AVALANCHE_MAC1_INT           28
4014 +#define AVALANCHE_I2CM_INT           29
4015 +#define AVALANCHE_PDMA_INT2          30
4016 +#define AVALANCHE_PDMA_INT3          31
4017 +/*  Line #32  Reserved               */
4018 +/*  Line #33  Reserved               */
4019 +/*  Line #34  Reserved               */
4020 +/*  Line #35  Reserved               */
4021 +/*  Line #36  Reserved               */
4022 +#define AVALANCHE_VDMA_VT_RX_INT     37
4023 +#define AVALANCHE_VDMA_VT_TX_INT     38
4024 +#define AVALANCHE_ADSLSS_INT         39
4025 +
4026 +/*-----------------------------------*/
4027 +/* Sangam Secondary Interrupts    */
4028 +/*-----------------------------------*/
4029 +#define PRIMARY_INTS                 40
4030 +
4031 +#define EMIF_INT                    (7 + PRIMARY_INTS)
4032 +
4033 +
4034 +extern void avalanche_int_set(int channel, int line);
4035 +
4036 +
4037 +#endif /* _AVALANCHE_INTC_H */
4038 diff -urN linux.old/include/asm-mips/ar7/avalanche_misc.h linux.dev/include/asm-mips/ar7/avalanche_misc.h
4039 --- linux.old/include/asm-mips/ar7/avalanche_misc.h     1970-01-01 01:00:00.000000000 +0100
4040 +++ linux.dev/include/asm-mips/ar7/avalanche_misc.h     2005-07-26 18:11:02.645501000 +0200
4041 @@ -0,0 +1,174 @@
4042 +#ifndef _AVALANCHE_MISC_H_
4043 +#define _AVALANCHE_MISC_H_
4044 +
4045 +typedef enum AVALANCHE_ERR_t
4046 +{
4047 +    AVALANCHE_ERR_OK        = 0,    /* OK or SUCCESS */
4048 +    AVALANCHE_ERR_ERROR     = -1,   /* Unspecified/Generic ERROR */
4049 +
4050 +    /* Pointers and args */
4051 +    AVALANCHE_ERR_INVARG        = -2,   /* Invaild argument to the call */
4052 +    AVALANCHE_ERR_NULLPTR       = -3,   /* NULL pointer */
4053 +    AVALANCHE_ERR_BADPTR        = -4,   /* Bad (out of mem) pointer */
4054 +
4055 +    /* Memory issues */
4056 +    AVALANCHE_ERR_ALLOC_FAIL    = -10,  /* allocation failed */
4057 +    AVALANCHE_ERR_FREE_FAIL     = -11,  /* free failed */
4058 +    AVALANCHE_ERR_MEM_CORRUPT   = -12,  /* corrupted memory */
4059 +    AVALANCHE_ERR_BUF_LINK      = -13,  /* buffer linking failed */
4060 +
4061 +    /* Device issues */
4062 +    AVALANCHE_ERR_DEVICE_TIMEOUT    = -20,  /* device timeout on read/write */
4063 +    AVALANCHE_ERR_DEVICE_MALFUNC    = -21,  /* device malfunction */
4064 +
4065 +    AVALANCHE_ERR_INVID     = -30   /* Invalid ID */
4066 +
4067 +} AVALANCHE_ERR;
4068 +
4069 +/*****************************************************************************
4070 + * Reset Control Module
4071 + *****************************************************************************/
4072 +
4073 +typedef enum AVALANCHE_RESET_MODULE_tag
4074 +{
4075 +    RESET_MODULE_UART0      = 0,
4076 +    RESET_MODULE_UART1      = 1,
4077 +    RESET_MODULE_I2C        = 2,
4078 +    RESET_MODULE_TIMER0     = 3,
4079 +    RESET_MODULE_TIMER1     = 4,
4080 +    RESET_MODULE_GPIO       = 6,
4081 +    RESET_MODULE_ADSLSS     = 7,
4082 +    RESET_MODULE_USBS       = 8,
4083 +    RESET_MODULE_SAR        = 9,
4084 +    RESET_MODULE_VDMA_VT    = 11,
4085 +    RESET_MODULE_FSER       = 12,
4086 +    RESET_MODULE_VLYNQ1     = 16,
4087 +    RESET_MODULE_EMAC0      = 17,
4088 +    RESET_MODULE_DMA        = 18,
4089 +    RESET_MODULE_BIST       = 19,
4090 +    RESET_MODULE_VLYNQ0     = 20,
4091 +    RESET_MODULE_EMAC1      = 21,
4092 +    RESET_MODULE_MDIO       = 22,
4093 +    RESET_MODULE_ADSLSS_DSP = 23,
4094 +    RESET_MODULE_EPHY       = 26
4095 +} AVALANCHE_RESET_MODULE_T;
4096 +
4097 +typedef enum AVALANCHE_RESET_CTRL_tag
4098 +{
4099 +    IN_RESET        = 0,
4100 +    OUT_OF_RESET
4101 +} AVALANCHE_RESET_CTRL_T;
4102 +
4103 +typedef enum AVALANCHE_SYS_RST_MODE_tag
4104 +{
4105 +    RESET_SOC_WITH_MEMCTRL      = 1,    /* SW0 bit in SWRCR register */
4106 +    RESET_SOC_WITHOUT_MEMCTRL   = 2     /* SW1 bit in SWRCR register */
4107 +} AVALANCHE_SYS_RST_MODE_T;
4108 +
4109 +typedef enum AVALANCHE_SYS_RESET_STATUS_tag
4110 +{
4111 +    HARDWARE_RESET = 0,
4112 +    SOFTWARE_RESET0,            /* Caused by writing 1 to SW0 bit in SWRCR register */
4113 +    WATCHDOG_RESET,
4114 +    SOFTWARE_RESET1             /* Caused by writing 1 to SW1 bit in SWRCR register */
4115 +} AVALANCHE_SYS_RESET_STATUS_T;
4116 +
4117 +AVALANCHE_RESET_CTRL_T avalanche_get_reset_status(AVALANCHE_RESET_MODULE_T reset_module);
4118 +void avalanche_sys_reset(AVALANCHE_SYS_RST_MODE_T mode);
4119 +AVALANCHE_SYS_RESET_STATUS_T avalanche_get_sys_last_reset_status(void);
4120 +
4121 +typedef int (*REMOTE_VLYNQ_DEV_RESET_CTRL_FN)(unsigned int reset_module, AVALANCHE_RESET_CTRL_T reset_ctrl);
4122 +
4123 +/*****************************************************************************
4124 + * Power Control Module
4125 + *****************************************************************************/
4126 +
4127 +typedef enum AVALANCHE_POWER_CTRL_tag
4128 +{
4129 +    POWER_CTRL_POWER_UP = 0,
4130 +    POWER_CTRL_POWER_DOWN
4131 +} AVALANCHE_POWER_CTRL_T;
4132 +
4133 +typedef enum AVALANCHE_SYS_POWER_MODE_tag
4134 +{
4135 +    GLOBAL_POWER_MODE_RUN       = 0,    /* All system is up */
4136 +    GLOBAL_POWER_MODE_IDLE,             /* MIPS is power down, all peripherals working */
4137 +    GLOBAL_POWER_MODE_STANDBY,          /* Chip in power down, but clock to ADSKL subsystem is running */
4138 +    GLOBAL_POWER_MODE_POWER_DOWN        /* Total chip is powered down */
4139 +} AVALANCHE_SYS_POWER_MODE_T;
4140 +
4141 +void avalanche_power_ctrl(unsigned int power_module,  AVALANCHE_POWER_CTRL_T power_ctrl);
4142 +AVALANCHE_POWER_CTRL_T avalanche_get_power_status(unsigned int power_module);
4143 +void avalanche_set_global_power_mode(AVALANCHE_SYS_POWER_MODE_T power_mode);
4144 +AVALANCHE_SYS_POWER_MODE_T avalanche_get_global_power_mode(void);
4145 +
4146 +/*****************************************************************************
4147 + * Wakeup Control
4148 + *****************************************************************************/
4149 +
4150 +typedef enum AVALANCHE_WAKEUP_INTERRUPT_tag
4151 +{
4152 +    WAKEUP_INT0 = 1,
4153 +    WAKEUP_INT1 = 2,
4154 +    WAKEUP_INT2 = 4,
4155 +    WAKEUP_INT3 = 8
4156 +} AVALANCHE_WAKEUP_INTERRUPT_T;
4157 +
4158 +typedef enum TNETV1050_WAKEUP_CTRL_tag
4159 +{
4160 +    WAKEUP_DISABLED = 0,
4161 +    WAKEUP_ENABLED
4162 +} AVALANCHE_WAKEUP_CTRL_T;
4163 +
4164 +typedef enum TNETV1050_WAKEUP_POLARITY_tag
4165 +{
4166 +    WAKEUP_ACTIVE_HIGH = 0,
4167 +    WAKEUP_ACTIVE_LOW
4168 +} AVALANCHE_WAKEUP_POLARITY_T;
4169 +
4170 +void avalanche_wakeup_ctrl(AVALANCHE_WAKEUP_INTERRUPT_T wakeup_int,
4171 +                           AVALANCHE_WAKEUP_CTRL_T wakeup_ctrl,
4172 +                           AVALANCHE_WAKEUP_POLARITY_T wakeup_polarity);
4173 +
4174 +/*****************************************************************************
4175 + * GPIO Control
4176 + *****************************************************************************/
4177 +
4178 +typedef enum AVALANCHE_GPIO_PIN_MODE_tag
4179 +{
4180 +    FUNCTIONAL_PIN = 0,
4181 +    GPIO_PIN = 1
4182 +} AVALANCHE_GPIO_PIN_MODE_T;
4183 +
4184 +typedef enum AVALANCHE_GPIO_PIN_DIRECTION_tag
4185 +{
4186 +    GPIO_OUTPUT_PIN = 0,
4187 +    GPIO_INPUT_PIN = 1
4188 +} AVALANCHE_GPIO_PIN_DIRECTION_T;
4189 +
4190 +typedef enum { GPIO_FALSE, GPIO_TRUE } AVALANCHE_GPIO_BOOL_T;
4191 +
4192 +void avalanche_gpio_init(void);
4193 +int avalanche_gpio_ctrl(unsigned int gpio_pin,
4194 +                         AVALANCHE_GPIO_PIN_MODE_T pin_mode,
4195 +                         AVALANCHE_GPIO_PIN_DIRECTION_T pin_direction);
4196 +int avalanche_gpio_ctrl_with_link_count(unsigned int gpio_pin,
4197 +                         AVALANCHE_GPIO_PIN_MODE_T pin_mode,
4198 +                         AVALANCHE_GPIO_PIN_DIRECTION_T pin_direction);
4199 +int avalanche_gpio_out_bit(unsigned int gpio_pin, int value);
4200 +int avalanche_gpio_in_bit(unsigned int gpio_pin);
4201 +int avalanche_gpio_out_value(unsigned int out_val, unsigned int set_mask, unsigned int reg_index);
4202 +int avalanche_gpio_out_value_with_link_count(unsigned int out_val, unsigned int set_mask, unsigned int reg_index);
4203 +int avalanche_gpio_in_value(unsigned int *in_val, unsigned int reg_index);
4204 +
4205 +unsigned int avalanche_get_chip_version_info(void);
4206 +
4207 +unsigned int avalanche_get_vbus_freq(void);
4208 +void         avalanche_set_vbus_freq(unsigned int);
4209 +
4210 +
4211 +typedef int (*SET_MDIX_ON_CHIP_FN_T)(unsigned int base_addr, unsigned int operation);
4212 +int avalanche_set_mdix_on_chip(unsigned int base_addr, unsigned int operation);
4213 +unsigned int avalanche_is_mdix_on_chip(void);
4214 +
4215 +#endif
4216 diff -urN linux.old/include/asm-mips/ar7/avalanche_regs.h linux.dev/include/asm-mips/ar7/avalanche_regs.h
4217 --- linux.old/include/asm-mips/ar7/avalanche_regs.h     1970-01-01 01:00:00.000000000 +0100
4218 +++ linux.dev/include/asm-mips/ar7/avalanche_regs.h     2005-07-26 18:11:02.646500000 +0200
4219 @@ -0,0 +1,567 @@
4220 +/*
4221 + *  $Id$
4222 + *  Avalanche Register Descriptions
4223 + *
4224 + *  Jeff Harrell, jharrell@ti.com
4225 + *  2000 (c) Texas Instruments Inc.
4226 + */
4227 +
4228 +#ifndef __AVALANCHE_REGS_H
4229 +#define __AVALANCHE_REGS_H
4230 +
4231 +#include <asm/addrspace.h>
4232 +#include <linux/config.h>
4233 +
4234 +/*----------------------------------------*/
4235 +/* Base offsets within the Avalanche ASIC */
4236 +/*----------------------------------------*/
4237 +
4238 +#define BBIF_SPACE0     (KSEG1ADDR(0x01000000))
4239 +#define BBIF_SPACE1     (KSEG1ADDR(0x01800000))
4240 +#define BBIF_CONTROL    (KSEG1ADDR(0x02000000))
4241 +#define ATM_SAR_BASE    (KSEG1ADDR(0x03000000))
4242 +#define USB_MCU_BASE    (KSEG1ADDR(0x03400000))
4243 +#define DES_BASE        (KSEG1ADDR(0x08600000))
4244 +#define ETH_MACA_BASE   (KSEG1ADDR(0x08610000))
4245 +#define ETH_MACB_BASE   (KSEG1ADDR(0x08612800))
4246 +#define MEM_CTRLR_BASE  (KSEG1ADDR(0x08610800))
4247 +#define GPIO_BASE       (KSEG1ADDR(0x08610900))
4248 +#define CLK_CTRL_BASE   (KSEG1ADDR(0x08610A00))
4249 +#define WATCH_DOG_BASE  (KSEG1ADDR(0x08610B00))
4250 +#define TMR1_BASE       (KSEG1ADDR(0x08610C00))
4251 +#define TRM2_BASE       (KSEG1ADDR(0x08610D00))
4252 +#define UARTA_BASE      (KSEG1ADDR(0x08610E00))
4253 +#define UARTB_BASE      (KSEG1ADDR(0x08610F00))
4254 +#define I2C_BASE        (KSEG1ADDR(0x08611000))
4255 +#define DEV_ID_BASE     (KSEG1ADDR(0x08611100))
4256 +#define USB_BASE        (KSEG1ADDR(0x08611200))
4257 +#define PCI_CONFIG_BASE (KSEG1ADDR(0x08611300))
4258 +#define DMA_BASE        (KSEG1ADDR(0x08611400))
4259 +#define RESET_CTRL_BASE (KSEG1ADDR(0x08611600))
4260 +#define DSL_IF_BASE     (KSEG1ADDR(0x08611B00))
4261 +#define INT_CTL_BASE    (KSEG1ADDR(0x08612400))
4262 +#define PHY_BASE        (KSEG1ADDR(0x1E000000))
4263 +
4264 +/*---------------------------------*/
4265 +/* Device ID, chip version number  */
4266 +/*---------------------------------*/
4267 +
4268 +#define AVALANCHE_CHVN  (*(volatile unsigned int *)(DEV_ID_BASE+0x14))
4269 +#define AVALANCHE_DEVID1 (*(volatile unsigned int *)(DEV_ID_BASE+0x18))
4270 +#define AVALANCHE_DEVID2 (*(volatile unsigned int *)(DEV_ID_BASE+0x1C))
4271 +
4272 +/*----------------------------------*/
4273 +/* Reset Control VW changed to ptrs */
4274 +/*----------------------------------*/
4275 +
4276 +#define AVALANCHE_PRCR  (*(volatile unsigned int *)(RESET_CTRL_BASE + 0x0))  /* Peripheral reset control */
4277 +#define AVALANCHE_SWRCR (*(volatile unsigned int *)(RESET_CTRL_BASE + 0x4))  /* Software reset control   */
4278 +#define AVALANCHE_RSR   (*(volatile unsigned int *)(RESET_CTRL_BASE + 0x8))  /* Reset status register    */
4279 +
4280 +/* reset control bits */
4281 +
4282 +#define AV_RST_UART0    (1<<0)    /* Brings UART0 out of reset              */
4283 +#define AV_RST_UART1    (1<<1)    /* Brings UART1 out of reset              */
4284 +#define AV_RST_IICM     (1<<2)    /* Brings the I2CM out of reset           */
4285 +#define AV_RST_TIMER0   (1<<3)    /* Brings Timer 0 out of reset            */
4286 +#define AV_RST_TIMER1   (1<<4)    /* Brings Timer 1 out of reset            */
4287 +#define AV_RST_DES      (1<<5)    /* Brings the DES module out of reset     */
4288 +#define AV_RST_GPIO     (1<<6)    /* Brings the GPIO module out of reset (see note below) */
4289 +/*
4290 +  JAH NOTE JAH NOTE JAH NOTE JAH NOTE JAH NOTE JAH NOTE JAH NOTE JAH NOTE
4291 +       If you reset the GPIO interface all of the directions (i/o) of the UART B
4292 +       interface pins are inputs and must be reconfigured so as not to lose the
4293 +       serial console interface
4294 +  JAH NOTE JAH NOTE JAH NOTE JAH NOTE JAH NOTE JAH NOTE JAH NOTE JAH NOTE
4295 +*/
4296 +#define AV_RST_BBIF     (1<<7)    /* Brings the Broadband interface out of reset */
4297 +#define AV_RST_USB      (1<<8)    /* Brings the USB module out of reset     */
4298 +#define AV_RST_SAR      (1<<9)    /* Brings the SAR out of reset            */
4299 +#define AV_RST_HDLC     (1<<10)   /* Brings the HDLC module out of reset    */
4300 +#define AV_RST_PCI      (1<<16)   /* Brings the PCI module out of reset     */
4301 +#define AV_RST_ETH_MAC0 (1<<17)   /* Brings the Ethernet MAC0 out of reset  */
4302 +#define AV_RST_PICO_DMA (1<<18)   /* Brings the PICO DMA module out of reset */
4303 +#define AV_RST_BIST     (1<<19)   /* Brings the BIST module out of reset    */
4304 +#define AV_RST_DSP      (1<<20)   /* Brings the DSP sub system out of reset */
4305 +#define AV_RST_ETH_MAC1 (1<<21)   /* Brings the Ethernet MAC1 out of reset  */
4306 +
4307 +/*----------------------*/
4308 +/* Physical interfaces  */
4309 +/*----------------------*/
4310 +
4311 +/* Phy loopback */
4312 +#define PHY_LOOPBACK    1
4313 +
4314 +
4315 +/* Phy 0 */
4316 +#define PHY0BASE        (PHY_BASE)
4317 +#define PHY0RST         (*(volatile unsigned char *) (PHY0BASE))      /* reset   */
4318 +#define PHY0CTRL        (*(volatile unsigned char *) (PHY0BASE+0x5))  /* control */
4319 +#define PHY0RACPCTRL    (*(volatile unsigned char *) (PHY0BASE+0x50)) /* RACP control/status */
4320 +#define PHY0TACPCTRL    (*(volatile unsigned char *) (PHY0BASE+0x60)) /* TACP idle/unassigned cell hdr */
4321 +#define PHY0RACPINT     (*(volatile unsigned char *) (PHY0BASE+0x51)) /* RACP interrupt enable/Status */
4322 +
4323 +
4324 +/* Phy 1 */
4325 +
4326 +#define PHY1BASE        (PHY_BASE + 0x100000)
4327 +#define PHY1RST         (*(volatile unsigned char *) (PHY1BASE))      /* reset   */
4328 +#define PHY1CTRL        (*(volatile unsigned char *) (PHY1BASE+0x5))  /* control */
4329 +#define PHY1RACPCTRL    (*(volatile unsigned char *) (PHY1BASE+0x50))
4330 +#define PHY1TACPCTRL    (*(volatile unsigned char *) (PHY1BASE+0x60))
4331 +#define PHY1RACPINT     (*(volatile unsigned char *) (PHY1BASE+0x51))
4332 +
4333 +/* Phy 2 */
4334 +
4335 +#define PHY2BASE        (PHY_BASE + 0x200000)
4336 +#define PHY2RST         (*(volatile unsigned char *) (PHY2BASE))      /* reset   */
4337 +#define PHY2CTRL        (*(volatile unsigned char *) (PHY2BASE+0x5))  /* control */
4338 +#define PHY2RACPCTRL    (*(volatile unsigned char *) (PHY2BASE+0x50))
4339 +#define PHY2TACPCTRL    (*(volatile unsigned char *) (PHY2BASE+0x60))
4340 +#define PHY2RACPINT     (*(volatile unsigned char *) (PHY2BASE+0x51))
4341 +
4342 +/*-------------------*/
4343 +/* Avalanche ATM SAR */
4344 +/*-------------------*/
4345 +
4346 +#define AVSAR_SYSCONFIG    (*(volatile unsigned int*)(ATM_SAR_BASE+0x00000000)) /* SAR system config register    */
4347 +#define AVSAR_SYSSTATUS    (*(volatile unsigned int*)(ATM_SAR_BASE+0x00000004)) /* SAR system status register    */
4348 +#define AVSAR_INT_ENABLE   (*(volatile unsigned int*)(ATM_SAR_BASE+0x00000008)) /* SAR interrupt enable register */
4349 +#define AVSAR_CONN_VPI_VCI (*(volatile unsigned int*)(ATM_SAR_BASE+0x0000000c)) /* VPI/VCI connection config     */
4350 +#define AVSAR_CONN_CONFIG  (*(volatile unsigned int*)(ATM_SAR_BASE+0x00000010)) /* Connection config register    */
4351 +#define AVSAR_OAM_CONFIG   (*(volatile unsigned int*)(ATM_SAR_BASE+0x00000018)) /* OAM configuration register    */
4352 +
4353 +/* Transmit completion ring registers */
4354 +
4355 +#define AVSAR_TCRAPTR       (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000100))
4356 +#define AVSAR_TCRASIZE      (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000104))
4357 +#define AVSAR_TCRAINTTHRESH (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000108))
4358 +#define AVSAR_TCRATOTENT    (*(volatile unsigned int *)(ATM_SAR_BASE+0x0000010c))
4359 +#define AVSAR_TCRAFREEENT   (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000110))
4360 +#define AVSAR_TCRAPENDENT   (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000114))
4361 +#define AVSAR_TCRAENTINC    (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000118))
4362 +#define AVSAR_TCRBPTR       (*(volatile unsigned int *)(ATM_SAR_BASE+0x0000011c))
4363 +#define AVSAR_TCRBSIZE      (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000120))
4364 +#define AVSAR_TCRBINTTHRESH (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000124))
4365 +#define AVSAR_TCRBTOTENT    (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000128))
4366 +#define AVSAR_TCRBFREEENT   (*(volatile unsigned int *)(ATM_SAR_BASE+0x0000012c))
4367 +#define AVSAR_TCRBPENDENT   (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000130))
4368 +#define AVSAR_TCRBENTINC    (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000134))
4369 +
4370 +/* Transmit Queue Packet registers */
4371 +#define AVSAR_TXQUEUE_PKT0  (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000140))
4372 +#define AVSAR_TXQUEUE_PKT1  (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000144))
4373 +#define AVSAR_TXQUEUE_PKT2  (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000148))
4374 +#define AVSAR_TX_FLUSH      (*(volatile unsigned int *)(ATM_SAR_BASE+0x0000014C))
4375 +/* Receive completion ring registers */
4376 +
4377 +#define AVSAR_RCRAPTR       (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000200))
4378 +#define AVSAR_RCRASIZE      (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000204))
4379 +#define AVSAR_RCRAINTTHRESH (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000208))
4380 +#define AVSAR_RCRATOTENT    (*(volatile unsigned int *)(ATM_SAR_BASE+0x0000020c))
4381 +#define AVSAR_RCRAFREEENT   (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000210))
4382 +#define AVSAR_RCRAPENDENT   (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000214))
4383 +#define AVSAR_RCRAENTINC    (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000218))
4384 +#define AVSAR_RCRBPTR       (*(volatile unsigned int *)(ATM_SAR_BASE+0x0000021c))
4385 +#define AVSAR_RCRBSIZE      (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000220))
4386 +#define AVSAR_RCRBINTTHRESH (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000224))
4387 +#define AVSAR_RCRBTOTENT    (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000228))
4388 +#define AVSAR_RCRBFREEENT   (*(volatile unsigned int *)(ATM_SAR_BASE+0x0000022c))
4389 +#define AVSAR_RCRBPENDENT   (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000230))
4390 +#define AVSAR_RCRBENTINC    (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000234))
4391 +
4392 +#define AVSAR_RXFBL_ADD0    (*(volatile unsigned int*)(ATM_SAR_BASE+0x00000240)) /* Rx Free buffer list add 0  */
4393 +#define AVSAR_RXFBL_ADD1    (*(volatile unsigned int*)(ATM_SAR_BASE+0x00000244)) /* Rx Free buffer list add 1  */
4394 +#define AVSAR_RXFBL_ADD2    (*(volatile unsigned int*)(ATM_SAR_BASE+0x00000248)) /* Rx Free buffer list add 2  */
4395 +#define AVSAR_RXFBLSIZE_0   (*(volatile unsigned int*)(ATM_SAR_BASE+0x0000028c)) /* Rx Free buffer list size 0 */
4396 +#define AVSAR_RXFBLSIZE_1   (*(volatile unsigned int*)(ATM_SAR_BASE+0x0000029c)) /* Rx Free buffer list size 1 */
4397 +#define AVSAR_RXFBLSIZE_2   (*(volatile unsigned int*)(ATM_SAR_BASE+0x000002ac)) /* Rx Free buffer list size 2 */
4398 +#define AVSAR_RXFBLSIZE_3   (*(volatile unsigned int*)(ATM_SAR_BASE+0x000002bc)) /* Rx Free buffer list size 3 */
4399 +
4400 +
4401 +#if defined(CONFIG_MIPS_EVM3D) || defined(CONFIG_MIPS_AR5D01) || defined(CONFIG_MIPS_AR5W01)
4402 +
4403 +#define AVSAR_SAR_FREQUENCY (*(volatile unsigned int*)(ATM_SAR_BASE+0x00010480))
4404 +#define AVSAR_OAM_CC_SINK   (*(volatile unsigned int*)(ATM_SAR_BASE+0x00010484))
4405 +#define AVSAR_OAM_AIS_RDI_RX (*(volatile unsigned int*)(ATM_SAR_BASE+0x00010488))
4406 +#define AVSAR_OAM_CPID0      (*(volatile unsigned int*)(ATM_SAR_BASE+0x000104E0))
4407 +#define AVSAR_OAM_LLID0      (*(volatile unsigned int*)(ATM_SAR_BASE+0x000104F0))
4408 +#define AVSAR_OAM_CPID1      (*(volatile unsigned int*)(ATM_SAR_BASE+0x000104E4))
4409 +#define AVSAR_OAM_LLID1      (*(volatile unsigned int*)(ATM_SAR_BASE+0x000104F4))
4410 +#define AVSAR_OAM_CPID2      (*(volatile unsigned int*)(ATM_SAR_BASE+0x000104E8))
4411 +#define AVSAR_OAM_LLID2      (*(volatile unsigned int*)(ATM_SAR_BASE+0x000104F8))
4412 +#define AVSAR_OAM_CPID3      (*(volatile unsigned int*)(ATM_SAR_BASE+0x000104EC))
4413 +#define AVSAR_OAM_LLID3      (*(volatile unsigned int*)(ATM_SAR_BASE+0x000104FC))
4414 +#define AVSAR_OAM_CORR_TAG      (*(volatile unsigned int*)(ATM_SAR_BASE+0x00010500))
4415 +#define AVSAR_OAM_FAR_COUNT      (*(volatile unsigned int*)(ATM_SAR_BASE+0x00010520))
4416 +#define AVSAR_OAM_NEAR_COUNT      (*(volatile unsigned int*)(ATM_SAR_BASE+0x00010540))
4417 +#define AVSAR_OAM_CONFIG_REG      (*(volatile unsigned int*)(ATM_SAR_BASE+0x00000018))
4418 +#define AVSAR_FAIRNESS_REG   (*(volatile unsigned int*)(ATM_SAR_BASE+0x000104B8))
4419 +#define AVSAR_UBR_PCR_REG   (*(volatile unsigned int*)(ATM_SAR_BASE+0x00010490))
4420 +
4421 +
4422 +/*
4423 +
4424 +#define OAM_CPID_ADD  0xa30104e0
4425 +
4426 +#define OAM_LLID_ADD  0xa30104f0
4427 +
4428 +#define OAM_LLID_VAL  0xffffffff
4429 +
4430 +#define OAM_CORR_TAG  0xa3010500
4431 +
4432 +#define OAM_FAR_COUNT_ADD 0xa3010520
4433 +
4434 +#define OAM_NEAR_COUNT_ADD 0xa3010540
4435 +
4436 +#define OAM_CONFIG_REG_ADD 0xa3000018
4437 +*/
4438 +
4439 +
4440 +#else /* CONFIG_MIPS_EVM3 || CONFIG_MIPS_ACPEP */
4441 +
4442 +#define AVSAR_SAR_FREQUENCY (*(volatile unsigned int*)(ATM_SAR_BASE+0x00012000))
4443 +#define AVSAR_OAM_CC_SINK   (*(volatile unsigned int*)(ATM_SAR_BASE+0x00012004))
4444 +#define AVSAR_OAM_AIS_RDI_RX (*(volatile unsigned int*)(ATM_SAR_BASE+0x00012008))
4445 +#define AVSAR_OAM_CPID      (*(volatile unsigned int*)(ATM_SAR_BASE+0x00012300))
4446 +
4447 +#endif /* CONFIG_MIPS_EVM3D || CONFIG_MIPS_AR5D01 || CONFIG_MIPS_AR5W01 */
4448 +
4449 +
4450 +#define AVSAR_STATE_RAM     (ATM_SAR_BASE + 0x010000) /* SAR state RAM */
4451 +#define AVSAR_PDSP_BASE     (ATM_SAR_BASE + 0x020000) /* SAR PDSP base address   */
4452 +#define AVSAR_TXDMA_BASE    (ATM_SAR_BASE + 0x030000) /* Transmit DMA state base */
4453 +#define AVSAR_TDMASTATE6    0x18                      /* Transmit DMA state word 6 */
4454 +#define AVSAR_RXDMA_BASE    (ATM_SAR_BASE + 0x040000) /* Receive  DMA state base */
4455 +#define AVSAR_RDMASTATE0    0x0                       /* Receive  DMA state word 0 */
4456 +
4457 +/*------------------------------------------*/
4458 +/* DSL Interface                            */
4459 +/*------------------------------------------*/
4460 +
4461 +#define AVDSL_TX_EN          (*(volatile unsigned int *)(DSL_IF_BASE + 0x00000000))
4462 +#define AVDSL_RX_EN          (*(volatile unsigned int *)(DSL_IF_BASE + 0x00000004))
4463 +#define AVDSL_POLL           (*(volatile unsigned int *)(DSL_IF_BASE + 0x00000008))
4464 +
4465 +/* Fast */
4466 +
4467 +#define AVDSL_TX_FIFO_ADDR0  (*(volatile unsigned int *)(DSL_IF_BASE + 0x0000000C))
4468 +#define AVDSL_TX_FIFO_BASE0  (*(volatile unsigned int *)(DSL_IF_BASE + 0x00000010))
4469 +#define AVDSL_TX_FIFO_LEN0   (*(volatile unsigned int *)(DSL_IF_BASE + 0x00000014))
4470 +#define AVDSL_TX_FIFO_PR0    (*(volatile unsigned int *)(DSL_IF_BASE + 0x00000018))
4471 +#define AVDSL_RX_FIFO_ADDR0  (*(volatile unsigned int *)(DSL_IF_BASE + 0x0000001C))
4472 +#define AVDSL_RX_FIFO_BASE0  (*(volatile unsigned int *)(DSL_IF_BASE + 0x00000020))
4473 +#define AVDSL_RX_FIFO_LEN0   (*(volatile unsigned int *)(DSL_IF_BASE + 0x00000024))
4474 +#define AVDSL_RX_FIFO_PR0    (*(volatile unsigned int *)(DSL_IF_BASE + 0x00000028))
4475 +
4476 +/* Interleaved */
4477 +
4478 +#define AVDSL_TX_FIFO_ADDR1  (*(volatile unsigned int *)(DSL_IF_BASE + 0x0000002C))
4479 +#define AVDSL_TX_FIFO_BASE1  (*(volatile unsigned int *)(DSL_IF_BASE + 0x00000030))
4480 +#define AVDSL_TX_FIFO_LEN1   (*(volatile unsigned int *)(DSL_IF_BASE + 0x00000034))
4481 +#define AVDSL_TX_FIFO_PR1    (*(volatile unsigned int *)(DSL_IF_BASE + 0x00000038))
4482 +#define AVDSL_RX_FIFO_ADDR1  (*(volatile unsigned int *)(DSL_IF_BASE + 0x0000003C))
4483 +#define AVDSL_RX_FIFO_BASE1  (*(volatile unsigned int *)(DSL_IF_BASE + 0x00000040))
4484 +#define AVDSL_RX_FIFO_LEN1   (*(volatile unsigned int *)(DSL_IF_BASE + 0x00000044))
4485 +#define AVDSL_RX_FIFO_PR1    (*(volatile unsigned int *)(DSL_IF_BASE + 0x00000048))
4486 +
4487 +/*------------------------------------------*/
4488 +/* Broadband I/F                            */
4489 +/*------------------------------------------*/
4490 +
4491 +#define AVBBIF_BBIF_CNTRL    (*(volatile unsigned int *)(BBIF_CONTROL + 0x00000000))
4492 +#define AVBBIF_ADDR_TRANS_0  (*(volatile unsigned int *)(BBIF_CONTROL + 0x00000004))
4493 +#define AVBBIF_ADDR_TRANS_1  (*(volatile unsigned int *)(BBIF_CONTROL + 0x00000008))
4494 +#define AVBBIF_ADDR_XB_MX_BL (*(volatile unsigned int *)(BBIF_CONTROL + 0x0000000C))
4495 +#define AVBBIF_INFIFO_LVL    (*(volatile unsigned int *)(BBIF_CONTROL + 0x00000010))
4496 +#define AVBBIF_OUTFIFO_LVL   (*(volatile unsigned int *)(BBIF_CONTROL + 0x00000014))
4497 +
4498 +#define AVBBIF_DISABLED    0x0
4499 +#define AVBBIF_LBT4040_INT 0x1
4500 +#define AVBBIF_XBUS        0x2
4501 +#define AVBBIF_LBT4040_EXT 0x4
4502 +
4503 +#define AVBBIF_ADDR_MASK0   0xff000000 /* handles upper bits of BBIF 0 address */
4504 +#define AVBBIF_ADDR_MASK1   0xff800000 /* handles upper bits of BBIF 1 address */
4505 +#define AVBBIF_TRANS_MASK   0xff000000
4506 +/*------------------------------------------*/
4507 +/* GPIO I/F                                 */
4508 +/*------------------------------------------*/
4509 +
4510 +#define GPIO_DATA_INPUT      (*(volatile unsigned int *)(GPIO_BASE + 0x00000000))
4511 +#define GPIO_DATA_OUTPUT     (*(volatile unsigned int *)(GPIO_BASE + 0x00000004))
4512 +#define GPIO_DATA_DIR        (*(volatile unsigned int *)(GPIO_BASE + 0x00000008)) /* 0=output 1=input  */
4513 +#define GPIO_DATA_ENABLE     (*(volatile unsigned int *)(GPIO_BASE + 0x0000000C)) /* 0=GPIO Mux 1=GPIO */
4514 +
4515 +#define GPIO_0 (1<<21)
4516 +#define GPIO_1 (1<<22)
4517 +#define GPIO_2 (1<<23)
4518 +#define GPIO_3 (1<<24)
4519 +#define EINT_1 (1<<18)
4520 +
4521 +/*
4522 +  JAH NOTE JAH NOTE JAH NOTE JAH NOTE JAH NOTE JAH NOTE JAH NOTE JAH NOTE
4523 +       If you reset the GPIO interface all of the directions (i/o) of the UART B
4524 +       interface pins are inputs and must be reconfigured so as not to lose the
4525 +       serial console interface
4526 +  JAH NOTE JAH NOTE JAH NOTE JAH NOTE JAH NOTE JAH NOTE JAH NOTE JAH NOTE
4527 +*/
4528 +
4529 +/*------------------------------------------*/
4530 +/* CLK_CTRL                                 */
4531 +/*------------------------------------------*/
4532 +#define PERIPH_CLK_CTL       (*(volatile unsigned int *)(CLK_CTRL_BASE + 0x00000004))
4533 +
4534 +#define PCLK_0_HALF_VBUS     (0<<16)
4535 +#define PCLK_EQ_INPUT        (1<<16)
4536 +#define BBIF_CLK_HALF_VBUS   (0<<17)
4537 +#define BBIF_CLK_EQ_VBUS     (1<<17)
4538 +#define BBIF_CLK_EQ_BBCLK    (3<<17)
4539 +#define DSP_MODCLK_DSPCLKI   (0<<20)
4540 +#define DSP_MODCLK_REFCLKI   (1<<20)
4541 +#define USB_CLK_EQ_USBCLKI   (0<<21)
4542 +#define USB_CLK_EQ_REFCLKI   (1<<21)
4543 +
4544 +/*------------------------------------------*/
4545 +/* PCI Control Registers                    */
4546 +/*------------------------------------------*/
4547 +#define        PCIC_CONTROL            (*(volatile unsigned int *)(PCI_CONFIG_BASE))
4548 +#define                PCIC_CONTROL_CFG_DONE                           (1<<0)
4549 +#define                PCIC_CONTROL_DIS_SLAVE_TO                       (1<<1)
4550 +#define                PCIC_CONTROL_FORCE_DELAY_READ           (1<<2)
4551 +#define                PCIC_CONTROL_FORCE_DELAY_READ_LINE      (1<<3)
4552 +#define                PCIC_CONTROL_FORCE_DELAY_READ_MULT      (1<<4)
4553 +#define                PCIC_CONTROL_MEM_SPACE_EN                       (1<<5)
4554 +#define                PCIC_CONTROL_MEM_MASK                           (1<<6)
4555 +#define                PCIC_CONTROL_IO_SPACE_EN                        (1<<7)
4556 +#define                PCIC_CONTROL_IO_MASK                            (1<<8)
4557 +/*                     PCIC_CONTROL_RESERVED                           (1<<9)  */
4558 +#define                PCIC_CONTROL_BASE0_EN                           (1<<10)
4559 +#define                PCIC_CONTROL_BASE1_EN                           (1<<11)
4560 +#define                PCIC_CONTROL_BASE2_EN                           (1<<12)
4561 +#define                PCIC_CONTROL_HOLD_MASTER_WRITE          (1<<13)
4562 +#define                PCIC_CONTROL_ARBITER_EN                         (1<<14)
4563 +#define        PCIC_INT_SOURCE         (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x00000004))
4564 +#define                PCIC_INT_SOURCE_PWR_MGMT                        (1<<0)
4565 +#define                PCIC_INT_SOURCE_PCI_TARGET                      (1<<1)
4566 +#define                PCIC_INT_SOURCE_PCI_MASTER                      (1<<2)
4567 +#define                PCIC_INT_SOURCE_POWER_WAKEUP            (1<<3)
4568 +#define                PCIC_INT_SOURCE_PMEIN                           (1<<4)
4569 +/*                     PCIC_INT_SOURCE_RESERVED                        (1<<5) */
4570 +/*                     PCIC_INT_SOURCE_RESERVED                        (1<<6) */
4571 +#define                PCIC_INT_SOURCE_PIC_INTA                        (1<<7)
4572 +#define                PCIC_INT_SOURCE_PIC_INTB                        (1<<8)
4573 +#define                PCIC_INT_SOURCE_PIC_INTC                        (1<<9)
4574 +#define                PCIC_INT_SOURCE_PIC_INTD                        (1<<10)
4575 +#define                PCIC_INT_SOURCE_SOFT_INT0                       (1<<11)
4576 +#define                PCIC_INT_SOURCE_SOFT_INT1                       (1<<12)
4577 +#define                PCIC_INT_SOURCE_SOFT_INT2                       (1<<13)
4578 +#define                PCIC_INT_SOURCE_SOFT_INT3                       (1<<14)
4579 +#define        PCIC_INT_CLEAR          (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x00000008))
4580 +#define                PCIC_INT_CLEAR_PM                                       (1<<0)
4581 +#define                PCIC_INT_CLEAR_PCI_TARGET                       (1<<1)
4582 +#define                PCIC_INT_CLEAR_PCI_MASTER                       (1<<2)
4583 +/*                     PCIC_INT_CLEAR_RESERVED                         (1<<3)  */
4584 +#define                PCIC_INT_CLEAR_PMEIN                            (1<<4)
4585 +/*                     PCIC_INT_CLEAR_RESERVED                         (1<<5)  */
4586 +/*                     PCIC_INT_CLEAR_RESERVED                         (1<<6)  */
4587 +#define                PCIC_INT_CLEAR_PCI_INTA                         (1<<7)
4588 +#define                PCIC_INT_CLEAR_PCI_INTB                         (1<<8)
4589 +#define                PCIC_INT_CLEAR_PCI_INTC                         (1<<9)
4590 +#define                PCIC_INT_CLEAR_PCI_INTD                         (1<<10)
4591 +#define                PCIC_INT_CLEAR_SOFT_INT0                        (1<<11)
4592 +#define                PCIC_INT_CLEAR_SOFT_INT1                        (1<<12)
4593 +#define                PCIC_INT_CLEAR_SOFT_INT2                        (1<<13)
4594 +#define                PCIC_INT_CLEAR_SOFT_INT3                        (1<<14)
4595 +#define        PCIC_INT_EN_AVAL        (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x0000000c))
4596 +#define                PCIC_INT_EN_AVAL_PM                                     (1<<0)
4597 +#define                PCIC_INT_EN_AVAL_PCI_TARGET                     (1<<1)
4598 +#define                PCIC_INT_EN_AVAL_PCI_MASTER                     (1<<2)
4599 +/*                     PCIC_INT_EN_AVAL_RESERVED                       (1<<3)  */
4600 +#define                PCIC_INT_EN_AVAL_PMEIN                          (1<<4)
4601 +/*                     PCIC_INT_EN_AVAL_RESERVED                       (1<<5)  */
4602 +/*                     PCIC_INT_EN_AVAL_RESERVED                       (1<<6)  */
4603 +#define                PCIC_INT_EN_AVAL_PCI_INTA                       (1<<7)
4604 +#define                PCIC_INT_EN_AVAL_PCI_INTB                       (1<<8)
4605 +#define                PCIC_INT_EN_AVAL_PCI_INTC                       (1<<9)
4606 +#define                PCIC_INT_EN_AVAL_PCI_INTD                       (1<<10)
4607 +#define                PCIC_INT_EN_AVAL_SOFT_INT0                      (1<<11)
4608 +#define                PCIC_INT_EN_AVAL_SOFT_INT1                      (1<<12)
4609 +#define                PCIC_INT_EN_AVAL_SOFT_INT2                      (1<<13)
4610 +#define                PCIC_INT_EN_AVAL_SOFT_INT3                      (1<<14)
4611 +#define        PCIC_INT_EN_PCI                 (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x00000010))
4612 +#define                PCIC_INT_EN_PCI_PM                                      (1<<0)
4613 +#define                PCIC_INT_EN_PCI_PCI_TARGET                      (1<<1)
4614 +#define                PCIC_INT_EN_PCI_PCI_MASTER                      (1<<2)
4615 +/*                     PCIC_INT_EN_PCI_RESERVED                        (1<<3)  */
4616 +#define                PCIC_INT_EN_PCI_PMEIN                           (1<<4)
4617 +/*                     PCIC_INT_EN_PCI_RESERVED                        (1<<5)  */
4618 +/*                     PCIC_INT_EN_PCI_RESERVED                        (1<<6)  */
4619 +#define                PCIC_INT_EN_PCI_PCI_INTA                        (1<<7)
4620 +#define                PCIC_INT_EN_PCI_PCI_INTB                        (1<<8)
4621 +#define                PCIC_INT_EN_PCI_PCI_INTC                        (1<<9)
4622 +#define                PCIC_INT_EN_PCI_PCI_INTD                        (1<<10)
4623 +#define                PCIC_INT_EN_PCI_SOFT_INT0                       (1<<11)
4624 +#define                PCIC_INT_EN_PCI_SOFT_INT1                       (1<<12)
4625 +#define                PCIC_INT_EN_PCI_SOFT_INT2                       (1<<13)
4626 +#define                PCIC_INT_EN_PCI_SOFT_INT3                       (1<<14)
4627 +#define        PCIC_INT_SWSET          (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x00000014))
4628 +#define                PCIC_INT_SWSET_SOFT_INT0                        (1<<0)
4629 +#define                PCIC_INT_SWSET_SOFT_INT1                        (1<<1)
4630 +#define                PCIC_INT_SWSET_SOFT_INT2                        (1<<2)
4631 +#define                PCIC_INT_SWSET_SOFT_INT3                        (1<<3)
4632 +#define        PCIC_PM_CTL                     (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x00000018))
4633 +#define                PCIC_PM_CTL_PWR_STATE_MASK                      (0x02)
4634 +/*                     PCIC_PM_CTL_RESERVED                            (1<<2) */
4635 +/*                     PCIC_PM_CTL_RESERVED                            (1<<3) */
4636 +/*                     PCIC_PM_CTL_RESERVED                            (1<<4) */
4637 +/*                     PCIC_PM_CTL_RESERVED                            (1<<5) */
4638 +/*                     PCIC_PM_CTL_RESERVED                            (1<<6) */
4639 +/*                     PCIC_PM_CTL_RESERVED                            (1<<7) */
4640 +/*                     PCIC_PM_CTL_RESERVED                            (1<<8) */
4641 +/*                     PCIC_PM_CTL_RESERVED                            (1<<9) */
4642 +#define                PCIC_PM_CTL_PWR_SUPPORT                         (1<<10)
4643 +#define                PCIC_PM_CTL_PMEIN                                       (1<<11)
4644 +#define                PCIC_PM_CTL_CAP_MASK    (*(volatile unsigned short int *)(PCI_CONFIG_BASE + 0x0000001a))
4645 +#define        PCIC_PM_CONSUME         (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x0000001c))
4646 +#define                PCIC_PM_CONSUME_D0              (*(volatile unsigned char *)(PCI_CONFIG_BASE + 0x0000001c))
4647 +#define                PCIC_PM_CONSUME_D1              (*(volatile unsigned char *)(PCI_CONFIG_BASE + 0x0000001d))
4648 +#define                PCIC_PM_CONSUME_D2              (*(volatile unsigned char *)(PCI_CONFIG_BASE + 0x0000001e))
4649 +#define                PCIC_PM_CONSUME_D3              (*(volatile unsigned char *)(PCI_CONFIG_BASE + 0x0000001f))
4650 +#define        PCIC_PM_DISSAPATED      (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x00000020))
4651 +#define                PCIC_PM_DISSAPATED_D0   (*(volatile unsigned char *)(PCI_CONFIG_BASE + 0x00000020))
4652 +#define                PCIC_PM_DISSAPATED_D1   (*(volatile unsigned char *)(PCI_CONFIG_BASE + 0x00000021))
4653 +#define                PCIC_PM_DISSAPATED_D2   (*(volatile unsigned char *)(PCI_CONFIG_BASE + 0x00000022))
4654 +#define                PCIC_PM_DISSAPATED_D3   (*(volatile unsigned char *)(PCI_CONFIG_BASE + 0x00000023))
4655 +#define        PCIC_PM_DATA_SCALE      (*(volatile unsigned short int *)(PCI_CONFIG_BASE + 0x00000024))
4656 +#define        PCIC_VEND_DEV_ID        (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x00000028))
4657 +#define        PCIC_SUB_VEND_DEV_ID    (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x0000002c))
4658 +#define        PCIC_CLASS_REV_ID       (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x00000030))
4659 +#define        PCIC_MAX_MIN            (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x00000034))
4660 +#define        PCIC_MAST_MEM_AT0       (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x0000003c))
4661 +#define        PCIC_MAST_MEM_AT1       (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x00000040))
4662 +#define        PCIC_MAST_MEM_AT2       (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x00000044))
4663 +#define        PCIC_SLAVE_MASK0        (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x0000004c))
4664 +#define        PCIC_SLAVE_MASK1        (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x00000050))
4665 +#define        PCIC_SLAVE_MASK2        (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x00000054))
4666 +#define        PCIC_SLAVE_BASE_AT0     (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x00000058))
4667 +#define        PCIC_SLAVE_BASE_AT1     (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x0000005c))
4668 +#define        PCIC_SLAVE_BASE_AT2     (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x00000060))
4669 +#define        PCIC_CONF_COMMAND       (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x00000090))
4670 +#define        PCIC_CONF_ADDR          (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x00000094))
4671 +#define        PCIC_CONF_DATA          (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x00000098))
4672 +
4673 +/*------------------------------------------*/
4674 +/* IIC_INTERFACE                            */
4675 +/*------------------------------------------*/
4676 +#define I2C_DATA_HI          (*(volatile unsigned int *)(I2C_BASE + 0x0))
4677 +#define I2C_DATA_LOW         (*(volatile unsigned int *)(I2C_BASE + 0x4))
4678 +#define I2C_CONFIG           (*(volatile unsigned int *)(I2C_BASE + 0x8))
4679 +#define I2C_DATA_READ        (*(volatile unsigned int *)(I2C_BASE + 0xC))
4680 +#define I2C_CLOCK_DIV        (*(volatile unsigned int *)(I2C_BASE + 0x10))
4681 +
4682 +#define I2CWRITE      0x200
4683 +#define I2CREAD       0x300
4684 +#define I2C_END_BURST 0x400
4685 +
4686 +/* read bits */
4687 +#define I2C_READ_ERROR    0x8000
4688 +#define I2C_READ_COMPLETE 0x4000
4689 +#define I2C_READ_BUSY     0x2000
4690 +
4691 +/* device types */
4692 +#define I2C_IO_EXPANDER      0x2
4693 +#define I2C_RTC              0xd
4694 +
4695 +/* device Addresses on I2C bus (EVM3) */
4696 +#define SEVEN_SEGMENT_DISP    0x23   /* Device type = 0x2, Addr = 3 */
4697 +#define EVM3_RTC              0xd0   /* Device type = 0xd, Addr = 0 */
4698 +#define EVM3_RTC_I2C_ADDR      0x0
4699 +
4700 +/*------------------------------------------*/
4701 +/* Ethernet MAC register offset definitions */
4702 +/*------------------------------------------*/
4703 +#define VMAC_DMACONFIG(X)      (*(volatile unsigned int *)(X + 0x00000000))
4704 +#define VMAC_INTSTS(X)         (*(volatile unsigned int *)(X + 0x00000004))
4705 +#define VMAC_INTMASK(X)        (*(volatile unsigned int *)(X + 0x00000008))
4706 +
4707 +#define VMAC_WRAPCLK(X)        (*(volatile unsigned int *)(X + 0x00000340))
4708 +#define VMAC_STATSBASE(X)      (*(volatile unsigned int *)(X + 0x00000400))
4709 +
4710 +#define VMAC_TCRPTR(X)         (*(volatile unsigned int *)(X + 0x00000100))
4711 +#define VMAC_TCRSIZE(X)        (*(volatile unsigned int *)(X + 0x00000104))
4712 +#define VMAC_TCRINTTHRESH(X)   (*(volatile unsigned int *)(X + 0x00000108))
4713 +#define VMAC_TCRTOTENT(X)      (*(volatile unsigned int *)(X + 0x0000010C))
4714 +#define VMAC_TCRFREEENT(X)     (*(volatile unsigned int *)(X + 0x00000110))
4715 +#define VMAC_TCRPENDENT(X)     (*(volatile unsigned int *)(X + 0x00000114))
4716 +#define VMAC_TCRENTINC(X)      (*(volatile unsigned int *)(X + 0x00000118))
4717 +#define VMAC_TXISRPACE(X)      (*(volatile unsigned int *)(X + 0x0000011c))
4718 +
4719 +
4720 +#define VMAC_TDMASTATE0(X)     (*(volatile unsigned int *)(X + 0x00000120))
4721 +#define VMAC_TDMASTATE1(X)     (*(volatile unsigned int *)(X + 0x00000124))
4722 +#define VMAC_TDMASTATE2(X)     (*(volatile unsigned int *)(X + 0x00000128))
4723 +#define VMAC_TDMASTATE3(X)     (*(volatile unsigned int *)(X + 0x0000012C))
4724 +#define VMAC_TDMASTATE4(X)     (*(volatile unsigned int *)(X + 0x00000130))
4725 +#define VMAC_TDMASTATE5(X)     (*(volatile unsigned int *)(X + 0x00000134))
4726 +#define VMAC_TDMASTATE6(X)     (*(volatile unsigned int *)(X + 0x00000138))
4727 +#define VMAC_TDMASTATE7(X)     (*(volatile unsigned int *)(X + 0x0000013C))
4728 +#define VMAC_TXPADDCNT(X)      (*(volatile unsigned int *)(X + 0x00000140))
4729 +#define VMAC_TXPADDSTART(X)    (*(volatile unsigned int *)(X + 0x00000144))
4730 +#define VMAC_TXPADDEND(X)      (*(volatile unsigned int *)(X + 0x00000148))
4731 +#define VMAC_TXQFLUSH(X)       (*(volatile unsigned int *)(X + 0x0000014C))
4732 +
4733 +#define VMAC_RCRPTR(X)         (*(volatile unsigned int *)(X + 0x00000200))
4734 +#define VMAC_RCRSIZE(X)        (*(volatile unsigned int *)(X + 0x00000204))
4735 +#define VMAC_RCRINTTHRESH(X)   (*(volatile unsigned int *)(X + 0x00000208))
4736 +#define VMAC_RCRTOTENT(X)      (*(volatile unsigned int *)(X + 0x0000020C))
4737 +#define VMAC_RCRFREEENT(X)     (*(volatile unsigned int *)(X + 0x00000210))
4738 +#define VMAC_RCRPENDENT(X)     (*(volatile unsigned int *)(X + 0x00000214))
4739 +#define VMAC_RCRENTINC(X)      (*(volatile unsigned int *)(X + 0x00000218))
4740 +#define VMAC_RXISRPACE(X)      (*(volatile unsigned int *)(X + 0x0000021c))
4741 +
4742 +#define VMAC_RDMASTATE0(X)     (*(volatile unsigned int *)(X + 0x00000220))
4743 +#define VMAC_RDMASTATE1(X)     (*(volatile unsigned int *)(X + 0x00000224))
4744 +#define VMAC_RDMASTATE2(X)     (*(volatile unsigned int *)(X + 0x00000228))
4745 +#define VMAC_RDMASTATE3(X)     (*(volatile unsigned int *)(X + 0x0000022C))
4746 +#define VMAC_RDMASTATE4(X)     (*(volatile unsigned int *)(X + 0x00000230))
4747 +#define VMAC_RDMASTATE5(X)     (*(volatile unsigned int *)(X + 0x00000234))
4748 +#define VMAC_RDMASTATE6(X)     (*(volatile unsigned int *)(X + 0x00000238))
4749 +#define VMAC_RDMASTATE7(X)     (*(volatile unsigned int *)(X + 0x0000023C))
4750 +#define VMAC_FBLADDCNT(X)      (*(volatile unsigned int *)(X + 0x00000240))
4751 +#define VMAC_FBLADDSTART(X)    (*(volatile unsigned int *)(X + 0x00000244))
4752 +#define VMAC_FBLADDEND(X)      (*(volatile unsigned int *)(X + 0x00000248))
4753 +#define VMAC_RXONOFF(X)        (*(volatile unsigned int *)(X + 0x0000024C))
4754 +
4755 +#define VMAC_FBL0NEXTD(X)      (*(volatile unsigned int *)(X + 0x00000280))
4756 +#define VMAC_FBL0LASTD(X)      (*(volatile unsigned int *)(X + 0x00000284))
4757 +#define VMAC_FBL0COUNTD(X)     (*(volatile unsigned int *)(X + 0x00000288))
4758 +#define VMAC_FBL0BUFSIZE(X)    (*(volatile unsigned int *)(X + 0x0000028C))
4759 +
4760 +#define VMAC_MACCONTROL(X)     (*(volatile unsigned int *)(X + 0x00000300))
4761 +#define VMAC_MACSTATUS(X)      (*(volatile unsigned int *)(X + 0x00000304))
4762 +#define VMAC_MACADDRHI(X)      (*(volatile unsigned int *)(X + 0x00000308))
4763 +#define VMAC_MACADDRLO(X)      (*(volatile unsigned int *)(X + 0x0000030C))
4764 +#define VMAC_MACHASH1(X)       (*(volatile unsigned int *)(X + 0x00000310))
4765 +#define VMAC_MACHASH2(X)       (*(volatile unsigned int *)(X + 0x00000314))
4766 +
4767 +#define VMAC_WRAPCLK(X)        (*(volatile unsigned int *)(X + 0x00000340))
4768 +#define VMAC_BOFTEST(X)        (*(volatile unsigned int *)(X + 0x00000344))
4769 +#define VMAC_PACTEST(X)        (*(volatile unsigned int *)(X + 0x00000348))
4770 +#define VMAC_PAUSEOP(X)        (*(volatile unsigned int *)(X + 0x0000034C))
4771 +
4772 +#define VMAC_MDIOCONTROL(X)    (*(volatile unsigned int *)(X + 0x00000380))
4773 +#define VMAC_MDIOUSERACCESS(X) (*(volatile unsigned int *)(X +0x00000384))
4774 +#define VMAC_MDIOACK(X)        (*(volatile unsigned int *)(X + 0x00000388))
4775 +#define VMAC_MDIOLINK(X)       (*(volatile unsigned int *)(X + 0x0000038C))
4776 +#define VMAC_MDIOMACPHY(X)     (*(volatile unsigned int *)(X + 0x00000390))
4777 +
4778 +#define VMAC_STATS_BASE(X)     (X + 0x00000400)
4779 +
4780 +#endif __AVALANCHE_REGS_H
4781 +
4782 +
4783 +
4784 +
4785 +
4786 +
4787 diff -urN linux.old/include/asm-mips/ar7/if_port.h linux.dev/include/asm-mips/ar7/if_port.h
4788 --- linux.old/include/asm-mips/ar7/if_port.h    1970-01-01 01:00:00.000000000 +0100
4789 +++ linux.dev/include/asm-mips/ar7/if_port.h    2005-07-26 18:11:02.647500000 +0200
4790 @@ -0,0 +1,26 @@
4791 +/*******************************************************************************
4792 + * FILE PURPOSE:    Interface port id Header file
4793 + *******************************************************************************
4794 + * FILE NAME:       if_port.h
4795 + *
4796 + * DESCRIPTION:     Header file carrying information about port ids of interfaces
4797 + *
4798 + *
4799 + * (C) Copyright 2003, Texas Instruments, Inc
4800 + ******************************************************************************/
4801 +#ifndef _IF_PORT_H_
4802 +#define _IF_PORT_H_
4803 +
4804 +#define AVALANCHE_CPMAC_LOW_PORT_ID         0
4805 +#define AVALANCHE_CPMAC_HIGH_PORT_ID        1
4806 +#define AVALANCHE_USB_PORT_ID               2
4807 +#define AVALANCHE_WLAN_PORT_ID              3
4808 +
4809 +
4810 +#define AVALANCHE_MARVELL_BASE_PORT_ID      4
4811 +
4812 +/* The marvell ports occupy port ids from  4 to 8 */
4813 +/* so the next port id number should start at 9   */
4814 +
4815 +
4816 +#endif /* _IF_PORT_H_ */
4817 diff -urN linux.old/include/asm-mips/ar7/sangam.h linux.dev/include/asm-mips/ar7/sangam.h
4818 --- linux.old/include/asm-mips/ar7/sangam.h     1970-01-01 01:00:00.000000000 +0100
4819 +++ linux.dev/include/asm-mips/ar7/sangam.h     2005-07-26 18:11:02.648500000 +0200
4820 @@ -0,0 +1,180 @@
4821 +#ifndef _SANGAM_H_
4822 +#define _SANGAM_H_
4823 +
4824 +#include <linux/config.h>
4825 +#include <asm/addrspace.h>
4826 +
4827 +/*----------------------------------------------------
4828 + * Sangam's Module Base Addresses
4829 + *--------------------------------------------------*/
4830 +#define AVALANCHE_ADSL_SUB_SYS_MEM_BASE       (KSEG1ADDR(0x01000000)) /* AVALANCHE ADSL Mem Base */
4831 +#define AVALANCHE_BROADBAND_INTERFACE__BASE   (KSEG1ADDR(0x02000000)) /* AVALANCHE BBIF */
4832 +#define AVALANCHE_ATM_SAR_BASE                (KSEG1ADDR(0x03000000)) /* AVALANCHE ATM SAR */
4833 +#define AVALANCHE_USB_SLAVE_BASE              (KSEG1ADDR(0x03400000)) /* AVALANCHE USB SLAVE */
4834 +#define AVALANCHE_LOW_VLYNQ_MEM_MAP_BASE      (KSEG1ADDR(0x04000000)) /* AVALANCHE VLYNQ 0 Mem map */
4835 +#define AVALANCHE_LOW_CPMAC_BASE              (KSEG1ADDR(0x08610000)) /* AVALANCHE CPMAC 0 */
4836 +#define AVALANCHE_EMIF_CONTROL_BASE           (KSEG1ADDR(0x08610800)) /* AVALANCHE EMIF */
4837 +#define AVALANCHE_GPIO_BASE                   (KSEG1ADDR(0x08610900)) /* AVALANCHE GPIO */
4838 +#define AVALANCHE_CLOCK_CONTROL_BASE          (KSEG1ADDR(0x08610A00)) /* AVALANCHE Clock Control */
4839 +#define AVALANCHE_WATCHDOG_TIMER_BASE         (KSEG1ADDR(0x08610B00)) /* AVALANCHE Watch Dog Timer */
4840 +#define AVALANCHE_TIMER0_BASE                 (KSEG1ADDR(0x08610C00)) /* AVALANCHE Timer 1 */
4841 +#define AVALANCHE_TIMER1_BASE                 (KSEG1ADDR(0x08610D00)) /* AVALANCHE Timer 2 */
4842 +#define AVALANCHE_UART0_REGS_BASE             (KSEG1ADDR(0x08610E00)) /* AVALANCHE UART 0 */
4843 +#define AVALANCHE_UART1_REGS_BASE             (KSEG1ADDR(0x08610F00)) /* AVALANCHE UART 0 */
4844 +#define AVALANCHE_I2C_BASE                    (KSEG1ADDR(0x08611000)) /* AVALANCHE I2C */
4845 +#define AVALANCHE_USB_SLAVE_CONTROL_BASE      (KSEG1ADDR(0x08611200)) /* AVALANCHE USB DMA */
4846 +#define AVALANCHE_MCDMA0_CTRL_BASE            (KSEG1ADDR(0x08611400)) /* AVALANCHE MC DMA 0 (channels 0-3) */
4847 +#define AVALANCHE_RESET_CONTROL_BASE          (KSEG1ADDR(0x08611600)) /* AVALANCHE Reset Control */
4848 +#define AVALANCHE_BIST_CONTROL_BASE           (KSEG1ADDR(0x08611700)) /* AVALANCHE BIST Control */
4849 +#define AVALANCHE_LOW_VLYNQ_CONTROL_BASE      (KSEG1ADDR(0x08611800)) /* AVALANCHE VLYNQ0 Control */
4850 +#define AVALANCHE_DEVICE_CONFIG_LATCH_BASE    (KSEG1ADDR(0x08611A00)) /* AVALANCHE Device Config Latch */
4851 +#define AVALANCHE_HIGH_VLYNQ_CONTROL_BASE     (KSEG1ADDR(0x08611C00)) /* AVALANCHE VLYNQ1 Control */
4852 +#define AVALANCHE_MDIO_BASE                   (KSEG1ADDR(0x08611E00)) /* AVALANCHE MDIO    */
4853 +#define AVALANCHE_FSER_BASE                   (KSEG1ADDR(0x08612000)) /* AVALANCHE FSER base */
4854 +#define AVALANCHE_INTC_BASE                   (KSEG1ADDR(0x08612400)) /* AVALANCHE INTC  */
4855 +#define AVALANCHE_HIGH_CPMAC_BASE             (KSEG1ADDR(0x08612800)) /* AVALANCHE CPMAC 1 */
4856 +#define AVALANCHE_HIGH_VLYNQ_MEM_MAP_BASE     (KSEG1ADDR(0x0C000000)) /* AVALANCHE VLYNQ 1 Mem map */
4857 +
4858 +#define AVALANCHE_SDRAM_BASE                  0x14000000UL
4859 +
4860 +
4861 +/*----------------------------------------------------
4862 + * Sangam Interrupt Map (Primary Interrupts)
4863 + *--------------------------------------------------*/
4864 +
4865 +#define AVALANCHE_UNIFIED_SECONDARY_INT            0
4866 +#define AVALANCHE_EXT_INT_0                        1
4867 +#define AVALANCHE_EXT_INT_1                        2
4868 +/* Line#  3 to 4 are reserved                            */
4869 +#define AVALANCHE_TIMER_0_INT                      5
4870 +#define AVALANCHE_TIMER_1_INT                      6
4871 +#define AVALANCHE_UART0_INT                        7
4872 +#define AVALANCHE_UART1_INT                        8
4873 +#define AVALANCHE_DMA_INT0                         9
4874 +#define AVALANCHE_DMA_INT1                        10
4875 +/* Line# 11 to 14 are reserved                    */
4876 +#define AVALANCHE_ATM_SAR_INT                     15
4877 +/* Line# 16 to 18 are reserved                    */
4878 +#define AVALANCHE_LOW_CPMAC_INT                   19
4879 +/* Line# 20 is reserved                           */
4880 +#define AVALANCHE_LOW_VLYNQ_INT                   21
4881 +#define AVALANCHE_CODEC_WAKEUP_INT                22
4882 +/* Line# 23 is reserved                           */
4883 +#define AVALANCHE_USB_SLAVE_INT                   24
4884 +#define AVALANCHE_HIGH_VLYNQ_INT                  25
4885 +/* Line# 26 to 27 are reserved                    */
4886 +#define AVALANCHE_UNIFIED_PHY_INT                 28
4887 +#define AVALANCHE_I2C_INT                         29
4888 +#define AVALANCHE_DMA_INT2                        30
4889 +#define AVALANCHE_DMA_INT3                        31
4890 +/* Line# 32 is reserved                           */
4891 +#define AVALANCHE_HIGH_CPMAC_INT                  33
4892 +/* Line# 34 to 36 is reserved                     */
4893 +#define AVALANCHE_VDMA_VT_RX_INT                  37
4894 +#define AVALANCHE_VDMA_VT_TX_INT                  38
4895 +#define AVALANCHE_ADSL_SUB_SYSTEM_INT             39
4896 +
4897 +
4898 +#define AVALANCHE_EMIF_INT                        47
4899 +
4900 +
4901 +
4902 +/*-----------------------------------------------------------
4903 + * Sangam's Reset Bits
4904 + *---------------------------------------------------------*/
4905 +
4906 +#define AVALANCHE_UART0_RESET_BIT                  0
4907 +#define AVALANCHE_UART1_RESET_BIT                  1
4908 +#define AVALANCHE_I2C_RESET_BIT                    2
4909 +#define AVALANCHE_TIMER0_RESET_BIT                 3
4910 +#define AVALANCHE_TIMER1_RESET_BIT                 4
4911 +/* Reset bit  5 is reserved.                       */
4912 +#define AVALANCHE_GPIO_RESET_BIT                   6
4913 +#define AVALANCHE_ADSL_SUB_SYS_RESET_BIT           7
4914 +#define AVALANCHE_USB_SLAVE_RESET_BIT              8
4915 +#define AVALANCHE_ATM_SAR_RESET_BIT                9
4916 +/* Reset bit 10 is reserved.                      */
4917 +#define AVALANCHE_VDMA_VT_RESET_BIT               11
4918 +#define AVALANCHE_FSER_RESET_BIT                  12
4919 +/* Reset bit 13 to 15 are reserved                */
4920 +#define AVALANCHE_HIGH_VLYNQ_RESET_BIT            16
4921 +#define AVALANCHE_LOW_CPMAC_RESET_BIT             17
4922 +#define AVALANCHE_MCDMA_RESET_BIT                 18
4923 +#define AVALANCHE_BIST_RESET_BIT                  19
4924 +#define AVALANCHE_LOW_VLYNQ_RESET_BIT             20
4925 +#define AVALANCHE_HIGH_CPMAC_RESET_BIT            21
4926 +#define AVALANCHE_MDIO_RESET_BIT                  22
4927 +#define AVALANCHE_ADSL_SUB_SYS_DSP_RESET_BIT      23
4928 +/* Reset bit 24 to 25 are reserved                */
4929 +#define AVALANCHE_LOW_EPHY_RESET_BIT              26
4930 +/* Reset bit 27 to 31 are reserved                */
4931 +
4932 +
4933 +#define AVALANCHE_POWER_MODULE_USBSP               0
4934 +#define AVALANCHE_POWER_MODULE_WDTP                1
4935 +#define AVALANCHE_POWER_MODULE_UT0P                2
4936 +#define AVALANCHE_POWER_MODULE_UT1P                3
4937 +#define AVALANCHE_POWER_MODULE_IICP                4
4938 +#define AVALANCHE_POWER_MODULE_VDMAP               5
4939 +#define AVALANCHE_POWER_MODULE_GPIOP               6
4940 +#define AVALANCHE_POWER_MODULE_VLYNQ1P             7
4941 +#define AVALANCHE_POWER_MODULE_SARP                8
4942 +#define AVALANCHE_POWER_MODULE_ADSLP               9
4943 +#define AVALANCHE_POWER_MODULE_EMIFP              10
4944 +#define AVALANCHE_POWER_MODULE_ADSPP              12
4945 +#define AVALANCHE_POWER_MODULE_RAMP               13
4946 +#define AVALANCHE_POWER_MODULE_ROMP               14
4947 +#define AVALANCHE_POWER_MODULE_DMAP               15
4948 +#define AVALANCHE_POWER_MODULE_BISTP              16
4949 +#define AVALANCHE_POWER_MODULE_TIMER0P            18
4950 +#define AVALANCHE_POWER_MODULE_TIMER1P            19
4951 +#define AVALANCHE_POWER_MODULE_EMAC0P             20
4952 +#define AVALANCHE_POWER_MODULE_EMAC1P             22
4953 +#define AVALANCHE_POWER_MODULE_EPHYP              24
4954 +#define AVALANCHE_POWER_MODULE_VLYNQ0P            27
4955 +
4956 +
4957 +
4958 +
4959 +
4960 +/*
4961 + * Sangam board vectors
4962 + */
4963 +
4964 +#define AVALANCHE_VECS       (KSEG1ADDR(AVALANCHE_SDRAM_BASE))
4965 +#define AVALANCHE_VECS_KSEG0 (KSEG0ADDR(AVALANCHE_SDRAM_BASE))
4966 +
4967 +/*-----------------------------------------------------------------------------
4968 + * Sangam's system register.
4969 + *
4970 + *---------------------------------------------------------------------------*/
4971 +#define AVALANCHE_DCL_BOOTCR          (KSEG1ADDR(0x08611A00))
4972 +#define AVALANCHE_EMIF_SDRAM_CFG      (AVALANCHE_EMIF_CONTROL_BASE + 0x8)
4973 +#define AVALANCHE_RST_CTRL_PRCR       (KSEG1ADDR(0x08611600))
4974 +#define AVALANCHE_RST_CTRL_SWRCR      (KSEG1ADDR(0x08611604))
4975 +#define AVALANCHE_RST_CTRL_RSR        (KSEG1ADDR(0x08611600))
4976 +
4977 +#define AVALANCHE_POWER_CTRL_PDCR     (KSEG1ADDR(0x08610A00))
4978 +#define AVALANCHE_WAKEUP_CTRL_WKCR    (KSEG1ADDR(0x08610A0C))
4979 +
4980 +#define AVALANCHE_GPIO_DATA_IN        (AVALANCHE_GPIO_BASE +  0x0)
4981 +#define AVALANCHE_GPIO_DATA_OUT       (AVALANCHE_GPIO_BASE +  0x4)
4982 +#define AVALANCHE_GPIO_DIR            (AVALANCHE_GPIO_BASE +  0x8)
4983 +#define AVALANCHE_GPIO_ENBL           (AVALANCHE_GPIO_BASE +  0xC)
4984 +#define AVALANCHE_CVR                 (AVALANCHE_GPIO_BASE +  0x14)
4985 +
4986 +/*
4987 + * Yamon Prom print address.
4988 + */
4989 +#define AVALANCHE_YAMON_FUNCTION_BASE             (KSEG1ADDR(0x10000500))
4990 +#define AVALANCHE_YAMON_PROM_PRINT_COUNT_ADDR     (AVALANCHE_YAMON_FUNCTION_BASE + 0x4)  /* print_count function */
4991 +#define AVALANCHE_YAMON_PROM_PRINT_ADDR           (AVALANCHE_YAMON_FUNCTION_BASE + 0x34)
4992 +
4993 +#define AVALANCHE_BASE_BAUD       ( 3686400 / 16 )
4994 +
4995 +#define  AVALANCHE_GPIO_PIN_COUNT         32
4996 +#define  AVALANCHE_GPIO_OFF_MAP           {0xF34FFFC0}
4997 +
4998 +#include "sangam_boards.h"
4999 +
5000 +#endif /*_SANGAM_H_ */
5001 diff -urN linux.old/include/asm-mips/ar7/sangam_boards.h linux.dev/include/asm-mips/ar7/sangam_boards.h
5002 --- linux.old/include/asm-mips/ar7/sangam_boards.h      1970-01-01 01:00:00.000000000 +0100
5003 +++ linux.dev/include/asm-mips/ar7/sangam_boards.h      2005-07-26 18:11:02.647500000 +0200
5004 @@ -0,0 +1,77 @@
5005 +#ifndef _SANGAM_BOARDS_H
5006 +#define _SANGAM_BOARDS_H
5007 +
5008 +// Let us define board specific information here.
5009 +
5010 +
5011 +#if defined(CONFIG_AR7DB)
5012 +
5013 +#define AFECLK_FREQ                                 35328000
5014 +#define REFCLK_FREQ                                 25000000
5015 +#define OSC3_FREQ                                   24000000
5016 +#define AVALANCHE_LOW_CPMAC_PHY_MASK                0x80000000
5017 +#define AVALANCHE_HIGH_CPMAC_PHY_MASK               0x55555555
5018 +#define AVALANCHE_LOW_CPMAC_MDIX_MASK               0x80000000
5019 +
5020 +#endif
5021 +
5022 +
5023 +#if defined(CONFIG_AR7RD)
5024 +#define AFECLK_FREQ                                 35328000
5025 +#define REFCLK_FREQ                                 25000000
5026 +#define OSC3_FREQ                                   24000000
5027 +#define AVALANCHE_LOW_CPMAC_PHY_MASK                0x80000000
5028 +#define AVALANCHE_HIGH_CPMAC_PHY_MASK               0x2
5029 +#define AVALANCHE_LOW_CPMAC_MDIX_MASK               0x80000000
5030 +#endif
5031 +
5032 +
5033 +#if defined(CONFIG_AR7WI)
5034 +#define AFECLK_FREQ                                 35328000
5035 +#define REFCLK_FREQ                                 25000000
5036 +#define OSC3_FREQ                                   24000000
5037 +#define AVALANCHE_LOW_CPMAC_PHY_MASK                0x80000000
5038 +#define AVALANCHE_HIGH_CPMAC_PHY_MASK               0x2
5039 +#define AVALANCHE_LOW_CPMAC_MDIX_MASK               0x80000000
5040 +#endif
5041 +
5042 +
5043 +#if defined(CONFIG_AR7V)
5044 +#define AFECLK_FREQ                                 35328000
5045 +#define REFCLK_FREQ                                 25000000
5046 +#define OSC3_FREQ                                   24000000
5047 +#define AVALANCHE_LOW_CPMAC_PHY_MASK                0x80000000
5048 +#define AVALANCHE_HIGH_CPMAC_PHY_MASK               0x2
5049 +#define AVALANCHE_LOW_CPMAC_MDIX_MASK               0x80000000
5050 +#endif
5051 +
5052 +
5053 +#if defined(CONFIG_AR7WRD)
5054 +#define AFECLK_FREQ                                 35328000
5055 +#define REFCLK_FREQ                                 25000000
5056 +#define OSC3_FREQ                                   24000000
5057 +#define AVALANCHE_LOW_CPMAC_PHY_MASK                0x80000000
5058 +#define AVALANCHE_HIGH_CPMAC_PHY_MASK               0x00010000
5059 +#define AVALANCHE_LOW_CPMAC_MDIX_MASK               0x80000000
5060 +#endif
5061 +
5062 +
5063 +#if defined(CONFIG_AR7VWI)
5064 +#define AFECLK_FREQ                                 35328000
5065 +#define REFCLK_FREQ                                 25000000
5066 +#define OSC3_FREQ                                   24000000
5067 +#define AVALANCHE_LOW_CPMAC_PHY_MASK                0x80000000
5068 +#define AVALANCHE_HIGH_CPMAC_PHY_MASK               0x00010000
5069 +#define AVALANCHE_LOW_CPMAC_MDIX_MASK               0x80000000
5070 +#endif
5071 +
5072 +
5073 +#if defined CONFIG_SEAD2
5074 +#define AVALANCHE_LOW_CPMAC_PHY_MASK                0xAAAAAAAA
5075 +#define AVALANCHE_HIGH_CPMAC_PHY_MASK               0x55555555
5076 +#define AVALANCHE_LOW_CPMAC_MDIX_MASK               0
5077 +#include <asm/mips-boards/sead.h>
5078 +#endif
5079 +
5080 +
5081 +#endif
5082 diff -urN linux.old/include/asm-mips/ar7/tnetd73xx.h linux.dev/include/asm-mips/ar7/tnetd73xx.h
5083 --- linux.old/include/asm-mips/ar7/tnetd73xx.h  1970-01-01 01:00:00.000000000 +0100
5084 +++ linux.dev/include/asm-mips/ar7/tnetd73xx.h  2005-07-26 18:11:02.650500000 +0200
5085 @@ -0,0 +1,338 @@
5086 +/******************************************************************************
5087 + * FILE PURPOSE:    TNETD73xx Common Header File
5088 + ******************************************************************************
5089 + * FILE NAME:       tnetd73xx.h
5090 + *
5091 + * DESCRIPTION:     shared typedef's, constants and API for TNETD73xx
5092 + *
5093 + * REVISION HISTORY:
5094 + * 27 Nov 02 - PSP TII
5095 + *
5096 + * (C) Copyright 2002, Texas Instruments, Inc
5097 + *******************************************************************************/
5098 +
5099 +/*
5100 + *
5101 + *
5102 + *   These are const, typedef, and api definitions for tnetd73xx.
5103 + *
5104 + *   NOTES:
5105 + *   1. This file may be included into both C and Assembly files.
5106 + *       - for .s files, please do #define _ASMLANGUAGE in your ASM file to
5107 + *           avoid C data types (typedefs) below;
5108 + *       - for .c files, you don't have to do anything special.
5109 + *
5110 + *   2. This file has a number of sections for each SOC subsystem. When adding
5111 + *       a new constant, find the subsystem you are working on and follow the
5112 + *       name pattern. If you are adding another typedef for your interface, please,
5113 + *       place it with other typedefs and function prototypes.
5114 + *
5115 + *   3. Please, DO NOT add any macros or types that are local to a subsystem to avoid
5116 + *       cluttering. Include such items directly into the module's .c file or have a
5117 + *       local .h file to pass data between smaller modules. This file defines only
5118 + *       shared items.
5119 + */
5120 +
5121 +#ifndef __TNETD73XX_H__
5122 +#define __TNETD73XX_H__
5123 +
5124 +#ifndef _ASMLANGUAGE        /* This part not for assembly language */
5125 +
5126 +extern unsigned int tnetd73xx_mips_freq;
5127 +extern unsigned int tnetd73xx_vbus_freq;
5128 +
5129 +#include "tnetd73xx_err.h"
5130 +
5131 +#endif /* _ASMLANGUAGE */
5132 +
5133 +
5134 +/*******************************************************************************************
5135 +*   Emerald core specific
5136 +******************************************************************************************** */
5137 +
5138 +#ifdef  BIG_ENDIAN
5139 +#elif defined(LITTLE_ENDIAN)
5140 +#else
5141 +#error Need to define endianism
5142 +#endif
5143 +
5144 +#ifndef KSEG_MSK
5145 +#define KSEG_MSK                    0xE0000000 /* Most significant 3 bits denote kseg choice */
5146 +#endif
5147 +
5148 +#ifndef KSEG_INV_MASK
5149 +#define KSEG_INV_MASK               0x1FFFFFFF /* Inverted mask for kseg address */
5150 +#endif
5151 +
5152 +#ifndef KSEG0_BASE
5153 +#define KSEG0_BASE                  0x80000000
5154 +#endif
5155 +
5156 +#ifndef KSEG1_BASE
5157 +#define KSEG1_BASE                  0xA0000000
5158 +#endif
5159 +
5160 +#ifndef KSEG0
5161 +#define KSEG0(addr)                 (((__u32)(addr) & ~KSEG_MSK) | KSEG0_BASE)
5162 +#endif
5163 +
5164 +#ifndef KSEG1
5165 +#define KSEG1(addr)                 (((__u32)(addr) & ~KSEG_MSK) | KSEG1_BASE)
5166 +#endif
5167 +
5168 +#ifndef KUSEG
5169 +#define KUSEG(addr)                 ((__u32)(addr) & ~KSEG_MSK)
5170 +#endif
5171 +
5172 +#ifndef PHYS_ADDR
5173 +#define PHYS_ADDR(addr)             ((addr) & KSEG_INV_MASK)
5174 +#endif
5175 +
5176 +#ifndef PHYS_TO_K0
5177 +#define PHYS_TO_K0(addr)            (PHYS_ADDR(addr)|KSEG0_BASE)
5178 +#endif
5179 +
5180 +#ifndef PHYS_TO_K1
5181 +#define PHYS_TO_K1(addr)            (PHYS_ADDR(addr)|KSEG1_BASE)
5182 +#endif
5183 +
5184 +#ifndef REG8_ADDR
5185 +#define REG8_ADDR(addr)             (volatile __u8 *)(PHYS_TO_K1(addr))
5186 +#define REG8_DATA(addr)             (*(volatile __u8 *)(PHYS_TO_K1(addr)))
5187 +#define REG8_WRITE(addr, data)      REG8_DATA(addr) = data;
5188 +#define REG8_READ(addr, data)       data = (__u8) REG8_DATA(addr);
5189 +#endif
5190 +
5191 +#ifndef REG16_ADDR
5192 +#define REG16_ADDR(addr)            (volatile __u16 *)(PHYS_TO_K1(addr))
5193 +#define REG16_DATA(addr)            (*(volatile __u16 *)(PHYS_TO_K1(addr)))
5194 +#define REG16_WRITE(addr, data)     REG16_DATA(addr) = data;
5195 +#define REG16_READ(addr, data)      data = (__u16) REG16_DATA(addr);
5196 +#endif
5197 +
5198 +#ifndef REG32_ADDR
5199 +#define REG32_ADDR(addr)            (volatile __u32 *)(PHYS_TO_K1(addr))
5200 +#define REG32_DATA(addr)            (*(volatile __u32 *)(PHYS_TO_K1(addr)))
5201 +#define REG32_WRITE(addr, data)     REG32_DATA(addr) = data;
5202 +#define REG32_READ(addr, data)      data = (__u32) REG32_DATA(addr);
5203 +#endif
5204 +
5205 +#ifdef  _LINK_KSEG0_                /* Application is linked into KSEG0 space */
5206 +#define VIRT_ADDR(addr)             PHYS_TO_K0(PHYS_ADDR(addr))
5207 +#endif
5208 +
5209 +#ifdef  _LINK_KSEG1_                /* Application is linked into KSEG1 space */
5210 +#define VIRT_ADDR(addr)             PHYS_TO_K1(PHYS_ADDR(addr))
5211 +#endif
5212 +
5213 +#if !defined(_LINK_KSEG0_) && !defined(_LINK_KSEG1_)
5214 +#error  You must define _LINK_KSEG0_ or _LINK_KSEG1_ to compile the code.
5215 +#endif
5216 +
5217 +/* TNETD73XX chip definations */
5218 +
5219 +#define FREQ_1MHZ                       1000000
5220 +#define TNETD73XX_MIPS_FREQ             tnetd73xx_mips_freq /* CPU clock frequency */
5221 +#define TNETD73XX_VBUS_FREQ             tnetd73xx_vbus_freq /* originally (TNETD73XX_MIPS_FREQ/2) */
5222 +
5223 +#ifdef AR7SEAD2
5224 +#define TNETD73XX_MIPS_FREQ_DEFAULT     25000000       /* 25 Mhz for sead2 board crystal */
5225 +#else
5226 +#define TNETD73XX_MIPS_FREQ_DEFAULT     125000000      /* 125 Mhz */
5227 +#endif
5228 +#define TNETD73XX_VBUS_FREQ_DEFAULT     (TNETD73XX_MIPS_FREQ_DEFAULT / 2) /* Sync mode */
5229 +
5230 +
5231 +
5232 +/* Module base addresses */
5233 +#define TNETD73XX_ADSLSS_BASE               PHYS_TO_K1(0x01000000)      /* ADSLSS Module */
5234 +#define TNETD73XX_BBIF_CTRL_BASE            PHYS_TO_K1(0x02000000)      /* BBIF Control */
5235 +#define TNETD73XX_ATMSAR_BASE               PHYS_TO_K1(0x03000000)      /* ATM SAR */
5236 +#define TNETD73XX_USB_BASE                  PHYS_TO_K1(0x03400000)      /* USB Module */
5237 +#define TNETD73XX_VLYNQ0_BASE               PHYS_TO_K1(0x04000000)      /* VLYNQ0 Module */
5238 +#define TNETD73xx_EMAC0_BASE                PHYS_TO_K1(0x08610000)      /* EMAC0 Module*/
5239 +#define TNETD73XX_EMIF_BASE                 PHYS_TO_K1(0x08610800)      /* EMIF Module */
5240 +#define TNETD73XX_GPIO_BASE                 PHYS_TO_K1(0x08610900)      /* GPIO control */
5241 +#define TNETD73XX_CLOCK_CTRL_BASE           PHYS_TO_K1(0x08610A00)      /* Clock Control */
5242 +#define TNETD73XX_WDTIMER_BASE              PHYS_TO_K1(0x08610B00)      /* WDTIMER Module */
5243 +#define TNETD73XX_TIMER0_BASE               PHYS_TO_K1(0x08610C00)      /* TIMER0 Module */
5244 +#define TNETD73XX_TIMER1_BASE               PHYS_TO_K1(0x08610D00)      /* TIMER1 Module */
5245 +#define TNETD73XX_UARTA_BASE                PHYS_TO_K1(0x08610E00)      /* UART A */
5246 +#define TNETD73XX_UARTB_BASE                PHYS_TO_K1(0x08610F00)      /* UART B */
5247 +#define TNETD73XX_I2C_BASE                  PHYS_TO_K1(0x08611000)      /* I2C Module */
5248 +#define TNETD73XX_USB_DMA_BASE              PHYS_TO_K1(0x08611200)      /* USB Module */
5249 +#define TNETD73XX_MCDMA_BASE                PHYS_TO_K1(0x08611400)      /* MC-DMA */
5250 +#define TNETD73xx_VDMAVT_BASE               PHYS_TO_K1(0x08611500)      /* VDMAVT Control */
5251 +#define TNETD73XX_RST_CTRL_BASE             PHYS_TO_K1(0x08611600)      /* Reset Control */
5252 +#define TNETD73xx_BIST_CTRL_BASE            PHYS_TO_K1(0x08611700)      /* BIST Control */
5253 +#define TNETD73xx_VLYNQ0_CTRL_BASE          PHYS_TO_K1(0x08611800)      /* VLYNQ0 Control */
5254 +#define TNETD73XX_DCL_BASE                  PHYS_TO_K1(0x08611A00)      /* Device Configuration Latch */
5255 +#define TNETD73xx_VLYNQ1_CTRL_BASE          PHYS_TO_K1(0x08611C00)      /* VLYNQ1 Control */
5256 +#define TNETD73xx_MDIO_BASE                 PHYS_TO_K1(0x08611E00)      /* MDIO Control */
5257 +#define TNETD73XX_FSER_BASE                 PHYS_TO_K1(0x08612000)      /* FSER Control */
5258 +#define TNETD73XX_INTC_BASE                 PHYS_TO_K1(0x08612400)      /* Interrupt Controller */
5259 +#define TNETD73xx_EMAC1_BASE                PHYS_TO_K1(0x08612800)      /* EMAC1 Module*/
5260 +#define TNETD73XX_VLYNQ1_BASE               PHYS_TO_K1(0x0C000000)      /* VLYNQ1 Module */
5261 +
5262 +/* BBIF Registers */
5263 +#define TNETD73XX_BBIF_ADSLADR              (TNETD73XX_BBIF_CTRL_BASE + 0x0)
5264 +
5265 +/* Device Configuration Latch Registers */
5266 +#define TNETD73XX_DCL_BOOTCR                (TNETD73XX_DCL_BASE + 0x0)
5267 +#define TNETD73XX_DCL_DPLLSELR              (TNETD73XX_DCL_BASE + 0x10)
5268 +#define TNETD73XX_DCL_SPEEDCTLR             (TNETD73XX_DCL_BASE + 0x14)
5269 +#define TNETD73XX_DCL_SPEEDPWDR             (TNETD73XX_DCL_BASE + 0x18)
5270 +#define TNETD73XX_DCL_SPEEDCAPR             (TNETD73XX_DCL_BASE + 0x1C)
5271 +
5272 +/* GPIO Control */
5273 +#define TNETD73XX_GPIODINR                  (TNETD73XX_GPIO_BASE + 0x0)
5274 +#define TNETD73XX_GPIODOUTR                 (TNETD73XX_GPIO_BASE + 0x4)
5275 +#define TNETD73XX_GPIOPDIRR                 (TNETD73XX_GPIO_BASE + 0x8)
5276 +#define TNETD73XX_GPIOENR                   (TNETD73XX_GPIO_BASE + 0xC)
5277 +#define TNETD73XX_CVR                       (TNETD73XX_GPIO_BASE + 0x14)
5278 +#define TNETD73XX_DIDR1                     (TNETD73XX_GPIO_BASE + 0x18)
5279 +#define TNETD73XX_DIDR2                     (TNETD73XX_GPIO_BASE + 0x1C)
5280 +
5281 +/* Reset Control  */
5282 +#define TNETD73XX_RST_CTRL_PRCR             (TNETD73XX_RST_CTRL_BASE + 0x0)
5283 +#define TNETD73XX_RST_CTRL_SWRCR            (TNETD73XX_RST_CTRL_BASE + 0x4)
5284 +#define TNETD73XX_RST_CTRL_RSR              (TNETD73XX_RST_CTRL_BASE + 0x8)
5285 +
5286 +/* Power Control  */
5287 +#define TNETD73XX_POWER_CTRL_PDCR           (TNETD73XX_CLOCK_CTRL_BASE + 0x0)
5288 +#define TNETD73XX_POWER_CTRL_PCLKCR         (TNETD73XX_CLOCK_CTRL_BASE + 0x4)
5289 +#define TNETD73XX_POWER_CTRL_PDUCR          (TNETD73XX_CLOCK_CTRL_BASE + 0x8)
5290 +#define TNETD73XX_POWER_CTRL_WKCR           (TNETD73XX_CLOCK_CTRL_BASE + 0xC)
5291 +
5292 +/* Clock Control */
5293 +#define TNETD73XX_CLK_CTRL_SCLKCR           (TNETD73XX_CLOCK_CTRL_BASE + 0x20)
5294 +#define TNETD73XX_CLK_CTRL_SCLKPLLCR        (TNETD73XX_CLOCK_CTRL_BASE + 0x30)
5295 +#define TNETD73XX_CLK_CTRL_MCLKCR           (TNETD73XX_CLOCK_CTRL_BASE + 0x40)
5296 +#define TNETD73XX_CLK_CTRL_MCLKPLLCR        (TNETD73XX_CLOCK_CTRL_BASE + 0x50)
5297 +#define TNETD73XX_CLK_CTRL_UCLKCR           (TNETD73XX_CLOCK_CTRL_BASE + 0x60)
5298 +#define TNETD73XX_CLK_CTRL_UCLKPLLCR        (TNETD73XX_CLOCK_CTRL_BASE + 0x70)
5299 +#define TNETD73XX_CLK_CTRL_ACLKCR0          (TNETD73XX_CLOCK_CTRL_BASE + 0x80)
5300 +#define TNETD73XX_CLK_CTRL_ACLKPLLCR0       (TNETD73XX_CLOCK_CTRL_BASE + 0x90)
5301 +#define TNETD73XX_CLK_CTRL_ACLKCR1          (TNETD73XX_CLOCK_CTRL_BASE + 0xA0)
5302 +#define TNETD73XX_CLK_CTRL_ACLKPLLCR1       (TNETD73XX_CLOCK_CTRL_BASE + 0xB0)
5303 +
5304 +/* EMIF control */
5305 +#define TNETD73XX_EMIF_SDRAM_CFG              ( TNETD73XX_EMIF_BASE + 0x08 )
5306 +
5307 +/* UART */
5308 +#ifdef AR7SEAD2
5309 +#define TNETD73XX_UART_FREQ                 3686400
5310 +#else
5311 +#define TNETD73XX_UART_FREQ                 TNETD73XX_VBUS_FREQ
5312 +#endif
5313 +
5314 +/* Interrupt Controller */
5315 +
5316 +/* Primary interrupts */
5317 +#define TNETD73XX_INTC_UNIFIED_SECONDARY    0   /* Unified secondary interrupt */
5318 +#define TNETD73XX_INTC_EXTERNAL0            1   /* External Interrupt Line 0 */
5319 +#define TNETD73XX_INTC_EXTERNAL1            2   /* External Interrupt Line 1 */
5320 +#define TNETD73XX_INTC_RESERVED3            3   /* Reserved */
5321 +#define TNETD73XX_INTC_RESERVED4            4   /* Reserved */
5322 +#define TNETD73XX_INTC_TIMER0               5   /* TIMER 0 int */
5323 +#define TNETD73XX_INTC_TIMER1               6   /* TIMER 1 int */
5324 +#define TNETD73XX_INTC_UART0                7   /* UART 0 int */
5325 +#define TNETD73XX_INTC_UART1                8   /* UART 1 int */
5326 +#define TNETD73XX_INTC_MCDMA0               9   /* MCDMA 0 int */
5327 +#define TNETD73XX_INTC_MCDMA1               10  /* MCDMA 1 int */
5328 +#define TNETD73XX_INTC_RESERVED11           11  /* Reserved */
5329 +#define TNETD73XX_INTC_RESERVED12           12  /* Reserved */
5330 +#define TNETD73XX_INTC_RESERVED13           13  /* Reserved */
5331 +#define TNETD73XX_INTC_RESERVED14           14  /* Reserved */
5332 +#define TNETD73XX_INTC_ATMSAR               15  /* ATM SAR int */
5333 +#define TNETD73XX_INTC_RESERVED16           16  /* Reserved */
5334 +#define TNETD73XX_INTC_RESERVED17           17  /* Reserved */
5335 +#define TNETD73XX_INTC_RESERVED18           18  /* Reserved */
5336 +#define TNETD73XX_INTC_EMAC0                19  /* EMAC 0 int */
5337 +#define TNETD73XX_INTC_RESERVED20           20  /* Reserved */
5338 +#define TNETD73XX_INTC_VLYNQ0               21  /* VLYNQ 0 int */
5339 +#define TNETD73XX_INTC_CODEC                22  /* CODEC int */
5340 +#define TNETD73XX_INTC_RESERVED23           23  /* Reserved */
5341 +#define TNETD73XX_INTC_USBSLAVE             24  /* USB Slave int */
5342 +#define TNETD73XX_INTC_VLYNQ1               25  /* VLYNQ 1 int */
5343 +#define TNETD73XX_INTC_RESERVED26           26  /* Reserved */
5344 +#define TNETD73XX_INTC_RESERVED27           27  /* Reserved */
5345 +#define TNETD73XX_INTC_ETH_PHY              28  /* Ethernet PHY   */
5346 +#define TNETD73XX_INTC_I2C                  29  /* I2C int */
5347 +#define TNETD73XX_INTC_MCDMA2               30  /* MCDMA 2 int */
5348 +#define TNETD73XX_INTC_MCDMA3               31  /* MCDMA 3 int */
5349 +#define TNETD73XX_INTC_RESERVED32           32  /* Reserved */
5350 +#define TNETD73XX_INTC_EMAC1                33  /* EMAC 1 int */
5351 +#define TNETD73XX_INTC_RESERVED34           34  /* Reserved */
5352 +#define TNETD73XX_INTC_RESERVED35           35  /* Reserved */
5353 +#define TNETD73XX_INTC_RESERVED36           36  /* Reserved */
5354 +#define TNETD73XX_INTC_VDMAVTRX             37  /* VDMAVTRX */
5355 +#define TNETD73XX_INTC_VDMAVTTX             38  /* VDMAVTTX */
5356 +#define TNETD73XX_INTC_ADSLSS               39  /* ADSLSS */
5357 +
5358 +/* Secondary interrupts */
5359 +#define TNETD73XX_INTC_SEC0                 40  /* Secondary */
5360 +#define TNETD73XX_INTC_SEC1                 41  /* Secondary */
5361 +#define TNETD73XX_INTC_SEC2                 42  /* Secondary */
5362 +#define TNETD73XX_INTC_SEC3                 43  /* Secondary */
5363 +#define TNETD73XX_INTC_SEC4                 44  /* Secondary */
5364 +#define TNETD73XX_INTC_SEC5                 45  /* Secondary */
5365 +#define TNETD73XX_INTC_SEC6                 46  /* Secondary */
5366 +#define TNETD73XX_INTC_EMIF                 47  /* EMIF */
5367 +#define TNETD73XX_INTC_SEC8                 48  /* Secondary */
5368 +#define TNETD73XX_INTC_SEC9                 49  /* Secondary */
5369 +#define TNETD73XX_INTC_SEC10                50  /* Secondary */
5370 +#define TNETD73XX_INTC_SEC11                51  /* Secondary */
5371 +#define TNETD73XX_INTC_SEC12                52  /* Secondary */
5372 +#define TNETD73XX_INTC_SEC13                53  /* Secondary */
5373 +#define TNETD73XX_INTC_SEC14                54  /* Secondary */
5374 +#define TNETD73XX_INTC_SEC15                55  /* Secondary */
5375 +#define TNETD73XX_INTC_SEC16                56  /* Secondary */
5376 +#define TNETD73XX_INTC_SEC17                57  /* Secondary */
5377 +#define TNETD73XX_INTC_SEC18                58  /* Secondary */
5378 +#define TNETD73XX_INTC_SEC19                59  /* Secondary */
5379 +#define TNETD73XX_INTC_SEC20                60  /* Secondary */
5380 +#define TNETD73XX_INTC_SEC21                61  /* Secondary */
5381 +#define TNETD73XX_INTC_SEC22                62  /* Secondary */
5382 +#define TNETD73XX_INTC_SEC23                63  /* Secondary */
5383 +#define TNETD73XX_INTC_SEC24                64  /* Secondary */
5384 +#define TNETD73XX_INTC_SEC25                65  /* Secondary */
5385 +#define TNETD73XX_INTC_SEC26                66  /* Secondary */
5386 +#define TNETD73XX_INTC_SEC27                67  /* Secondary */
5387 +#define TNETD73XX_INTC_SEC28                68  /* Secondary */
5388 +#define TNETD73XX_INTC_SEC29                69  /* Secondary */
5389 +#define TNETD73XX_INTC_SEC30                70  /* Secondary */
5390 +#define TNETD73XX_INTC_SEC31                71  /* Secondary */
5391 +
5392 +/* These ugly macros are to access the -1 registers, like config1 */
5393 +#define MFC0_SEL1_OPCODE(dst, src)\
5394 +        .word (0x40000000 | ((dst)<<16) | ((src)<<11) | 1);\
5395 +        nop; \
5396 +        nop; \
5397 +        nop
5398 +
5399 +#define MTC0_SEL1_OPCODE(dst, src)\
5400 +        .word (0x40800000 | ((dst)<<16) | ((src)<<11) | 1);\
5401 +        nop; \
5402 +        nop; \
5403 +        nop
5404 +
5405 +
5406 +/* Below are Jade core specific */
5407 +#define CFG0_4K_IL_MASK         0x00380000
5408 +#define CFG0_4K_IL_SHIFT        19
5409 +#define CFG0_4K_IA_MASK         0x00070000
5410 +#define CFG0_4K_IA_SHIFT        16
5411 +#define CFG0_4K_IS_MASK         0x01c00000
5412 +#define CFG0_4K_IS_SHIFT        22
5413 +
5414 +#define CFG0_4K_DL_MASK         0x00001c00
5415 +#define CFG0_4K_DL_SHIFT        10
5416 +#define CFG0_4K_DA_MASK         0x00000380
5417 +#define CFG0_4K_DA_SHIFT        7
5418 +#define CFG0_4K_DS_MASK         0x0000E000
5419 +#define CFG0_4K_DS_SHIFT        13
5420 +
5421 +
5422 +
5423 +#endif /* __TNETD73XX_H_ */
5424 diff -urN linux.old/include/asm-mips/ar7/tnetd73xx_err.h linux.dev/include/asm-mips/ar7/tnetd73xx_err.h
5425 --- linux.old/include/asm-mips/ar7/tnetd73xx_err.h      1970-01-01 01:00:00.000000000 +0100
5426 +++ linux.dev/include/asm-mips/ar7/tnetd73xx_err.h      2005-07-26 18:11:02.649500000 +0200
5427 @@ -0,0 +1,42 @@
5428 +/******************************************************************************
5429 + * FILE PURPOSE:    TNETD73xx Error Definations Header File
5430 + ******************************************************************************
5431 + * FILE NAME:       tnetd73xx_err.h
5432 + *
5433 + * DESCRIPTION:     Error definations for TNETD73XX
5434 + *
5435 + * REVISION HISTORY:
5436 + * 27 Nov 02 - PSP TII
5437 + *
5438 + * (C) Copyright 2002, Texas Instruments, Inc
5439 + *******************************************************************************/
5440 +
5441 +
5442 +#ifndef __TNETD73XX_ERR_H__
5443 +#define __TNETD73XX_ERR_H__
5444 +
5445 +typedef enum TNETD73XX_ERR_t
5446 +{
5447 +    TNETD73XX_ERR_OK        = 0,    /* OK or SUCCESS */
5448 +    TNETD73XX_ERR_ERROR     = -1,   /* Unspecified/Generic ERROR */
5449 +
5450 +    /* Pointers and args */
5451 +    TNETD73XX_ERR_INVARG        = -2,   /* Invaild argument to the call */
5452 +    TNETD73XX_ERR_NULLPTR       = -3,   /* NULL pointer */
5453 +    TNETD73XX_ERR_BADPTR        = -4,   /* Bad (out of mem) pointer */
5454 +
5455 +    /* Memory issues */
5456 +    TNETD73XX_ERR_ALLOC_FAIL    = -10,  /* allocation failed */
5457 +    TNETD73XX_ERR_FREE_FAIL     = -11,  /* free failed */
5458 +    TNETD73XX_ERR_MEM_CORRUPT   = -12,  /* corrupted memory */
5459 +    TNETD73XX_ERR_BUF_LINK      = -13,  /* buffer linking failed */
5460 +
5461 +    /* Device issues */
5462 +    TNETD73XX_ERR_DEVICE_TIMEOUT    = -20,  /* device timeout on read/write */
5463 +    TNETD73XX_ERR_DEVICE_MALFUNC    = -21,  /* device malfunction */
5464 +
5465 +    TNETD73XX_ERR_INVID     = -30   /* Invalid ID */
5466 +
5467 +} TNETD73XX_ERR;
5468 +
5469 +#endif /* __TNETD73XX_ERR_H__ */
5470 diff -urN linux.old/include/asm-mips/ar7/tnetd73xx_misc.h linux.dev/include/asm-mips/ar7/tnetd73xx_misc.h
5471 --- linux.old/include/asm-mips/ar7/tnetd73xx_misc.h     1970-01-01 01:00:00.000000000 +0100
5472 +++ linux.dev/include/asm-mips/ar7/tnetd73xx_misc.h     2005-07-26 18:11:02.651500000 +0200
5473 @@ -0,0 +1,239 @@
5474 +/******************************************************************************
5475 + * FILE PURPOSE:    TNETD73xx Misc modules API Header
5476 + ******************************************************************************
5477 + * FILE NAME:       tnetd73xx_misc.h
5478 + *
5479 + * DESCRIPTION:     Clock Control, Reset Control, Power Management, GPIO
5480 + *                  FSER Modules API
5481 + *                  As per TNETD73xx specifications
5482 + *
5483 + * REVISION HISTORY:
5484 + * 27 Nov 02 - Sharath Kumar     PSP TII
5485 + * 14 Feb 03 - Anant Gole        PSP TII
5486 + *
5487 + * (C) Copyright 2002, Texas Instruments, Inc
5488 + *******************************************************************************/
5489 +
5490 +#ifndef __TNETD73XX_MISC_H__
5491 +#define __TNETD73XX_MISC_H__
5492 +
5493 +/*****************************************************************************
5494 + * Reset Control Module
5495 + *****************************************************************************/
5496 +
5497 +typedef enum TNETD73XX_RESET_MODULE_tag
5498 +{
5499 +    RESET_MODULE_UART0      = 0,
5500 +    RESET_MODULE_UART1      = 1,
5501 +    RESET_MODULE_I2C        = 2,
5502 +    RESET_MODULE_TIMER0     = 3,
5503 +    RESET_MODULE_TIMER1     = 4,
5504 +    RESET_MODULE_GPIO       = 6,
5505 +    RESET_MODULE_ADSLSS     = 7,
5506 +    RESET_MODULE_USBS       = 8,
5507 +    RESET_MODULE_SAR        = 9,
5508 +    RESET_MODULE_VDMA_VT    = 11,
5509 +    RESET_MODULE_FSER       = 12,
5510 +    RESET_MODULE_VLYNQ1     = 16,
5511 +    RESET_MODULE_EMAC0      = 17,
5512 +    RESET_MODULE_DMA        = 18,
5513 +    RESET_MODULE_BIST       = 19,
5514 +    RESET_MODULE_VLYNQ0     = 20,
5515 +    RESET_MODULE_EMAC1      = 21,
5516 +    RESET_MODULE_MDIO       = 22,
5517 +    RESET_MODULE_ADSLSS_DSP = 23,
5518 +    RESET_MODULE_EPHY       = 26
5519 +} TNETD73XX_RESET_MODULE_T;
5520 +
5521 +typedef enum TNETD73XX_RESET_CTRL_tag
5522 +{
5523 +    IN_RESET        = 0,
5524 +    OUT_OF_RESET
5525 +} TNETD73XX_RESET_CTRL_T;
5526 +
5527 +typedef enum TNETD73XX_SYS_RST_MODE_tag
5528 +{
5529 +    RESET_SOC_WITH_MEMCTRL      = 1,    /* SW0 bit in SWRCR register */
5530 +    RESET_SOC_WITHOUT_MEMCTRL   = 2     /* SW1 bit in SWRCR register */
5531 +} TNETD73XX_SYS_RST_MODE_T;
5532 +
5533 +typedef enum TNETD73XX_SYS_RESET_STATUS_tag
5534 +{
5535 +    HARDWARE_RESET = 0,
5536 +    SOFTWARE_RESET0,            /* Caused by writing 1 to SW0 bit in SWRCR register */
5537 +    WATCHDOG_RESET,
5538 +    SOFTWARE_RESET1             /* Caused by writing 1 to SW1 bit in SWRCR register */
5539 +} TNETD73XX_SYS_RESET_STATUS_T;
5540 +
5541 +void tnetd73xx_reset_ctrl(TNETD73XX_RESET_MODULE_T reset_module,
5542 +                                TNETD73XX_RESET_CTRL_T reset_ctrl);
5543 +TNETD73XX_RESET_CTRL_T tnetd73xx_get_reset_status(TNETD73XX_RESET_MODULE_T reset_module);
5544 +void tnetd73xx_sys_reset(TNETD73XX_SYS_RST_MODE_T mode);
5545 +TNETD73XX_SYS_RESET_STATUS_T tnetd73xx_get_sys_last_reset_status(void);
5546 +
5547 +/*****************************************************************************
5548 + * Power Control Module
5549 + *****************************************************************************/
5550 +
5551 +typedef enum TNETD73XX_POWER_MODULE_tag
5552 +{
5553 +    POWER_MODULE_USBSP      = 0,
5554 +    POWER_MODULE_WDTP       = 1,
5555 +    POWER_MODULE_UT0P       = 2,
5556 +    POWER_MODULE_UT1P       = 3,
5557 +    POWER_MODULE_IICP       = 4,
5558 +    POWER_MODULE_VDMAP      = 5,
5559 +    POWER_MODULE_GPIOP      = 6,
5560 +    POWER_MODULE_VLYNQ1P    = 7,
5561 +    POWER_MODULE_SARP       = 8,
5562 +    POWER_MODULE_ADSLP      = 9,
5563 +    POWER_MODULE_EMIFP      = 10,
5564 +    POWER_MODULE_ADSPP      = 12,
5565 +    POWER_MODULE_RAMP       = 13,
5566 +    POWER_MODULE_ROMP       = 14,
5567 +    POWER_MODULE_DMAP       = 15,
5568 +    POWER_MODULE_BISTP      = 16,
5569 +    POWER_MODULE_TIMER0P    = 18,
5570 +    POWER_MODULE_TIMER1P    = 19,
5571 +    POWER_MODULE_EMAC0P     = 20,
5572 +    POWER_MODULE_EMAC1P     = 22,
5573 +    POWER_MODULE_EPHYP      = 24,
5574 +    POWER_MODULE_VLYNQ0P    = 27,
5575 +} TNETD73XX_POWER_MODULE_T;
5576 +
5577 +typedef enum TNETD73XX_POWER_CTRL_tag
5578 +{
5579 +    POWER_CTRL_POWER_UP = 0,
5580 +    POWER_CTRL_POWER_DOWN
5581 +} TNETD73XX_POWER_CTRL_T;
5582 +
5583 +typedef enum TNETD73XX_SYS_POWER_MODE_tag
5584 +{
5585 +    GLOBAL_POWER_MODE_RUN       = 0,    /* All system is up */
5586 +    GLOBAL_POWER_MODE_IDLE,             /* MIPS is power down, all peripherals working */
5587 +    GLOBAL_POWER_MODE_STANDBY,          /* Chip in power down, but clock to ADSKL subsystem is running */
5588 +    GLOBAL_POWER_MODE_POWER_DOWN        /* Total chip is powered down */
5589 +} TNETD73XX_SYS_POWER_MODE_T;
5590 +
5591 +void tnetd73xx_power_ctrl(TNETD73XX_POWER_MODULE_T power_module,  TNETD73XX_POWER_CTRL_T power_ctrl);
5592 +TNETD73XX_POWER_CTRL_T tnetd73xx_get_pwr_status(TNETD73XX_POWER_MODULE_T power_module);
5593 +void tnetd73xx_set_global_pwr_mode(TNETD73XX_SYS_POWER_MODE_T power_mode);
5594 +TNETD73XX_SYS_POWER_MODE_T tnetd73xx_get_global_pwr_mode(void);
5595 +
5596 +/*****************************************************************************
5597 + * Wakeup Control
5598 + *****************************************************************************/
5599 +
5600 +typedef enum TNETD73XX_WAKEUP_INTERRUPT_tag
5601 +{
5602 +    WAKEUP_INT0 = 1,
5603 +    WAKEUP_INT1 = 2,
5604 +    WAKEUP_INT2 = 4,
5605 +    WAKEUP_INT3 = 8
5606 +} TNETD73XX_WAKEUP_INTERRUPT_T;
5607 +
5608 +typedef enum TNETD73XX_WAKEUP_CTRL_tag
5609 +{
5610 +    WAKEUP_DISABLED = 0,
5611 +    WAKEUP_ENABLED
5612 +} TNETD73XX_WAKEUP_CTRL_T;
5613 +
5614 +typedef enum TNETD73XX_WAKEUP_POLARITY_tag
5615 +{
5616 +    WAKEUP_ACTIVE_HIGH = 0,
5617 +    WAKEUP_ACTIVE_LOW
5618 +} TNETD73XX_WAKEUP_POLARITY_T;
5619 +
5620 +void tnetd73xx_wakeup_ctrl(TNETD73XX_WAKEUP_INTERRUPT_T wakeup_int,
5621 +                           TNETD73XX_WAKEUP_CTRL_T wakeup_ctrl,
5622 +                           TNETD73XX_WAKEUP_POLARITY_T wakeup_polarity);
5623 +
5624 +/*****************************************************************************
5625 + * FSER  Control
5626 + *****************************************************************************/
5627 +
5628 +typedef enum TNETD73XX_FSER_MODE_tag
5629 +{
5630 +    FSER_I2C    = 0,
5631 +    FSER_UART   = 1
5632 +} TNETD73XX_FSER_MODE_T;
5633 +
5634 +void tnetd73xx_fser_ctrl(TNETD73XX_FSER_MODE_T fser_mode);
5635 +
5636 +/*****************************************************************************
5637 + * Clock Control
5638 + *****************************************************************************/
5639 +
5640 +#define CLK_MHZ(x)    ( (x) * 1000000 )
5641 +
5642 +typedef enum TNETD73XX_CLKC_ID_tag
5643 +{
5644 +    CLKC_SYS = 0,
5645 +    CLKC_MIPS,
5646 +    CLKC_USB,
5647 +    CLKC_ADSLSS
5648 +} TNETD73XX_CLKC_ID_T;
5649 +
5650 +void tnetd73xx_clkc_init(__u32 afeclk, __u32 refclk, __u32 xtal3in);
5651 +TNETD73XX_ERR tnetd73xx_clkc_set_freq(TNETD73XX_CLKC_ID_T clk_id, __u32 output_freq);
5652 +__u32 tnetd73xx_clkc_get_freq(TNETD73XX_CLKC_ID_T clk_id);
5653 +
5654 +/*****************************************************************************
5655 + * GPIO Control
5656 + *****************************************************************************/
5657 +
5658 +typedef enum TNETD73XX_GPIO_PIN_tag
5659 +{
5660 +    GPIO_UART0_RD           = 0,
5661 +    GPIO_UART0_TD           = 1,
5662 +    GPIO_UART0_RTS          = 2,
5663 +    GPIO_UART0_CTS          = 3,
5664 +    GPIO_FSER_CLK           = 4,
5665 +    GPIO_FSER_D             = 5,
5666 +    GPIO_EXT_AFE_SCLK       = 6,
5667 +    GPIO_EXT_AFE_TX_FS      = 7,
5668 +    GPIO_EXT_AFE_TXD        = 8,
5669 +    GPIO_EXT_AFE_RS_FS      = 9,
5670 +    GPIO_EXT_AFE_RXD1       = 10,
5671 +    GPIO_EXT_AFE_RXD0       = 11,
5672 +    GPIO_EXT_AFE_CDIN       = 12,
5673 +    GPIO_EXT_AFE_CDOUT      = 13,
5674 +    GPIO_EPHY_SPEED100      = 14,
5675 +    GPIO_EPHY_LINKON        = 15,
5676 +    GPIO_EPHY_ACTIVITY      = 16,
5677 +    GPIO_EPHY_FDUPLEX       = 17,
5678 +    GPIO_EINT0              = 18,
5679 +    GPIO_EINT1              = 19,
5680 +    GPIO_MBSP0_TCLK         = 20,
5681 +    GPIO_MBSP0_RCLK         = 21,
5682 +    GPIO_MBSP0_RD           = 22,
5683 +    GPIO_MBSP0_TD           = 23,
5684 +    GPIO_MBSP0_RFS          = 24,
5685 +    GPIO_MBSP0_TFS          = 25,
5686 +    GPIO_MII_DIO            = 26,
5687 +    GPIO_MII_DCLK           = 27,
5688 +} TNETD73XX_GPIO_PIN_T;
5689 +
5690 +typedef enum TNETD73XX_GPIO_PIN_MODE_tag
5691 +{
5692 +    FUNCTIONAL_PIN = 0,
5693 +    GPIO_PIN = 1
5694 +} TNETD73XX_GPIO_PIN_MODE_T;
5695 +
5696 +typedef enum TNETD73XX_GPIO_PIN_DIRECTION_tag
5697 +{
5698 +    GPIO_OUTPUT_PIN = 0,
5699 +    GPIO_INPUT_PIN = 1
5700 +} TNETD73XX_GPIO_PIN_DIRECTION_T;
5701 +
5702 +void tnetd73xx_gpio_init(void);
5703 +void tnetd73xx_gpio_ctrl(TNETD73XX_GPIO_PIN_T gpio_pin,
5704 +                         TNETD73XX_GPIO_PIN_MODE_T pin_mode,
5705 +                         TNETD73XX_GPIO_PIN_DIRECTION_T pin_direction);
5706 +void tnetd73xx_gpio_out(TNETD73XX_GPIO_PIN_T gpio_pin, int value);
5707 +int tnetd73xx_gpio_in(TNETD73XX_GPIO_PIN_T gpio_pin);
5708 +
5709 +/* TNETD73XX Revision */
5710 +__u32 tnetd73xx_get_revision(void);
5711 +
5712 +#endif /* __TNETD73XX_MISC_H__ */
5713 diff -urN linux.old/include/asm-mips/io.h linux.dev/include/asm-mips/io.h
5714 --- linux.old/include/asm-mips/io.h     2005-07-26 18:18:16.283578056 +0200
5715 +++ linux.dev/include/asm-mips/io.h     2005-07-26 18:11:02.651500000 +0200
5716 @@ -63,8 +63,12 @@
5717  #ifdef CONFIG_64BIT_PHYS_ADDR
5718  #define page_to_phys(page)     ((u64)(page - mem_map) << PAGE_SHIFT)
5719  #else
5720 +#ifdef CONFIG_AR7_PAGING
5721 +#define page_to_phys(page)     (((page - mem_map) << PAGE_SHIFT) + CONFIG_AR7_MEMORY)
5722 +#else
5723  #define page_to_phys(page)     ((page - mem_map) << PAGE_SHIFT)
5724  #endif
5725 +#endif
5726
5727  #define IO_SPACE_LIMIT 0xffff
5728
5729 diff -urN linux.old/include/asm-mips/irq.h linux.dev/include/asm-mips/irq.h
5730 --- linux.old/include/asm-mips/irq.h    2005-07-26 18:18:16.284577904 +0200
5731 +++ linux.dev/include/asm-mips/irq.h    2005-07-26 18:11:02.652500000 +0200
5732 @@ -14,7 +14,12 @@
5733  #include <linux/config.h>
5734  #include <linux/linkage.h>
5735
5736 +#ifdef CONFIG_AR7
5737 +#include <asm/ar7/avalanche_intc.h>
5738 +#define NR_IRQS AVALANCHE_INT_END + 1
5739 +#else
5740  #define NR_IRQS 128            /* Largest number of ints of all machines.  */
5741 +#endif
5742
5743  #ifdef CONFIG_I8259
5744  static inline int irq_cannonicalize(int irq)
5745 diff -urN linux.old/include/asm-mips/page.h linux.dev/include/asm-mips/page.h
5746 --- linux.old/include/asm-mips/page.h   2005-07-26 18:18:16.284577904 +0200
5747 +++ linux.dev/include/asm-mips/page.h   2005-07-26 18:11:02.652500000 +0200
5748 @@ -129,7 +129,11 @@
5749
5750  #define __pa(x)                ((unsigned long) (x) - PAGE_OFFSET)
5751  #define __va(x)                ((void *)((unsigned long) (x) + PAGE_OFFSET))
5752 +#ifdef CONFIG_AR7_PAGING
5753 +#define virt_to_page(kaddr)    phys_to_page(__pa(kaddr))
5754 +#else
5755  #define virt_to_page(kaddr)    (mem_map + (__pa(kaddr) >> PAGE_SHIFT))
5756 +#endif
5757  #define VALID_PAGE(page)       ((page - mem_map) < max_mapnr)
5758
5759  #define VM_DATA_DEFAULT_FLAGS  (VM_READ | VM_WRITE | VM_EXEC | \
5760 diff -urN linux.old/include/asm-mips/pgtable-32.h linux.dev/include/asm-mips/pgtable-32.h
5761 --- linux.old/include/asm-mips/pgtable-32.h     2005-07-26 18:18:16.284577904 +0200
5762 +++ linux.dev/include/asm-mips/pgtable-32.h     2005-07-26 18:11:02.653499000 +0200
5763 @@ -108,7 +108,18 @@
5764   * and a page entry and page directory to the page they refer to.
5765   */
5766
5767 -#ifdef CONFIG_CPU_VR41XX
5768 +#if defined(CONFIG_AR7_PAGING)
5769 +#define mk_pte(page, pgprot)                                           \
5770 +({                                                                     \
5771 +       pte_t   __pte;                                                  \
5772 +                                                                       \
5773 +       pte_val(__pte) = ((phys_t)(page - mem_map) << (PAGE_SHIFT) |    \
5774 +               CONFIG_AR7_MEMORY) |                                    \
5775 +       pgprot_val(pgprot);                                             \
5776 +                                                                       \
5777 +       __pte;                                                          \
5778 +})
5779 +#elif defined(CONFIG_CPU_VR41XX)
5780  #define mk_pte(page, pgprot)                                            \
5781  ({                                                                      \
5782          pte_t   __pte;                                                  \
5783 @@ -130,6 +141,7 @@
5784  })
5785  #endif
5786
5787 +
5788  static inline pte_t mk_pte_phys(phys_t physpage, pgprot_t pgprot)
5789  {
5790  #ifdef CONFIG_CPU_VR41XX
5791 @@ -175,7 +187,10 @@
5792                 set_pte(ptep, __pte(0));
5793  }
5794
5795 -#ifdef CONFIG_CPU_VR41XX
5796 +#if defined(CONFIG_AR7_PAGING)
5797 +#define phys_to_page(phys)     (mem_map + (((phys)-CONFIG_AR7_MEMORY) >> PAGE_SHIFT))
5798 +#define pte_page(x)            phys_to_page(pte_val(x))
5799 +#elif defined(CONFIG_CPU_VR41XX)
5800  #define pte_page(x)  (mem_map+((unsigned long)(((x).pte_low >> (PAGE_SHIFT+2)))))
5801  #define __mk_pte(page_nr,pgprot) __pte(((page_nr) << (PAGE_SHIFT+2)) | pgprot_val(pgprot))
5802  #else
5803 diff -urN linux.old/include/asm-mips/serial.h linux.dev/include/asm-mips/serial.h
5804 --- linux.old/include/asm-mips/serial.h 2005-07-26 18:18:16.285577752 +0200
5805 +++ linux.dev/include/asm-mips/serial.h 2005-07-26 18:11:02.654499000 +0200
5806 @@ -65,6 +65,15 @@
5807
5808  #define C_P(card,port) (((card)<<6|(port)<<3) + 1)
5809
5810 +#ifdef CONFIG_AR7
5811 +#include <asm/ar7/ar7.h>
5812 +#define AR7_SERIAL_PORT_DEFNS  \
5813 +       { 0, AR7_BASE_BAUD, AR7_UART0_REGS_BASE, LNXINTNUM(AVALANCHE_UART0_INT), STD_COM_FLAGS }, \
5814 +       { 0, AR7_BASE_BAUD, AR7_UART1_REGS_BASE, LNXINTNUM(AVALANCHE_UART1_INT), STD_COM_FLAGS },
5815 +#else
5816 +#define AR7_SERIAL_PORT_DEFNS
5817 +#endif
5818 +
5819  #ifdef CONFIG_MIPS_JAZZ
5820  #define _JAZZ_SERIAL_INIT(int, base)                                   \
5821         { .baud_base = JAZZ_BASE_BAUD, .irq = int, .flags = STD_COM_FLAGS,      \
5822 @@ -468,6 +477,7 @@
5823  #endif
5824
5825  #define SERIAL_PORT_DFNS                       \
5826 +       AR7_SERIAL_PORT_DEFNS                   \
5827         ATLAS_SERIAL_PORT_DEFNS                 \
5828         AU1000_SERIAL_PORT_DEFNS                \
5829         COBALT_SERIAL_PORT_DEFNS                \