d1d2ff28db3ca6639f072e9917b7635b5cb5aa2d
[15.05/openwrt.git] / target / linux / lantiq / patches-3.8 / 0014-PINCTRL-lantiq-fix-pin-availability-check.patch
1 From 51d5029bd9cd0ff85e1df87a4df57e544c52dc34 Mon Sep 17 00:00:00 2001
2 From: John Crispin <blogic@openwrt.org>
3 Date: Wed, 30 Jan 2013 20:16:22 +0100
4 Subject: [PATCH 14/40] PINCTRL: lantiq: fix pin availability check
5
6 The clock needs to be activated for the check to work. In order to be compatible
7 with future silicon make sure that at least 1 pin is available before probing
8 the pad controller.
9
10 Signed-off-by: Thomas Langer <thomas.langer@lantiq.com>
11 Signed-off-by: John Crispin <blogic@openwrt.org>
12 ---
13  drivers/pinctrl/pinctrl-falcon.c |   11 ++++++++---
14  1 file changed, 8 insertions(+), 3 deletions(-)
15
16 diff --git a/drivers/pinctrl/pinctrl-falcon.c b/drivers/pinctrl/pinctrl-falcon.c
17 index 4a0d54a..de9d1db 100644
18 --- a/drivers/pinctrl/pinctrl-falcon.c
19 +++ b/drivers/pinctrl/pinctrl-falcon.c
20 @@ -455,12 +455,17 @@ static int pinctrl_falcon_probe(struct platform_device *pdev)
21                                 *bank);
22                         return -ENOMEM;
23                 }
24 +               clk_activate(falcon_info.clk[*bank]);
25                 avail = pad_r32(falcon_info.membase[*bank],
26                                         LTQ_PADC_AVAIL);
27                 pins = fls(avail);
28 -               lantiq_load_pin_desc(&falcon_pads[pad_count], *bank, pins);
29 -               pad_count += pins;
30 -               clk_enable(falcon_info.clk[*bank]);
31 +               if (pins) {
32 +                       lantiq_load_pin_desc(&falcon_pads[pad_count],
33 +                                                               *bank, pins);
34 +                       pad_count += pins;
35 +               } else {
36 +                       clk_deactivate(falcon_info.clk[*bank]);
37 +               }
38                 dev_dbg(&pdev->dev, "found %s with %d pads\n",
39                                 res.name, pins);
40         }
41 -- 
42 1.7.10.4
43