target/linux/lantiq/patches-3.7/0301-gptu.patch

   1 --- /dev/null
   2 +++ b/arch/mips/lantiq/xway/timer.c
   3 @@ -0,0 +1,841 @@
   4 +#include <linux/kernel.h>
   5 +#include <linux/module.h>
   6 +#include <linux/version.h>
   7 +#include <linux/types.h>
   8 +#include <linux/fs.h>
   9 +#include <linux/miscdevice.h>
  10 +#include <linux/init.h>
  11 +#include <linux/uaccess.h>
  12 +#include <linux/unistd.h>
  13 +#include <linux/errno.h>
  14 +#include <linux/interrupt.h>
  15 +#include <linux/sched.h>
  16 +
  17 +#include <asm/irq.h>
  18 +#include <asm/div64.h>
  19 +#include "../clk.h"
  20 +
  21 +#include <lantiq_soc.h>
  22 +#include <lantiq_irq.h>
  23 +#include <lantiq_timer.h>
  24 +
  25 +#define MAX_NUM_OF_32BIT_TIMER_BLOCKS  6
  26 +
  27 +#ifdef TIMER1A
  28 +#define FIRST_TIMER                    TIMER1A
  29 +#else
  30 +#define FIRST_TIMER                    2
  31 +#endif
  32 +
  33 +/*
  34 + *  GPTC divider is set or not.
  35 + */
  36 +#define GPTU_CLC_RMC_IS_SET            0
  37 +
  38 +/*
  39 + *  Timer Interrupt (IRQ)
  40 + */
  41 +/*  Must be adjusted when ICU driver is available */
  42 +#define TIMER_INTERRUPT                        (INT_NUM_IM3_IRL0 + 22)
  43 +
  44 +/*
  45 + *  Bits Operation
  46 + */
  47 +#define GET_BITS(x, msb, lsb)          \
  48 +       (((x) & ((1 << ((msb) + 1)) - 1)) >> (lsb))
  49 +#define SET_BITS(x, msb, lsb, value)   \
  50 +       (((x) & ~(((1 << ((msb) + 1)) - 1) ^ ((1 << (lsb)) - 1))) | \
  51 +       (((value) & ((1 << (1 + (msb) - (lsb))) - 1)) << (lsb)))
  52 +
  53 +/*
  54 + *  GPTU Register Mapping
  55 + */
  56 +#define LQ_GPTU                        (KSEG1 + 0x1E100A00)
  57 +#define LQ_GPTU_CLC            ((volatile u32 *)(LQ_GPTU + 0x0000))
  58 +#define LQ_GPTU_ID                     ((volatile u32 *)(LQ_GPTU + 0x0008))
  59 +#define LQ_GPTU_CON(n, X)              ((volatile u32 *)(LQ_GPTU + 0x0010 + ((X) * 4) + ((n) - 1) * 0x0020))   /* X must be either A or B */
  60 +#define LQ_GPTU_RUN(n, X)              ((volatile u32 *)(LQ_GPTU + 0x0018 + ((X) * 4) + ((n) - 1) * 0x0020))   /* X must be either A or B */
  61 +#define LQ_GPTU_RELOAD(n, X)   ((volatile u32 *)(LQ_GPTU + 0x0020 + ((X) * 4) + ((n) - 1) * 0x0020))   /* X must be either A or B */
  62 +#define LQ_GPTU_COUNT(n, X)    ((volatile u32 *)(LQ_GPTU + 0x0028 + ((X) * 4) + ((n) - 1) * 0x0020))   /* X must be either A or B */
  63 +#define LQ_GPTU_IRNEN          ((volatile u32 *)(LQ_GPTU + 0x00F4))
  64 +#define LQ_GPTU_IRNICR         ((volatile u32 *)(LQ_GPTU + 0x00F8))
  65 +#define LQ_GPTU_IRNCR          ((volatile u32 *)(LQ_GPTU + 0x00FC))
  66 +
  67 +/*
  68 + *  Clock Control Register
  69 + */
  70 +#define GPTU_CLC_SMC                   GET_BITS(*LQ_GPTU_CLC, 23, 16)
  71 +#define GPTU_CLC_RMC                   GET_BITS(*LQ_GPTU_CLC, 15, 8)
  72 +#define GPTU_CLC_FSOE                  (*LQ_GPTU_CLC & (1 << 5))
  73 +#define GPTU_CLC_EDIS                  (*LQ_GPTU_CLC & (1 << 3))
  74 +#define GPTU_CLC_SPEN                  (*LQ_GPTU_CLC & (1 << 2))
  75 +#define GPTU_CLC_DISS                  (*LQ_GPTU_CLC & (1 << 1))
  76 +#define GPTU_CLC_DISR                  (*LQ_GPTU_CLC & (1 << 0))
  77 +
  78 +#define GPTU_CLC_SMC_SET(value)                SET_BITS(0, 23, 16, (value))
  79 +#define GPTU_CLC_RMC_SET(value)                SET_BITS(0, 15, 8, (value))
  80 +#define GPTU_CLC_FSOE_SET(value)       ((value) ? (1 << 5) : 0)
  81 +#define GPTU_CLC_SBWE_SET(value)       ((value) ? (1 << 4) : 0)
  82 +#define GPTU_CLC_EDIS_SET(value)       ((value) ? (1 << 3) : 0)
  83 +#define GPTU_CLC_SPEN_SET(value)       ((value) ? (1 << 2) : 0)
  84 +#define GPTU_CLC_DISR_SET(value)       ((value) ? (1 << 0) : 0)
  85 +
  86 +/*
  87 + *  ID Register
  88 + */
  89 +#define GPTU_ID_ID                     GET_BITS(*LQ_GPTU_ID, 15, 8)
  90 +#define GPTU_ID_CFG                    GET_BITS(*LQ_GPTU_ID, 7, 5)
  91 +#define GPTU_ID_REV                    GET_BITS(*LQ_GPTU_ID, 4, 0)
  92 +
  93 +/*
  94 + *  Control Register of Timer/Counter nX
  95 + *    n is the index of block (1 based index)
  96 + *    X is either A or B
  97 + */
  98 +#define GPTU_CON_SRC_EG(n, X)          (*LQ_GPTU_CON(n, X) & (1 << 10))
  99 +#define GPTU_CON_SRC_EXT(n, X)         (*LQ_GPTU_CON(n, X) & (1 << 9))
 100 +#define GPTU_CON_SYNC(n, X)            (*LQ_GPTU_CON(n, X) & (1 << 8))
 101 +#define GPTU_CON_EDGE(n, X)            GET_BITS(*LQ_GPTU_CON(n, X), 7, 6)
 102 +#define GPTU_CON_INV(n, X)             (*LQ_GPTU_CON(n, X) & (1 << 5))
 103 +#define GPTU_CON_EXT(n, X)             (*LQ_GPTU_CON(n, A) & (1 << 4)) /* Timer/Counter B does not have this bit */
 104 +#define GPTU_CON_STP(n, X)             (*LQ_GPTU_CON(n, X) & (1 << 3))
 105 +#define GPTU_CON_CNT(n, X)             (*LQ_GPTU_CON(n, X) & (1 << 2))
 106 +#define GPTU_CON_DIR(n, X)             (*LQ_GPTU_CON(n, X) & (1 << 1))
 107 +#define GPTU_CON_EN(n, X)              (*LQ_GPTU_CON(n, X) & (1 << 0))
 108 +
 109 +#define GPTU_CON_SRC_EG_SET(value)     ((value) ? 0 : (1 << 10))
 110 +#define GPTU_CON_SRC_EXT_SET(value)    ((value) ? (1 << 9) : 0)
 111 +#define GPTU_CON_SYNC_SET(value)       ((value) ? (1 << 8) : 0)
 112 +#define GPTU_CON_EDGE_SET(value)       SET_BITS(0, 7, 6, (value))
 113 +#define GPTU_CON_INV_SET(value)                ((value) ? (1 << 5) : 0)
 114 +#define GPTU_CON_EXT_SET(value)                ((value) ? (1 << 4) : 0)
 115 +#define GPTU_CON_STP_SET(value)                ((value) ? (1 << 3) : 0)
 116 +#define GPTU_CON_CNT_SET(value)                ((value) ? (1 << 2) : 0)
 117 +#define GPTU_CON_DIR_SET(value)                ((value) ? (1 << 1) : 0)
 118 +
 119 +#define GPTU_RUN_RL_SET(value)         ((value) ? (1 << 2) : 0)
 120 +#define GPTU_RUN_CEN_SET(value)                ((value) ? (1 << 1) : 0)
 121 +#define GPTU_RUN_SEN_SET(value)                ((value) ? (1 << 0) : 0)
 122 +
 123 +#define GPTU_IRNEN_TC_SET(n, X, value) ((value) ? (1 << (((n) - 1) * 2 + (X))) : 0)
 124 +#define GPTU_IRNCR_TC_SET(n, X, value) ((value) ? (1 << (((n) - 1) * 2 + (X))) : 0)
 125 +
 126 +#define TIMER_FLAG_MASK_SIZE(x)                (x & 0x0001)
 127 +#define TIMER_FLAG_MASK_TYPE(x)                (x & 0x0002)
 128 +#define TIMER_FLAG_MASK_STOP(x)                (x & 0x0004)
 129 +#define TIMER_FLAG_MASK_DIR(x)         (x & 0x0008)
 130 +#define TIMER_FLAG_NONE_EDGE           0x0000
 131 +#define TIMER_FLAG_MASK_EDGE(x)                (x & 0x0030)
 132 +#define TIMER_FLAG_REAL                        0x0000
 133 +#define TIMER_FLAG_INVERT              0x0040
 134 +#define TIMER_FLAG_MASK_INVERT(x)      (x & 0x0040)
 135 +#define TIMER_FLAG_MASK_TRIGGER(x)     (x & 0x0070)
 136 +#define TIMER_FLAG_MASK_SYNC(x)                (x & 0x0080)
 137 +#define TIMER_FLAG_CALLBACK_IN_HB      0x0200
 138 +#define TIMER_FLAG_MASK_HANDLE(x)      (x & 0x0300)
 139 +#define TIMER_FLAG_MASK_SRC(x)         (x & 0x1000)
 140 +
 141 +struct timer_dev_timer {
 142 +       unsigned int f_irq_on;
 143 +       unsigned int irq;
 144 +       unsigned int flag;
 145 +       unsigned long arg1;
 146 +       unsigned long arg2;
 147 +};
 148 +
 149 +struct timer_dev {
 150 +       struct mutex gptu_mutex;
 151 +       unsigned int number_of_timers;
 152 +       unsigned int occupation;
 153 +       unsigned int f_gptu_on;
 154 +       struct timer_dev_timer timer[MAX_NUM_OF_32BIT_TIMER_BLOCKS * 2];
 155 +};
 156 +
 157 +
 158 +unsigned int ltq_get_fpi_bus_clock(int fpi) {
 159 +       struct clk *clk = clk_get_fpi();
 160 +       return clk_get_rate(clk);
 161 +}
 162 +
 163 +
 164 +static long gptu_ioctl(struct file *, unsigned int, unsigned long);
 165 +static int gptu_open(struct inode *, struct file *);
 166 +static int gptu_release(struct inode *, struct file *);
 167 +
 168 +static struct file_operations gptu_fops = {
 169 +       .owner = THIS_MODULE,
 170 +       .unlocked_ioctl = gptu_ioctl,
 171 +       .open = gptu_open,
 172 +       .release = gptu_release
 173 +};
 174 +
 175 +static struct miscdevice gptu_miscdev = {
 176 +       .minor = MISC_DYNAMIC_MINOR,
 177 +       .name = "gptu",
 178 +       .fops = &gptu_fops,
 179 +};
 180 +
 181 +static struct timer_dev timer_dev;
 182 +
 183 +static irqreturn_t timer_irq_handler(int irq, void *p)
 184 +{
 185 +       unsigned int timer;
 186 +       unsigned int flag;
 187 +       struct timer_dev_timer *dev_timer = (struct timer_dev_timer *)p;
 188 +
 189 +       timer = irq - TIMER_INTERRUPT;
 190 +       if (timer < timer_dev.number_of_timers
 191 +               && dev_timer == &timer_dev.timer[timer]) {
 192 +               /*  Clear interrupt.    */
 193 +               ltq_w32(1 << timer, LQ_GPTU_IRNCR);
 194 +
 195 +               /*  Call user hanler or signal. */
 196 +               flag = dev_timer->flag;
 197 +               if (!(timer & 0x01)
 198 +                       || TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT) {
 199 +                       /* 16-bit timer or timer A of 32-bit timer  */
 200 +                       switch (TIMER_FLAG_MASK_HANDLE(flag)) {
 201 +                       case TIMER_FLAG_CALLBACK_IN_IRQ:
 202 +                       case TIMER_FLAG_CALLBACK_IN_HB:
 203 +                               if (dev_timer->arg1)
 204 +                                       (*(timer_callback)dev_timer->arg1)(dev_timer->arg2);
 205 +                               break;
 206 +                       case TIMER_FLAG_SIGNAL:
 207 +                               send_sig((int)dev_timer->arg2, (struct task_struct *)dev_timer->arg1, 0);
 208 +                               break;
 209 +                       }
 210 +               }
 211 +       }
 212 +       return IRQ_HANDLED;
 213 +}
 214 +
 215 +static inline void lq_enable_gptu(void)
 216 +{
 217 +       struct clk *clk = clk_get_sys("1e100a00.gptu", NULL);
 218 +       clk_enable(clk);
 219 +
 220 +       //ltq_pmu_enable(PMU_GPT);
 221 +
 222 +       /*  Set divider as 1, disable write protection for SPEN, enable module. */
 223 +       *LQ_GPTU_CLC =
 224 +               GPTU_CLC_SMC_SET(0x00) |
 225 +               GPTU_CLC_RMC_SET(0x01) |
 226 +               GPTU_CLC_FSOE_SET(0) |
 227 +               GPTU_CLC_SBWE_SET(1) |
 228 +               GPTU_CLC_EDIS_SET(0) |
 229 +               GPTU_CLC_SPEN_SET(0) |
 230 +               GPTU_CLC_DISR_SET(0);
 231 +}
 232 +
 233 +static inline void lq_disable_gptu(void)
 234 +{
 235 +       struct clk *clk = clk_get_sys("1e100a00.gptu", NULL);
 236 +       ltq_w32(0x00, LQ_GPTU_IRNEN);
 237 +       ltq_w32(0xfff, LQ_GPTU_IRNCR);
 238 +
 239 +       /*  Set divider as 0, enable write protection for SPEN, disable module. */
 240 +       *LQ_GPTU_CLC =
 241 +               GPTU_CLC_SMC_SET(0x00) |
 242 +               GPTU_CLC_RMC_SET(0x00) |
 243 +               GPTU_CLC_FSOE_SET(0) |
 244 +               GPTU_CLC_SBWE_SET(0) |
 245 +               GPTU_CLC_EDIS_SET(0) |
 246 +               GPTU_CLC_SPEN_SET(0) |
 247 +               GPTU_CLC_DISR_SET(1);
 248 +
 249 +       clk_enable(clk);
 250 +}
 251 +
 252 +int lq_request_timer(unsigned int timer, unsigned int flag,
 253 +       unsigned long value, unsigned long arg1, unsigned long arg2)
 254 +{
 255 +       int ret = 0;
 256 +       unsigned int con_reg, irnen_reg;
 257 +       int n, X;
 258 +
 259 +       if (timer >= FIRST_TIMER + timer_dev.number_of_timers)
 260 +               return -EINVAL;
 261 +
 262 +       printk(KERN_INFO "request_timer(%d, 0x%08X, %lu)...",
 263 +               timer, flag, value);
 264 +
 265 +       if (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT)
 266 +               value &= 0xFFFF;
 267 +       else
 268 +               timer &= ~0x01;
 269 +
 270 +       mutex_lock(&timer_dev.gptu_mutex);
 271 +
 272 +       /*
 273 +        *  Allocate timer.
 274 +        */
 275 +       if (timer < FIRST_TIMER) {
 276 +               unsigned int mask;
 277 +               unsigned int shift;
 278 +               /* This takes care of TIMER1B which is the only choice for Voice TAPI system */
 279 +               unsigned int offset = TIMER2A;
 280 +
 281 +               /*
 282 +                *  Pick up a free timer.
 283 +                */
 284 +               if (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT) {
 285 +                       mask = 1 << offset;
 286 +                       shift = 1;
 287 +               } else {
 288 +                       mask = 3 << offset;
 289 +                       shift = 2;
 290 +               }
 291 +               for (timer = offset;
 292 +                    timer < offset + timer_dev.number_of_timers;
 293 +                    timer += shift, mask <<= shift)
 294 +                       if (!(timer_dev.occupation & mask)) {
 295 +                               timer_dev.occupation |= mask;
 296 +                               break;
 297 +                       }
 298 +               if (timer >= offset + timer_dev.number_of_timers) {
 299 +                       printk("failed![%d]\n", __LINE__);
 300 +                       mutex_unlock(&timer_dev.gptu_mutex);
 301 +                       return -EINVAL;
 302 +               } else
 303 +                       ret = timer;
 304 +       } else {
 305 +               register unsigned int mask;
 306 +
 307 +               /*
 308 +                *  Check if the requested timer is free.
 309 +                */
 310 +               mask = (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT ? 1 : 3) << timer;
 311 +               if ((timer_dev.occupation & mask)) {
 312 +                       printk("failed![%d] mask %#x, timer_dev.occupation %#x\n",
 313 +                               __LINE__, mask, timer_dev.occupation);
 314 +                       mutex_unlock(&timer_dev.gptu_mutex);
 315 +                       return -EBUSY;
 316 +               } else {
 317 +                       timer_dev.occupation |= mask;
 318 +                       ret = 0;
 319 +               }
 320 +       }
 321 +
 322 +       /*
 323 +        *  Prepare control register value.
 324 +        */
 325 +       switch (TIMER_FLAG_MASK_EDGE(flag)) {
 326 +       default:
 327 +       case TIMER_FLAG_NONE_EDGE:
 328 +               con_reg = GPTU_CON_EDGE_SET(0x00);
 329 +               break;
 330 +       case TIMER_FLAG_RISE_EDGE:
 331 +               con_reg = GPTU_CON_EDGE_SET(0x01);
 332 +               break;
 333 +       case TIMER_FLAG_FALL_EDGE:
 334 +               con_reg = GPTU_CON_EDGE_SET(0x02);
 335 +               break;
 336 +       case TIMER_FLAG_ANY_EDGE:
 337 +               con_reg = GPTU_CON_EDGE_SET(0x03);
 338 +               break;
 339 +       }
 340 +       if (TIMER_FLAG_MASK_TYPE(flag) == TIMER_FLAG_TIMER)
 341 +               con_reg |=
 342 +                       TIMER_FLAG_MASK_SRC(flag) ==
 343 +                       TIMER_FLAG_EXT_SRC ? GPTU_CON_SRC_EXT_SET(1) :
 344 +                       GPTU_CON_SRC_EXT_SET(0);
 345 +       else
 346 +               con_reg |=
 347 +                       TIMER_FLAG_MASK_SRC(flag) ==
 348 +                       TIMER_FLAG_EXT_SRC ? GPTU_CON_SRC_EG_SET(1) :
 349 +                       GPTU_CON_SRC_EG_SET(0);
 350 +       con_reg |=
 351 +               TIMER_FLAG_MASK_SYNC(flag) ==
 352 +               TIMER_FLAG_UNSYNC ? GPTU_CON_SYNC_SET(0) :
 353 +               GPTU_CON_SYNC_SET(1);
 354 +       con_reg |=
 355 +               TIMER_FLAG_MASK_INVERT(flag) ==
 356 +               TIMER_FLAG_REAL ? GPTU_CON_INV_SET(0) : GPTU_CON_INV_SET(1);
 357 +       con_reg |=
 358 +               TIMER_FLAG_MASK_SIZE(flag) ==
 359 +               TIMER_FLAG_16BIT ? GPTU_CON_EXT_SET(0) :
 360 +               GPTU_CON_EXT_SET(1);
 361 +       con_reg |=
 362 +               TIMER_FLAG_MASK_STOP(flag) ==
 363 +               TIMER_FLAG_ONCE ? GPTU_CON_STP_SET(1) : GPTU_CON_STP_SET(0);
 364 +       con_reg |=
 365 +               TIMER_FLAG_MASK_TYPE(flag) ==
 366 +               TIMER_FLAG_TIMER ? GPTU_CON_CNT_SET(0) :
 367 +               GPTU_CON_CNT_SET(1);
 368 +       con_reg |=
 369 +               TIMER_FLAG_MASK_DIR(flag) ==
 370 +               TIMER_FLAG_UP ? GPTU_CON_DIR_SET(1) : GPTU_CON_DIR_SET(0);
 371 +
 372 +       /*
 373 +        *  Fill up running data.
 374 +        */
 375 +       timer_dev.timer[timer - FIRST_TIMER].flag = flag;
 376 +       timer_dev.timer[timer - FIRST_TIMER].arg1 = arg1;
 377 +       timer_dev.timer[timer - FIRST_TIMER].arg2 = arg2;
 378 +       if (TIMER_FLAG_MASK_SIZE(flag) != TIMER_FLAG_16BIT)
 379 +               timer_dev.timer[timer - FIRST_TIMER + 1].flag = flag;
 380 +
 381 +       /*
 382 +        *  Enable GPTU module.
 383 +        */
 384 +       if (!timer_dev.f_gptu_on) {
 385 +               lq_enable_gptu();
 386 +               timer_dev.f_gptu_on = 1;
 387 +       }
 388 +
 389 +       /*
 390 +        *  Enable IRQ.
 391 +        */
 392 +       if (TIMER_FLAG_MASK_HANDLE(flag) != TIMER_FLAG_NO_HANDLE) {
 393 +               if (TIMER_FLAG_MASK_HANDLE(flag) == TIMER_FLAG_SIGNAL)
 394 +                       timer_dev.timer[timer - FIRST_TIMER].arg1 =
 395 +                               (unsigned long) find_task_by_vpid((int) arg1);
 396 +
 397 +               irnen_reg = 1 << (timer - FIRST_TIMER);
 398 +
 399 +               if (TIMER_FLAG_MASK_HANDLE(flag) == TIMER_FLAG_SIGNAL
 400 +                   || (TIMER_FLAG_MASK_HANDLE(flag) ==
 401 +                       TIMER_FLAG_CALLBACK_IN_IRQ
 402 +                       && timer_dev.timer[timer - FIRST_TIMER].arg1)) {
 403 +                       enable_irq(timer_dev.timer[timer - FIRST_TIMER].irq);
 404 +                       timer_dev.timer[timer - FIRST_TIMER].f_irq_on = 1;
 405 +               }
 406 +       } else
 407 +               irnen_reg = 0;
 408 +
 409 +       /*
 410 +        *  Write config register, reload value and enable interrupt.
 411 +        */
 412 +       n = timer >> 1;
 413 +       X = timer & 0x01;
 414 +       *LQ_GPTU_CON(n, X) = con_reg;
 415 +       *LQ_GPTU_RELOAD(n, X) = value;
 416 +       /* printk("reload value = %d\n", (u32)value); */
 417 +       *LQ_GPTU_IRNEN |= irnen_reg;
 418 +
 419 +       mutex_unlock(&timer_dev.gptu_mutex);
 420 +       printk("successful!\n");
 421 +       return ret;
 422 +}
 423 +EXPORT_SYMBOL(lq_request_timer);
 424 +
 425 +int lq_free_timer(unsigned int timer)
 426 +{
 427 +       unsigned int flag;
 428 +       unsigned int mask;
 429 +       int n, X;
 430 +
 431 +       if (!timer_dev.f_gptu_on)
 432 +               return -EINVAL;
 433 +
 434 +       if (timer < FIRST_TIMER || timer >= FIRST_TIMER + timer_dev.number_of_timers)
 435 +               return -EINVAL;
 436 +
 437 +       mutex_lock(&timer_dev.gptu_mutex);
 438 +
 439 +       flag = timer_dev.timer[timer - FIRST_TIMER].flag;
 440 +       if (TIMER_FLAG_MASK_SIZE(flag) != TIMER_FLAG_16BIT)
 441 +               timer &= ~0x01;
 442 +
 443 +       mask = (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT ? 1 : 3) << timer;
 444 +       if (((timer_dev.occupation & mask) ^ mask)) {
 445 +               mutex_unlock(&timer_dev.gptu_mutex);
 446 +               return -EINVAL;
 447 +       }
 448 +
 449 +       n = timer >> 1;
 450 +       X = timer & 0x01;
 451 +
 452 +       if (GPTU_CON_EN(n, X))
 453 +               *LQ_GPTU_RUN(n, X) = GPTU_RUN_CEN_SET(1);
 454 +
 455 +       *LQ_GPTU_IRNEN &= ~GPTU_IRNEN_TC_SET(n, X, 1);
 456 +       *LQ_GPTU_IRNCR |= GPTU_IRNCR_TC_SET(n, X, 1);
 457 +
 458 +       if (timer_dev.timer[timer - FIRST_TIMER].f_irq_on) {
 459 +               disable_irq(timer_dev.timer[timer - FIRST_TIMER].irq);
 460 +               timer_dev.timer[timer - FIRST_TIMER].f_irq_on = 0;
 461 +       }
 462 +
 463 +       timer_dev.occupation &= ~mask;
 464 +       if (!timer_dev.occupation && timer_dev.f_gptu_on) {
 465 +               lq_disable_gptu();
 466 +               timer_dev.f_gptu_on = 0;
 467 +       }
 468 +
 469 +       mutex_unlock(&timer_dev.gptu_mutex);
 470 +
 471 +       return 0;
 472 +}
 473 +EXPORT_SYMBOL(lq_free_timer);
 474 +
 475 +int lq_start_timer(unsigned int timer, int is_resume)
 476 +{
 477 +       unsigned int flag;
 478 +       unsigned int mask;
 479 +       int n, X;
 480 +
 481 +       if (!timer_dev.f_gptu_on)
 482 +               return -EINVAL;
 483 +
 484 +       if (timer < FIRST_TIMER || timer >= FIRST_TIMER + timer_dev.number_of_timers)
 485 +               return -EINVAL;
 486 +
 487 +       mutex_lock(&timer_dev.gptu_mutex);
 488 +
 489 +       flag = timer_dev.timer[timer - FIRST_TIMER].flag;
 490 +       if (TIMER_FLAG_MASK_SIZE(flag) != TIMER_FLAG_16BIT)
 491 +               timer &= ~0x01;
 492 +
 493 +       mask = (TIMER_FLAG_MASK_SIZE(flag) ==
 494 +       TIMER_FLAG_16BIT ? 1 : 3) << timer;
 495 +       if (((timer_dev.occupation & mask) ^ mask)) {
 496 +               mutex_unlock(&timer_dev.gptu_mutex);
 497 +               return -EINVAL;
 498 +       }
 499 +
 500 +       n = timer >> 1;
 501 +       X = timer & 0x01;
 502 +
 503 +       *LQ_GPTU_RUN(n, X) = GPTU_RUN_RL_SET(!is_resume) | GPTU_RUN_SEN_SET(1);
 504 +
 505 +
 506 +       mutex_unlock(&timer_dev.gptu_mutex);
 507 +
 508 +       return 0;
 509 +}
 510 +EXPORT_SYMBOL(lq_start_timer);
 511 +
 512 +int lq_stop_timer(unsigned int timer)
 513 +{
 514 +       unsigned int flag;
 515 +       unsigned int mask;
 516 +       int n, X;
 517 +
 518 +       if (!timer_dev.f_gptu_on)
 519 +               return -EINVAL;
 520 +
 521 +       if (timer < FIRST_TIMER
 522 +           || timer >= FIRST_TIMER + timer_dev.number_of_timers)
 523 +               return -EINVAL;
 524 +
 525 +       mutex_lock(&timer_dev.gptu_mutex);
 526 +
 527 +       flag = timer_dev.timer[timer - FIRST_TIMER].flag;
 528 +       if (TIMER_FLAG_MASK_SIZE(flag) != TIMER_FLAG_16BIT)
 529 +               timer &= ~0x01;
 530 +
 531 +       mask = (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT ? 1 : 3) << timer;
 532 +       if (((timer_dev.occupation & mask) ^ mask)) {
 533 +               mutex_unlock(&timer_dev.gptu_mutex);
 534 +               return -EINVAL;
 535 +       }
 536 +
 537 +       n = timer >> 1;
 538 +       X = timer & 0x01;
 539 +
 540 +       *LQ_GPTU_RUN(n, X) = GPTU_RUN_CEN_SET(1);
 541 +
 542 +       mutex_unlock(&timer_dev.gptu_mutex);
 543 +
 544 +       return 0;
 545 +}
 546 +EXPORT_SYMBOL(lq_stop_timer);
 547 +
 548 +int lq_reset_counter_flags(u32 timer, u32 flags)
 549 +{
 550 +       unsigned int oflag;
 551 +       unsigned int mask, con_reg;
 552 +       int n, X;
 553 +
 554 +       if (!timer_dev.f_gptu_on)
 555 +               return -EINVAL;
 556 +
 557 +       if (timer < FIRST_TIMER || timer >= FIRST_TIMER + timer_dev.number_of_timers)
 558 +               return -EINVAL;
 559 +
 560 +       mutex_lock(&timer_dev.gptu_mutex);
 561 +
 562 +       oflag = timer_dev.timer[timer - FIRST_TIMER].flag;
 563 +       if (TIMER_FLAG_MASK_SIZE(oflag) != TIMER_FLAG_16BIT)
 564 +               timer &= ~0x01;
 565 +
 566 +       mask = (TIMER_FLAG_MASK_SIZE(oflag) == TIMER_FLAG_16BIT ? 1 : 3) << timer;
 567 +       if (((timer_dev.occupation & mask) ^ mask)) {
 568 +               mutex_unlock(&timer_dev.gptu_mutex);
 569 +               return -EINVAL;
 570 +       }
 571 +
 572 +       switch (TIMER_FLAG_MASK_EDGE(flags)) {
 573 +       default:
 574 +       case TIMER_FLAG_NONE_EDGE:
 575 +               con_reg = GPTU_CON_EDGE_SET(0x00);
 576 +               break;
 577 +       case TIMER_FLAG_RISE_EDGE:
 578 +               con_reg = GPTU_CON_EDGE_SET(0x01);
 579 +               break;
 580 +       case TIMER_FLAG_FALL_EDGE:
 581 +               con_reg = GPTU_CON_EDGE_SET(0x02);
 582 +               break;
 583 +       case TIMER_FLAG_ANY_EDGE:
 584 +               con_reg = GPTU_CON_EDGE_SET(0x03);
 585 +               break;
 586 +       }
 587 +       if (TIMER_FLAG_MASK_TYPE(flags) == TIMER_FLAG_TIMER)
 588 +               con_reg |= TIMER_FLAG_MASK_SRC(flags) == TIMER_FLAG_EXT_SRC ? GPTU_CON_SRC_EXT_SET(1) : GPTU_CON_SRC_EXT_SET(0);
 589 +       else
 590 +               con_reg |= TIMER_FLAG_MASK_SRC(flags) == TIMER_FLAG_EXT_SRC ? GPTU_CON_SRC_EG_SET(1) : GPTU_CON_SRC_EG_SET(0);
 591 +       con_reg |= TIMER_FLAG_MASK_SYNC(flags) == TIMER_FLAG_UNSYNC ? GPTU_CON_SYNC_SET(0) : GPTU_CON_SYNC_SET(1);
 592 +       con_reg |= TIMER_FLAG_MASK_INVERT(flags) == TIMER_FLAG_REAL ? GPTU_CON_INV_SET(0) : GPTU_CON_INV_SET(1);
 593 +       con_reg |= TIMER_FLAG_MASK_SIZE(flags) == TIMER_FLAG_16BIT ? GPTU_CON_EXT_SET(0) : GPTU_CON_EXT_SET(1);
 594 +       con_reg |= TIMER_FLAG_MASK_STOP(flags) == TIMER_FLAG_ONCE ? GPTU_CON_STP_SET(1) : GPTU_CON_STP_SET(0);
 595 +       con_reg |= TIMER_FLAG_MASK_TYPE(flags) == TIMER_FLAG_TIMER ? GPTU_CON_CNT_SET(0) : GPTU_CON_CNT_SET(1);
 596 +       con_reg |= TIMER_FLAG_MASK_DIR(flags) == TIMER_FLAG_UP ? GPTU_CON_DIR_SET(1) : GPTU_CON_DIR_SET(0);
 597 +
 598 +       timer_dev.timer[timer - FIRST_TIMER].flag = flags;
 599 +       if (TIMER_FLAG_MASK_SIZE(flags) != TIMER_FLAG_16BIT)
 600 +               timer_dev.timer[timer - FIRST_TIMER + 1].flag = flags;
 601 +
 602 +       n = timer >> 1;
 603 +       X = timer & 0x01;
 604 +
 605 +       *LQ_GPTU_CON(n, X) = con_reg;
 606 +       smp_wmb();
 607 +       mutex_unlock(&timer_dev.gptu_mutex);
 608 +       return 0;
 609 +}
 610 +EXPORT_SYMBOL(lq_reset_counter_flags);
 611 +
 612 +int lq_get_count_value(unsigned int timer, unsigned long *value)
 613 +{
 614 +       unsigned int flag;
 615 +       unsigned int mask;
 616 +       int n, X;
 617 +
 618 +       if (!timer_dev.f_gptu_on)
 619 +               return -EINVAL;
 620 +
 621 +       if (timer < FIRST_TIMER
 622 +           || timer >= FIRST_TIMER + timer_dev.number_of_timers)
 623 +               return -EINVAL;
 624 +
 625 +       mutex_lock(&timer_dev.gptu_mutex);
 626 +
 627 +       flag = timer_dev.timer[timer - FIRST_TIMER].flag;
 628 +       if (TIMER_FLAG_MASK_SIZE(flag) != TIMER_FLAG_16BIT)
 629 +               timer &= ~0x01;
 630 +
 631 +       mask = (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT ? 1 : 3) << timer;
 632 +       if (((timer_dev.occupation & mask) ^ mask)) {
 633 +               mutex_unlock(&timer_dev.gptu_mutex);
 634 +               return -EINVAL;
 635 +       }
 636 +
 637 +       n = timer >> 1;
 638 +       X = timer & 0x01;
 639 +
 640 +       *value = *LQ_GPTU_COUNT(n, X);
 641 +
 642 +
 643 +       mutex_unlock(&timer_dev.gptu_mutex);
 644 +
 645 +       return 0;
 646 +}
 647 +EXPORT_SYMBOL(lq_get_count_value);
 648 +
 649 +u32 lq_cal_divider(unsigned long freq)
 650 +{
 651 +       u64 module_freq, fpi = ltq_get_fpi_bus_clock(2);
 652 +       u32 clock_divider = 1;
 653 +       module_freq = fpi * 1000;
 654 +       do_div(module_freq, clock_divider * freq);
 655 +       return module_freq;
 656 +}
 657 +EXPORT_SYMBOL(lq_cal_divider);
 658 +
 659 +int lq_set_timer(unsigned int timer, unsigned int freq, int is_cyclic,
 660 +       int is_ext_src, unsigned int handle_flag, unsigned long arg1,
 661 +       unsigned long arg2)
 662 +{
 663 +       unsigned long divider;
 664 +       unsigned int flag;
 665 +
 666 +       divider = lq_cal_divider(freq);
 667 +       if (divider == 0)
 668 +               return -EINVAL;
 669 +       flag = ((divider & ~0xFFFF) ? TIMER_FLAG_32BIT : TIMER_FLAG_16BIT)
 670 +               | (is_cyclic ? TIMER_FLAG_CYCLIC : TIMER_FLAG_ONCE)
 671 +               | (is_ext_src ? TIMER_FLAG_EXT_SRC : TIMER_FLAG_INT_SRC)
 672 +               | TIMER_FLAG_TIMER | TIMER_FLAG_DOWN
 673 +               | TIMER_FLAG_MASK_HANDLE(handle_flag);
 674 +
 675 +       printk(KERN_INFO "lq_set_timer(%d, %d), divider = %lu\n",
 676 +               timer, freq, divider);
 677 +       return lq_request_timer(timer, flag, divider, arg1, arg2);
 678 +}
 679 +EXPORT_SYMBOL(lq_set_timer);
 680 +
 681 +int lq_set_counter(unsigned int timer, unsigned int flag, u32 reload,
 682 +       unsigned long arg1, unsigned long arg2)
 683 +{
 684 +       printk(KERN_INFO "lq_set_counter(%d, %#x, %d)\n", timer, flag, reload);
 685 +       return lq_request_timer(timer, flag, reload, arg1, arg2);
 686 +}
 687 +EXPORT_SYMBOL(lq_set_counter);
 688 +
 689 +static long gptu_ioctl(struct file *file, unsigned int cmd,
 690 +       unsigned long arg)
 691 +{
 692 +       int ret;
 693 +       struct gptu_ioctl_param param;
 694 +
 695 +       if (!access_ok(VERIFY_READ, arg, sizeof(struct gptu_ioctl_param)))
 696 +               return -EFAULT;
 697 +       copy_from_user(&param, (void *) arg, sizeof(param));
 698 +
 699 +       if ((((cmd == GPTU_REQUEST_TIMER || cmd == GPTU_SET_TIMER
 700 +              || GPTU_SET_COUNTER) && param.timer < 2)
 701 +            || cmd == GPTU_GET_COUNT_VALUE || cmd == GPTU_CALCULATE_DIVIDER)
 702 +           && !access_ok(VERIFY_WRITE, arg,
 703 +                          sizeof(struct gptu_ioctl_param)))
 704 +               return -EFAULT;
 705 +
 706 +       switch (cmd) {
 707 +       case GPTU_REQUEST_TIMER:
 708 +               ret = lq_request_timer(param.timer, param.flag, param.value,
 709 +                                    (unsigned long) param.pid,
 710 +                                    (unsigned long) param.sig);
 711 +               if (ret > 0) {
 712 +                       copy_to_user(&((struct gptu_ioctl_param *) arg)->
 713 +                                     timer, &ret, sizeof(&ret));
 714 +                       ret = 0;
 715 +               }
 716 +               break;
 717 +       case GPTU_FREE_TIMER:
 718 +               ret = lq_free_timer(param.timer);
 719 +               break;
 720 +       case GPTU_START_TIMER:
 721 +               ret = lq_start_timer(param.timer, param.flag);
 722 +               break;
 723 +       case GPTU_STOP_TIMER:
 724 +               ret = lq_stop_timer(param.timer);
 725 +               break;
 726 +       case GPTU_GET_COUNT_VALUE:
 727 +               ret = lq_get_count_value(param.timer, &param.value);
 728 +               if (!ret)
 729 +                       copy_to_user(&((struct gptu_ioctl_param *) arg)->
 730 +                                     value, &param.value,
 731 +                                     sizeof(param.value));
 732 +               break;
 733 +       case GPTU_CALCULATE_DIVIDER:
 734 +               param.value = lq_cal_divider(param.value);
 735 +               if (param.value == 0)
 736 +                       ret = -EINVAL;
 737 +               else {
 738 +                       copy_to_user(&((struct gptu_ioctl_param *) arg)->
 739 +                                     value, &param.value,
 740 +                                     sizeof(param.value));
 741 +                       ret = 0;
 742 +               }
 743 +               break;
 744 +       case GPTU_SET_TIMER:
 745 +               ret = lq_set_timer(param.timer, param.value,
 746 +                                TIMER_FLAG_MASK_STOP(param.flag) !=
 747 +                                TIMER_FLAG_ONCE ? 1 : 0,
 748 +                                TIMER_FLAG_MASK_SRC(param.flag) ==
 749 +                                TIMER_FLAG_EXT_SRC ? 1 : 0,
 750 +                                TIMER_FLAG_MASK_HANDLE(param.flag) ==
 751 +                                TIMER_FLAG_SIGNAL ? TIMER_FLAG_SIGNAL :
 752 +                                TIMER_FLAG_NO_HANDLE,
 753 +                                (unsigned long) param.pid,
 754 +                                (unsigned long) param.sig);
 755 +               if (ret > 0) {
 756 +                       copy_to_user(&((struct gptu_ioctl_param *) arg)->
 757 +                                     timer, &ret, sizeof(&ret));
 758 +                       ret = 0;
 759 +               }
 760 +               break;
 761 +       case GPTU_SET_COUNTER:
 762 +               lq_set_counter(param.timer, param.flag, param.value, 0, 0);
 763 +               if (ret > 0) {
 764 +                       copy_to_user(&((struct gptu_ioctl_param *) arg)->
 765 +                                     timer, &ret, sizeof(&ret));
 766 +                       ret = 0;
 767 +               }
 768 +               break;
 769 +       default:
 770 +               ret = -ENOTTY;
 771 +       }
 772 +
 773 +       return ret;
 774 +}
 775 +
 776 +static int gptu_open(struct inode *inode, struct file *file)
 777 +{
 778 +       return 0;
 779 +}
 780 +
 781 +static int gptu_release(struct inode *inode, struct file *file)
 782 +{
 783 +       return 0;
 784 +}
 785 +
 786 +int __init lq_gptu_init(void)
 787 +{
 788 +       int ret;
 789 +       unsigned int i;
 790 +
 791 +       ltq_w32(0, LQ_GPTU_IRNEN);
 792 +       ltq_w32(0xfff, LQ_GPTU_IRNCR);
 793 +
 794 +       memset(&timer_dev, 0, sizeof(timer_dev));
 795 +       mutex_init(&timer_dev.gptu_mutex);
 796 +
 797 +       lq_enable_gptu();
 798 +       timer_dev.number_of_timers = GPTU_ID_CFG * 2;
 799 +       lq_disable_gptu();
 800 +       if (timer_dev.number_of_timers > MAX_NUM_OF_32BIT_TIMER_BLOCKS * 2)
 801 +               timer_dev.number_of_timers = MAX_NUM_OF_32BIT_TIMER_BLOCKS * 2;
 802 +       printk(KERN_INFO "gptu: totally %d 16-bit timers/counters\n", timer_dev.number_of_timers);
 803 +
 804 +       ret = misc_register(&gptu_miscdev);
 805 +       if (ret) {
 806 +               printk(KERN_ERR "gptu: can't misc_register, get error %d\n", -ret);
 807 +               return ret;
 808 +       } else {
 809 +               printk(KERN_INFO "gptu: misc_register on minor %d\n", gptu_miscdev.minor);
 810 +       }
 811 +
 812 +       for (i = 0; i < timer_dev.number_of_timers; i++) {
 813 +               ret = request_irq(TIMER_INTERRUPT + i, timer_irq_handler, IRQF_TIMER, gptu_miscdev.name, &timer_dev.timer[i]);
 814 +               if (ret) {
 815 +                       for (; i >= 0; i--)
 816 +                               free_irq(TIMER_INTERRUPT + i, &timer_dev.timer[i]);
 817 +                       misc_deregister(&gptu_miscdev);
 818 +                       printk(KERN_ERR "gptu: failed in requesting irq (%d), get error %d\n", i, -ret);
 819 +                       return ret;
 820 +               } else {
 821 +                       timer_dev.timer[i].irq = TIMER_INTERRUPT + i;
 822 +                       disable_irq(timer_dev.timer[i].irq);
 823 +                       printk(KERN_INFO "gptu: succeeded to request irq %d\n", timer_dev.timer[i].irq);
 824 +               }
 825 +       }
 826 +
 827 +       return 0;
 828 +}
 829 +
 830 +void __exit lq_gptu_exit(void)
 831 +{
 832 +       unsigned int i;
 833 +
 834 +       for (i = 0; i < timer_dev.number_of_timers; i++) {
 835 +               if (timer_dev.timer[i].f_irq_on)
 836 +                       disable_irq(timer_dev.timer[i].irq);
 837 +               free_irq(timer_dev.timer[i].irq, &timer_dev.timer[i]);
 838 +       }
 839 +       lq_disable_gptu();
 840 +       misc_deregister(&gptu_miscdev);
 841 +}
 842 +
 843 +module_init(lq_gptu_init);
 844 +module_exit(lq_gptu_exit);
 845 --- /dev/null
 846 +++ b/arch/mips/include/asm/mach-lantiq/lantiq_timer.h
 847 @@ -0,0 +1,155 @@
 848 +#ifndef __DANUBE_GPTU_DEV_H__2005_07_26__10_19__
 849 +#define __DANUBE_GPTU_DEV_H__2005_07_26__10_19__
 850 +
 851 +
 852 +/******************************************************************************
 853 +       Copyright (c) 2002, Infineon Technologies.  All rights reserved.
 854 +
 855 +                               No Warranty
 856 +   Because the program is licensed free of charge, there is no warranty for
 857 +   the program, to the extent permitted by applicable law.  Except when
 858 +   otherwise stated in writing the copyright holders and/or other parties
 859 +   provide the program "as is" without warranty of any kind, either
 860 +   expressed or implied, including, but not limited to, the implied
 861 +   warranties of merchantability and fitness for a particular purpose. The
 862 +   entire risk as to the quality and performance of the program is with
 863 +   you.  should the program prove defective, you assume the cost of all
 864 +   necessary servicing, repair or correction.
 865 +
 866 +   In no event unless required by applicable law or agreed to in writing
 867 +   will any copyright holder, or any other party who may modify and/or
 868 +   redistribute the program as permitted above, be liable to you for
 869 +   damages, including any general, special, incidental or consequential
 870 +   damages arising out of the use or inability to use the program
 871 +   (including but not limited to loss of data or data being rendered
 872 +   inaccurate or losses sustained by you or third parties or a failure of
 873 +   the program to operate with any other programs), even if such holder or
 874 +   other party has been advised of the possibility of such damages.
 875 +******************************************************************************/
 876 +
 877 +
 878 +/*
 879 + * ####################################
 880 + *              Definition
 881 + * ####################################
 882 + */
 883 +
 884 +/*
 885 + *  Available Timer/Counter Index
 886 + */
 887 +#define TIMER(n, X)                     (n * 2 + (X ? 1 : 0))
 888 +#define TIMER_ANY                       0x00
 889 +#define TIMER1A                         TIMER(1, 0)
 890 +#define TIMER1B                         TIMER(1, 1)
 891 +#define TIMER2A                         TIMER(2, 0)
 892 +#define TIMER2B                         TIMER(2, 1)
 893 +#define TIMER3A                         TIMER(3, 0)
 894 +#define TIMER3B                         TIMER(3, 1)
 895 +
 896 +/*
 897 + *  Flag of Timer/Counter
 898 + *  These flags specify the way in which timer is configured.
 899 + */
 900 +/*  Bit size of timer/counter.                      */
 901 +#define TIMER_FLAG_16BIT                0x0000
 902 +#define TIMER_FLAG_32BIT                0x0001
 903 +/*  Switch between timer and counter.               */
 904 +#define TIMER_FLAG_TIMER                0x0000
 905 +#define TIMER_FLAG_COUNTER              0x0002
 906 +/*  Stop or continue when overflowing/underflowing. */
 907 +#define TIMER_FLAG_ONCE                 0x0000
 908 +#define TIMER_FLAG_CYCLIC               0x0004
 909 +/*  Count up or counter down.                       */
 910 +#define TIMER_FLAG_UP                   0x0000
 911 +#define TIMER_FLAG_DOWN                 0x0008
 912 +/*  Count on specific level or edge.                */
 913 +#define TIMER_FLAG_HIGH_LEVEL_SENSITIVE 0x0000
 914 +#define TIMER_FLAG_LOW_LEVEL_SENSITIVE  0x0040
 915 +#define TIMER_FLAG_RISE_EDGE            0x0010
 916 +#define TIMER_FLAG_FALL_EDGE            0x0020
 917 +#define TIMER_FLAG_ANY_EDGE             0x0030
 918 +/*  Signal is syncronous to module clock or not.    */
 919 +#define TIMER_FLAG_UNSYNC               0x0000
 920 +#define TIMER_FLAG_SYNC                 0x0080
 921 +/*  Different interrupt handle type.                */
 922 +#define TIMER_FLAG_NO_HANDLE            0x0000
 923 +#if defined(__KERNEL__)
 924 +    #define TIMER_FLAG_CALLBACK_IN_IRQ  0x0100
 925 +#endif  //  defined(__KERNEL__)
 926 +#define TIMER_FLAG_SIGNAL               0x0300
 927 +/*  Internal clock source or external clock source  */
 928 +#define TIMER_FLAG_INT_SRC              0x0000
 929 +#define TIMER_FLAG_EXT_SRC              0x1000
 930 +
 931 +
 932 +/*
 933 + *  ioctl Command
 934 + */
 935 +#define GPTU_REQUEST_TIMER              0x01    /*  General method to setup timer/counter.  */
 936 +#define GPTU_FREE_TIMER                 0x02    /*  Free timer/counter.                     */
 937 +#define GPTU_START_TIMER                0x03    /*  Start or resume timer/counter.          */
 938 +#define GPTU_STOP_TIMER                 0x04    /*  Suspend timer/counter.                  */
 939 +#define GPTU_GET_COUNT_VALUE            0x05    /*  Get current count value.                */
 940 +#define GPTU_CALCULATE_DIVIDER          0x06    /*  Calculate timer divider from given freq.*/
 941 +#define GPTU_SET_TIMER                  0x07    /*  Simplified method to setup timer.       */
 942 +#define GPTU_SET_COUNTER                0x08    /*  Simplified method to setup counter.     */
 943 +
 944 +/*
 945 + *  Data Type Used to Call ioctl
 946 + */
 947 +struct gptu_ioctl_param {
 948 +    unsigned int                        timer;  /*  In command GPTU_REQUEST_TIMER, GPTU_SET_TIMER, and  *
 949 +                                                 *  GPTU_SET_COUNTER, this field is ID of expected      *
 950 +                                                 *  timer/counter. If it's zero, a timer/counter would  *
 951 +                                                 *  be dynamically allocated and ID would be stored in  *
 952 +                                                 *  this field.                                         *
 953 +                                                 *  In command GPTU_GET_COUNT_VALUE, this field is      *
 954 +                                                 *  ignored.                                            *
 955 +                                                 *  In other command, this field is ID of timer/counter *
 956 +                                                 *  allocated.                                          */
 957 +    unsigned int                        flag;   /*  In command GPTU_REQUEST_TIMER, GPTU_SET_TIMER, and  *
 958 +                                                 *  GPTU_SET_COUNTER, this field contains flags to      *
 959 +                                                 *  specify how to configure timer/counter.             *
 960 +                                                 *  In command GPTU_START_TIMER, zero indicate start    *
 961 +                                                 *  and non-zero indicate resume timer/counter.         *
 962 +                                                 *  In other command, this field is ignored.            */
 963 +    unsigned long                       value;  /*  In command GPTU_REQUEST_TIMER, this field contains  *
 964 +                                                 *  init/reload value.                                  *
 965 +                                                 *  In command GPTU_SET_TIMER, this field contains      *
 966 +                                                 *  frequency (0.001Hz) of timer.                       *
 967 +                                                 *  In command GPTU_GET_COUNT_VALUE, current count      *
 968 +                                                 *  value would be stored in this field.                *
 969 +                                                 *  In command GPTU_CALCULATE_DIVIDER, this field       *
 970 +                                                 *  contains frequency wanted, and after calculation,   *
 971 +                                                 *  divider would be stored in this field to overwrite  *
 972 +                                                 *  the frequency.                                      *
 973 +                                                 *  In other command, this field is ignored.            */
 974 +    int                                 pid;    /*  In command GPTU_REQUEST_TIMER and GPTU_SET_TIMER,   *
 975 +                                                 *  if signal is required, this field contains process  *
 976 +                                                 *  ID to which signal would be sent.                   *
 977 +                                                 *  In other command, this field is ignored.            */
 978 +    int                                 sig;    /*  In command GPTU_REQUEST_TIMER and GPTU_SET_TIMER,   *
 979 +                                                 *  if signal is required, this field contains signal   *
 980 +                                                 *  number which would be sent.                         *
 981 +                                                 *  In other command, this field is ignored.            */
 982 +};
 983 +
 984 +/*
 985 + * ####################################
 986 + *              Data Type
 987 + * ####################################
 988 + */
 989 +typedef void (*timer_callback)(unsigned long arg);
 990 +
 991 +extern int lq_request_timer(unsigned int, unsigned int, unsigned long, unsigned long, unsigned long);
 992 +extern int lq_free_timer(unsigned int);
 993 +extern int lq_start_timer(unsigned int, int);
 994 +extern int lq_stop_timer(unsigned int);
 995 +extern int lq_reset_counter_flags(u32 timer, u32 flags);
 996 +extern int lq_get_count_value(unsigned int, unsigned long *);
 997 +extern u32 lq_cal_divider(unsigned long);
 998 +extern int lq_set_timer(unsigned int, unsigned int, int, int, unsigned int, unsigned long, unsigned long);
 999 +extern int lq_set_counter(unsigned int timer, unsigned int flag,
1000 +       u32 reload, unsigned long arg1, unsigned long arg2);
1001 +
1002 +#endif /* __DANUBE_GPTU_DEV_H__2005_07_26__10_19__ */
1003 --- a/arch/mips/lantiq/xway/Makefile
1004 +++ b/arch/mips/lantiq/xway/Makefile
1005 @@ -1,3 +1,3 @@
1006 -obj-y := prom.o sysctrl.o clk.o reset.o dma.o gptu.o dcdc.o
1007 +obj-y := prom.o sysctrl.o clk.o reset.o dma.o timer.o dcdc.o
1008
1009  obj-$(CONFIG_XRX200_PHY_FW) += xrx200_phy_fw.o