target/linux/lantiq/patches-3.7/0301-gptu.patch

   1 Index: linux-3.7.4/arch/mips/lantiq/xway/timer.c
   2 ===================================================================
   3 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
   4 +++ linux-3.7.4/arch/mips/lantiq/xway/timer.c   2013-01-28 18:37:52.316180918 +0100
   5 @@ -0,0 +1,845 @@
   6 +#ifndef CONFIG_SOC_AMAZON_SE
   7 +
   8 +#include <linux/kernel.h>
   9 +#include <linux/module.h>
  10 +#include <linux/version.h>
  11 +#include <linux/types.h>
  12 +#include <linux/fs.h>
  13 +#include <linux/miscdevice.h>
  14 +#include <linux/init.h>
  15 +#include <linux/uaccess.h>
  16 +#include <linux/unistd.h>
  17 +#include <linux/errno.h>
  18 +#include <linux/interrupt.h>
  19 +#include <linux/sched.h>
  20 +
  21 +#include <asm/irq.h>
  22 +#include <asm/div64.h>
  23 +#include "../clk.h"
  24 +
  25 +#include <lantiq_soc.h>
  26 +#include <lantiq_irq.h>
  27 +#include <lantiq_timer.h>
  28 +
  29 +#define MAX_NUM_OF_32BIT_TIMER_BLOCKS  6
  30 +
  31 +#ifdef TIMER1A
  32 +#define FIRST_TIMER                    TIMER1A
  33 +#else
  34 +#define FIRST_TIMER                    2
  35 +#endif
  36 +
  37 +/*
  38 + *  GPTC divider is set or not.
  39 + */
  40 +#define GPTU_CLC_RMC_IS_SET            0
  41 +
  42 +/*
  43 + *  Timer Interrupt (IRQ)
  44 + */
  45 +/*  Must be adjusted when ICU driver is available */
  46 +#define TIMER_INTERRUPT                        (INT_NUM_IM3_IRL0 + 22)
  47 +
  48 +/*
  49 + *  Bits Operation
  50 + */
  51 +#define GET_BITS(x, msb, lsb)          \
  52 +       (((x) & ((1 << ((msb) + 1)) - 1)) >> (lsb))
  53 +#define SET_BITS(x, msb, lsb, value)   \
  54 +       (((x) & ~(((1 << ((msb) + 1)) - 1) ^ ((1 << (lsb)) - 1))) | \
  55 +       (((value) & ((1 << (1 + (msb) - (lsb))) - 1)) << (lsb)))
  56 +
  57 +/*
  58 + *  GPTU Register Mapping
  59 + */
  60 +#define LQ_GPTU                        (KSEG1 + 0x1E100A00)
  61 +#define LQ_GPTU_CLC            ((volatile u32 *)(LQ_GPTU + 0x0000))
  62 +#define LQ_GPTU_ID                     ((volatile u32 *)(LQ_GPTU + 0x0008))
  63 +#define LQ_GPTU_CON(n, X)              ((volatile u32 *)(LQ_GPTU + 0x0010 + ((X) * 4) + ((n) - 1) * 0x0020))   /* X must be either A or B */
  64 +#define LQ_GPTU_RUN(n, X)              ((volatile u32 *)(LQ_GPTU + 0x0018 + ((X) * 4) + ((n) - 1) * 0x0020))   /* X must be either A or B */
  65 +#define LQ_GPTU_RELOAD(n, X)   ((volatile u32 *)(LQ_GPTU + 0x0020 + ((X) * 4) + ((n) - 1) * 0x0020))   /* X must be either A or B */
  66 +#define LQ_GPTU_COUNT(n, X)    ((volatile u32 *)(LQ_GPTU + 0x0028 + ((X) * 4) + ((n) - 1) * 0x0020))   /* X must be either A or B */
  67 +#define LQ_GPTU_IRNEN          ((volatile u32 *)(LQ_GPTU + 0x00F4))
  68 +#define LQ_GPTU_IRNICR         ((volatile u32 *)(LQ_GPTU + 0x00F8))
  69 +#define LQ_GPTU_IRNCR          ((volatile u32 *)(LQ_GPTU + 0x00FC))
  70 +
  71 +/*
  72 + *  Clock Control Register
  73 + */
  74 +#define GPTU_CLC_SMC                   GET_BITS(*LQ_GPTU_CLC, 23, 16)
  75 +#define GPTU_CLC_RMC                   GET_BITS(*LQ_GPTU_CLC, 15, 8)
  76 +#define GPTU_CLC_FSOE                  (*LQ_GPTU_CLC & (1 << 5))
  77 +#define GPTU_CLC_EDIS                  (*LQ_GPTU_CLC & (1 << 3))
  78 +#define GPTU_CLC_SPEN                  (*LQ_GPTU_CLC & (1 << 2))
  79 +#define GPTU_CLC_DISS                  (*LQ_GPTU_CLC & (1 << 1))
  80 +#define GPTU_CLC_DISR                  (*LQ_GPTU_CLC & (1 << 0))
  81 +
  82 +#define GPTU_CLC_SMC_SET(value)                SET_BITS(0, 23, 16, (value))
  83 +#define GPTU_CLC_RMC_SET(value)                SET_BITS(0, 15, 8, (value))
  84 +#define GPTU_CLC_FSOE_SET(value)       ((value) ? (1 << 5) : 0)
  85 +#define GPTU_CLC_SBWE_SET(value)       ((value) ? (1 << 4) : 0)
  86 +#define GPTU_CLC_EDIS_SET(value)       ((value) ? (1 << 3) : 0)
  87 +#define GPTU_CLC_SPEN_SET(value)       ((value) ? (1 << 2) : 0)
  88 +#define GPTU_CLC_DISR_SET(value)       ((value) ? (1 << 0) : 0)
  89 +
  90 +/*
  91 + *  ID Register
  92 + */
  93 +#define GPTU_ID_ID                     GET_BITS(*LQ_GPTU_ID, 15, 8)
  94 +#define GPTU_ID_CFG                    GET_BITS(*LQ_GPTU_ID, 7, 5)
  95 +#define GPTU_ID_REV                    GET_BITS(*LQ_GPTU_ID, 4, 0)
  96 +
  97 +/*
  98 + *  Control Register of Timer/Counter nX
  99 + *    n is the index of block (1 based index)
 100 + *    X is either A or B
 101 + */
 102 +#define GPTU_CON_SRC_EG(n, X)          (*LQ_GPTU_CON(n, X) & (1 << 10))
 103 +#define GPTU_CON_SRC_EXT(n, X)         (*LQ_GPTU_CON(n, X) & (1 << 9))
 104 +#define GPTU_CON_SYNC(n, X)            (*LQ_GPTU_CON(n, X) & (1 << 8))
 105 +#define GPTU_CON_EDGE(n, X)            GET_BITS(*LQ_GPTU_CON(n, X), 7, 6)
 106 +#define GPTU_CON_INV(n, X)             (*LQ_GPTU_CON(n, X) & (1 << 5))
 107 +#define GPTU_CON_EXT(n, X)             (*LQ_GPTU_CON(n, A) & (1 << 4)) /* Timer/Counter B does not have this bit */
 108 +#define GPTU_CON_STP(n, X)             (*LQ_GPTU_CON(n, X) & (1 << 3))
 109 +#define GPTU_CON_CNT(n, X)             (*LQ_GPTU_CON(n, X) & (1 << 2))
 110 +#define GPTU_CON_DIR(n, X)             (*LQ_GPTU_CON(n, X) & (1 << 1))
 111 +#define GPTU_CON_EN(n, X)              (*LQ_GPTU_CON(n, X) & (1 << 0))
 112 +
 113 +#define GPTU_CON_SRC_EG_SET(value)     ((value) ? 0 : (1 << 10))
 114 +#define GPTU_CON_SRC_EXT_SET(value)    ((value) ? (1 << 9) : 0)
 115 +#define GPTU_CON_SYNC_SET(value)       ((value) ? (1 << 8) : 0)
 116 +#define GPTU_CON_EDGE_SET(value)       SET_BITS(0, 7, 6, (value))
 117 +#define GPTU_CON_INV_SET(value)                ((value) ? (1 << 5) : 0)
 118 +#define GPTU_CON_EXT_SET(value)                ((value) ? (1 << 4) : 0)
 119 +#define GPTU_CON_STP_SET(value)                ((value) ? (1 << 3) : 0)
 120 +#define GPTU_CON_CNT_SET(value)                ((value) ? (1 << 2) : 0)
 121 +#define GPTU_CON_DIR_SET(value)                ((value) ? (1 << 1) : 0)
 122 +
 123 +#define GPTU_RUN_RL_SET(value)         ((value) ? (1 << 2) : 0)
 124 +#define GPTU_RUN_CEN_SET(value)                ((value) ? (1 << 1) : 0)
 125 +#define GPTU_RUN_SEN_SET(value)                ((value) ? (1 << 0) : 0)
 126 +
 127 +#define GPTU_IRNEN_TC_SET(n, X, value) ((value) ? (1 << (((n) - 1) * 2 + (X))) : 0)
 128 +#define GPTU_IRNCR_TC_SET(n, X, value) ((value) ? (1 << (((n) - 1) * 2 + (X))) : 0)
 129 +
 130 +#define TIMER_FLAG_MASK_SIZE(x)                (x & 0x0001)
 131 +#define TIMER_FLAG_MASK_TYPE(x)                (x & 0x0002)
 132 +#define TIMER_FLAG_MASK_STOP(x)                (x & 0x0004)
 133 +#define TIMER_FLAG_MASK_DIR(x)         (x & 0x0008)
 134 +#define TIMER_FLAG_NONE_EDGE           0x0000
 135 +#define TIMER_FLAG_MASK_EDGE(x)                (x & 0x0030)
 136 +#define TIMER_FLAG_REAL                        0x0000
 137 +#define TIMER_FLAG_INVERT              0x0040
 138 +#define TIMER_FLAG_MASK_INVERT(x)      (x & 0x0040)
 139 +#define TIMER_FLAG_MASK_TRIGGER(x)     (x & 0x0070)
 140 +#define TIMER_FLAG_MASK_SYNC(x)                (x & 0x0080)
 141 +#define TIMER_FLAG_CALLBACK_IN_HB      0x0200
 142 +#define TIMER_FLAG_MASK_HANDLE(x)      (x & 0x0300)
 143 +#define TIMER_FLAG_MASK_SRC(x)         (x & 0x1000)
 144 +
 145 +struct timer_dev_timer {
 146 +       unsigned int f_irq_on;
 147 +       unsigned int irq;
 148 +       unsigned int flag;
 149 +       unsigned long arg1;
 150 +       unsigned long arg2;
 151 +};
 152 +
 153 +struct timer_dev {
 154 +       struct mutex gptu_mutex;
 155 +       unsigned int number_of_timers;
 156 +       unsigned int occupation;
 157 +       unsigned int f_gptu_on;
 158 +       struct timer_dev_timer timer[MAX_NUM_OF_32BIT_TIMER_BLOCKS * 2];
 159 +};
 160 +
 161 +
 162 +unsigned int ltq_get_fpi_bus_clock(int fpi) {
 163 +       struct clk *clk = clk_get_fpi();
 164 +       return clk_get_rate(clk);
 165 +}
 166 +
 167 +
 168 +static long gptu_ioctl(struct file *, unsigned int, unsigned long);
 169 +static int gptu_open(struct inode *, struct file *);
 170 +static int gptu_release(struct inode *, struct file *);
 171 +
 172 +static struct file_operations gptu_fops = {
 173 +       .owner = THIS_MODULE,
 174 +       .unlocked_ioctl = gptu_ioctl,
 175 +       .open = gptu_open,
 176 +       .release = gptu_release
 177 +};
 178 +
 179 +static struct miscdevice gptu_miscdev = {
 180 +       .minor = MISC_DYNAMIC_MINOR,
 181 +       .name = "gptu",
 182 +       .fops = &gptu_fops,
 183 +};
 184 +
 185 +static struct timer_dev timer_dev;
 186 +
 187 +static irqreturn_t timer_irq_handler(int irq, void *p)
 188 +{
 189 +       unsigned int timer;
 190 +       unsigned int flag;
 191 +       struct timer_dev_timer *dev_timer = (struct timer_dev_timer *)p;
 192 +
 193 +       timer = irq - TIMER_INTERRUPT;
 194 +       if (timer < timer_dev.number_of_timers
 195 +               && dev_timer == &timer_dev.timer[timer]) {
 196 +               /*  Clear interrupt.    */
 197 +               ltq_w32(1 << timer, LQ_GPTU_IRNCR);
 198 +
 199 +               /*  Call user hanler or signal. */
 200 +               flag = dev_timer->flag;
 201 +               if (!(timer & 0x01)
 202 +                       || TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT) {
 203 +                       /* 16-bit timer or timer A of 32-bit timer  */
 204 +                       switch (TIMER_FLAG_MASK_HANDLE(flag)) {
 205 +                       case TIMER_FLAG_CALLBACK_IN_IRQ:
 206 +                       case TIMER_FLAG_CALLBACK_IN_HB:
 207 +                               if (dev_timer->arg1)
 208 +                                       (*(timer_callback)dev_timer->arg1)(dev_timer->arg2);
 209 +                               break;
 210 +                       case TIMER_FLAG_SIGNAL:
 211 +                               send_sig((int)dev_timer->arg2, (struct task_struct *)dev_timer->arg1, 0);
 212 +                               break;
 213 +                       }
 214 +               }
 215 +       }
 216 +       return IRQ_HANDLED;
 217 +}
 218 +
 219 +static inline void lq_enable_gptu(void)
 220 +{
 221 +       struct clk *clk = clk_get_sys("1e100a00.gptu", NULL);
 222 +       clk_enable(clk);
 223 +
 224 +       //ltq_pmu_enable(PMU_GPT);
 225 +
 226 +       /*  Set divider as 1, disable write protection for SPEN, enable module. */
 227 +       *LQ_GPTU_CLC =
 228 +               GPTU_CLC_SMC_SET(0x00) |
 229 +               GPTU_CLC_RMC_SET(0x01) |
 230 +               GPTU_CLC_FSOE_SET(0) |
 231 +               GPTU_CLC_SBWE_SET(1) |
 232 +               GPTU_CLC_EDIS_SET(0) |
 233 +               GPTU_CLC_SPEN_SET(0) |
 234 +               GPTU_CLC_DISR_SET(0);
 235 +}
 236 +
 237 +static inline void lq_disable_gptu(void)
 238 +{
 239 +       struct clk *clk = clk_get_sys("1e100a00.gptu", NULL);
 240 +       ltq_w32(0x00, LQ_GPTU_IRNEN);
 241 +       ltq_w32(0xfff, LQ_GPTU_IRNCR);
 242 +
 243 +       /*  Set divider as 0, enable write protection for SPEN, disable module. */
 244 +       *LQ_GPTU_CLC =
 245 +               GPTU_CLC_SMC_SET(0x00) |
 246 +               GPTU_CLC_RMC_SET(0x00) |
 247 +               GPTU_CLC_FSOE_SET(0) |
 248 +               GPTU_CLC_SBWE_SET(0) |
 249 +               GPTU_CLC_EDIS_SET(0) |
 250 +               GPTU_CLC_SPEN_SET(0) |
 251 +               GPTU_CLC_DISR_SET(1);
 252 +
 253 +       clk_enable(clk);
 254 +}
 255 +
 256 +int lq_request_timer(unsigned int timer, unsigned int flag,
 257 +       unsigned long value, unsigned long arg1, unsigned long arg2)
 258 +{
 259 +       int ret = 0;
 260 +       unsigned int con_reg, irnen_reg;
 261 +       int n, X;
 262 +
 263 +       if (timer >= FIRST_TIMER + timer_dev.number_of_timers)
 264 +               return -EINVAL;
 265 +
 266 +       printk(KERN_INFO "request_timer(%d, 0x%08X, %lu)...",
 267 +               timer, flag, value);
 268 +
 269 +       if (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT)
 270 +               value &= 0xFFFF;
 271 +       else
 272 +               timer &= ~0x01;
 273 +
 274 +       mutex_lock(&timer_dev.gptu_mutex);
 275 +
 276 +       /*
 277 +        *  Allocate timer.
 278 +        */
 279 +       if (timer < FIRST_TIMER) {
 280 +               unsigned int mask;
 281 +               unsigned int shift;
 282 +               /* This takes care of TIMER1B which is the only choice for Voice TAPI system */
 283 +               unsigned int offset = TIMER2A;
 284 +
 285 +               /*
 286 +                *  Pick up a free timer.
 287 +                */
 288 +               if (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT) {
 289 +                       mask = 1 << offset;
 290 +                       shift = 1;
 291 +               } else {
 292 +                       mask = 3 << offset;
 293 +                       shift = 2;
 294 +               }
 295 +               for (timer = offset;
 296 +                    timer < offset + timer_dev.number_of_timers;
 297 +                    timer += shift, mask <<= shift)
 298 +                       if (!(timer_dev.occupation & mask)) {
 299 +                               timer_dev.occupation |= mask;
 300 +                               break;
 301 +                       }
 302 +               if (timer >= offset + timer_dev.number_of_timers) {
 303 +                       printk("failed![%d]\n", __LINE__);
 304 +                       mutex_unlock(&timer_dev.gptu_mutex);
 305 +                       return -EINVAL;
 306 +               } else
 307 +                       ret = timer;
 308 +       } else {
 309 +               register unsigned int mask;
 310 +
 311 +               /*
 312 +                *  Check if the requested timer is free.
 313 +                */
 314 +               mask = (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT ? 1 : 3) << timer;
 315 +               if ((timer_dev.occupation & mask)) {
 316 +                       printk("failed![%d] mask %#x, timer_dev.occupation %#x\n",
 317 +                               __LINE__, mask, timer_dev.occupation);
 318 +                       mutex_unlock(&timer_dev.gptu_mutex);
 319 +                       return -EBUSY;
 320 +               } else {
 321 +                       timer_dev.occupation |= mask;
 322 +                       ret = 0;
 323 +               }
 324 +       }
 325 +
 326 +       /*
 327 +        *  Prepare control register value.
 328 +        */
 329 +       switch (TIMER_FLAG_MASK_EDGE(flag)) {
 330 +       default:
 331 +       case TIMER_FLAG_NONE_EDGE:
 332 +               con_reg = GPTU_CON_EDGE_SET(0x00);
 333 +               break;
 334 +       case TIMER_FLAG_RISE_EDGE:
 335 +               con_reg = GPTU_CON_EDGE_SET(0x01);
 336 +               break;
 337 +       case TIMER_FLAG_FALL_EDGE:
 338 +               con_reg = GPTU_CON_EDGE_SET(0x02);
 339 +               break;
 340 +       case TIMER_FLAG_ANY_EDGE:
 341 +               con_reg = GPTU_CON_EDGE_SET(0x03);
 342 +               break;
 343 +       }
 344 +       if (TIMER_FLAG_MASK_TYPE(flag) == TIMER_FLAG_TIMER)
 345 +               con_reg |=
 346 +                       TIMER_FLAG_MASK_SRC(flag) ==
 347 +                       TIMER_FLAG_EXT_SRC ? GPTU_CON_SRC_EXT_SET(1) :
 348 +                       GPTU_CON_SRC_EXT_SET(0);
 349 +       else
 350 +               con_reg |=
 351 +                       TIMER_FLAG_MASK_SRC(flag) ==
 352 +                       TIMER_FLAG_EXT_SRC ? GPTU_CON_SRC_EG_SET(1) :
 353 +                       GPTU_CON_SRC_EG_SET(0);
 354 +       con_reg |=
 355 +               TIMER_FLAG_MASK_SYNC(flag) ==
 356 +               TIMER_FLAG_UNSYNC ? GPTU_CON_SYNC_SET(0) :
 357 +               GPTU_CON_SYNC_SET(1);
 358 +       con_reg |=
 359 +               TIMER_FLAG_MASK_INVERT(flag) ==
 360 +               TIMER_FLAG_REAL ? GPTU_CON_INV_SET(0) : GPTU_CON_INV_SET(1);
 361 +       con_reg |=
 362 +               TIMER_FLAG_MASK_SIZE(flag) ==
 363 +               TIMER_FLAG_16BIT ? GPTU_CON_EXT_SET(0) :
 364 +               GPTU_CON_EXT_SET(1);
 365 +       con_reg |=
 366 +               TIMER_FLAG_MASK_STOP(flag) ==
 367 +               TIMER_FLAG_ONCE ? GPTU_CON_STP_SET(1) : GPTU_CON_STP_SET(0);
 368 +       con_reg |=
 369 +               TIMER_FLAG_MASK_TYPE(flag) ==
 370 +               TIMER_FLAG_TIMER ? GPTU_CON_CNT_SET(0) :
 371 +               GPTU_CON_CNT_SET(1);
 372 +       con_reg |=
 373 +               TIMER_FLAG_MASK_DIR(flag) ==
 374 +               TIMER_FLAG_UP ? GPTU_CON_DIR_SET(1) : GPTU_CON_DIR_SET(0);
 375 +
 376 +       /*
 377 +        *  Fill up running data.
 378 +        */
 379 +       timer_dev.timer[timer - FIRST_TIMER].flag = flag;
 380 +       timer_dev.timer[timer - FIRST_TIMER].arg1 = arg1;
 381 +       timer_dev.timer[timer - FIRST_TIMER].arg2 = arg2;
 382 +       if (TIMER_FLAG_MASK_SIZE(flag) != TIMER_FLAG_16BIT)
 383 +               timer_dev.timer[timer - FIRST_TIMER + 1].flag = flag;
 384 +
 385 +       /*
 386 +        *  Enable GPTU module.
 387 +        */
 388 +       if (!timer_dev.f_gptu_on) {
 389 +               lq_enable_gptu();
 390 +               timer_dev.f_gptu_on = 1;
 391 +       }
 392 +
 393 +       /*
 394 +        *  Enable IRQ.
 395 +        */
 396 +       if (TIMER_FLAG_MASK_HANDLE(flag) != TIMER_FLAG_NO_HANDLE) {
 397 +               if (TIMER_FLAG_MASK_HANDLE(flag) == TIMER_FLAG_SIGNAL)
 398 +                       timer_dev.timer[timer - FIRST_TIMER].arg1 =
 399 +                               (unsigned long) find_task_by_vpid((int) arg1);
 400 +
 401 +               irnen_reg = 1 << (timer - FIRST_TIMER);
 402 +
 403 +               if (TIMER_FLAG_MASK_HANDLE(flag) == TIMER_FLAG_SIGNAL
 404 +                   || (TIMER_FLAG_MASK_HANDLE(flag) ==
 405 +                       TIMER_FLAG_CALLBACK_IN_IRQ
 406 +                       && timer_dev.timer[timer - FIRST_TIMER].arg1)) {
 407 +                       enable_irq(timer_dev.timer[timer - FIRST_TIMER].irq);
 408 +                       timer_dev.timer[timer - FIRST_TIMER].f_irq_on = 1;
 409 +               }
 410 +       } else
 411 +               irnen_reg = 0;
 412 +
 413 +       /*
 414 +        *  Write config register, reload value and enable interrupt.
 415 +        */
 416 +       n = timer >> 1;
 417 +       X = timer & 0x01;
 418 +       *LQ_GPTU_CON(n, X) = con_reg;
 419 +       *LQ_GPTU_RELOAD(n, X) = value;
 420 +       /* printk("reload value = %d\n", (u32)value); */
 421 +       *LQ_GPTU_IRNEN |= irnen_reg;
 422 +
 423 +       mutex_unlock(&timer_dev.gptu_mutex);
 424 +       printk("successful!\n");
 425 +       return ret;
 426 +}
 427 +EXPORT_SYMBOL(lq_request_timer);
 428 +
 429 +int lq_free_timer(unsigned int timer)
 430 +{
 431 +       unsigned int flag;
 432 +       unsigned int mask;
 433 +       int n, X;
 434 +
 435 +       if (!timer_dev.f_gptu_on)
 436 +               return -EINVAL;
 437 +
 438 +       if (timer < FIRST_TIMER || timer >= FIRST_TIMER + timer_dev.number_of_timers)
 439 +               return -EINVAL;
 440 +
 441 +       mutex_lock(&timer_dev.gptu_mutex);
 442 +
 443 +       flag = timer_dev.timer[timer - FIRST_TIMER].flag;
 444 +       if (TIMER_FLAG_MASK_SIZE(flag) != TIMER_FLAG_16BIT)
 445 +               timer &= ~0x01;
 446 +
 447 +       mask = (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT ? 1 : 3) << timer;
 448 +       if (((timer_dev.occupation & mask) ^ mask)) {
 449 +               mutex_unlock(&timer_dev.gptu_mutex);
 450 +               return -EINVAL;
 451 +       }
 452 +
 453 +       n = timer >> 1;
 454 +       X = timer & 0x01;
 455 +
 456 +       if (GPTU_CON_EN(n, X))
 457 +               *LQ_GPTU_RUN(n, X) = GPTU_RUN_CEN_SET(1);
 458 +
 459 +       *LQ_GPTU_IRNEN &= ~GPTU_IRNEN_TC_SET(n, X, 1);
 460 +       *LQ_GPTU_IRNCR |= GPTU_IRNCR_TC_SET(n, X, 1);
 461 +
 462 +       if (timer_dev.timer[timer - FIRST_TIMER].f_irq_on) {
 463 +               disable_irq(timer_dev.timer[timer - FIRST_TIMER].irq);
 464 +               timer_dev.timer[timer - FIRST_TIMER].f_irq_on = 0;
 465 +       }
 466 +
 467 +       timer_dev.occupation &= ~mask;
 468 +       if (!timer_dev.occupation && timer_dev.f_gptu_on) {
 469 +               lq_disable_gptu();
 470 +               timer_dev.f_gptu_on = 0;
 471 +       }
 472 +
 473 +       mutex_unlock(&timer_dev.gptu_mutex);
 474 +
 475 +       return 0;
 476 +}
 477 +EXPORT_SYMBOL(lq_free_timer);
 478 +
 479 +int lq_start_timer(unsigned int timer, int is_resume)
 480 +{
 481 +       unsigned int flag;
 482 +       unsigned int mask;
 483 +       int n, X;
 484 +
 485 +       if (!timer_dev.f_gptu_on)
 486 +               return -EINVAL;
 487 +
 488 +       if (timer < FIRST_TIMER || timer >= FIRST_TIMER + timer_dev.number_of_timers)
 489 +               return -EINVAL;
 490 +
 491 +       mutex_lock(&timer_dev.gptu_mutex);
 492 +
 493 +       flag = timer_dev.timer[timer - FIRST_TIMER].flag;
 494 +       if (TIMER_FLAG_MASK_SIZE(flag) != TIMER_FLAG_16BIT)
 495 +               timer &= ~0x01;
 496 +
 497 +       mask = (TIMER_FLAG_MASK_SIZE(flag) ==
 498 +       TIMER_FLAG_16BIT ? 1 : 3) << timer;
 499 +       if (((timer_dev.occupation & mask) ^ mask)) {
 500 +               mutex_unlock(&timer_dev.gptu_mutex);
 501 +               return -EINVAL;
 502 +       }
 503 +
 504 +       n = timer >> 1;
 505 +       X = timer & 0x01;
 506 +
 507 +       *LQ_GPTU_RUN(n, X) = GPTU_RUN_RL_SET(!is_resume) | GPTU_RUN_SEN_SET(1);
 508 +
 509 +
 510 +       mutex_unlock(&timer_dev.gptu_mutex);
 511 +
 512 +       return 0;
 513 +}
 514 +EXPORT_SYMBOL(lq_start_timer);
 515 +
 516 +int lq_stop_timer(unsigned int timer)
 517 +{
 518 +       unsigned int flag;
 519 +       unsigned int mask;
 520 +       int n, X;
 521 +
 522 +       if (!timer_dev.f_gptu_on)
 523 +               return -EINVAL;
 524 +
 525 +       if (timer < FIRST_TIMER
 526 +           || timer >= FIRST_TIMER + timer_dev.number_of_timers)
 527 +               return -EINVAL;
 528 +
 529 +       mutex_lock(&timer_dev.gptu_mutex);
 530 +
 531 +       flag = timer_dev.timer[timer - FIRST_TIMER].flag;
 532 +       if (TIMER_FLAG_MASK_SIZE(flag) != TIMER_FLAG_16BIT)
 533 +               timer &= ~0x01;
 534 +
 535 +       mask = (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT ? 1 : 3) << timer;
 536 +       if (((timer_dev.occupation & mask) ^ mask)) {
 537 +               mutex_unlock(&timer_dev.gptu_mutex);
 538 +               return -EINVAL;
 539 +       }
 540 +
 541 +       n = timer >> 1;
 542 +       X = timer & 0x01;
 543 +
 544 +       *LQ_GPTU_RUN(n, X) = GPTU_RUN_CEN_SET(1);
 545 +
 546 +       mutex_unlock(&timer_dev.gptu_mutex);
 547 +
 548 +       return 0;
 549 +}
 550 +EXPORT_SYMBOL(lq_stop_timer);
 551 +
 552 +int lq_reset_counter_flags(u32 timer, u32 flags)
 553 +{
 554 +       unsigned int oflag;
 555 +       unsigned int mask, con_reg;
 556 +       int n, X;
 557 +
 558 +       if (!timer_dev.f_gptu_on)
 559 +               return -EINVAL;
 560 +
 561 +       if (timer < FIRST_TIMER || timer >= FIRST_TIMER + timer_dev.number_of_timers)
 562 +               return -EINVAL;
 563 +
 564 +       mutex_lock(&timer_dev.gptu_mutex);
 565 +
 566 +       oflag = timer_dev.timer[timer - FIRST_TIMER].flag;
 567 +       if (TIMER_FLAG_MASK_SIZE(oflag) != TIMER_FLAG_16BIT)
 568 +               timer &= ~0x01;
 569 +
 570 +       mask = (TIMER_FLAG_MASK_SIZE(oflag) == TIMER_FLAG_16BIT ? 1 : 3) << timer;
 571 +       if (((timer_dev.occupation & mask) ^ mask)) {
 572 +               mutex_unlock(&timer_dev.gptu_mutex);
 573 +               return -EINVAL;
 574 +       }
 575 +
 576 +       switch (TIMER_FLAG_MASK_EDGE(flags)) {
 577 +       default:
 578 +       case TIMER_FLAG_NONE_EDGE:
 579 +               con_reg = GPTU_CON_EDGE_SET(0x00);
 580 +               break;
 581 +       case TIMER_FLAG_RISE_EDGE:
 582 +               con_reg = GPTU_CON_EDGE_SET(0x01);
 583 +               break;
 584 +       case TIMER_FLAG_FALL_EDGE:
 585 +               con_reg = GPTU_CON_EDGE_SET(0x02);
 586 +               break;
 587 +       case TIMER_FLAG_ANY_EDGE:
 588 +               con_reg = GPTU_CON_EDGE_SET(0x03);
 589 +               break;
 590 +       }
 591 +       if (TIMER_FLAG_MASK_TYPE(flags) == TIMER_FLAG_TIMER)
 592 +               con_reg |= TIMER_FLAG_MASK_SRC(flags) == TIMER_FLAG_EXT_SRC ? GPTU_CON_SRC_EXT_SET(1) : GPTU_CON_SRC_EXT_SET(0);
 593 +       else
 594 +               con_reg |= TIMER_FLAG_MASK_SRC(flags) == TIMER_FLAG_EXT_SRC ? GPTU_CON_SRC_EG_SET(1) : GPTU_CON_SRC_EG_SET(0);
 595 +       con_reg |= TIMER_FLAG_MASK_SYNC(flags) == TIMER_FLAG_UNSYNC ? GPTU_CON_SYNC_SET(0) : GPTU_CON_SYNC_SET(1);
 596 +       con_reg |= TIMER_FLAG_MASK_INVERT(flags) == TIMER_FLAG_REAL ? GPTU_CON_INV_SET(0) : GPTU_CON_INV_SET(1);
 597 +       con_reg |= TIMER_FLAG_MASK_SIZE(flags) == TIMER_FLAG_16BIT ? GPTU_CON_EXT_SET(0) : GPTU_CON_EXT_SET(1);
 598 +       con_reg |= TIMER_FLAG_MASK_STOP(flags) == TIMER_FLAG_ONCE ? GPTU_CON_STP_SET(1) : GPTU_CON_STP_SET(0);
 599 +       con_reg |= TIMER_FLAG_MASK_TYPE(flags) == TIMER_FLAG_TIMER ? GPTU_CON_CNT_SET(0) : GPTU_CON_CNT_SET(1);
 600 +       con_reg |= TIMER_FLAG_MASK_DIR(flags) == TIMER_FLAG_UP ? GPTU_CON_DIR_SET(1) : GPTU_CON_DIR_SET(0);
 601 +
 602 +       timer_dev.timer[timer - FIRST_TIMER].flag = flags;
 603 +       if (TIMER_FLAG_MASK_SIZE(flags) != TIMER_FLAG_16BIT)
 604 +               timer_dev.timer[timer - FIRST_TIMER + 1].flag = flags;
 605 +
 606 +       n = timer >> 1;
 607 +       X = timer & 0x01;
 608 +
 609 +       *LQ_GPTU_CON(n, X) = con_reg;
 610 +       smp_wmb();
 611 +       mutex_unlock(&timer_dev.gptu_mutex);
 612 +       return 0;
 613 +}
 614 +EXPORT_SYMBOL(lq_reset_counter_flags);
 615 +
 616 +int lq_get_count_value(unsigned int timer, unsigned long *value)
 617 +{
 618 +       unsigned int flag;
 619 +       unsigned int mask;
 620 +       int n, X;
 621 +
 622 +       if (!timer_dev.f_gptu_on)
 623 +               return -EINVAL;
 624 +
 625 +       if (timer < FIRST_TIMER
 626 +           || timer >= FIRST_TIMER + timer_dev.number_of_timers)
 627 +               return -EINVAL;
 628 +
 629 +       mutex_lock(&timer_dev.gptu_mutex);
 630 +
 631 +       flag = timer_dev.timer[timer - FIRST_TIMER].flag;
 632 +       if (TIMER_FLAG_MASK_SIZE(flag) != TIMER_FLAG_16BIT)
 633 +               timer &= ~0x01;
 634 +
 635 +       mask = (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT ? 1 : 3) << timer;
 636 +       if (((timer_dev.occupation & mask) ^ mask)) {
 637 +               mutex_unlock(&timer_dev.gptu_mutex);
 638 +               return -EINVAL;
 639 +       }
 640 +
 641 +       n = timer >> 1;
 642 +       X = timer & 0x01;
 643 +
 644 +       *value = *LQ_GPTU_COUNT(n, X);
 645 +
 646 +
 647 +       mutex_unlock(&timer_dev.gptu_mutex);
 648 +
 649 +       return 0;
 650 +}
 651 +EXPORT_SYMBOL(lq_get_count_value);
 652 +
 653 +u32 lq_cal_divider(unsigned long freq)
 654 +{
 655 +       u64 module_freq, fpi = ltq_get_fpi_bus_clock(2);
 656 +       u32 clock_divider = 1;
 657 +       module_freq = fpi * 1000;
 658 +       do_div(module_freq, clock_divider * freq);
 659 +       return module_freq;
 660 +}
 661 +EXPORT_SYMBOL(lq_cal_divider);
 662 +
 663 +int lq_set_timer(unsigned int timer, unsigned int freq, int is_cyclic,
 664 +       int is_ext_src, unsigned int handle_flag, unsigned long arg1,
 665 +       unsigned long arg2)
 666 +{
 667 +       unsigned long divider;
 668 +       unsigned int flag;
 669 +
 670 +       divider = lq_cal_divider(freq);
 671 +       if (divider == 0)
 672 +               return -EINVAL;
 673 +       flag = ((divider & ~0xFFFF) ? TIMER_FLAG_32BIT : TIMER_FLAG_16BIT)
 674 +               | (is_cyclic ? TIMER_FLAG_CYCLIC : TIMER_FLAG_ONCE)
 675 +               | (is_ext_src ? TIMER_FLAG_EXT_SRC : TIMER_FLAG_INT_SRC)
 676 +               | TIMER_FLAG_TIMER | TIMER_FLAG_DOWN
 677 +               | TIMER_FLAG_MASK_HANDLE(handle_flag);
 678 +
 679 +       printk(KERN_INFO "lq_set_timer(%d, %d), divider = %lu\n",
 680 +               timer, freq, divider);
 681 +       return lq_request_timer(timer, flag, divider, arg1, arg2);
 682 +}
 683 +EXPORT_SYMBOL(lq_set_timer);
 684 +
 685 +int lq_set_counter(unsigned int timer, unsigned int flag, u32 reload,
 686 +       unsigned long arg1, unsigned long arg2)
 687 +{
 688 +       printk(KERN_INFO "lq_set_counter(%d, %#x, %d)\n", timer, flag, reload);
 689 +       return lq_request_timer(timer, flag, reload, arg1, arg2);
 690 +}
 691 +EXPORT_SYMBOL(lq_set_counter);
 692 +
 693 +static long gptu_ioctl(struct file *file, unsigned int cmd,
 694 +       unsigned long arg)
 695 +{
 696 +       int ret;
 697 +       struct gptu_ioctl_param param;
 698 +
 699 +       if (!access_ok(VERIFY_READ, arg, sizeof(struct gptu_ioctl_param)))
 700 +               return -EFAULT;
 701 +       copy_from_user(&param, (void *) arg, sizeof(param));
 702 +
 703 +       if ((((cmd == GPTU_REQUEST_TIMER || cmd == GPTU_SET_TIMER
 704 +              || GPTU_SET_COUNTER) && param.timer < 2)
 705 +            || cmd == GPTU_GET_COUNT_VALUE || cmd == GPTU_CALCULATE_DIVIDER)
 706 +           && !access_ok(VERIFY_WRITE, arg,
 707 +                          sizeof(struct gptu_ioctl_param)))
 708 +               return -EFAULT;
 709 +
 710 +       switch (cmd) {
 711 +       case GPTU_REQUEST_TIMER:
 712 +               ret = lq_request_timer(param.timer, param.flag, param.value,
 713 +                                    (unsigned long) param.pid,
 714 +                                    (unsigned long) param.sig);
 715 +               if (ret > 0) {
 716 +                       copy_to_user(&((struct gptu_ioctl_param *) arg)->
 717 +                                     timer, &ret, sizeof(&ret));
 718 +                       ret = 0;
 719 +               }
 720 +               break;
 721 +       case GPTU_FREE_TIMER:
 722 +               ret = lq_free_timer(param.timer);
 723 +               break;
 724 +       case GPTU_START_TIMER:
 725 +               ret = lq_start_timer(param.timer, param.flag);
 726 +               break;
 727 +       case GPTU_STOP_TIMER:
 728 +               ret = lq_stop_timer(param.timer);
 729 +               break;
 730 +       case GPTU_GET_COUNT_VALUE:
 731 +               ret = lq_get_count_value(param.timer, &param.value);
 732 +               if (!ret)
 733 +                       copy_to_user(&((struct gptu_ioctl_param *) arg)->
 734 +                                     value, &param.value,
 735 +                                     sizeof(param.value));
 736 +               break;
 737 +       case GPTU_CALCULATE_DIVIDER:
 738 +               param.value = lq_cal_divider(param.value);
 739 +               if (param.value == 0)
 740 +                       ret = -EINVAL;
 741 +               else {
 742 +                       copy_to_user(&((struct gptu_ioctl_param *) arg)->
 743 +                                     value, &param.value,
 744 +                                     sizeof(param.value));
 745 +                       ret = 0;
 746 +               }
 747 +               break;
 748 +       case GPTU_SET_TIMER:
 749 +               ret = lq_set_timer(param.timer, param.value,
 750 +                                TIMER_FLAG_MASK_STOP(param.flag) !=
 751 +                                TIMER_FLAG_ONCE ? 1 : 0,
 752 +                                TIMER_FLAG_MASK_SRC(param.flag) ==
 753 +                                TIMER_FLAG_EXT_SRC ? 1 : 0,
 754 +                                TIMER_FLAG_MASK_HANDLE(param.flag) ==
 755 +                                TIMER_FLAG_SIGNAL ? TIMER_FLAG_SIGNAL :
 756 +                                TIMER_FLAG_NO_HANDLE,
 757 +                                (unsigned long) param.pid,
 758 +                                (unsigned long) param.sig);
 759 +               if (ret > 0) {
 760 +                       copy_to_user(&((struct gptu_ioctl_param *) arg)->
 761 +                                     timer, &ret, sizeof(&ret));
 762 +                       ret = 0;
 763 +               }
 764 +               break;
 765 +       case GPTU_SET_COUNTER:
 766 +               lq_set_counter(param.timer, param.flag, param.value, 0, 0);
 767 +               if (ret > 0) {
 768 +                       copy_to_user(&((struct gptu_ioctl_param *) arg)->
 769 +                                     timer, &ret, sizeof(&ret));
 770 +                       ret = 0;
 771 +               }
 772 +               break;
 773 +       default:
 774 +               ret = -ENOTTY;
 775 +       }
 776 +
 777 +       return ret;
 778 +}
 779 +
 780 +static int gptu_open(struct inode *inode, struct file *file)
 781 +{
 782 +       return 0;
 783 +}
 784 +
 785 +static int gptu_release(struct inode *inode, struct file *file)
 786 +{
 787 +       return 0;
 788 +}
 789 +
 790 +int __init lq_gptu_init(void)
 791 +{
 792 +       int ret;
 793 +       unsigned int i;
 794 +
 795 +       ltq_w32(0, LQ_GPTU_IRNEN);
 796 +       ltq_w32(0xfff, LQ_GPTU_IRNCR);
 797 +
 798 +       memset(&timer_dev, 0, sizeof(timer_dev));
 799 +       mutex_init(&timer_dev.gptu_mutex);
 800 +
 801 +       lq_enable_gptu();
 802 +       timer_dev.number_of_timers = GPTU_ID_CFG * 2;
 803 +       lq_disable_gptu();
 804 +       if (timer_dev.number_of_timers > MAX_NUM_OF_32BIT_TIMER_BLOCKS * 2)
 805 +               timer_dev.number_of_timers = MAX_NUM_OF_32BIT_TIMER_BLOCKS * 2;
 806 +       printk(KERN_INFO "gptu: totally %d 16-bit timers/counters\n", timer_dev.number_of_timers);
 807 +
 808 +       ret = misc_register(&gptu_miscdev);
 809 +       if (ret) {
 810 +               printk(KERN_ERR "gptu: can't misc_register, get error %d\n", -ret);
 811 +               return ret;
 812 +       } else {
 813 +               printk(KERN_INFO "gptu: misc_register on minor %d\n", gptu_miscdev.minor);
 814 +       }
 815 +
 816 +       for (i = 0; i < timer_dev.number_of_timers; i++) {
 817 +               ret = request_irq(TIMER_INTERRUPT + i, timer_irq_handler, IRQF_TIMER, gptu_miscdev.name, &timer_dev.timer[i]);
 818 +               if (ret) {
 819 +                       for (; i >= 0; i--)
 820 +                               free_irq(TIMER_INTERRUPT + i, &timer_dev.timer[i]);
 821 +                       misc_deregister(&gptu_miscdev);
 822 +                       printk(KERN_ERR "gptu: failed in requesting irq (%d), get error %d\n", i, -ret);
 823 +                       return ret;
 824 +               } else {
 825 +                       timer_dev.timer[i].irq = TIMER_INTERRUPT + i;
 826 +                       disable_irq(timer_dev.timer[i].irq);
 827 +                       printk(KERN_INFO "gptu: succeeded to request irq %d\n", timer_dev.timer[i].irq);
 828 +               }
 829 +       }
 830 +
 831 +       return 0;
 832 +}
 833 +
 834 +void __exit lq_gptu_exit(void)
 835 +{
 836 +       unsigned int i;
 837 +
 838 +       for (i = 0; i < timer_dev.number_of_timers; i++) {
 839 +               if (timer_dev.timer[i].f_irq_on)
 840 +                       disable_irq(timer_dev.timer[i].irq);
 841 +               free_irq(timer_dev.timer[i].irq, &timer_dev.timer[i]);
 842 +       }
 843 +       lq_disable_gptu();
 844 +       misc_deregister(&gptu_miscdev);
 845 +}
 846 +
 847 +module_init(lq_gptu_init);
 848 +module_exit(lq_gptu_exit);
 849 +
 850 +#endif
 851 Index: linux-3.7.4/arch/mips/include/asm/mach-lantiq/lantiq_timer.h
 852 ===================================================================
 853 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
 854 +++ linux-3.7.4/arch/mips/include/asm/mach-lantiq/lantiq_timer.h        2013-01-28 18:26:14.280164283 +0100
 855 @@ -0,0 +1,155 @@
 856 +#ifndef __DANUBE_GPTU_DEV_H__2005_07_26__10_19__
 857 +#define __DANUBE_GPTU_DEV_H__2005_07_26__10_19__
 858 +
 859 +
 860 +/******************************************************************************
 861 +       Copyright (c) 2002, Infineon Technologies.  All rights reserved.
 862 +
 863 +                               No Warranty
 864 +   Because the program is licensed free of charge, there is no warranty for
 865 +   the program, to the extent permitted by applicable law.  Except when
 866 +   otherwise stated in writing the copyright holders and/or other parties
 867 +   provide the program "as is" without warranty of any kind, either
 868 +   expressed or implied, including, but not limited to, the implied
 869 +   warranties of merchantability and fitness for a particular purpose. The
 870 +   entire risk as to the quality and performance of the program is with
 871 +   you.  should the program prove defective, you assume the cost of all
 872 +   necessary servicing, repair or correction.
 873 +
 874 +   In no event unless required by applicable law or agreed to in writing
 875 +   will any copyright holder, or any other party who may modify and/or
 876 +   redistribute the program as permitted above, be liable to you for
 877 +   damages, including any general, special, incidental or consequential
 878 +   damages arising out of the use or inability to use the program
 879 +   (including but not limited to loss of data or data being rendered
 880 +   inaccurate or losses sustained by you or third parties or a failure of
 881 +   the program to operate with any other programs), even if such holder or
 882 +   other party has been advised of the possibility of such damages.
 883 +******************************************************************************/
 884 +
 885 +
 886 +/*
 887 + * ####################################
 888 + *              Definition
 889 + * ####################################
 890 + */
 891 +
 892 +/*
 893 + *  Available Timer/Counter Index
 894 + */
 895 +#define TIMER(n, X)                     (n * 2 + (X ? 1 : 0))
 896 +#define TIMER_ANY                       0x00
 897 +#define TIMER1A                         TIMER(1, 0)
 898 +#define TIMER1B                         TIMER(1, 1)
 899 +#define TIMER2A                         TIMER(2, 0)
 900 +#define TIMER2B                         TIMER(2, 1)
 901 +#define TIMER3A                         TIMER(3, 0)
 902 +#define TIMER3B                         TIMER(3, 1)
 903 +
 904 +/*
 905 + *  Flag of Timer/Counter
 906 + *  These flags specify the way in which timer is configured.
 907 + */
 908 +/*  Bit size of timer/counter.                      */
 909 +#define TIMER_FLAG_16BIT                0x0000
 910 +#define TIMER_FLAG_32BIT                0x0001
 911 +/*  Switch between timer and counter.               */
 912 +#define TIMER_FLAG_TIMER                0x0000
 913 +#define TIMER_FLAG_COUNTER              0x0002
 914 +/*  Stop or continue when overflowing/underflowing. */
 915 +#define TIMER_FLAG_ONCE                 0x0000
 916 +#define TIMER_FLAG_CYCLIC               0x0004
 917 +/*  Count up or counter down.                       */
 918 +#define TIMER_FLAG_UP                   0x0000
 919 +#define TIMER_FLAG_DOWN                 0x0008
 920 +/*  Count on specific level or edge.                */
 921 +#define TIMER_FLAG_HIGH_LEVEL_SENSITIVE 0x0000
 922 +#define TIMER_FLAG_LOW_LEVEL_SENSITIVE  0x0040
 923 +#define TIMER_FLAG_RISE_EDGE            0x0010
 924 +#define TIMER_FLAG_FALL_EDGE            0x0020
 925 +#define TIMER_FLAG_ANY_EDGE             0x0030
 926 +/*  Signal is syncronous to module clock or not.    */
 927 +#define TIMER_FLAG_UNSYNC               0x0000
 928 +#define TIMER_FLAG_SYNC                 0x0080
 929 +/*  Different interrupt handle type.                */
 930 +#define TIMER_FLAG_NO_HANDLE            0x0000
 931 +#if defined(__KERNEL__)
 932 +    #define TIMER_FLAG_CALLBACK_IN_IRQ  0x0100
 933 +#endif  //  defined(__KERNEL__)
 934 +#define TIMER_FLAG_SIGNAL               0x0300
 935 +/*  Internal clock source or external clock source  */
 936 +#define TIMER_FLAG_INT_SRC              0x0000
 937 +#define TIMER_FLAG_EXT_SRC              0x1000
 938 +
 939 +
 940 +/*
 941 + *  ioctl Command
 942 + */
 943 +#define GPTU_REQUEST_TIMER              0x01    /*  General method to setup timer/counter.  */
 944 +#define GPTU_FREE_TIMER                 0x02    /*  Free timer/counter.                     */
 945 +#define GPTU_START_TIMER                0x03    /*  Start or resume timer/counter.          */
 946 +#define GPTU_STOP_TIMER                 0x04    /*  Suspend timer/counter.                  */
 947 +#define GPTU_GET_COUNT_VALUE            0x05    /*  Get current count value.                */
 948 +#define GPTU_CALCULATE_DIVIDER          0x06    /*  Calculate timer divider from given freq.*/
 949 +#define GPTU_SET_TIMER                  0x07    /*  Simplified method to setup timer.       */
 950 +#define GPTU_SET_COUNTER                0x08    /*  Simplified method to setup counter.     */
 951 +
 952 +/*
 953 + *  Data Type Used to Call ioctl
 954 + */
 955 +struct gptu_ioctl_param {
 956 +    unsigned int                        timer;  /*  In command GPTU_REQUEST_TIMER, GPTU_SET_TIMER, and  *
 957 +                                                 *  GPTU_SET_COUNTER, this field is ID of expected      *
 958 +                                                 *  timer/counter. If it's zero, a timer/counter would  *
 959 +                                                 *  be dynamically allocated and ID would be stored in  *
 960 +                                                 *  this field.                                         *
 961 +                                                 *  In command GPTU_GET_COUNT_VALUE, this field is      *
 962 +                                                 *  ignored.                                            *
 963 +                                                 *  In other command, this field is ID of timer/counter *
 964 +                                                 *  allocated.                                          */
 965 +    unsigned int                        flag;   /*  In command GPTU_REQUEST_TIMER, GPTU_SET_TIMER, and  *
 966 +                                                 *  GPTU_SET_COUNTER, this field contains flags to      *
 967 +                                                 *  specify how to configure timer/counter.             *
 968 +                                                 *  In command GPTU_START_TIMER, zero indicate start    *
 969 +                                                 *  and non-zero indicate resume timer/counter.         *
 970 +                                                 *  In other command, this field is ignored.            */
 971 +    unsigned long                       value;  /*  In command GPTU_REQUEST_TIMER, this field contains  *
 972 +                                                 *  init/reload value.                                  *
 973 +                                                 *  In command GPTU_SET_TIMER, this field contains      *
 974 +                                                 *  frequency (0.001Hz) of timer.                       *
 975 +                                                 *  In command GPTU_GET_COUNT_VALUE, current count      *
 976 +                                                 *  value would be stored in this field.                *
 977 +                                                 *  In command GPTU_CALCULATE_DIVIDER, this field       *
 978 +                                                 *  contains frequency wanted, and after calculation,   *
 979 +                                                 *  divider would be stored in this field to overwrite  *
 980 +                                                 *  the frequency.                                      *
 981 +                                                 *  In other command, this field is ignored.            */
 982 +    int                                 pid;    /*  In command GPTU_REQUEST_TIMER and GPTU_SET_TIMER,   *
 983 +                                                 *  if signal is required, this field contains process  *
 984 +                                                 *  ID to which signal would be sent.                   *
 985 +                                                 *  In other command, this field is ignored.            */
 986 +    int                                 sig;    /*  In command GPTU_REQUEST_TIMER and GPTU_SET_TIMER,   *
 987 +                                                 *  if signal is required, this field contains signal   *
 988 +                                                 *  number which would be sent.                         *
 989 +                                                 *  In other command, this field is ignored.            */
 990 +};
 991 +
 992 +/*
 993 + * ####################################
 994 + *              Data Type
 995 + * ####################################
 996 + */
 997 +typedef void (*timer_callback)(unsigned long arg);
 998 +
 999 +extern int lq_request_timer(unsigned int, unsigned int, unsigned long, unsigned long, unsigned long);
1000 +extern int lq_free_timer(unsigned int);
1001 +extern int lq_start_timer(unsigned int, int);
1002 +extern int lq_stop_timer(unsigned int);
1003 +extern int lq_reset_counter_flags(u32 timer, u32 flags);
1004 +extern int lq_get_count_value(unsigned int, unsigned long *);
1005 +extern u32 lq_cal_divider(unsigned long);
1006 +extern int lq_set_timer(unsigned int, unsigned int, int, int, unsigned int, unsigned long, unsigned long);
1007 +extern int lq_set_counter(unsigned int timer, unsigned int flag,
1008 +       u32 reload, unsigned long arg1, unsigned long arg2);
1009 +
1010 +#endif /* __DANUBE_GPTU_DEV_H__2005_07_26__10_19__ */
1011 Index: linux-3.7.4/arch/mips/lantiq/xway/Makefile
1012 ===================================================================
1013 --- linux-3.7.4.orig/arch/mips/lantiq/xway/Makefile     2013-01-28 18:26:06.580164100 +0100
1014 +++ linux-3.7.4/arch/mips/lantiq/xway/Makefile  2013-01-28 18:38:07.848181285 +0100
1015 @@ -1,3 +1,3 @@
1016 -obj-y := prom.o sysctrl.o clk.o reset.o dma.o gptu.o dcdc.o
1017 +obj-y := prom.o sysctrl.o clk.o reset.o dma.o timer.o dcdc.o
1018
1019  obj-$(CONFIG_XRX200_PHY_FW) += xrx200_phy_fw.o