target/linux/lantiq/patches-3.6/0008-MIPS-lantiq-enable-pci-clk-conditional-for-xrx200-So.patch

   1 From f40e1f9d856ec417468c090c4b56826171daa670 Mon Sep 17 00:00:00 2001
   2 From: John Crispin <blogic@openwrt.org>
   3 Date: Thu, 16 Aug 2012 08:25:42 +0000
   4 Subject: [PATCH 8/9] MIPS: lantiq: enable pci clk conditional for xrx200 SoC
   5
   6 The xrx200 SoC family has the same PCI clock register layout as the AR9.
   7 Enable the same quirk as for AR9
   8
   9 Signed-off-by: John Crispin <blogic@openwrt.org>
  10 Patchwork: http://patchwork.linux-mips.org/patch/4235/
  11 ---
  12  arch/mips/lantiq/xway/sysctrl.c |    3 ++-
  13  1 file changed, 2 insertions(+), 1 deletion(-)
  14
  15 diff --git a/arch/mips/lantiq/xway/sysctrl.c b/arch/mips/lantiq/xway/sysctrl.c
  16 index befbb76..67c3a91 100644
  17 --- a/arch/mips/lantiq/xway/sysctrl.c
  18 +++ b/arch/mips/lantiq/xway/sysctrl.c
  19 @@ -145,7 +145,8 @@ static int pci_enable(struct clk *clk)
  20  {
  21         unsigned int val = ltq_cgu_r32(ifccr);
  22         /* set bus clock speed */
  23 -       if (of_machine_is_compatible("lantiq,ar9")) {
  24 +       if (of_machine_is_compatible("lantiq,ar9") ||
  25 +                       of_machine_is_compatible("lantiq,vr9")) {
  26                 val &= ~0x1f00000;
  27                 if (clk->rate == CLOCK_33M)
  28                         val |= 0xe00000;
  29 --
  30 1.7.10.4
  31