target/linux/lantiq/patches-3.3/0048-MIPS-lantiq-pci-rename-variable-inside.patch

   1 From 202f1bad2707e843dccc0fb08233692f8c845f90 Mon Sep 17 00:00:00 2001
   2 From: John Crispin <blogic@openwrt.org>
   3 Date: Thu, 8 Mar 2012 12:00:17 +0100
   4 Subject: [PATCH 48/70] MIPS: lantiq: pci: rename variable inside
   5
   6 * rename a global var inside the pci code
   7 ---
   8  arch/mips/pci/ops-lantiq.c |    6 +++---
   9  arch/mips/pci/pci-lantiq.c |    6 +++---
  10  arch/mips/pci/pci-lantiq.h |    2 +-
  11  3 files changed, 7 insertions(+), 7 deletions(-)
  12
  13 diff --git a/arch/mips/pci/ops-lantiq.c b/arch/mips/pci/ops-lantiq.c
  14 index 1f2afb5..5cbb0cf 100644
  15 --- a/arch/mips/pci/ops-lantiq.c
  16 +++ b/arch/mips/pci/ops-lantiq.c
  17 @@ -41,7 +41,7 @@ static int ltq_pci_config_access(unsigned char access_type, struct pci_bus *bus,
  18
  19         spin_lock_irqsave(&ebu_lock, flags);
  20
  21 -       cfg_base = (unsigned long) ltq_pci_mapped_cfg;
  22 +       cfg_base = (unsigned long) ltq_pci_cfgbase;
  23         cfg_base |= (bus->number << LTQ_PCI_CFG_BUSNUM_SHF) | (devfn <<
  24                         LTQ_PCI_CFG_FUNNUM_SHF) | (where & ~0x3);
  25
  26 @@ -55,11 +55,11 @@ static int ltq_pci_config_access(unsigned char access_type, struct pci_bus *bus,
  27         wmb();
  28
  29         /* clean possible Master abort */
  30 -       cfg_base = (unsigned long) ltq_pci_mapped_cfg;
  31 +       cfg_base = (unsigned long) ltq_pci_cfgbase;
  32         cfg_base |= (0x0 << LTQ_PCI_CFG_FUNNUM_SHF) + 4;
  33         temp = ltq_r32(((u32 *)(cfg_base)));
  34         temp = swab32(temp);
  35 -       cfg_base = (unsigned long) ltq_pci_mapped_cfg;
  36 +       cfg_base = (unsigned long) ltq_pci_cfgbase;
  37         cfg_base |= (0x68 << LTQ_PCI_CFG_FUNNUM_SHF) + 4;
  38         ltq_w32(temp, ((u32 *)cfg_base));
  39
  40 diff --git a/arch/mips/pci/pci-lantiq.c b/arch/mips/pci/pci-lantiq.c
  41 index 47b551c..efcdd45 100644
  42 --- a/arch/mips/pci/pci-lantiq.c
  43 +++ b/arch/mips/pci/pci-lantiq.c
  44 @@ -65,8 +65,8 @@
  45  #define ltq_pci_w32(x, y)      ltq_w32((x), ltq_pci_membase + (y))
  46  #define ltq_pci_r32(x)         ltq_r32(ltq_pci_membase + (x))
  47
  48 -#define ltq_pci_cfg_w32(x, y)  ltq_w32((x), ltq_pci_mapped_cfg + (y))
  49 -#define ltq_pci_cfg_r32(x)     ltq_r32(ltq_pci_mapped_cfg + (x))
  50 +#define ltq_pci_cfg_w32(x, y)  ltq_w32((x), ltq_pci_cfgbase + (y))
  51 +#define ltq_pci_cfg_r32(x)     ltq_r32(ltq_pci_cfgbase + (x))
  52
  53  struct ltq_pci_gpio_map {
  54         int pin;
  55 @@ -273,7 +273,7 @@ static int __devinit ltq_pci_probe(struct platform_device *pdev)
  56         pci_probe_only = 0;
  57         ltq_pci_irq_map = ltq_pci_data->irq;
  58         ltq_pci_membase = ioremap_nocache(PCI_CR_BASE_ADDR, PCI_CR_SIZE);
  59 -       ltq_pci_mapped_cfg =
  60 +       ltq_pci_cfgbase =
  61                 ioremap_nocache(LTQ_PCI_CFG_BASE, LTQ_PCI_CFG_BASE);
  62         ltq_pci_controller.io_map_base =
  63                 (unsigned long)ioremap(LTQ_PCI_IO_BASE, LTQ_PCI_IO_SIZE - 1);
  64 diff --git a/arch/mips/pci/pci-lantiq.h b/arch/mips/pci/pci-lantiq.h
  65 index 66bf6cd..c4721b4 100644
  66 --- a/arch/mips/pci/pci-lantiq.h
  67 +++ b/arch/mips/pci/pci-lantiq.h
  68 @@ -9,7 +9,7 @@
  69  #ifndef _LTQ_PCI_H__
  70  #define _LTQ_PCI_H__
  71
  72 -extern __iomem void *ltq_pci_mapped_cfg;
  73 +extern __iomem void *ltq_pci_cfgbase;
  74  extern int ltq_pci_read_config_dword(struct pci_bus *bus,
  75         unsigned int devfn, int where, int size, u32 *val);
  76  extern int ltq_pci_write_config_dword(struct pci_bus *bus,
  77 --
  78 1.7.9.1
  79