target/linux/lantiq/patches-3.3/0003-svip-hack.patch

   1 From 03de60e7fd96c0d78d293dc859a2a9ad2d2f16c4 Mon Sep 17 00:00:00 2001
   2 From: John Crispin <blogic@openwrt.org>
   3 Date: Fri, 3 Aug 2012 10:22:41 +0200
   4 Subject: [PATCH 03/25] svip hack
   5
   6 ---
   7  arch/mips/kernel/cevt-r4k.c |    2 ++
   8  arch/mips/mm/c-r4k.c        |    3 +++
   9  2 files changed, 5 insertions(+), 0 deletions(-)
  10
  11 diff --git a/arch/mips/kernel/cevt-r4k.c b/arch/mips/kernel/cevt-r4k.c
  12 index 51095dd..db9070c 100644
  13 --- a/arch/mips/kernel/cevt-r4k.c
  14 +++ b/arch/mips/kernel/cevt-r4k.c
  15 @@ -171,8 +171,10 @@ int __cpuinit r4k_clockevent_init(void)
  16         if (!cpu_has_counter || !mips_hpt_frequency)
  17                 return -ENXIO;
  18
  19 +#ifndef CONFIG_SOC_SVIP
  20         if (!c0_compare_int_usable())
  21                 return -ENXIO;
  22 +#endif
  23
  24         /*
  25          * With vectored interrupts things are getting platform specific.
  26 diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
  27 index 4f9eb0b..de3475e 100644
  28 --- a/arch/mips/mm/c-r4k.c
  29 +++ b/arch/mips/mm/c-r4k.c
  30 @@ -1252,6 +1252,9 @@ static void __cpuinit setup_scache(void)
  31                                        way_string[c->scache.ways], c->scache.linesz);
  32                         }
  33  #else
  34 +#ifdef CONFIG_SOC_SVIP
  35 +                       return;
  36 +#endif
  37                         if (!(c->scache.flags & MIPS_CACHE_NOT_PRESENT))
  38                                 panic("Dunno how to handle MIPS32 / MIPS64 second level cache");
  39  #endif
  40 --
  41 1.7.9.1
  42