target/linux/lantiq/patches-3.2/0046-MIPS-lantiq-adds-GPTU-driver.patch

   1 From 688c075ddc08723848df01fc0426d69d0b3a464b Mon Sep 17 00:00:00 2001
   2 From: John Crispin <blogic@openwrt.org>
   3 Date: Thu, 29 Sep 2011 17:16:38 +0200
   4 Subject: [PATCH 46/73] MIPS: lantiq: adds GPTU driver
   5
   6 ---
   7  arch/mips/include/asm/mach-lantiq/lantiq_timer.h |  155 ++++
   8  arch/mips/lantiq/xway/Makefile                   |    2 +-
   9  arch/mips/lantiq/xway/sysctrl.c                  |    1 +
  10  arch/mips/lantiq/xway/timer.c                    |  846 ++++++++++++++++++++++
  11  4 files changed, 1003 insertions(+), 1 deletions(-)
  12  create mode 100644 arch/mips/include/asm/mach-lantiq/lantiq_timer.h
  13  create mode 100644 arch/mips/lantiq/xway/timer.c
  14
  15 diff --git a/arch/mips/include/asm/mach-lantiq/lantiq_timer.h b/arch/mips/include/asm/mach-lantiq/lantiq_timer.h
  16 new file mode 100644
  17 index 0000000..ef564ab
  18 --- /dev/null
  19 +++ b/arch/mips/include/asm/mach-lantiq/lantiq_timer.h
  20 @@ -0,0 +1,155 @@
  21 +#ifndef __DANUBE_GPTU_DEV_H__2005_07_26__10_19__
  22 +#define __DANUBE_GPTU_DEV_H__2005_07_26__10_19__
  23 +
  24 +
  25 +/******************************************************************************
  26 +       Copyright (c) 2002, Infineon Technologies.  All rights reserved.
  27 +
  28 +                               No Warranty
  29 +   Because the program is licensed free of charge, there is no warranty for
  30 +   the program, to the extent permitted by applicable law.  Except when
  31 +   otherwise stated in writing the copyright holders and/or other parties
  32 +   provide the program "as is" without warranty of any kind, either
  33 +   expressed or implied, including, but not limited to, the implied
  34 +   warranties of merchantability and fitness for a particular purpose. The
  35 +   entire risk as to the quality and performance of the program is with
  36 +   you.  should the program prove defective, you assume the cost of all
  37 +   necessary servicing, repair or correction.
  38 +
  39 +   In no event unless required by applicable law or agreed to in writing
  40 +   will any copyright holder, or any other party who may modify and/or
  41 +   redistribute the program as permitted above, be liable to you for
  42 +   damages, including any general, special, incidental or consequential
  43 +   damages arising out of the use or inability to use the program
  44 +   (including but not limited to loss of data or data being rendered
  45 +   inaccurate or losses sustained by you or third parties or a failure of
  46 +   the program to operate with any other programs), even if such holder or
  47 +   other party has been advised of the possibility of such damages.
  48 +******************************************************************************/
  49 +
  50 +
  51 +/*
  52 + * ####################################
  53 + *              Definition
  54 + * ####################################
  55 + */
  56 +
  57 +/*
  58 + *  Available Timer/Counter Index
  59 + */
  60 +#define TIMER(n, X)                     (n * 2 + (X ? 1 : 0))
  61 +#define TIMER_ANY                       0x00
  62 +#define TIMER1A                         TIMER(1, 0)
  63 +#define TIMER1B                         TIMER(1, 1)
  64 +#define TIMER2A                         TIMER(2, 0)
  65 +#define TIMER2B                         TIMER(2, 1)
  66 +#define TIMER3A                         TIMER(3, 0)
  67 +#define TIMER3B                         TIMER(3, 1)
  68 +
  69 +/*
  70 + *  Flag of Timer/Counter
  71 + *  These flags specify the way in which timer is configured.
  72 + */
  73 +/*  Bit size of timer/counter.                      */
  74 +#define TIMER_FLAG_16BIT                0x0000
  75 +#define TIMER_FLAG_32BIT                0x0001
  76 +/*  Switch between timer and counter.               */
  77 +#define TIMER_FLAG_TIMER                0x0000
  78 +#define TIMER_FLAG_COUNTER              0x0002
  79 +/*  Stop or continue when overflowing/underflowing. */
  80 +#define TIMER_FLAG_ONCE                 0x0000
  81 +#define TIMER_FLAG_CYCLIC               0x0004
  82 +/*  Count up or counter down.                       */
  83 +#define TIMER_FLAG_UP                   0x0000
  84 +#define TIMER_FLAG_DOWN                 0x0008
  85 +/*  Count on specific level or edge.                */
  86 +#define TIMER_FLAG_HIGH_LEVEL_SENSITIVE 0x0000
  87 +#define TIMER_FLAG_LOW_LEVEL_SENSITIVE  0x0040
  88 +#define TIMER_FLAG_RISE_EDGE            0x0010
  89 +#define TIMER_FLAG_FALL_EDGE            0x0020
  90 +#define TIMER_FLAG_ANY_EDGE             0x0030
  91 +/*  Signal is syncronous to module clock or not.    */
  92 +#define TIMER_FLAG_UNSYNC               0x0000
  93 +#define TIMER_FLAG_SYNC                 0x0080
  94 +/*  Different interrupt handle type.                */
  95 +#define TIMER_FLAG_NO_HANDLE            0x0000
  96 +#if defined(__KERNEL__)
  97 +    #define TIMER_FLAG_CALLBACK_IN_IRQ  0x0100
  98 +#endif  //  defined(__KERNEL__)
  99 +#define TIMER_FLAG_SIGNAL               0x0300
 100 +/*  Internal clock source or external clock source  */
 101 +#define TIMER_FLAG_INT_SRC              0x0000
 102 +#define TIMER_FLAG_EXT_SRC              0x1000
 103 +
 104 +
 105 +/*
 106 + *  ioctl Command
 107 + */
 108 +#define GPTU_REQUEST_TIMER              0x01    /*  General method to setup timer/counter.  */
 109 +#define GPTU_FREE_TIMER                 0x02    /*  Free timer/counter.                     */
 110 +#define GPTU_START_TIMER                0x03    /*  Start or resume timer/counter.          */
 111 +#define GPTU_STOP_TIMER                 0x04    /*  Suspend timer/counter.                  */
 112 +#define GPTU_GET_COUNT_VALUE            0x05    /*  Get current count value.                */
 113 +#define GPTU_CALCULATE_DIVIDER          0x06    /*  Calculate timer divider from given freq.*/
 114 +#define GPTU_SET_TIMER                  0x07    /*  Simplified method to setup timer.       */
 115 +#define GPTU_SET_COUNTER                0x08    /*  Simplified method to setup counter.     */
 116 +
 117 +/*
 118 + *  Data Type Used to Call ioctl
 119 + */
 120 +struct gptu_ioctl_param {
 121 +    unsigned int                        timer;  /*  In command GPTU_REQUEST_TIMER, GPTU_SET_TIMER, and  *
 122 +                                                 *  GPTU_SET_COUNTER, this field is ID of expected      *
 123 +                                                 *  timer/counter. If it's zero, a timer/counter would  *
 124 +                                                 *  be dynamically allocated and ID would be stored in  *
 125 +                                                 *  this field.                                         *
 126 +                                                 *  In command GPTU_GET_COUNT_VALUE, this field is      *
 127 +                                                 *  ignored.                                            *
 128 +                                                 *  In other command, this field is ID of timer/counter *
 129 +                                                 *  allocated.                                          */
 130 +    unsigned int                        flag;   /*  In command GPTU_REQUEST_TIMER, GPTU_SET_TIMER, and  *
 131 +                                                 *  GPTU_SET_COUNTER, this field contains flags to      *
 132 +                                                 *  specify how to configure timer/counter.             *
 133 +                                                 *  In command GPTU_START_TIMER, zero indicate start    *
 134 +                                                 *  and non-zero indicate resume timer/counter.         *
 135 +                                                 *  In other command, this field is ignored.            */
 136 +    unsigned long                       value;  /*  In command GPTU_REQUEST_TIMER, this field contains  *
 137 +                                                 *  init/reload value.                                  *
 138 +                                                 *  In command GPTU_SET_TIMER, this field contains      *
 139 +                                                 *  frequency (0.001Hz) of timer.                       *
 140 +                                                 *  In command GPTU_GET_COUNT_VALUE, current count      *
 141 +                                                 *  value would be stored in this field.                *
 142 +                                                 *  In command GPTU_CALCULATE_DIVIDER, this field       *
 143 +                                                 *  contains frequency wanted, and after calculation,   *
 144 +                                                 *  divider would be stored in this field to overwrite  *
 145 +                                                 *  the frequency.                                      *
 146 +                                                 *  In other command, this field is ignored.            */
 147 +    int                                 pid;    /*  In command GPTU_REQUEST_TIMER and GPTU_SET_TIMER,   *
 148 +                                                 *  if signal is required, this field contains process  *
 149 +                                                 *  ID to which signal would be sent.                   *
 150 +                                                 *  In other command, this field is ignored.            */
 151 +    int                                 sig;    /*  In command GPTU_REQUEST_TIMER and GPTU_SET_TIMER,   *
 152 +                                                 *  if signal is required, this field contains signal   *
 153 +                                                 *  number which would be sent.                         *
 154 +                                                 *  In other command, this field is ignored.            */
 155 +};
 156 +
 157 +/*
 158 + * ####################################
 159 + *              Data Type
 160 + * ####################################
 161 + */
 162 +typedef void (*timer_callback)(unsigned long arg);
 163 +
 164 +extern int lq_request_timer(unsigned int, unsigned int, unsigned long, unsigned long, unsigned long);
 165 +extern int lq_free_timer(unsigned int);
 166 +extern int lq_start_timer(unsigned int, int);
 167 +extern int lq_stop_timer(unsigned int);
 168 +extern int lq_reset_counter_flags(u32 timer, u32 flags);
 169 +extern int lq_get_count_value(unsigned int, unsigned long *);
 170 +extern u32 lq_cal_divider(unsigned long);
 171 +extern int lq_set_timer(unsigned int, unsigned int, int, int, unsigned int, unsigned long, unsigned long);
 172 +extern int lq_set_counter(unsigned int timer, unsigned int flag,
 173 +       u32 reload, unsigned long arg1, unsigned long arg2);
 174 +
 175 +#endif /* __DANUBE_GPTU_DEV_H__2005_07_26__10_19__ */
 176 diff --git a/arch/mips/lantiq/xway/Makefile b/arch/mips/lantiq/xway/Makefile
 177 index 277aa34..4c3106f 100644
 178 --- a/arch/mips/lantiq/xway/Makefile
 179 +++ b/arch/mips/lantiq/xway/Makefile
 180 @@ -1,4 +1,4 @@
 181 -obj-y := sysctrl.o reset.o gpio.o gpio_stp.o gpio_ebu.o devices.o dma.o clk.o prom.o nand.o
 182 +obj-y := sysctrl.o reset.o gpio.o gpio_stp.o gpio_ebu.o devices.o dma.o clk.o prom.o nand.o timer.o
 183
 184  obj-$(CONFIG_LANTIQ_MACH_EASY50712) += mach-easy50712.o
 185  obj-$(CONFIG_LANTIQ_MACH_EASY50601) += mach-easy50601.o
 186 diff --git a/arch/mips/lantiq/xway/sysctrl.c b/arch/mips/lantiq/xway/sysctrl.c
 187 index 38f02f9..1a2e2d4 100644
 188 --- a/arch/mips/lantiq/xway/sysctrl.c
 189 +++ b/arch/mips/lantiq/xway/sysctrl.c
 190 @@ -147,6 +147,7 @@ void __init ltq_soc_init(void)
 191         clkdev_add_pmu("ltq_dma", NULL, 0, PMU_DMA);
 192         clkdev_add_pmu("ltq_stp", NULL, 0, PMU_STP);
 193         clkdev_add_pmu("ltq_spi", NULL, 0, PMU_SPI);
 194 +        clkdev_add_pmu("ltq_gptu", NULL, 0, PMU_GPT);
 195         if (!ltq_is_vr9())
 196                 clkdev_add_pmu("ltq_etop", NULL, 0, PMU_PPE);
 197         if (ltq_is_ase()) {
 198 diff --git a/arch/mips/lantiq/xway/timer.c b/arch/mips/lantiq/xway/timer.c
 199 new file mode 100644
 200 index 0000000..9794c87
 201 --- /dev/null
 202 +++ b/arch/mips/lantiq/xway/timer.c
 203 @@ -0,0 +1,846 @@
 204 +#include <linux/kernel.h>
 205 +#include <linux/module.h>
 206 +#include <linux/version.h>
 207 +#include <linux/types.h>
 208 +#include <linux/fs.h>
 209 +#include <linux/miscdevice.h>
 210 +#include <linux/init.h>
 211 +#include <linux/uaccess.h>
 212 +#include <linux/unistd.h>
 213 +#include <linux/errno.h>
 214 +#include <linux/interrupt.h>
 215 +#include <linux/sched.h>
 216 +
 217 +#include <asm/irq.h>
 218 +#include <asm/div64.h>
 219 +#include "../clk.h"
 220 +
 221 +#include <lantiq_soc.h>
 222 +#include <lantiq_irq.h>
 223 +#include <lantiq_timer.h>
 224 +
 225 +#define MAX_NUM_OF_32BIT_TIMER_BLOCKS  6
 226 +
 227 +#ifdef TIMER1A
 228 +#define FIRST_TIMER                    TIMER1A
 229 +#else
 230 +#define FIRST_TIMER                    2
 231 +#endif
 232 +
 233 +/*
 234 + *  GPTC divider is set or not.
 235 + */
 236 +#define GPTU_CLC_RMC_IS_SET            0
 237 +
 238 +/*
 239 + *  Timer Interrupt (IRQ)
 240 + */
 241 +/*  Must be adjusted when ICU driver is available */
 242 +#define TIMER_INTERRUPT                        (INT_NUM_IM3_IRL0 + 22)
 243 +
 244 +/*
 245 + *  Bits Operation
 246 + */
 247 +#define GET_BITS(x, msb, lsb)          \
 248 +       (((x) & ((1 << ((msb) + 1)) - 1)) >> (lsb))
 249 +#define SET_BITS(x, msb, lsb, value)   \
 250 +       (((x) & ~(((1 << ((msb) + 1)) - 1) ^ ((1 << (lsb)) - 1))) | \
 251 +       (((value) & ((1 << (1 + (msb) - (lsb))) - 1)) << (lsb)))
 252 +
 253 +/*
 254 + *  GPTU Register Mapping
 255 + */
 256 +#define LQ_GPTU                        (KSEG1 + 0x1E100A00)
 257 +#define LQ_GPTU_CLC            ((volatile u32 *)(LQ_GPTU + 0x0000))
 258 +#define LQ_GPTU_ID                     ((volatile u32 *)(LQ_GPTU + 0x0008))
 259 +#define LQ_GPTU_CON(n, X)              ((volatile u32 *)(LQ_GPTU + 0x0010 + ((X) * 4) + ((n) - 1) * 0x0020))   /* X must be either A or B */
 260 +#define LQ_GPTU_RUN(n, X)              ((volatile u32 *)(LQ_GPTU + 0x0018 + ((X) * 4) + ((n) - 1) * 0x0020))   /* X must be either A or B */
 261 +#define LQ_GPTU_RELOAD(n, X)   ((volatile u32 *)(LQ_GPTU + 0x0020 + ((X) * 4) + ((n) - 1) * 0x0020))   /* X must be either A or B */
 262 +#define LQ_GPTU_COUNT(n, X)    ((volatile u32 *)(LQ_GPTU + 0x0028 + ((X) * 4) + ((n) - 1) * 0x0020))   /* X must be either A or B */
 263 +#define LQ_GPTU_IRNEN          ((volatile u32 *)(LQ_GPTU + 0x00F4))
 264 +#define LQ_GPTU_IRNICR         ((volatile u32 *)(LQ_GPTU + 0x00F8))
 265 +#define LQ_GPTU_IRNCR          ((volatile u32 *)(LQ_GPTU + 0x00FC))
 266 +
 267 +/*
 268 + *  Clock Control Register
 269 + */
 270 +#define GPTU_CLC_SMC                   GET_BITS(*LQ_GPTU_CLC, 23, 16)
 271 +#define GPTU_CLC_RMC                   GET_BITS(*LQ_GPTU_CLC, 15, 8)
 272 +#define GPTU_CLC_FSOE                  (*LQ_GPTU_CLC & (1 << 5))
 273 +#define GPTU_CLC_EDIS                  (*LQ_GPTU_CLC & (1 << 3))
 274 +#define GPTU_CLC_SPEN                  (*LQ_GPTU_CLC & (1 << 2))
 275 +#define GPTU_CLC_DISS                  (*LQ_GPTU_CLC & (1 << 1))
 276 +#define GPTU_CLC_DISR                  (*LQ_GPTU_CLC & (1 << 0))
 277 +
 278 +#define GPTU_CLC_SMC_SET(value)                SET_BITS(0, 23, 16, (value))
 279 +#define GPTU_CLC_RMC_SET(value)                SET_BITS(0, 15, 8, (value))
 280 +#define GPTU_CLC_FSOE_SET(value)       ((value) ? (1 << 5) : 0)
 281 +#define GPTU_CLC_SBWE_SET(value)       ((value) ? (1 << 4) : 0)
 282 +#define GPTU_CLC_EDIS_SET(value)       ((value) ? (1 << 3) : 0)
 283 +#define GPTU_CLC_SPEN_SET(value)       ((value) ? (1 << 2) : 0)
 284 +#define GPTU_CLC_DISR_SET(value)       ((value) ? (1 << 0) : 0)
 285 +
 286 +/*
 287 + *  ID Register
 288 + */
 289 +#define GPTU_ID_ID                     GET_BITS(*LQ_GPTU_ID, 15, 8)
 290 +#define GPTU_ID_CFG                    GET_BITS(*LQ_GPTU_ID, 7, 5)
 291 +#define GPTU_ID_REV                    GET_BITS(*LQ_GPTU_ID, 4, 0)
 292 +
 293 +/*
 294 + *  Control Register of Timer/Counter nX
 295 + *    n is the index of block (1 based index)
 296 + *    X is either A or B
 297 + */
 298 +#define GPTU_CON_SRC_EG(n, X)          (*LQ_GPTU_CON(n, X) & (1 << 10))
 299 +#define GPTU_CON_SRC_EXT(n, X)         (*LQ_GPTU_CON(n, X) & (1 << 9))
 300 +#define GPTU_CON_SYNC(n, X)            (*LQ_GPTU_CON(n, X) & (1 << 8))
 301 +#define GPTU_CON_EDGE(n, X)            GET_BITS(*LQ_GPTU_CON(n, X), 7, 6)
 302 +#define GPTU_CON_INV(n, X)             (*LQ_GPTU_CON(n, X) & (1 << 5))
 303 +#define GPTU_CON_EXT(n, X)             (*LQ_GPTU_CON(n, A) & (1 << 4)) /* Timer/Counter B does not have this bit */
 304 +#define GPTU_CON_STP(n, X)             (*LQ_GPTU_CON(n, X) & (1 << 3))
 305 +#define GPTU_CON_CNT(n, X)             (*LQ_GPTU_CON(n, X) & (1 << 2))
 306 +#define GPTU_CON_DIR(n, X)             (*LQ_GPTU_CON(n, X) & (1 << 1))
 307 +#define GPTU_CON_EN(n, X)              (*LQ_GPTU_CON(n, X) & (1 << 0))
 308 +
 309 +#define GPTU_CON_SRC_EG_SET(value)     ((value) ? 0 : (1 << 10))
 310 +#define GPTU_CON_SRC_EXT_SET(value)    ((value) ? (1 << 9) : 0)
 311 +#define GPTU_CON_SYNC_SET(value)       ((value) ? (1 << 8) : 0)
 312 +#define GPTU_CON_EDGE_SET(value)       SET_BITS(0, 7, 6, (value))
 313 +#define GPTU_CON_INV_SET(value)                ((value) ? (1 << 5) : 0)
 314 +#define GPTU_CON_EXT_SET(value)                ((value) ? (1 << 4) : 0)
 315 +#define GPTU_CON_STP_SET(value)                ((value) ? (1 << 3) : 0)
 316 +#define GPTU_CON_CNT_SET(value)                ((value) ? (1 << 2) : 0)
 317 +#define GPTU_CON_DIR_SET(value)                ((value) ? (1 << 1) : 0)
 318 +
 319 +#define GPTU_RUN_RL_SET(value)         ((value) ? (1 << 2) : 0)
 320 +#define GPTU_RUN_CEN_SET(value)                ((value) ? (1 << 1) : 0)
 321 +#define GPTU_RUN_SEN_SET(value)                ((value) ? (1 << 0) : 0)
 322 +
 323 +#define GPTU_IRNEN_TC_SET(n, X, value) ((value) ? (1 << (((n) - 1) * 2 + (X))) : 0)
 324 +#define GPTU_IRNCR_TC_SET(n, X, value) ((value) ? (1 << (((n) - 1) * 2 + (X))) : 0)
 325 +
 326 +#define TIMER_FLAG_MASK_SIZE(x)                (x & 0x0001)
 327 +#define TIMER_FLAG_MASK_TYPE(x)                (x & 0x0002)
 328 +#define TIMER_FLAG_MASK_STOP(x)                (x & 0x0004)
 329 +#define TIMER_FLAG_MASK_DIR(x)         (x & 0x0008)
 330 +#define TIMER_FLAG_NONE_EDGE           0x0000
 331 +#define TIMER_FLAG_MASK_EDGE(x)                (x & 0x0030)
 332 +#define TIMER_FLAG_REAL                        0x0000
 333 +#define TIMER_FLAG_INVERT              0x0040
 334 +#define TIMER_FLAG_MASK_INVERT(x)      (x & 0x0040)
 335 +#define TIMER_FLAG_MASK_TRIGGER(x)     (x & 0x0070)
 336 +#define TIMER_FLAG_MASK_SYNC(x)                (x & 0x0080)
 337 +#define TIMER_FLAG_CALLBACK_IN_HB      0x0200
 338 +#define TIMER_FLAG_MASK_HANDLE(x)      (x & 0x0300)
 339 +#define TIMER_FLAG_MASK_SRC(x)         (x & 0x1000)
 340 +
 341 +struct timer_dev_timer {
 342 +       unsigned int f_irq_on;
 343 +       unsigned int irq;
 344 +       unsigned int flag;
 345 +       unsigned long arg1;
 346 +       unsigned long arg2;
 347 +};
 348 +
 349 +struct timer_dev {
 350 +       struct mutex gptu_mutex;
 351 +       unsigned int number_of_timers;
 352 +       unsigned int occupation;
 353 +       unsigned int f_gptu_on;
 354 +       struct timer_dev_timer timer[MAX_NUM_OF_32BIT_TIMER_BLOCKS * 2];
 355 +};
 356 +
 357 +unsigned long ltq_danube_fpi_bus_clock(int fpi);
 358 +unsigned long ltq_vr9_fpi_bus_clock(int fpi);
 359 +
 360 +unsigned int ltq_get_fpi_bus_clock(int fpi) {
 361 +       if (ltq_is_ase())
 362 +               return CLOCK_133M;
 363 +       else if (ltq_is_vr9())
 364 +               return ltq_vr9_fpi_bus_clock(fpi);
 365 +
 366 +       return ltq_danube_fpi_bus_clock(fpi);
 367 +}
 368 +
 369 +
 370 +static long gptu_ioctl(struct file *, unsigned int, unsigned long);
 371 +static int gptu_open(struct inode *, struct file *);
 372 +static int gptu_release(struct inode *, struct file *);
 373 +
 374 +static struct file_operations gptu_fops = {
 375 +       .owner = THIS_MODULE,
 376 +       .unlocked_ioctl = gptu_ioctl,
 377 +       .open = gptu_open,
 378 +       .release = gptu_release
 379 +};
 380 +
 381 +static struct miscdevice gptu_miscdev = {
 382 +       .minor = MISC_DYNAMIC_MINOR,
 383 +       .name = "gptu",
 384 +       .fops = &gptu_fops,
 385 +};
 386 +
 387 +static struct timer_dev timer_dev;
 388 +
 389 +static irqreturn_t timer_irq_handler(int irq, void *p)
 390 +{
 391 +       unsigned int timer;
 392 +       unsigned int flag;
 393 +       struct timer_dev_timer *dev_timer = (struct timer_dev_timer *)p;
 394 +
 395 +       timer = irq - TIMER_INTERRUPT;
 396 +       if (timer < timer_dev.number_of_timers
 397 +               && dev_timer == &timer_dev.timer[timer]) {
 398 +               /*  Clear interrupt.    */
 399 +               ltq_w32(1 << timer, LQ_GPTU_IRNCR);
 400 +
 401 +               /*  Call user hanler or signal. */
 402 +               flag = dev_timer->flag;
 403 +               if (!(timer & 0x01)
 404 +                       || TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT) {
 405 +                       /* 16-bit timer or timer A of 32-bit timer  */
 406 +                       switch (TIMER_FLAG_MASK_HANDLE(flag)) {
 407 +                       case TIMER_FLAG_CALLBACK_IN_IRQ:
 408 +                       case TIMER_FLAG_CALLBACK_IN_HB:
 409 +                               if (dev_timer->arg1)
 410 +                                       (*(timer_callback)dev_timer->arg1)(dev_timer->arg2);
 411 +                               break;
 412 +                       case TIMER_FLAG_SIGNAL:
 413 +                               send_sig((int)dev_timer->arg2, (struct task_struct *)dev_timer->arg1, 0);
 414 +                               break;
 415 +                       }
 416 +               }
 417 +       }
 418 +       return IRQ_HANDLED;
 419 +}
 420 +
 421 +static inline void lq_enable_gptu(void)
 422 +{
 423 +       struct clk *clk = clk_get_sys("ltq_gptu", NULL);
 424 +       clk_enable(clk);
 425 +
 426 +       //ltq_pmu_enable(PMU_GPT);
 427 +
 428 +       /*  Set divider as 1, disable write protection for SPEN, enable module. */
 429 +       *LQ_GPTU_CLC =
 430 +               GPTU_CLC_SMC_SET(0x00) |
 431 +               GPTU_CLC_RMC_SET(0x01) |
 432 +               GPTU_CLC_FSOE_SET(0) |
 433 +               GPTU_CLC_SBWE_SET(1) |
 434 +               GPTU_CLC_EDIS_SET(0) |
 435 +               GPTU_CLC_SPEN_SET(0) |
 436 +               GPTU_CLC_DISR_SET(0);
 437 +}
 438 +
 439 +static inline void lq_disable_gptu(void)
 440 +{
 441 +       struct clk *clk = clk_get_sys("ltq_gptu", NULL);
 442 +       ltq_w32(0x00, LQ_GPTU_IRNEN);
 443 +       ltq_w32(0xfff, LQ_GPTU_IRNCR);
 444 +
 445 +       /*  Set divider as 0, enable write protection for SPEN, disable module. */
 446 +       *LQ_GPTU_CLC =
 447 +               GPTU_CLC_SMC_SET(0x00) |
 448 +               GPTU_CLC_RMC_SET(0x00) |
 449 +               GPTU_CLC_FSOE_SET(0) |
 450 +               GPTU_CLC_SBWE_SET(0) |
 451 +               GPTU_CLC_EDIS_SET(0) |
 452 +               GPTU_CLC_SPEN_SET(0) |
 453 +               GPTU_CLC_DISR_SET(1);
 454 +
 455 +       clk_enable(clk);
 456 +}
 457 +
 458 +int lq_request_timer(unsigned int timer, unsigned int flag,
 459 +       unsigned long value, unsigned long arg1, unsigned long arg2)
 460 +{
 461 +       int ret = 0;
 462 +       unsigned int con_reg, irnen_reg;
 463 +       int n, X;
 464 +
 465 +       if (timer >= FIRST_TIMER + timer_dev.number_of_timers)
 466 +               return -EINVAL;
 467 +
 468 +       printk(KERN_INFO "request_timer(%d, 0x%08X, %lu)...",
 469 +               timer, flag, value);
 470 +
 471 +       if (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT)
 472 +               value &= 0xFFFF;
 473 +       else
 474 +               timer &= ~0x01;
 475 +
 476 +       mutex_lock(&timer_dev.gptu_mutex);
 477 +
 478 +       /*
 479 +        *  Allocate timer.
 480 +        */
 481 +       if (timer < FIRST_TIMER) {
 482 +               unsigned int mask;
 483 +               unsigned int shift;
 484 +               /* This takes care of TIMER1B which is the only choice for Voice TAPI system */
 485 +               unsigned int offset = TIMER2A;
 486 +
 487 +               /*
 488 +                *  Pick up a free timer.
 489 +                */
 490 +               if (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT) {
 491 +                       mask = 1 << offset;
 492 +                       shift = 1;
 493 +               } else {
 494 +                       mask = 3 << offset;
 495 +                       shift = 2;
 496 +               }
 497 +               for (timer = offset;
 498 +                    timer < offset + timer_dev.number_of_timers;
 499 +                    timer += shift, mask <<= shift)
 500 +                       if (!(timer_dev.occupation & mask)) {
 501 +                               timer_dev.occupation |= mask;
 502 +                               break;
 503 +                       }
 504 +               if (timer >= offset + timer_dev.number_of_timers) {
 505 +                       printk("failed![%d]\n", __LINE__);
 506 +                       mutex_unlock(&timer_dev.gptu_mutex);
 507 +                       return -EINVAL;
 508 +               } else
 509 +                       ret = timer;
 510 +       } else {
 511 +               register unsigned int mask;
 512 +
 513 +               /*
 514 +                *  Check if the requested timer is free.
 515 +                */
 516 +               mask = (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT ? 1 : 3) << timer;
 517 +               if ((timer_dev.occupation & mask)) {
 518 +                       printk("failed![%d] mask %#x, timer_dev.occupation %#x\n",
 519 +                               __LINE__, mask, timer_dev.occupation);
 520 +                       mutex_unlock(&timer_dev.gptu_mutex);
 521 +                       return -EBUSY;
 522 +               } else {
 523 +                       timer_dev.occupation |= mask;
 524 +                       ret = 0;
 525 +               }
 526 +       }
 527 +
 528 +       /*
 529 +        *  Prepare control register value.
 530 +        */
 531 +       switch (TIMER_FLAG_MASK_EDGE(flag)) {
 532 +       default:
 533 +       case TIMER_FLAG_NONE_EDGE:
 534 +               con_reg = GPTU_CON_EDGE_SET(0x00);
 535 +               break;
 536 +       case TIMER_FLAG_RISE_EDGE:
 537 +               con_reg = GPTU_CON_EDGE_SET(0x01);
 538 +               break;
 539 +       case TIMER_FLAG_FALL_EDGE:
 540 +               con_reg = GPTU_CON_EDGE_SET(0x02);
 541 +               break;
 542 +       case TIMER_FLAG_ANY_EDGE:
 543 +               con_reg = GPTU_CON_EDGE_SET(0x03);
 544 +               break;
 545 +       }
 546 +       if (TIMER_FLAG_MASK_TYPE(flag) == TIMER_FLAG_TIMER)
 547 +               con_reg |=
 548 +                       TIMER_FLAG_MASK_SRC(flag) ==
 549 +                       TIMER_FLAG_EXT_SRC ? GPTU_CON_SRC_EXT_SET(1) :
 550 +                       GPTU_CON_SRC_EXT_SET(0);
 551 +       else
 552 +               con_reg |=
 553 +                       TIMER_FLAG_MASK_SRC(flag) ==
 554 +                       TIMER_FLAG_EXT_SRC ? GPTU_CON_SRC_EG_SET(1) :
 555 +                       GPTU_CON_SRC_EG_SET(0);
 556 +       con_reg |=
 557 +               TIMER_FLAG_MASK_SYNC(flag) ==
 558 +               TIMER_FLAG_UNSYNC ? GPTU_CON_SYNC_SET(0) :
 559 +               GPTU_CON_SYNC_SET(1);
 560 +       con_reg |=
 561 +               TIMER_FLAG_MASK_INVERT(flag) ==
 562 +               TIMER_FLAG_REAL ? GPTU_CON_INV_SET(0) : GPTU_CON_INV_SET(1);
 563 +       con_reg |=
 564 +               TIMER_FLAG_MASK_SIZE(flag) ==
 565 +               TIMER_FLAG_16BIT ? GPTU_CON_EXT_SET(0) :
 566 +               GPTU_CON_EXT_SET(1);
 567 +       con_reg |=
 568 +               TIMER_FLAG_MASK_STOP(flag) ==
 569 +               TIMER_FLAG_ONCE ? GPTU_CON_STP_SET(1) : GPTU_CON_STP_SET(0);
 570 +       con_reg |=
 571 +               TIMER_FLAG_MASK_TYPE(flag) ==
 572 +               TIMER_FLAG_TIMER ? GPTU_CON_CNT_SET(0) :
 573 +               GPTU_CON_CNT_SET(1);
 574 +       con_reg |=
 575 +               TIMER_FLAG_MASK_DIR(flag) ==
 576 +               TIMER_FLAG_UP ? GPTU_CON_DIR_SET(1) : GPTU_CON_DIR_SET(0);
 577 +
 578 +       /*
 579 +        *  Fill up running data.
 580 +        */
 581 +       timer_dev.timer[timer - FIRST_TIMER].flag = flag;
 582 +       timer_dev.timer[timer - FIRST_TIMER].arg1 = arg1;
 583 +       timer_dev.timer[timer - FIRST_TIMER].arg2 = arg2;
 584 +       if (TIMER_FLAG_MASK_SIZE(flag) != TIMER_FLAG_16BIT)
 585 +               timer_dev.timer[timer - FIRST_TIMER + 1].flag = flag;
 586 +
 587 +       /*
 588 +        *  Enable GPTU module.
 589 +        */
 590 +       if (!timer_dev.f_gptu_on) {
 591 +               lq_enable_gptu();
 592 +               timer_dev.f_gptu_on = 1;
 593 +       }
 594 +
 595 +       /*
 596 +        *  Enable IRQ.
 597 +        */
 598 +       if (TIMER_FLAG_MASK_HANDLE(flag) != TIMER_FLAG_NO_HANDLE) {
 599 +               if (TIMER_FLAG_MASK_HANDLE(flag) == TIMER_FLAG_SIGNAL)
 600 +                       timer_dev.timer[timer - FIRST_TIMER].arg1 =
 601 +                               (unsigned long) find_task_by_vpid((int) arg1);
 602 +
 603 +               irnen_reg = 1 << (timer - FIRST_TIMER);
 604 +
 605 +               if (TIMER_FLAG_MASK_HANDLE(flag) == TIMER_FLAG_SIGNAL
 606 +                   || (TIMER_FLAG_MASK_HANDLE(flag) ==
 607 +                       TIMER_FLAG_CALLBACK_IN_IRQ
 608 +                       && timer_dev.timer[timer - FIRST_TIMER].arg1)) {
 609 +                       enable_irq(timer_dev.timer[timer - FIRST_TIMER].irq);
 610 +                       timer_dev.timer[timer - FIRST_TIMER].f_irq_on = 1;
 611 +               }
 612 +       } else
 613 +               irnen_reg = 0;
 614 +
 615 +       /*
 616 +        *  Write config register, reload value and enable interrupt.
 617 +        */
 618 +       n = timer >> 1;
 619 +       X = timer & 0x01;
 620 +       *LQ_GPTU_CON(n, X) = con_reg;
 621 +       *LQ_GPTU_RELOAD(n, X) = value;
 622 +       /* printk("reload value = %d\n", (u32)value); */
 623 +       *LQ_GPTU_IRNEN |= irnen_reg;
 624 +
 625 +       mutex_unlock(&timer_dev.gptu_mutex);
 626 +       printk("successful!\n");
 627 +       return ret;
 628 +}
 629 +EXPORT_SYMBOL(lq_request_timer);
 630 +
 631 +int lq_free_timer(unsigned int timer)
 632 +{
 633 +       unsigned int flag;
 634 +       unsigned int mask;
 635 +       int n, X;
 636 +
 637 +       if (!timer_dev.f_gptu_on)
 638 +               return -EINVAL;
 639 +
 640 +       if (timer < FIRST_TIMER || timer >= FIRST_TIMER + timer_dev.number_of_timers)
 641 +               return -EINVAL;
 642 +
 643 +       mutex_lock(&timer_dev.gptu_mutex);
 644 +
 645 +       flag = timer_dev.timer[timer - FIRST_TIMER].flag;
 646 +       if (TIMER_FLAG_MASK_SIZE(flag) != TIMER_FLAG_16BIT)
 647 +               timer &= ~0x01;
 648 +
 649 +       mask = (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT ? 1 : 3) << timer;
 650 +       if (((timer_dev.occupation & mask) ^ mask)) {
 651 +               mutex_unlock(&timer_dev.gptu_mutex);
 652 +               return -EINVAL;
 653 +       }
 654 +
 655 +       n = timer >> 1;
 656 +       X = timer & 0x01;
 657 +
 658 +       if (GPTU_CON_EN(n, X))
 659 +               *LQ_GPTU_RUN(n, X) = GPTU_RUN_CEN_SET(1);
 660 +
 661 +       *LQ_GPTU_IRNEN &= ~GPTU_IRNEN_TC_SET(n, X, 1);
 662 +       *LQ_GPTU_IRNCR |= GPTU_IRNCR_TC_SET(n, X, 1);
 663 +
 664 +       if (timer_dev.timer[timer - FIRST_TIMER].f_irq_on) {
 665 +               disable_irq(timer_dev.timer[timer - FIRST_TIMER].irq);
 666 +               timer_dev.timer[timer - FIRST_TIMER].f_irq_on = 0;
 667 +       }
 668 +
 669 +       timer_dev.occupation &= ~mask;
 670 +       if (!timer_dev.occupation && timer_dev.f_gptu_on) {
 671 +               lq_disable_gptu();
 672 +               timer_dev.f_gptu_on = 0;
 673 +       }
 674 +
 675 +       mutex_unlock(&timer_dev.gptu_mutex);
 676 +
 677 +       return 0;
 678 +}
 679 +EXPORT_SYMBOL(lq_free_timer);
 680 +
 681 +int lq_start_timer(unsigned int timer, int is_resume)
 682 +{
 683 +       unsigned int flag;
 684 +       unsigned int mask;
 685 +       int n, X;
 686 +
 687 +       if (!timer_dev.f_gptu_on)
 688 +               return -EINVAL;
 689 +
 690 +       if (timer < FIRST_TIMER || timer >= FIRST_TIMER + timer_dev.number_of_timers)
 691 +               return -EINVAL;
 692 +
 693 +       mutex_lock(&timer_dev.gptu_mutex);
 694 +
 695 +       flag = timer_dev.timer[timer - FIRST_TIMER].flag;
 696 +       if (TIMER_FLAG_MASK_SIZE(flag) != TIMER_FLAG_16BIT)
 697 +               timer &= ~0x01;
 698 +
 699 +       mask = (TIMER_FLAG_MASK_SIZE(flag) ==
 700 +       TIMER_FLAG_16BIT ? 1 : 3) << timer;
 701 +       if (((timer_dev.occupation & mask) ^ mask)) {
 702 +               mutex_unlock(&timer_dev.gptu_mutex);
 703 +               return -EINVAL;
 704 +       }
 705 +
 706 +       n = timer >> 1;
 707 +       X = timer & 0x01;
 708 +
 709 +       *LQ_GPTU_RUN(n, X) = GPTU_RUN_RL_SET(!is_resume) | GPTU_RUN_SEN_SET(1);
 710 +
 711 +       mutex_unlock(&timer_dev.gptu_mutex);
 712 +
 713 +       return 0;
 714 +}
 715 +EXPORT_SYMBOL(lq_start_timer);
 716 +
 717 +int lq_stop_timer(unsigned int timer)
 718 +{
 719 +       unsigned int flag;
 720 +       unsigned int mask;
 721 +       int n, X;
 722 +
 723 +       if (!timer_dev.f_gptu_on)
 724 +               return -EINVAL;
 725 +
 726 +       if (timer < FIRST_TIMER
 727 +           || timer >= FIRST_TIMER + timer_dev.number_of_timers)
 728 +               return -EINVAL;
 729 +
 730 +       mutex_lock(&timer_dev.gptu_mutex);
 731 +
 732 +       flag = timer_dev.timer[timer - FIRST_TIMER].flag;
 733 +       if (TIMER_FLAG_MASK_SIZE(flag) != TIMER_FLAG_16BIT)
 734 +               timer &= ~0x01;
 735 +
 736 +       mask = (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT ? 1 : 3) << timer;
 737 +       if (((timer_dev.occupation & mask) ^ mask)) {
 738 +               mutex_unlock(&timer_dev.gptu_mutex);
 739 +               return -EINVAL;
 740 +       }
 741 +
 742 +       n = timer >> 1;
 743 +       X = timer & 0x01;
 744 +
 745 +       *LQ_GPTU_RUN(n, X) = GPTU_RUN_CEN_SET(1);
 746 +
 747 +       mutex_unlock(&timer_dev.gptu_mutex);
 748 +
 749 +       return 0;
 750 +}
 751 +EXPORT_SYMBOL(lq_stop_timer);
 752 +
 753 +int lq_reset_counter_flags(u32 timer, u32 flags)
 754 +{
 755 +       unsigned int oflag;
 756 +       unsigned int mask, con_reg;
 757 +       int n, X;
 758 +
 759 +       if (!timer_dev.f_gptu_on)
 760 +               return -EINVAL;
 761 +
 762 +       if (timer < FIRST_TIMER || timer >= FIRST_TIMER + timer_dev.number_of_timers)
 763 +               return -EINVAL;
 764 +
 765 +       mutex_lock(&timer_dev.gptu_mutex);
 766 +
 767 +       oflag = timer_dev.timer[timer - FIRST_TIMER].flag;
 768 +       if (TIMER_FLAG_MASK_SIZE(oflag) != TIMER_FLAG_16BIT)
 769 +               timer &= ~0x01;
 770 +
 771 +       mask = (TIMER_FLAG_MASK_SIZE(oflag) == TIMER_FLAG_16BIT ? 1 : 3) << timer;
 772 +       if (((timer_dev.occupation & mask) ^ mask)) {
 773 +               mutex_unlock(&timer_dev.gptu_mutex);
 774 +               return -EINVAL;
 775 +       }
 776 +
 777 +       switch (TIMER_FLAG_MASK_EDGE(flags)) {
 778 +       default:
 779 +       case TIMER_FLAG_NONE_EDGE:
 780 +               con_reg = GPTU_CON_EDGE_SET(0x00);
 781 +               break;
 782 +       case TIMER_FLAG_RISE_EDGE:
 783 +               con_reg = GPTU_CON_EDGE_SET(0x01);
 784 +               break;
 785 +       case TIMER_FLAG_FALL_EDGE:
 786 +               con_reg = GPTU_CON_EDGE_SET(0x02);
 787 +               break;
 788 +       case TIMER_FLAG_ANY_EDGE:
 789 +               con_reg = GPTU_CON_EDGE_SET(0x03);
 790 +               break;
 791 +       }
 792 +       if (TIMER_FLAG_MASK_TYPE(flags) == TIMER_FLAG_TIMER)
 793 +               con_reg |= TIMER_FLAG_MASK_SRC(flags) == TIMER_FLAG_EXT_SRC ? GPTU_CON_SRC_EXT_SET(1) : GPTU_CON_SRC_EXT_SET(0);
 794 +       else
 795 +               con_reg |= TIMER_FLAG_MASK_SRC(flags) == TIMER_FLAG_EXT_SRC ? GPTU_CON_SRC_EG_SET(1) : GPTU_CON_SRC_EG_SET(0);
 796 +       con_reg |= TIMER_FLAG_MASK_SYNC(flags) == TIMER_FLAG_UNSYNC ? GPTU_CON_SYNC_SET(0) : GPTU_CON_SYNC_SET(1);
 797 +       con_reg |= TIMER_FLAG_MASK_INVERT(flags) == TIMER_FLAG_REAL ? GPTU_CON_INV_SET(0) : GPTU_CON_INV_SET(1);
 798 +       con_reg |= TIMER_FLAG_MASK_SIZE(flags) == TIMER_FLAG_16BIT ? GPTU_CON_EXT_SET(0) : GPTU_CON_EXT_SET(1);
 799 +       con_reg |= TIMER_FLAG_MASK_STOP(flags) == TIMER_FLAG_ONCE ? GPTU_CON_STP_SET(1) : GPTU_CON_STP_SET(0);
 800 +       con_reg |= TIMER_FLAG_MASK_TYPE(flags) == TIMER_FLAG_TIMER ? GPTU_CON_CNT_SET(0) : GPTU_CON_CNT_SET(1);
 801 +       con_reg |= TIMER_FLAG_MASK_DIR(flags) == TIMER_FLAG_UP ? GPTU_CON_DIR_SET(1) : GPTU_CON_DIR_SET(0);
 802 +
 803 +       timer_dev.timer[timer - FIRST_TIMER].flag = flags;
 804 +       if (TIMER_FLAG_MASK_SIZE(flags) != TIMER_FLAG_16BIT)
 805 +               timer_dev.timer[timer - FIRST_TIMER + 1].flag = flags;
 806 +
 807 +       n = timer >> 1;
 808 +       X = timer & 0x01;
 809 +
 810 +       *LQ_GPTU_CON(n, X) = con_reg;
 811 +       smp_wmb();
 812 +       printk(KERN_INFO "[%s]: counter%d oflags %#x, nflags %#x, GPTU_CON %#x\n", __func__, timer, oflag, flags, *LQ_GPTU_CON(n, X));
 813 +       mutex_unlock(&timer_dev.gptu_mutex);
 814 +       return 0;
 815 +}
 816 +EXPORT_SYMBOL(lq_reset_counter_flags);
 817 +
 818 +int lq_get_count_value(unsigned int timer, unsigned long *value)
 819 +{
 820 +       unsigned int flag;
 821 +       unsigned int mask;
 822 +       int n, X;
 823 +
 824 +       if (!timer_dev.f_gptu_on)
 825 +               return -EINVAL;
 826 +
 827 +       if (timer < FIRST_TIMER
 828 +           || timer >= FIRST_TIMER + timer_dev.number_of_timers)
 829 +               return -EINVAL;
 830 +
 831 +       mutex_lock(&timer_dev.gptu_mutex);
 832 +
 833 +       flag = timer_dev.timer[timer - FIRST_TIMER].flag;
 834 +       if (TIMER_FLAG_MASK_SIZE(flag) != TIMER_FLAG_16BIT)
 835 +               timer &= ~0x01;
 836 +
 837 +       mask = (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT ? 1 : 3) << timer;
 838 +       if (((timer_dev.occupation & mask) ^ mask)) {
 839 +               mutex_unlock(&timer_dev.gptu_mutex);
 840 +               return -EINVAL;
 841 +       }
 842 +
 843 +       n = timer >> 1;
 844 +       X = timer & 0x01;
 845 +
 846 +       *value = *LQ_GPTU_COUNT(n, X);
 847 +
 848 +       mutex_unlock(&timer_dev.gptu_mutex);
 849 +
 850 +       return 0;
 851 +}
 852 +EXPORT_SYMBOL(lq_get_count_value);
 853 +
 854 +u32 lq_cal_divider(unsigned long freq)
 855 +{
 856 +       u64 module_freq, fpi = ltq_get_fpi_bus_clock(2);
 857 +       u32 clock_divider = 1;
 858 +       module_freq = fpi * 1000;
 859 +       do_div(module_freq, clock_divider * freq);
 860 +       return module_freq;
 861 +}
 862 +EXPORT_SYMBOL(lq_cal_divider);
 863 +
 864 +int lq_set_timer(unsigned int timer, unsigned int freq, int is_cyclic,
 865 +       int is_ext_src, unsigned int handle_flag, unsigned long arg1,
 866 +       unsigned long arg2)
 867 +{
 868 +       unsigned long divider;
 869 +       unsigned int flag;
 870 +
 871 +       divider = lq_cal_divider(freq);
 872 +       if (divider == 0)
 873 +               return -EINVAL;
 874 +       flag = ((divider & ~0xFFFF) ? TIMER_FLAG_32BIT : TIMER_FLAG_16BIT)
 875 +               | (is_cyclic ? TIMER_FLAG_CYCLIC : TIMER_FLAG_ONCE)
 876 +               | (is_ext_src ? TIMER_FLAG_EXT_SRC : TIMER_FLAG_INT_SRC)
 877 +               | TIMER_FLAG_TIMER | TIMER_FLAG_DOWN
 878 +               | TIMER_FLAG_MASK_HANDLE(handle_flag);
 879 +
 880 +       printk(KERN_INFO "lq_set_timer(%d, %d), divider = %lu\n",
 881 +               timer, freq, divider);
 882 +       return lq_request_timer(timer, flag, divider, arg1, arg2);
 883 +}
 884 +EXPORT_SYMBOL(lq_set_timer);
 885 +
 886 +int lq_set_counter(unsigned int timer, unsigned int flag, u32 reload,
 887 +       unsigned long arg1, unsigned long arg2)
 888 +{
 889 +       printk(KERN_INFO "lq_set_counter(%d, %#x, %d)\n", timer, flag, reload);
 890 +       return lq_request_timer(timer, flag, reload, arg1, arg2);
 891 +}
 892 +EXPORT_SYMBOL(lq_set_counter);
 893 +
 894 +static long gptu_ioctl(struct file *file, unsigned int cmd,
 895 +       unsigned long arg)
 896 +{
 897 +       int ret;
 898 +       struct gptu_ioctl_param param;
 899 +
 900 +       if (!access_ok(VERIFY_READ, arg, sizeof(struct gptu_ioctl_param)))
 901 +               return -EFAULT;
 902 +       copy_from_user(&param, (void *) arg, sizeof(param));
 903 +
 904 +       if ((((cmd == GPTU_REQUEST_TIMER || cmd == GPTU_SET_TIMER
 905 +              || GPTU_SET_COUNTER) && param.timer < 2)
 906 +            || cmd == GPTU_GET_COUNT_VALUE || cmd == GPTU_CALCULATE_DIVIDER)
 907 +           && !access_ok(VERIFY_WRITE, arg,
 908 +                          sizeof(struct gptu_ioctl_param)))
 909 +               return -EFAULT;
 910 +
 911 +       switch (cmd) {
 912 +       case GPTU_REQUEST_TIMER:
 913 +               ret = lq_request_timer(param.timer, param.flag, param.value,
 914 +                                    (unsigned long) param.pid,
 915 +                                    (unsigned long) param.sig);
 916 +               if (ret > 0) {
 917 +                       copy_to_user(&((struct gptu_ioctl_param *) arg)->
 918 +                                     timer, &ret, sizeof(&ret));
 919 +                       ret = 0;
 920 +               }
 921 +               break;
 922 +       case GPTU_FREE_TIMER:
 923 +               ret = lq_free_timer(param.timer);
 924 +               break;
 925 +       case GPTU_START_TIMER:
 926 +               ret = lq_start_timer(param.timer, param.flag);
 927 +               break;
 928 +       case GPTU_STOP_TIMER:
 929 +               ret = lq_stop_timer(param.timer);
 930 +               break;
 931 +       case GPTU_GET_COUNT_VALUE:
 932 +               ret = lq_get_count_value(param.timer, &param.value);
 933 +               if (!ret)
 934 +                       copy_to_user(&((struct gptu_ioctl_param *) arg)->
 935 +                                     value, &param.value,
 936 +                                     sizeof(param.value));
 937 +               break;
 938 +       case GPTU_CALCULATE_DIVIDER:
 939 +               param.value = lq_cal_divider(param.value);
 940 +               if (param.value == 0)
 941 +                       ret = -EINVAL;
 942 +               else {
 943 +                       copy_to_user(&((struct gptu_ioctl_param *) arg)->
 944 +                                     value, &param.value,
 945 +                                     sizeof(param.value));
 946 +                       ret = 0;
 947 +               }
 948 +               break;
 949 +       case GPTU_SET_TIMER:
 950 +               ret = lq_set_timer(param.timer, param.value,
 951 +                                TIMER_FLAG_MASK_STOP(param.flag) !=
 952 +                                TIMER_FLAG_ONCE ? 1 : 0,
 953 +                                TIMER_FLAG_MASK_SRC(param.flag) ==
 954 +                                TIMER_FLAG_EXT_SRC ? 1 : 0,
 955 +                                TIMER_FLAG_MASK_HANDLE(param.flag) ==
 956 +                                TIMER_FLAG_SIGNAL ? TIMER_FLAG_SIGNAL :
 957 +                                TIMER_FLAG_NO_HANDLE,
 958 +                                (unsigned long) param.pid,
 959 +                                (unsigned long) param.sig);
 960 +               if (ret > 0) {
 961 +                       copy_to_user(&((struct gptu_ioctl_param *) arg)->
 962 +                                     timer, &ret, sizeof(&ret));
 963 +                       ret = 0;
 964 +               }
 965 +               break;
 966 +       case GPTU_SET_COUNTER:
 967 +               lq_set_counter(param.timer, param.flag, param.value, 0, 0);
 968 +               if (ret > 0) {
 969 +                       copy_to_user(&((struct gptu_ioctl_param *) arg)->
 970 +                                     timer, &ret, sizeof(&ret));
 971 +                       ret = 0;
 972 +               }
 973 +               break;
 974 +       default:
 975 +               ret = -ENOTTY;
 976 +       }
 977 +
 978 +       return ret;
 979 +}
 980 +
 981 +static int gptu_open(struct inode *inode, struct file *file)
 982 +{
 983 +       return 0;
 984 +}
 985 +
 986 +static int gptu_release(struct inode *inode, struct file *file)
 987 +{
 988 +       return 0;
 989 +}
 990 +
 991 +int __init lq_gptu_init(void)
 992 +{
 993 +       int ret;
 994 +       unsigned int i;
 995 +
 996 +       ltq_w32(0, LQ_GPTU_IRNEN);
 997 +       ltq_w32(0xfff, LQ_GPTU_IRNCR);
 998 +
 999 +       memset(&timer_dev, 0, sizeof(timer_dev));
1000 +       mutex_init(&timer_dev.gptu_mutex);
1001 +
1002 +       lq_enable_gptu();
1003 +       timer_dev.number_of_timers = GPTU_ID_CFG * 2;
1004 +       lq_disable_gptu();
1005 +       if (timer_dev.number_of_timers > MAX_NUM_OF_32BIT_TIMER_BLOCKS * 2)
1006 +               timer_dev.number_of_timers = MAX_NUM_OF_32BIT_TIMER_BLOCKS * 2;
1007 +       printk(KERN_INFO "gptu: totally %d 16-bit timers/counters\n", timer_dev.number_of_timers);
1008 +
1009 +       ret = misc_register(&gptu_miscdev);
1010 +       if (ret) {
1011 +               printk(KERN_ERR "gptu: can't misc_register, get error %d\n", -ret);
1012 +               return ret;
1013 +       } else {
1014 +               printk(KERN_INFO "gptu: misc_register on minor %d\n", gptu_miscdev.minor);
1015 +       }
1016 +
1017 +       for (i = 0; i < timer_dev.number_of_timers; i++) {
1018 +               ret = request_irq(TIMER_INTERRUPT + i, timer_irq_handler, IRQF_TIMER, gptu_miscdev.name, &timer_dev.timer[i]);
1019 +               if (ret) {
1020 +                       for (; i >= 0; i--)
1021 +                               free_irq(TIMER_INTERRUPT + i, &timer_dev.timer[i]);
1022 +                       misc_deregister(&gptu_miscdev);
1023 +                       printk(KERN_ERR "gptu: failed in requesting irq (%d), get error %d\n", i, -ret);
1024 +                       return ret;
1025 +               } else {
1026 +                       timer_dev.timer[i].irq = TIMER_INTERRUPT + i;
1027 +                       disable_irq(timer_dev.timer[i].irq);
1028 +                       printk(KERN_INFO "gptu: succeeded to request irq %d\n", timer_dev.timer[i].irq);
1029 +               }
1030 +       }
1031 +
1032 +       return 0;
1033 +}
1034 +
1035 +void __exit lq_gptu_exit(void)
1036 +{
1037 +       unsigned int i;
1038 +
1039 +       for (i = 0; i < timer_dev.number_of_timers; i++) {
1040 +               if (timer_dev.timer[i].f_irq_on)
1041 +                       disable_irq(timer_dev.timer[i].irq);
1042 +               free_irq(timer_dev.timer[i].irq, &timer_dev.timer[i]);
1043 +       }
1044 +       lq_disable_gptu();
1045 +       misc_deregister(&gptu_miscdev);
1046 +}
1047 +
1048 +module_init(lq_gptu_init);
1049 +module_exit(lq_gptu_exit);
1050 --
1051 1.7.9.1
1052