1 From 958d1d653fe13627d13907e61ae201fe62ddd99f Mon Sep 17 00:00:00 2001
2 From: John Crispin <blogic@openwrt.org>
3 Date: Tue, 21 Feb 2012 09:48:11 +0100
4 Subject: [PATCH 35/73] MIPS: lantiq: add vr9 support
6 VR9 is a VDSL SoC made by Lantiq. It is very similar to the AR9.
7 This patch adds the clkdev init code and SoC detection for the VR9.
9 Signed-off-by: John Crispin <blogic@openwrt.org>
10 Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
12 .../mips/include/asm/mach-lantiq/xway/lantiq_soc.h | 3 +
13 arch/mips/lantiq/xway/clk.c | 83 ++++++++++++++++++++
14 arch/mips/lantiq/xway/prom.c | 6 ++
15 arch/mips/lantiq/xway/sysctrl.c | 12 +++-
16 4 files changed, 103 insertions(+), 1 deletions(-)
18 --- a/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h
19 +++ b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h
21 #define SOC_ID_ARX188 0x16C
22 #define SOC_ID_ARX168 0x16D
23 #define SOC_ID_ARX182 0x16F
24 +#define SOC_ID_VRX288 0x1C0 /* VRX288 v1.1 */
25 +#define SOC_ID_VRX268 0x1C2 /* VRX268 v1.1 */
26 +#define SOC_ID_GRX288 0x1C9 /* GRX288 v1.1 */
29 #define SOC_TYPE_DANUBE 0x01
30 --- a/arch/mips/lantiq/xway/clk.c
31 +++ b/arch/mips/lantiq/xway/clk.c
32 @@ -225,3 +225,86 @@ unsigned long ltq_danube_fpi_hz(void)
33 return ddr_clock >> 1;
37 +unsigned long ltq_vr9_cpu_hz(void)
39 + unsigned int cpu_sel;
42 + cpu_sel = (ltq_cgu_r32(LTQ_CGU_SYS_VR9) >> 4) & 0xf;
59 + clk = CLOCK_196_608M;
77 +unsigned long ltq_vr9_fpi_hz(void)
79 + unsigned int ocp_sel, cpu_clk;
82 + cpu_clk = ltq_vr9_cpu_hz();
83 + ocp_sel = ltq_cgu_r32(LTQ_CGU_SYS_VR9) & 0x3;
96 + clk = (cpu_clk * 2) / 5;
110 +unsigned long ltq_vr9_io_region_clock(void)
112 + return ltq_vr9_fpi_hz();
115 +unsigned long ltq_vr9_fpi_bus_clock(int fpi)
117 + return ltq_vr9_fpi_hz();
119 --- a/arch/mips/lantiq/xway/prom.c
120 +++ b/arch/mips/lantiq/xway/prom.c
121 @@ -60,6 +60,12 @@ void __init ltq_soc_detect(struct ltq_so
125 + case SOC_ID_VRX268:
126 + case SOC_ID_VRX288:
128 + i->type = SOC_TYPE_VR9;
134 --- a/arch/mips/lantiq/xway/sysctrl.c
135 +++ b/arch/mips/lantiq/xway/sysctrl.c
136 @@ -147,7 +147,8 @@ void __init ltq_soc_init(void)
137 clkdev_add_pmu("ltq_dma", NULL, 0, PMU_DMA);
138 clkdev_add_pmu("ltq_stp", NULL, 0, PMU_STP);
139 clkdev_add_pmu("ltq_spi", NULL, 0, PMU_SPI);
140 - clkdev_add_pmu("ltq_etop", NULL, 0, PMU_PPE);
142 + clkdev_add_pmu("ltq_etop", NULL, 0, PMU_PPE);
144 if (ltq_cgu_r32(LTQ_CGU_SYS) & (1 << 5))
145 clkdev_add_static(CLOCK_266M, CLOCK_133M, CLOCK_133M);
146 @@ -155,6 +156,15 @@ void __init ltq_soc_init(void)
147 clkdev_add_static(CLOCK_133M, CLOCK_133M, CLOCK_133M);
148 clkdev_add_cgu("ltq_etop", "ephycgu", CGU_EPHY),
149 clkdev_add_pmu("ltq_etop", "ephy", 0, PMU_EPHY);
150 + } else if (ltq_is_vr9()) {
151 + clkdev_add_static(ltq_vr9_cpu_hz(), ltq_vr9_fpi_hz(),
152 + ltq_vr9_io_region_clock());
153 + clkdev_add_pmu("ltq_pcie", "phy", 1, PMU1_PCIE_PHY);
154 + clkdev_add_pmu("ltq_pcie", "bus", 0, PMU_PCIE_CLK);
155 + clkdev_add_pmu("ltq_pcie", "msi", 1, PMU1_PCIE_MSI);
156 + clkdev_add_pmu("ltq_pcie", "pdi", 1, PMU1_PCIE_PDI);
157 + clkdev_add_pmu("ltq_pcie", "ctl", 1, PMU1_PCIE_CTL);
158 + clkdev_add_pmu("ltq_pcie", "ahb", 0, PMU_AHBM | PMU_AHBS);
160 clkdev_add_static(ltq_danube_cpu_hz(), ltq_danube_fpi_hz(),
161 ltq_danube_io_region_clock());