target/linux/lantiq/patches-3.14/0023-NET-PHY-adds-driver-for-lantiq-PHY11G.patch

   1 From 0a63ab263725c427051a8bbaa0732b749627da27 Mon Sep 17 00:00:00 2001
   2 From: John Crispin <blogic@openwrt.org>
   3 Date: Thu, 7 Aug 2014 18:15:36 +0200
   4 Subject: [PATCH 23/36] NET: PHY: adds driver for lantiq PHY11G
   5
   6 Signed-off-by: John Crispin <blogic@openwrt.org>
   7 ---
   8  drivers/net/phy/Kconfig  |    5 +
   9  drivers/net/phy/Makefile |    1 +
  10  drivers/net/phy/lantiq.c |  231 ++++++++++++++++++++++++++++++++++++++++++++++
  11  3 files changed, 237 insertions(+)
  12  create mode 100644 drivers/net/phy/lantiq.c
  13
  14 diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig
  15 index 9b5d46c..f3724b1 100644
  16 --- a/drivers/net/phy/Kconfig
  17 +++ b/drivers/net/phy/Kconfig
  18 @@ -106,6 +106,11 @@ config MICREL_PHY
  19         ---help---
  20           Supports the KSZ9021, VSC8201, KS8001 PHYs.
  21
  22 +config LANTIQ_PHY
  23 +       tristate "Driver for Lantiq PHYs"
  24 +       ---help---
  25 +         Supports the 11G and 22E PHYs.
  26 +
  27  config FIXED_PHY
  28         bool "Driver for MDIO Bus/PHY emulation with fixed speed/link PHYs"
  29         depends on PHYLIB=y
  30 diff --git a/drivers/net/phy/Makefile b/drivers/net/phy/Makefile
  31 index 9013dfa..b5e030f 100644
  32 --- a/drivers/net/phy/Makefile
  33 +++ b/drivers/net/phy/Makefile
  34 @@ -23,6 +23,7 @@ obj-$(CONFIG_NATIONAL_PHY)    += national.o
  35  obj-$(CONFIG_DP83640_PHY)      += dp83640.o
  36  obj-$(CONFIG_STE10XP)          += ste10Xp.o
  37  obj-$(CONFIG_MICREL_PHY)       += micrel.o
  38 +obj-$(CONFIG_LANTIQ_PHY)        += lantiq.o
  39  obj-$(CONFIG_MDIO_OCTEON)      += mdio-octeon.o
  40  obj-$(CONFIG_MICREL_KS8995MA)  += spi_ks8995.o
  41  obj-$(CONFIG_AT803X_PHY)       += at803x.o
  42 diff --git a/drivers/net/phy/lantiq.c b/drivers/net/phy/lantiq.c
  43 new file mode 100644
  44 index 0000000..f109bb9
  45 --- /dev/null
  46 +++ b/drivers/net/phy/lantiq.c
  47 @@ -0,0 +1,231 @@
  48 +/*
  49 + *   This program is free software; you can redistribute it and/or modify
  50 + *   it under the terms of the GNU General Public License as published by
  51 + *   the Free Software Foundation; either version 2 of the License, or
  52 + *   (at your option) any later version.
  53 + *
  54 + *   This program is distributed in the hope that it will be useful,
  55 + *   but WITHOUT ANY WARRANTY; without even the implied warranty of
  56 + *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  57 + *   GNU General Public License for more details.
  58 + *
  59 + *   You should have received a copy of the GNU General Public License
  60 + *   along with this program; if not, write to the Free Software
  61 + *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
  62 + *
  63 + *   Copyright (C) 2012 Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
  64 + */
  65 +
  66 +#include <linux/module.h>
  67 +#include <linux/phy.h>
  68 +
  69 +#define MII_MMDCTRL            0x0d
  70 +#define MII_MMDDATA            0x0e
  71 +
  72 +#define MII_VR9_11G_IMASK      0x19    /* interrupt mask */
  73 +#define MII_VR9_11G_ISTAT      0x1a    /* interrupt status */
  74 +
  75 +#define INT_VR9_11G_WOL                BIT(15) /* Wake-On-LAN */
  76 +#define INT_VR9_11G_ANE                BIT(11) /* Auto-Neg error */
  77 +#define INT_VR9_11G_ANC                BIT(10) /* Auto-Neg complete */
  78 +#define INT_VR9_11G_ADSC       BIT(5)  /* Link auto-downspeed detect */
  79 +#define INT_VR9_11G_DXMC       BIT(2)  /* Duplex mode change */
  80 +#define INT_VR9_11G_LSPC       BIT(1)  /* Link speed change */
  81 +#define INT_VR9_11G_LSTC       BIT(0)  /* Link state change */
  82 +#define INT_VR9_11G_MASK       (INT_VR9_11G_LSTC | INT_VR9_11G_ADSC)
  83 +
  84 +#define ADVERTISED_MPD         BIT(10) /* Multi-port device */
  85 +
  86 +#define MMD_DEVAD              0x1f
  87 +#define MMD_ACTYPE_SHIFT       14
  88 +#define MMD_ACTYPE_ADDRESS     (0 << MMD_ACTYPE_SHIFT)
  89 +#define MMD_ACTYPE_DATA                (1 << MMD_ACTYPE_SHIFT)
  90 +#define MMD_ACTYPE_DATA_PI     (2 << MMD_ACTYPE_SHIFT)
  91 +#define MMD_ACTYPE_DATA_PIWR   (3 << MMD_ACTYPE_SHIFT)
  92 +
  93 +static __maybe_unused int vr9_gphy_mmd_read(struct phy_device *phydev,
  94 +                                               u16 regnum)
  95 +{
  96 +       phy_write(phydev, MII_MMDCTRL, MMD_ACTYPE_ADDRESS | MMD_DEVAD);
  97 +       phy_write(phydev, MII_MMDDATA, regnum);
  98 +       phy_write(phydev, MII_MMDCTRL, MMD_ACTYPE_DATA | MMD_DEVAD);
  99 +
 100 +       return phy_read(phydev, MII_MMDDATA);
 101 +}
 102 +
 103 +static __maybe_unused int vr9_gphy_mmd_write(struct phy_device *phydev,
 104 +                                               u16 regnum, u16 val)
 105 +{
 106 +       phy_write(phydev, MII_MMDCTRL, MMD_ACTYPE_ADDRESS | MMD_DEVAD);
 107 +       phy_write(phydev, MII_MMDDATA, regnum);
 108 +       phy_write(phydev, MII_MMDCTRL, MMD_ACTYPE_DATA | MMD_DEVAD);
 109 +       phy_write(phydev, MII_MMDDATA, val);
 110 +
 111 +       return 0;
 112 +}
 113 +
 114 +static int vr9_gphy_config_init(struct phy_device *phydev)
 115 +{
 116 +       int err;
 117 +
 118 +       dev_dbg(&phydev->dev, "%s\n", __func__);
 119 +
 120 +       /* Mask all interrupts */
 121 +       err = phy_write(phydev, MII_VR9_11G_IMASK, 0);
 122 +       if (err)
 123 +               return err;
 124 +
 125 +       /* Clear all pending interrupts */
 126 +       phy_read(phydev, MII_VR9_11G_ISTAT);
 127 +
 128 +       vr9_gphy_mmd_write(phydev, 0x1e0, 0xc5);
 129 +       vr9_gphy_mmd_write(phydev, 0x1e1, 0x67);
 130 +       vr9_gphy_mmd_write(phydev, 0x1e2, 0x42);
 131 +       vr9_gphy_mmd_write(phydev, 0x1e3, 0x10);
 132 +       vr9_gphy_mmd_write(phydev, 0x1e4, 0x70);
 133 +       vr9_gphy_mmd_write(phydev, 0x1e5, 0x03);
 134 +       vr9_gphy_mmd_write(phydev, 0x1e6, 0x20);
 135 +       vr9_gphy_mmd_write(phydev, 0x1e7, 0x00);
 136 +       vr9_gphy_mmd_write(phydev, 0x1e8, 0x40);
 137 +       vr9_gphy_mmd_write(phydev, 0x1e9, 0x20);
 138 +
 139 +       return 0;
 140 +}
 141 +
 142 +static int vr9_gphy_config_aneg(struct phy_device *phydev)
 143 +{
 144 +       int reg, err;
 145 +
 146 +       /* Advertise as multi-port device */
 147 +       reg = phy_read(phydev, MII_CTRL1000);
 148 +       reg |= ADVERTISED_MPD;
 149 +       err = phy_write(phydev, MII_CTRL1000, reg);
 150 +       if (err)
 151 +               return err;
 152 +
 153 +       return genphy_config_aneg(phydev);
 154 +}
 155 +
 156 +static int vr9_gphy_ack_interrupt(struct phy_device *phydev)
 157 +{
 158 +       int reg;
 159 +
 160 +       /*
 161 +        * Possible IRQ numbers:
 162 +        * - IM3_IRL18 for GPHY0
 163 +        * - IM3_IRL17 for GPHY1
 164 +        *
 165 +        * Due to a silicon bug IRQ lines are not really independent from
 166 +        * each other. Sometimes the two lines are driven at the same time
 167 +        * if only one GPHY core raises the interrupt.
 168 +        */
 169 +
 170 +       reg = phy_read(phydev, MII_VR9_11G_ISTAT);
 171 +
 172 +       return (reg < 0) ? reg : 0;
 173 +}
 174 +
 175 +static int vr9_gphy_did_interrupt(struct phy_device *phydev)
 176 +{
 177 +       int reg;
 178 +
 179 +       reg = phy_read(phydev, MII_VR9_11G_ISTAT);
 180 +
 181 +       return reg > 0;
 182 +}
 183 +
 184 +static int vr9_gphy_config_intr(struct phy_device *phydev)
 185 +{
 186 +       int err;
 187 +
 188 +       if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
 189 +               err = phy_write(phydev, MII_VR9_11G_IMASK, INT_VR9_11G_MASK);
 190 +       else
 191 +               err = phy_write(phydev, MII_VR9_11G_IMASK, 0);
 192 +
 193 +       return err;
 194 +}
 195 +
 196 +static struct phy_driver lantiq_phy[] = {
 197 +       {
 198 +               .phy_id         = 0xd565a400,
 199 +               .phy_id_mask    = 0xffffffff,
 200 +               .name           = "Lantiq XWAY PEF7071",
 201 +               .features       = (PHY_GBIT_FEATURES | SUPPORTED_Pause),
 202 +               .flags          = 0, /*PHY_HAS_INTERRUPT,*/
 203 +               .config_init    = vr9_gphy_config_init,
 204 +               .config_aneg    = vr9_gphy_config_aneg,
 205 +               .read_status    = genphy_read_status,
 206 +               .ack_interrupt  = vr9_gphy_ack_interrupt,
 207 +               .did_interrupt  = vr9_gphy_did_interrupt,
 208 +               .config_intr    = vr9_gphy_config_intr,
 209 +               .driver         = { .owner = THIS_MODULE },
 210 +       }, {
 211 +               .phy_id         = 0x030260D0,
 212 +               .phy_id_mask    = 0xfffffff0,
 213 +               .name           = "Lantiq XWAY VR9 GPHY 11G v1.3",
 214 +               .features       = (PHY_GBIT_FEATURES | SUPPORTED_Pause),
 215 +               .flags          = 0, /*PHY_HAS_INTERRUPT,*/
 216 +               .config_init    = vr9_gphy_config_init,
 217 +               .config_aneg    = vr9_gphy_config_aneg,
 218 +               .read_status    = genphy_read_status,
 219 +               .ack_interrupt  = vr9_gphy_ack_interrupt,
 220 +               .did_interrupt  = vr9_gphy_did_interrupt,
 221 +               .config_intr    = vr9_gphy_config_intr,
 222 +               .driver         = { .owner = THIS_MODULE },
 223 +       }, {
 224 +               .phy_id         = 0xd565a408,
 225 +               .phy_id_mask    = 0xfffffff8,
 226 +               .name           = "Lantiq XWAY VR9 GPHY 11G v1.4",
 227 +               .features       = (PHY_GBIT_FEATURES | SUPPORTED_Pause),
 228 +               .flags          = 0, /*PHY_HAS_INTERRUPT,*/
 229 +               .config_init    = vr9_gphy_config_init,
 230 +               .config_aneg    = vr9_gphy_config_aneg,
 231 +               .read_status    = genphy_read_status,
 232 +               .ack_interrupt  = vr9_gphy_ack_interrupt,
 233 +               .did_interrupt  = vr9_gphy_did_interrupt,
 234 +               .config_intr    = vr9_gphy_config_intr,
 235 +               .driver         = { .owner = THIS_MODULE },
 236 +       }, {
 237 +               .phy_id         = 0xd565a418,
 238 +               .phy_id_mask    = 0xfffffff8,
 239 +               .name           = "Lantiq XWAY XRX PHY22F v1.4",
 240 +               .features       = (PHY_BASIC_FEATURES | SUPPORTED_Pause),
 241 +               .flags          = 0, /*PHY_HAS_INTERRUPT,*/
 242 +               .config_init    = vr9_gphy_config_init,
 243 +               .config_aneg    = vr9_gphy_config_aneg,
 244 +               .read_status    = genphy_read_status,
 245 +               .ack_interrupt  = vr9_gphy_ack_interrupt,
 246 +               .did_interrupt  = vr9_gphy_did_interrupt,
 247 +               .config_intr    = vr9_gphy_config_intr,
 248 +               .driver         = { .owner = THIS_MODULE },
 249 +       },
 250 +};
 251 +
 252 +static int __init ltq_phy_init(void)
 253 +{
 254 +       int i;
 255 +
 256 +       for (i = 0; i < ARRAY_SIZE(lantiq_phy); i++) {
 257 +               int err = phy_driver_register(&lantiq_phy[i]);
 258 +               if (err)
 259 +                       pr_err("lantiq_phy: failed to load %s\n", lantiq_phy[i].name);
 260 +       }
 261 +
 262 +       return 0;
 263 +}
 264 +
 265 +static void __exit ltq_phy_exit(void)
 266 +{
 267 +       int i;
 268 +
 269 +       for (i = 0; i < ARRAY_SIZE(lantiq_phy); i++)
 270 +               phy_driver_unregister(&lantiq_phy[i]);
 271 +}
 272 +
 273 +module_init(ltq_phy_init);
 274 +module_exit(ltq_phy_exit);
 275 +
 276 +MODULE_DESCRIPTION("Lantiq PHY drivers");
 277 +MODULE_AUTHOR("Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>");
 278 +MODULE_LICENSE("GPL");
 279 --
 280 1.7.10.4
 281