1 --- a/drivers/i2c/busses/Makefile
2 +++ b/drivers/i2c/busses/Makefile
3 @@ -82,5 +82,6 @@ obj-$(CONFIG_I2C_SIBYTE) += i2c-sibyte.o
4 obj-$(CONFIG_I2C_STUB) += i2c-stub.o
5 obj-$(CONFIG_SCx200_ACB) += scx200_acb.o
6 obj-$(CONFIG_SCx200_I2C) += scx200_i2c.o
7 +obj-$(CONFIG_I2C_FALCON) += i2c-falcon.o
9 ccflags-$(CONFIG_I2C_DEBUG_BUS) := -DDEBUG
10 --- a/drivers/i2c/busses/Kconfig
11 +++ b/drivers/i2c/busses/Kconfig
12 @@ -284,6 +284,10 @@ config I2C_POWERMAC
14 comment "I2C system bus drivers (mostly embedded / system-on-chip)"
17 + tristate "Falcon I2C interface"
18 +# depends on SOC_FALCON
21 tristate "Atmel AT91 I2C Two-Wire interface (TWI)"
22 depends on ARCH_AT91 && EXPERIMENTAL && BROKEN
24 +++ b/drivers/i2c/busses/i2c-falcon.c
27 + * Lantiq FALC(tm) ON - I2C bus adapter
29 + * Parts based on i2c-designware.c and other i2c drivers from Linux 2.6.33
31 + * This program is free software; you can redistribute it and/or modify
32 + * it under the terms of the GNU General Public License as published by
33 + * the Free Software Foundation; either version 2 of the License, or
34 + * (at your option) any later version.
36 + * This program is distributed in the hope that it will be useful,
37 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
38 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
39 + * GNU General Public License for more details.
41 + * You should have received a copy of the GNU General Public License
42 + * along with this program; if not, write to the Free Software
43 + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
48 +#include <linux/kernel.h>
49 +#include <linux/module.h>
50 +#include <linux/delay.h>
51 +#include <linux/slab.h> /* for kzalloc, kfree */
52 +#include <linux/i2c.h>
53 +#include <linux/clk.h>
54 +#include <linux/errno.h>
55 +#include <linux/sched.h>
56 +#include <linux/err.h>
57 +#include <linux/interrupt.h>
58 +#include <linux/platform_device.h>
59 +#include <linux/io.h>
60 +#include <linux/gpio.h>
62 +#include <falcon/lantiq_soc.h>
65 + * - no high speed support
66 + * - supports only master mode
67 + * - ten bit mode is not tested (no slave devices)
70 +/* mapping for access macros */
71 +#define reg_r32(reg) __raw_readl(reg)
72 +#define reg_w32(val, reg) __raw_writel(val, reg)
73 +#define reg_w32_mask(clear, set, reg) \
74 + reg_w32((reg_r32(reg) & ~(clear)) | (set), reg)
75 +#define reg_r32_table(reg, idx) reg_r32(&((uint32_t *)®)[idx])
76 +#define reg_w32_table(val, reg, idx) reg_w32(val, &((uint32_t *)®)[idx])
77 +#define i2c (priv->membase)
78 +#include <falcon/i2c_reg.h>
80 +#define DRV_NAME "i2c-falcon"
81 +#define DRV_VERSION "1.01"
83 +#define FALCON_I2C_BUSY_TIMEOUT 20 /* ms */
86 +#define FALCON_I2C_XFER_TIMEOUT 25*HZ
88 +#define FALCON_I2C_XFER_TIMEOUT HZ
90 +#if defined(DEBUG) && 0
91 +#define PRINTK(arg...) printk(arg)
93 +#define PRINTK(arg...) do {} while (0)
96 +#define FALCON_I2C_IMSC_DEFAULT_MASK (I2C_IMSC_I2C_P_INT_EN | \
97 + I2C_IMSC_I2C_ERR_INT_EN)
99 +#define FALCON_I2C_ARB_LOST (1 << 0)
100 +#define FALCON_I2C_NACK (1 << 1)
101 +#define FALCON_I2C_RX_UFL (1 << 2)
102 +#define FALCON_I2C_RX_OFL (1 << 3)
103 +#define FALCON_I2C_TX_UFL (1 << 4)
104 +#define FALCON_I2C_TX_OFL (1 << 5)
107 + struct mutex mutex;
110 + FALCON_I2C_MODE_100 = 1,
111 + FALCON_I2C_MODE_400 = 2,
112 + FALCON_I2C_MODE_3400 = 3
113 + } mode; /* current speed mode */
115 + struct clk *clk; /* clock input for i2c hardware block */
116 + struct gpon_reg_i2c __iomem *membase; /* base of mapped registers */
117 + int irq_lb, irq_b, irq_err, irq_p; /* last burst, burst, error,
120 + struct i2c_adapter adap;
121 + struct device *dev;
123 + struct completion cmd_complete;
125 + /* message transfer data */
126 + /* current message */
127 + struct i2c_msg *current_msg;
128 + /* number of messages to handle */
130 + /* current buffer */
132 + /* remaining length of current buffer */
134 + /* error status of the current transfer */
137 + /* master status codes */
140 + STATUS_ADDR, /* address phase */
148 +static irqreturn_t falcon_i2c_isr(int irq, void *dev_id);
150 +static inline void enable_burst_irq(struct falcon_i2c *priv)
152 + i2c_w32_mask(0, I2C_IMSC_LBREQ_INT_EN | I2C_IMSC_BREQ_INT_EN, imsc);
154 +static inline void disable_burst_irq(struct falcon_i2c *priv)
156 + i2c_w32_mask(I2C_IMSC_LBREQ_INT_EN | I2C_IMSC_BREQ_INT_EN, 0, imsc);
159 +static void prepare_msg_send_addr(struct falcon_i2c *priv)
161 + struct i2c_msg *msg = priv->current_msg;
162 + int rd = !!(msg->flags & I2C_M_RD); /* extends to 0 or 1 */
163 + u16 addr = msg->addr;
166 + priv->msg_buf = msg->buf;
167 + priv->msg_buf_len = msg->len;
169 + priv->status = STATUS_READ;
171 + priv->status = STATUS_WRITE;
173 + /* send slave address */
174 + if (msg->flags & I2C_M_TEN) {
175 + i2c_w32(0xf0 | ((addr & 0x300) >> 7) | rd, txd);
176 + i2c_w32(addr & 0xff, txd);
178 + i2c_w32((addr & 0x7f) << 1 | rd, txd);
181 +static void set_tx_len(struct falcon_i2c *priv)
183 + struct i2c_msg *msg = priv->current_msg;
184 + int len = (msg->flags & I2C_M_TEN) ? 2 : 1;
186 + PRINTK("set_tx_len %cX\n", (msg->flags & I2C_M_RD)?'R':'T');
188 + priv->status = STATUS_ADDR;
190 + if (!(msg->flags & I2C_M_RD)) {
193 + /* set maximum received packet size (before rx int!) */
194 + i2c_w32(msg->len, mrps_ctrl);
196 + i2c_w32(len, tps_ctrl);
197 + enable_burst_irq(priv);
200 +static int falcon_i2c_hw_init(struct i2c_adapter *adap)
202 + struct falcon_i2c *priv = i2c_get_adapdata(adap);
205 + i2c_w32_mask(I2C_RUN_CTRL_RUN_EN, 0, run_ctrl);
208 + /* set normal operation clock divider */
209 + i2c_w32(1 << I2C_CLC_RMC_OFFSET, clc);
211 + /* for debugging a higher divider value! */
212 + i2c_w32(0xF0 << I2C_CLC_RMC_OFFSET, clc);
215 + /* set frequency */
216 + if (priv->mode == FALCON_I2C_MODE_100) {
217 + dev_dbg(priv->dev, "set standard mode (100 kHz)\n");
218 + i2c_w32(0, fdiv_high_cfg);
219 + i2c_w32((1 << I2C_FDIV_CFG_INC_OFFSET) |
220 + (499 << I2C_FDIV_CFG_DEC_OFFSET),
222 + } else if (priv->mode == FALCON_I2C_MODE_400) {
223 + dev_dbg(priv->dev, "set fast mode (400 kHz)\n");
224 + i2c_w32(0, fdiv_high_cfg);
225 + i2c_w32((1 << I2C_FDIV_CFG_INC_OFFSET) |
226 + (124 << I2C_FDIV_CFG_DEC_OFFSET),
228 + } else if (priv->mode == FALCON_I2C_MODE_3400) {
229 + dev_dbg(priv->dev, "set high mode (3.4 MHz)\n");
230 + i2c_w32(0, fdiv_cfg);
231 + /* TODO recalculate value for 100MHz input */
232 + i2c_w32((41 << I2C_FDIV_HIGH_CFG_INC_OFFSET) |
233 + (152 << I2C_FDIV_HIGH_CFG_DEC_OFFSET),
236 + dev_warn(priv->dev, "unknown mode\n");
240 + /* configure fifo */
241 + i2c_w32(I2C_FIFO_CFG_TXFC | /* tx fifo as flow controller */
242 + I2C_FIFO_CFG_RXFC | /* rx fifo as flow controller */
243 + I2C_FIFO_CFG_TXFA_TXFA2 | /* tx fifo 4-byte aligned */
244 + I2C_FIFO_CFG_RXFA_RXFA2 | /* rx fifo 4-byte aligned */
245 + I2C_FIFO_CFG_TXBS_TXBS0 | /* tx fifo burst size is 1 word */
246 + I2C_FIFO_CFG_RXBS_RXBS0, /* rx fifo burst size is 1 word */
249 + /* configure address */
250 + i2c_w32(I2C_ADDR_CFG_SOPE_EN | /* generate stop when no more data in the
252 + I2C_ADDR_CFG_SONA_EN | /* generate stop when NA received */
253 + I2C_ADDR_CFG_MnS_EN | /* we are master device */
254 + 0, /* our slave address (not used!) */
258 + i2c_w32_mask(0, I2C_RUN_CTRL_RUN_EN, run_ctrl);
263 +static int falcon_i2c_wait_bus_not_busy(struct falcon_i2c *priv)
265 + int timeout = FALCON_I2C_BUSY_TIMEOUT;
267 + while ((i2c_r32(bus_stat) & I2C_BUS_STAT_BS_MASK)
268 + != I2C_BUS_STAT_BS_FREE) {
269 + if (timeout <= 0) {
270 + dev_warn(priv->dev, "timeout waiting for bus ready\n");
280 +static void falcon_i2c_tx(struct falcon_i2c *priv, int last)
282 + if (priv->msg_buf_len && priv->msg_buf) {
283 + i2c_w32(*priv->msg_buf, txd);
285 + if (--priv->msg_buf_len)
288 + priv->msg_buf = NULL;
293 + disable_burst_irq(priv);
297 +static void falcon_i2c_rx(struct falcon_i2c *priv, int last)
299 + u32 fifo_stat,timeout;
300 + if (priv->msg_buf_len && priv->msg_buf) {
303 + fifo_stat = i2c_r32(ffs_stat);
304 + } while (!fifo_stat && --timeout);
307 + PRINTK("\nrx timeout\n");
310 + while (fifo_stat) {
311 + *priv->msg_buf = i2c_r32(rxd);
312 + if (--priv->msg_buf_len)
315 + priv->msg_buf = NULL;
320 + fifo_stat = i2c_r32(ffs_stat);
322 + /* do not read more than burst size, otherwise no "last
323 + burst" is generated and the transaction is blocked! */
332 + disable_burst_irq(priv);
334 + if (priv->status == STATUS_READ_END) {
335 + /* do the STATUS_STOP and complete() here, as sometimes
336 + the tx_end is already seen before this is finished */
337 + priv->status = STATUS_STOP;
338 + complete(&priv->cmd_complete);
340 + i2c_w32(I2C_ENDD_CTRL_SETEND, endd_ctrl);
341 + priv->status = STATUS_READ_END;
346 +static void falcon_i2c_xfer_init(struct falcon_i2c *priv)
348 + /* enable interrupts */
349 + i2c_w32(FALCON_I2C_IMSC_DEFAULT_MASK, imsc);
351 + /* trigger transfer of first msg */
355 +static void dump_msgs(struct i2c_msg msgs[], int num, int rx)
359 + printk("Messages %d %s\n", num, rx ? "out" : "in");
360 + for (i = 0; i < num; i++) {
361 + printk("%2d %cX Msg(%d) addr=0x%X: ", i,
362 + (msgs[i].flags & I2C_M_RD)?'R':'T',
363 + msgs[i].len, msgs[i].addr);
364 + if (!(msgs[i].flags & I2C_M_RD) || rx) {
365 + for (j = 0; j < msgs[i].len; j++)
366 + printk("%02X ", msgs[i].buf[j]);
373 +static void falcon_i2c_release_bus(struct falcon_i2c *priv)
375 + if ((i2c_r32(bus_stat) & I2C_BUS_STAT_BS_MASK) == I2C_BUS_STAT_BS_BM)
376 + i2c_w32(I2C_ENDD_CTRL_SETEND, endd_ctrl);
379 +static int falcon_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[],
382 + struct falcon_i2c *priv = i2c_get_adapdata(adap);
385 + dev_dbg(priv->dev, "xfer %u messages\n", num);
386 + dump_msgs(msgs, num, 0);
388 + mutex_lock(&priv->mutex);
390 + INIT_COMPLETION(priv->cmd_complete);
391 + priv->current_msg = msgs;
392 + priv->msgs_num = num;
394 + priv->status = STATUS_IDLE;
396 + /* wait for the bus to become ready */
397 + ret = falcon_i2c_wait_bus_not_busy(priv);
401 + while (priv->msgs_num) {
402 + /* start the transfers */
403 + falcon_i2c_xfer_init(priv);
405 + /* wait for transfers to complete */
406 + ret = wait_for_completion_interruptible_timeout(
407 + &priv->cmd_complete, FALCON_I2C_XFER_TIMEOUT);
409 + dev_err(priv->dev, "controller timed out\n");
410 + falcon_i2c_hw_init(adap);
413 + } else if (ret < 0)
416 + if (priv->msg_err) {
417 + if (priv->msg_err & FALCON_I2C_NACK)
423 + if (--priv->msgs_num) {
424 + priv->current_msg++;
431 + falcon_i2c_release_bus(priv);
433 + mutex_unlock(&priv->mutex);
436 + dump_msgs(msgs, num, 1);
438 + PRINTK("XFER ret %d\n", ret);
442 +static irqreturn_t falcon_i2c_isr_burst(int irq, void *dev_id)
444 + struct falcon_i2c *priv = dev_id;
445 + struct i2c_msg *msg = priv->current_msg;
446 + int last = (irq == priv->irq_lb);
453 + if (msg->flags & I2C_M_RD) {
454 + switch (priv->status) {
457 + prepare_msg_send_addr(priv);
458 + disable_burst_irq(priv);
461 + case STATUS_READ_END:
463 + falcon_i2c_rx(priv, last);
466 + disable_burst_irq(priv);
467 + printk("Status R %d\n", priv->status);
471 + switch (priv->status) {
474 + prepare_msg_send_addr(priv);
478 + falcon_i2c_tx(priv, last);
481 + disable_burst_irq(priv);
482 + printk("Status W %d\n", priv->status);
487 + i2c_w32(I2C_ICR_BREQ_INT_CLR | I2C_ICR_LBREQ_INT_CLR, icr);
488 + return IRQ_HANDLED;
491 +static void falcon_i2c_isr_prot(struct falcon_i2c *priv)
493 + u32 i_pro = i2c_r32(p_irqss);
497 + /* not acknowledge */
498 + if (i_pro & I2C_P_IRQSS_NACK) {
499 + priv->msg_err |= FALCON_I2C_NACK;
503 + /* arbitration lost */
504 + if (i_pro & I2C_P_IRQSS_AL) {
505 + priv->msg_err |= FALCON_I2C_ARB_LOST;
506 + PRINTK(" arb-lost");
508 + /* tx -> rx switch */
509 + if (i_pro & I2C_P_IRQSS_RX)
513 + if (i_pro & I2C_P_IRQSS_TX_END)
517 + if (!priv->msg_err) {
518 + /* tx -> rx switch */
519 + if (i_pro & I2C_P_IRQSS_RX) {
520 + priv->status = STATUS_READ;
521 + enable_burst_irq(priv);
523 + if (i_pro & I2C_P_IRQSS_TX_END) {
524 + if (priv->status == STATUS_READ)
525 + priv->status = STATUS_READ_END;
527 + disable_burst_irq(priv);
528 + priv->status = STATUS_STOP;
533 + i2c_w32(i_pro, p_irqsc);
536 +static irqreturn_t falcon_i2c_isr(int irq, void *dev_id)
538 + u32 i_raw, i_err=0;
539 + struct falcon_i2c *priv = dev_id;
541 + i_raw = i2c_r32(mis);
542 + PRINTK("i_raw 0x%08X\n", i_raw);
544 + /* error interrupt */
545 + if (i_raw & I2C_RIS_I2C_ERR_INT_INTOCC) {
546 + i_err = i2c_r32(err_irqss);
547 + PRINTK("i_err 0x%08X bus_stat 0x%04X\n",
548 + i_err, i2c_r32(bus_stat));
550 + /* tx fifo overflow (8) */
551 + if (i_err & I2C_ERR_IRQSS_TXF_OFL)
552 + priv->msg_err |= FALCON_I2C_TX_OFL;
554 + /* tx fifo underflow (4) */
555 + if (i_err & I2C_ERR_IRQSS_TXF_UFL)
556 + priv->msg_err |= FALCON_I2C_TX_UFL;
558 + /* rx fifo overflow (2) */
559 + if (i_err & I2C_ERR_IRQSS_RXF_OFL)
560 + priv->msg_err |= FALCON_I2C_RX_OFL;
562 + /* rx fifo underflow (1) */
563 + if (i_err & I2C_ERR_IRQSS_RXF_UFL)
564 + priv->msg_err |= FALCON_I2C_RX_UFL;
566 + i2c_w32(i_err, err_irqsc);
569 + /* protocol interrupt */
570 + if (i_raw & I2C_RIS_I2C_P_INT_INTOCC)
571 + falcon_i2c_isr_prot(priv);
573 + if ((priv->msg_err) || (priv->status == STATUS_STOP))
574 + complete(&priv->cmd_complete);
576 + return IRQ_HANDLED;
579 +static u32 falcon_i2c_functionality(struct i2c_adapter *adap)
581 + return I2C_FUNC_I2C |
582 + I2C_FUNC_10BIT_ADDR |
583 + I2C_FUNC_SMBUS_EMUL;
586 +static struct i2c_algorithm falcon_i2c_algorithm = {
587 + .master_xfer = falcon_i2c_xfer,
588 + .functionality = falcon_i2c_functionality,
591 +static int __devinit falcon_i2c_probe(struct platform_device *pdev)
594 + struct falcon_i2c *priv;
595 + struct i2c_adapter *adap;
596 + struct resource *mmres, *ioarea,
597 + *irqres_lb, *irqres_b, *irqres_err, *irqres_p;
600 + dev_dbg(&pdev->dev, "probing\n");
602 + mmres = platform_get_resource(pdev, IORESOURCE_MEM, 0);
603 + irqres_lb = platform_get_resource_byname(pdev, IORESOURCE_IRQ,
605 + irqres_b = platform_get_resource_byname(pdev, IORESOURCE_IRQ, "i2c_b");
606 + irqres_err = platform_get_resource_byname(pdev, IORESOURCE_IRQ,
608 + irqres_p = platform_get_resource_byname(pdev, IORESOURCE_IRQ, "i2c_p");
610 + if (!mmres || !irqres_lb || !irqres_b || !irqres_err || !irqres_p) {
611 + dev_err(&pdev->dev, "no resources\n");
615 + clk = clk_get(&pdev->dev, "fpi");
617 + dev_err(&pdev->dev, "failed to get fpi clk\n");
621 + if (clk_get_rate(clk) != 100000000) {
622 + dev_err(&pdev->dev, "input clock is not 100MHz\n");
626 + /* allocate private data */
627 + priv = kzalloc(sizeof(*priv), GFP_KERNEL);
629 + dev_err(&pdev->dev, "can't allocate private data\n");
633 + adap = &priv->adap;
634 + i2c_set_adapdata(adap, priv);
635 + adap->owner = THIS_MODULE;
636 + adap->class = I2C_CLASS_HWMON | I2C_CLASS_SPD;
637 + strlcpy(adap->name, DRV_NAME "-adapter", sizeof(adap->name));
638 + adap->algo = &falcon_i2c_algorithm;
640 + priv->mode = FALCON_I2C_MODE_100;
642 + priv->dev = &pdev->dev;
644 + init_completion(&priv->cmd_complete);
645 + mutex_init(&priv->mutex);
647 + ret = ltq_gpio_request(107, 0, 0, 0, DRV_NAME":sda");
649 + dev_err(&pdev->dev, "I2C gpio 107 (sda) not available\n");
651 + goto err_free_priv;
653 + ret = ltq_gpio_request(108, 0, 0, 0, DRV_NAME":scl");
656 + dev_err(&pdev->dev, "I2C gpio 108 (scl) not available\n");
658 + goto err_free_priv;
661 + ioarea = request_mem_region(mmres->start, resource_size(mmres),
664 + if (ioarea == NULL) {
665 + dev_err(&pdev->dev, "I2C region already claimed\n");
667 + goto err_free_gpio;
671 + priv->membase = ioremap_nocache(mmres->start & ~KSEG1,
672 + resource_size(mmres));
673 + if (priv->membase == NULL) {
675 + goto err_release_region;
678 + priv->irq_lb = irqres_lb->start;
679 + ret = request_irq(priv->irq_lb, falcon_i2c_isr_burst, IRQF_DISABLED,
680 + irqres_lb->name, priv);
682 + dev_err(&pdev->dev, "can't get last burst IRQ %d\n", irqres_lb->start);
684 + goto err_unmap_mem;
687 + priv->irq_b = irqres_b->start;
688 + ret = request_irq(priv->irq_b, falcon_i2c_isr_burst, IRQF_DISABLED,
689 + irqres_b->name, priv);
691 + dev_err(&pdev->dev, "can't get burst IRQ %d\n", irqres_b->start);
693 + goto err_free_lb_irq;
696 + priv->irq_err = irqres_err->start;
697 + ret = request_irq(priv->irq_err, falcon_i2c_isr, IRQF_DISABLED,
698 + irqres_err->name, priv);
700 + dev_err(&pdev->dev, "can't get error IRQ %d\n", irqres_err->start);
702 + goto err_free_b_irq;
705 + priv->irq_p = irqres_p->start;
706 + ret = request_irq(priv->irq_p, falcon_i2c_isr, IRQF_DISABLED,
707 + irqres_p->name, priv);
709 + dev_err(&pdev->dev, "can't get protocol IRQ %d\n", irqres_p->start);
711 + goto err_free_err_irq;
714 + dev_dbg(&pdev->dev, "mapped io-space to %p\n", priv->membase);
715 + dev_dbg(&pdev->dev, "use IRQs %d, %d, %d, %d\n", irqres_lb->start,
716 + irqres_b->start, irqres_err->start, irqres_p->start);
718 + /* add our adapter to the i2c stack */
719 + ret = i2c_add_numbered_adapter(adap);
721 + dev_err(&pdev->dev, "can't register I2C adapter\n");
722 + goto err_free_p_irq;
725 + platform_set_drvdata(pdev, priv);
726 + i2c_set_adapdata(adap, priv);
728 + /* print module version information */
729 + dev_dbg(&pdev->dev, "module id=%u revision=%u\n",
730 + (i2c_r32(id) & I2C_ID_ID_MASK) >> I2C_ID_ID_OFFSET,
731 + (i2c_r32(id) & I2C_ID_REV_MASK) >> I2C_ID_REV_OFFSET);
733 + /* initialize HW */
734 + ret = falcon_i2c_hw_init(adap);
736 + dev_err(&pdev->dev, "can't configure adapter\n");
737 + goto err_remove_adapter;
740 + dev_info(&pdev->dev, "version %s\n", DRV_VERSION);
745 + i2c_del_adapter(adap);
746 + platform_set_drvdata(pdev, NULL);
749 + free_irq(priv->irq_p, priv);
752 + free_irq(priv->irq_err, priv);
755 + free_irq(priv->irq_b, priv);
758 + free_irq(priv->irq_lb, priv);
761 + iounmap(priv->membase);
764 + release_mem_region(mmres->start, resource_size(mmres));
776 +static int __devexit falcon_i2c_remove(struct platform_device *pdev)
778 + struct falcon_i2c *priv = platform_get_drvdata(pdev);
779 + struct resource *mmres;
782 + i2c_w32_mask(I2C_RUN_CTRL_RUN_EN, 0, run_ctrl);
784 + /* remove driver */
785 + platform_set_drvdata(pdev, NULL);
786 + i2c_del_adapter(&priv->adap);
788 + free_irq(priv->irq_lb, priv);
789 + free_irq(priv->irq_b, priv);
790 + free_irq(priv->irq_err, priv);
791 + free_irq(priv->irq_p, priv);
793 + iounmap(priv->membase);
800 + mmres = platform_get_resource(pdev, IORESOURCE_MEM, 0);
801 + release_mem_region(mmres->start, resource_size(mmres));
803 + dev_dbg(&pdev->dev, "removed\n");
808 +static struct platform_driver falcon_i2c_driver = {
809 + .probe = falcon_i2c_probe,
810 + .remove = __devexit_p(falcon_i2c_remove),
813 + .owner = THIS_MODULE,
817 +static int __init falcon_i2c_init(void)
821 + ret = platform_driver_register(&falcon_i2c_driver);
824 + pr_debug(DRV_NAME ": can't register platform driver\n");
829 +static void __exit falcon_i2c_exit(void)
831 + platform_driver_unregister(&falcon_i2c_driver);
834 +module_init(falcon_i2c_init);
835 +module_exit(falcon_i2c_exit);
837 +MODULE_DESCRIPTION("Lantiq FALC(tm) ON - I2C bus adapter");
838 +MODULE_ALIAS("platform:" DRV_NAME);
839 +MODULE_LICENSE("GPL");
840 +MODULE_VERSION(DRV_VERSION);