target/linux/lantiq/patches-3.0/0006-MIPS-lantiq-add-basic-support-for-FALC-ON.patch

   1 From ff57bc17a9964d24708759c6d78a51e337563d5f Mon Sep 17 00:00:00 2001
   2 From: John Crispin <blogic@openwrt.org>
   3 Date: Thu, 11 Aug 2011 14:33:04 +0200
   4 Subject: [PATCH 06/24] MIPS: lantiq: add basic support for FALC-ON
   5
   6 Adds support for the FALC-ON SoC. This SoC is from the fiber to the home GPON
   7 series.
   8
   9 Signed-off-by: John Crispin <blogic@openwrt.org>
  10 Signed-off-by: Thomas Langer <thomas.langer@lantiq.com>
  11 Cc: linux-mips@linux-mips.org
  12 ---
  13  .../include/asm/mach-lantiq/falcon/falcon_irq.h    |  268 ++++++++++++++++++++
  14  arch/mips/include/asm/mach-lantiq/falcon/irq.h     |   18 ++
  15  .../include/asm/mach-lantiq/falcon/lantiq_soc.h    |  140 ++++++++++
  16  arch/mips/include/asm/mach-lantiq/lantiq.h         |    1 +
  17  arch/mips/lantiq/Kconfig                           |    4 +
  18  arch/mips/lantiq/Makefile                          |    1 +
  19  arch/mips/lantiq/Platform                          |    1 +
  20  arch/mips/lantiq/falcon/Makefile                   |    1 +
  21  arch/mips/lantiq/falcon/clk.c                      |   44 ++++
  22  arch/mips/lantiq/falcon/devices.c                  |   87 +++++++
  23  arch/mips/lantiq/falcon/devices.h                  |   18 ++
  24  arch/mips/lantiq/falcon/prom.c                     |   72 ++++++
  25  arch/mips/lantiq/falcon/reset.c                    |   87 +++++++
  26  arch/mips/lantiq/falcon/sysctrl.c                  |  181 +++++++++++++
  27  14 files changed, 923 insertions(+), 0 deletions(-)
  28  create mode 100644 arch/mips/include/asm/mach-lantiq/falcon/falcon_irq.h
  29  create mode 100644 arch/mips/include/asm/mach-lantiq/falcon/irq.h
  30  create mode 100644 arch/mips/include/asm/mach-lantiq/falcon/lantiq_soc.h
  31  create mode 100644 arch/mips/lantiq/falcon/Makefile
  32  create mode 100644 arch/mips/lantiq/falcon/clk.c
  33  create mode 100644 arch/mips/lantiq/falcon/devices.c
  34  create mode 100644 arch/mips/lantiq/falcon/devices.h
  35  create mode 100644 arch/mips/lantiq/falcon/prom.c
  36  create mode 100644 arch/mips/lantiq/falcon/reset.c
  37  create mode 100644 arch/mips/lantiq/falcon/sysctrl.c
  38
  39 diff --git a/arch/mips/include/asm/mach-lantiq/falcon/falcon_irq.h b/arch/mips/include/asm/mach-lantiq/falcon/falcon_irq.h
  40 new file mode 100644
  41 index 0000000..4dc6466
  42 --- /dev/null
  43 +++ b/arch/mips/include/asm/mach-lantiq/falcon/falcon_irq.h
  44 @@ -0,0 +1,268 @@
  45 +/*
  46 + *  This program is free software; you can redistribute it and/or modify it
  47 + *  under the terms of the GNU General Public License version 2 as published
  48 + *  by the Free Software Foundation.
  49 + *
  50 + *  Copyright (C) 2010 Thomas Langer <thomas.langer@lantiq.com>
  51 + */
  52 +
  53 +#ifndef _FALCON_IRQ__
  54 +#define _FALCON_IRQ__
  55 +
  56 +#define INT_NUM_IRQ0                   8
  57 +#define INT_NUM_IM0_IRL0               (INT_NUM_IRQ0 + 0)
  58 +#define INT_NUM_IM1_IRL0               (INT_NUM_IM0_IRL0 + 32)
  59 +#define INT_NUM_IM2_IRL0               (INT_NUM_IM1_IRL0 + 32)
  60 +#define INT_NUM_IM3_IRL0               (INT_NUM_IM2_IRL0 + 32)
  61 +#define INT_NUM_IM4_IRL0               (INT_NUM_IM3_IRL0 + 32)
  62 +#define INT_NUM_EXTRA_START            (INT_NUM_IM4_IRL0 + 32)
  63 +#define INT_NUM_IM_OFFSET              (INT_NUM_IM1_IRL0 - INT_NUM_IM0_IRL0)
  64 +
  65 +#define MIPS_CPU_TIMER_IRQ                     7
  66 +
  67 +/* HOST IF Event Interrupt */
  68 +#define FALCON_IRQ_HOST                                (INT_NUM_IM0_IRL0 + 0)
  69 +/* HOST IF Mailbox0 Receive Interrupt */
  70 +#define FALCON_IRQ_HOST_MB0_RX                 (INT_NUM_IM0_IRL0 + 1)
  71 +/* HOST IF Mailbox0 Transmit Interrupt */
  72 +#define FALCON_IRQ_HOST_MB0_TX                 (INT_NUM_IM0_IRL0 + 2)
  73 +/* HOST IF Mailbox1 Receive Interrupt */
  74 +#define FALCON_IRQ_HOST_MB1_RX                 (INT_NUM_IM0_IRL0 + 3)
  75 +/* HOST IF Mailbox1 Transmit Interrupt */
  76 +#define FALCON_IRQ_HOST_MB1_TX                 (INT_NUM_IM0_IRL0 + 4)
  77 +/* I2C Last Single Data Transfer Request */
  78 +#define FALCON_IRQ_I2C_LSREQ                   (INT_NUM_IM0_IRL0 + 8)
  79 +/* I2C Single Data Transfer Request */
  80 +#define FALCON_IRQ_I2C_SREQ                    (INT_NUM_IM0_IRL0 + 9)
  81 +/* I2C Last Burst Data Transfer Request */
  82 +#define FALCON_IRQ_I2C_LBREQ                   (INT_NUM_IM0_IRL0 + 10)
  83 +/* I2C Burst Data Transfer Request */
  84 +#define FALCON_IRQ_I2C_BREQ                    (INT_NUM_IM0_IRL0 + 11)
  85 +/* I2C Error Interrupt */
  86 +#define FALCON_IRQ_I2C_I2C_ERR                 (INT_NUM_IM0_IRL0 + 12)
  87 +/* I2C Protocol Interrupt */
  88 +#define FALCON_IRQ_I2C_I2C_P                   (INT_NUM_IM0_IRL0 + 13)
  89 +/* SSC Transmit Interrupt */
  90 +#define FALCON_IRQ_SSC_T                       (INT_NUM_IM0_IRL0 + 14)
  91 +/* SSC Receive Interrupt */
  92 +#define FALCON_IRQ_SSC_R                       (INT_NUM_IM0_IRL0 + 15)
  93 +/* SSC Error Interrupt */
  94 +#define FALCON_IRQ_SSC_E                       (INT_NUM_IM0_IRL0 + 16)
  95 +/* SSC Frame Interrupt */
  96 +#define FALCON_IRQ_SSC_F                       (INT_NUM_IM0_IRL0 + 17)
  97 +/* Advanced Encryption Standard Interrupt */
  98 +#define FALCON_IRQ_AES_AES                     (INT_NUM_IM0_IRL0 + 27)
  99 +/* Secure Hash Algorithm Interrupt */
 100 +#define FALCON_IRQ_SHA_HASH                    (INT_NUM_IM0_IRL0 + 28)
 101 +/* PCM Receive Interrupt */
 102 +#define FALCON_IRQ_PCM_RX                      (INT_NUM_IM0_IRL0 + 29)
 103 +/* PCM Transmit Interrupt */
 104 +#define FALCON_IRQ_PCM_TX                      (INT_NUM_IM0_IRL0 + 30)
 105 +/* PCM Transmit Crash Interrupt */
 106 +#define FALCON_IRQ_PCM_HW2_CRASH               (INT_NUM_IM0_IRL0 + 31)
 107 +
 108 +/* EBU Serial Flash Command Error */
 109 +#define FALCON_IRQ_EBU_SF_CMDERR               (INT_NUM_IM1_IRL0 + 0)
 110 +/* EBU Serial Flash Command Overwrite Error */
 111 +#define FALCON_IRQ_EBU_SF_COVERR               (INT_NUM_IM1_IRL0 + 1)
 112 +/* EBU Serial Flash Busy */
 113 +#define FALCON_IRQ_EBU_SF_BUSY                 (INT_NUM_IM1_IRL0 + 2)
 114 +/* External Interrupt from GPIO P0 */
 115 +#define FALCON_IRQ_GPIO_P0                     (INT_NUM_IM1_IRL0 + 4)
 116 +/* External Interrupt from GPIO P1 */
 117 +#define FALCON_IRQ_GPIO_P1                     (INT_NUM_IM1_IRL0 + 5)
 118 +/* External Interrupt from GPIO P2 */
 119 +#define FALCON_IRQ_GPIO_P2                     (INT_NUM_IM1_IRL0 + 6)
 120 +/* External Interrupt from GPIO P3 */
 121 +#define FALCON_IRQ_GPIO_P3                     (INT_NUM_IM1_IRL0 + 7)
 122 +/* External Interrupt from GPIO P4 */
 123 +#define FALCON_IRQ_GPIO_P4                     (INT_NUM_IM1_IRL0 + 8)
 124 +/* 8kHz backup interrupt derived from core-PLL */
 125 +#define FALCON_IRQ_FSC_BKP                     (INT_NUM_IM1_IRL0 + 10)
 126 +/* FSC Timer Interrupt 0 */
 127 +#define FALCON_IRQ_FSCT_CMP0                   (INT_NUM_IM1_IRL0 + 11)
 128 +/* FSC Timer Interrupt 1 */
 129 +#define FALCON_IRQ_FSCT_CMP1                   (INT_NUM_IM1_IRL0 + 12)
 130 +/* 8kHz root interrupt derived from GPON interface */
 131 +#define FALCON_IRQ_FSC_ROOT                    (INT_NUM_IM1_IRL0 + 13)
 132 +/* Time of Day */
 133 +#define FALCON_IRQ_TOD                         (INT_NUM_IM1_IRL0 + 14)
 134 +/* PMA Interrupt from IntNode of the 200MHz Domain */
 135 +#define FALCON_IRQ_PMA_200M                    (INT_NUM_IM1_IRL0 + 15)
 136 +/* PMA Interrupt from IntNode of the TX Clk Domain */
 137 +#define FALCON_IRQ_PMA_TX                      (INT_NUM_IM1_IRL0 + 16)
 138 +/* PMA Interrupt from IntNode of the RX Clk Domain */
 139 +#define FALCON_IRQ_PMA_RX                      (INT_NUM_IM1_IRL0 + 17)
 140 +/* SYS1 Interrupt */
 141 +#define FALCON_IRQ_SYS1                                (INT_NUM_IM1_IRL0 + 20)
 142 +/* SYS GPE Interrupt */
 143 +#define FALCON_IRQ_SYS_GPE                     (INT_NUM_IM1_IRL0 + 21)
 144 +/* Watchdog Access Error Interrupt */
 145 +#define FALCON_IRQ_WDT_AEIR                    (INT_NUM_IM1_IRL0 + 24)
 146 +/* Watchdog Prewarning Interrupt */
 147 +#define FALCON_IRQ_WDT_PIR                     (INT_NUM_IM1_IRL0 + 25)
 148 +/* SBIU interrupt */
 149 +#define FALCON_IRQ_SBIU0                       (INT_NUM_IM1_IRL0 + 27)
 150 +/* FPI Bus Control Unit Interrupt */
 151 +#define FALCON_IRQ_BCU0                                (INT_NUM_IM1_IRL0 + 29)
 152 +/* DDR Controller Interrupt */
 153 +#define FALCON_IRQ_DDR                         (INT_NUM_IM1_IRL0 + 30)
 154 +/* Crossbar Error Interrupt */
 155 +#define FALCON_IRQ_XBAR_ERROR                  (INT_NUM_IM1_IRL0 + 31)
 156 +
 157 +/* ICTRLL 0 Interrupt */
 158 +#define FALCON_IRQ_ICTRLL0                     (INT_NUM_IM2_IRL0 + 0)
 159 +/* ICTRLL 1 Interrupt */
 160 +#define FALCON_IRQ_ICTRLL1                     (INT_NUM_IM2_IRL0 + 1)
 161 +/* ICTRLL 2 Interrupt */
 162 +#define FALCON_IRQ_ICTRLL2                     (INT_NUM_IM2_IRL0 + 2)
 163 +/* ICTRLL 3 Interrupt */
 164 +#define FALCON_IRQ_ICTRLL3                     (INT_NUM_IM2_IRL0 + 3)
 165 +/* OCTRLL 0 Interrupt */
 166 +#define FALCON_IRQ_OCTRLL0                     (INT_NUM_IM2_IRL0 + 4)
 167 +/* OCTRLL 1 Interrupt */
 168 +#define FALCON_IRQ_OCTRLL1                     (INT_NUM_IM2_IRL0 + 5)
 169 +/* OCTRLL 2 Interrupt */
 170 +#define FALCON_IRQ_OCTRLL2                     (INT_NUM_IM2_IRL0 + 6)
 171 +/* OCTRLL 3 Interrupt */
 172 +#define FALCON_IRQ_OCTRLL3                     (INT_NUM_IM2_IRL0 + 7)
 173 +/* OCTRLG Interrupt */
 174 +#define FALCON_IRQ_OCTRLG                      (INT_NUM_IM2_IRL0 + 9)
 175 +/* IQM Interrupt */
 176 +#define FALCON_IRQ_IQM                         (INT_NUM_IM2_IRL0 + 10)
 177 +/* FSQM Interrupt */
 178 +#define FALCON_IRQ_FSQM                                (INT_NUM_IM2_IRL0 + 11)
 179 +/* TMU Interrupt */
 180 +#define FALCON_IRQ_TMU                         (INT_NUM_IM2_IRL0 + 12)
 181 +/* LINK1 Interrupt */
 182 +#define FALCON_IRQ_LINK1                       (INT_NUM_IM2_IRL0 + 14)
 183 +/* ICTRLC 0 Interrupt */
 184 +#define FALCON_IRQ_ICTRLC0                     (INT_NUM_IM2_IRL0 + 16)
 185 +/* ICTRLC 1 Interrupt */
 186 +#define FALCON_IRQ_ICTRLC1                     (INT_NUM_IM2_IRL0 + 17)
 187 +/* OCTRLC Interrupt */
 188 +#define FALCON_IRQ_OCTRLC                      (INT_NUM_IM2_IRL0 + 18)
 189 +/* CONFIG Break Interrupt */
 190 +#define FALCON_IRQ_CONFIG_BREAK                        (INT_NUM_IM2_IRL0 + 19)
 191 +/* CONFIG Interrupt */
 192 +#define FALCON_IRQ_CONFIG                      (INT_NUM_IM2_IRL0 + 20)
 193 +/* Dispatcher Interrupt */
 194 +#define FALCON_IRQ_DISP                                (INT_NUM_IM2_IRL0 + 21)
 195 +/* TBM Interrupt */
 196 +#define FALCON_IRQ_TBM                         (INT_NUM_IM2_IRL0 + 22)
 197 +/* GTC Downstream Interrupt */
 198 +#define FALCON_IRQ_GTC_DS                      (INT_NUM_IM2_IRL0 + 29)
 199 +/* GTC Upstream Interrupt */
 200 +#define FALCON_IRQ_GTC_US                      (INT_NUM_IM2_IRL0 + 30)
 201 +/* EIM Interrupt */
 202 +#define FALCON_IRQ_EIM                         (INT_NUM_IM2_IRL0 + 31)
 203 +
 204 +/* ASC0 Transmit Interrupt */
 205 +#define FALCON_IRQ_ASC0_T                      (INT_NUM_IM3_IRL0 + 0)
 206 +/* ASC0 Receive Interrupt */
 207 +#define FALCON_IRQ_ASC0_R                      (INT_NUM_IM3_IRL0 + 1)
 208 +/* ASC0 Error Interrupt */
 209 +#define FALCON_IRQ_ASC0_E                      (INT_NUM_IM3_IRL0 + 2)
 210 +/* ASC0 Transmit Buffer Interrupt */
 211 +#define FALCON_IRQ_ASC0_TB                     (INT_NUM_IM3_IRL0 + 3)
 212 +/* ASC0 Autobaud Start Interrupt */
 213 +#define FALCON_IRQ_ASC0_ABST                   (INT_NUM_IM3_IRL0 + 4)
 214 +/* ASC0 Autobaud Detection Interrupt */
 215 +#define FALCON_IRQ_ASC0_ABDET                  (INT_NUM_IM3_IRL0 + 5)
 216 +/* ASC1 Modem Status Interrupt */
 217 +#define FALCON_IRQ_ASC0_MS                     (INT_NUM_IM3_IRL0 + 6)
 218 +/* ASC0 Soft Flow Control Interrupt */
 219 +#define FALCON_IRQ_ASC0_SFC                    (INT_NUM_IM3_IRL0 + 7)
 220 +/* ASC1 Transmit Interrupt */
 221 +#define FALCON_IRQ_ASC1_T                      (INT_NUM_IM3_IRL0 + 8)
 222 +/* ASC1 Receive Interrupt */
 223 +#define FALCON_IRQ_ASC1_R                      (INT_NUM_IM3_IRL0 + 9)
 224 +/* ASC1 Error Interrupt */
 225 +#define FALCON_IRQ_ASC1_E                      (INT_NUM_IM3_IRL0 + 10)
 226 +/* ASC1 Transmit Buffer Interrupt */
 227 +#define FALCON_IRQ_ASC1_TB                     (INT_NUM_IM3_IRL0 + 11)
 228 +/* ASC1 Autobaud Start Interrupt */
 229 +#define FALCON_IRQ_ASC1_ABST                   (INT_NUM_IM3_IRL0 + 12)
 230 +/* ASC1 Autobaud Detection Interrupt */
 231 +#define FALCON_IRQ_ASC1_ABDET                  (INT_NUM_IM3_IRL0 + 13)
 232 +/* ASC1 Modem Status Interrupt */
 233 +#define FALCON_IRQ_ASC1_MS                     (INT_NUM_IM3_IRL0 + 14)
 234 +/* ASC1 Soft Flow Control Interrupt */
 235 +#define FALCON_IRQ_ASC1_SFC                    (INT_NUM_IM3_IRL0 + 15)
 236 +/* GPTC Timer/Counter 1A Interrupt */
 237 +#define FALCON_IRQ_GPTC_TC1A                   (INT_NUM_IM3_IRL0 + 16)
 238 +/* GPTC Timer/Counter 1B Interrupt */
 239 +#define FALCON_IRQ_GPTC_TC1B                   (INT_NUM_IM3_IRL0 + 17)
 240 +/* GPTC Timer/Counter 2A Interrupt */
 241 +#define FALCON_IRQ_GPTC_TC2A                   (INT_NUM_IM3_IRL0 + 18)
 242 +/* GPTC Timer/Counter 2B Interrupt */
 243 +#define FALCON_IRQ_GPTC_TC2B                   (INT_NUM_IM3_IRL0 + 19)
 244 +/* GPTC Timer/Counter 3A Interrupt */
 245 +#define FALCON_IRQ_GPTC_TC3A                   (INT_NUM_IM3_IRL0 + 20)
 246 +/* GPTC Timer/Counter 3B Interrupt */
 247 +#define FALCON_IRQ_GPTC_TC3B                   (INT_NUM_IM3_IRL0 + 21)
 248 +/* DFEV0, Channel 1 Transmit Interrupt */
 249 +#define FALCON_IRQ_DFEV0_2TX                   (INT_NUM_IM3_IRL0 + 26)
 250 +/* DFEV0, Channel 1 Receive Interrupt */
 251 +#define FALCON_IRQ_DFEV0_2RX                   (INT_NUM_IM3_IRL0 + 27)
 252 +/* DFEV0, Channel 1 General Purpose Interrupt */
 253 +#define FALCON_IRQ_DFEV0_2GP                   (INT_NUM_IM3_IRL0 + 28)
 254 +/* DFEV0, Channel 0 Transmit Interrupt */
 255 +#define FALCON_IRQ_DFEV0_1TX                   (INT_NUM_IM3_IRL0 + 29)
 256 +/* DFEV0, Channel 0 Receive Interrupt */
 257 +#define FALCON_IRQ_DFEV0_1RX                   (INT_NUM_IM3_IRL0 + 30)
 258 +/* DFEV0, Channel 0 General Purpose Interrupt */
 259 +#define FALCON_IRQ_DFEV0_1GP                   (INT_NUM_IM3_IRL0 + 31)
 260 +
 261 +/* ICTRLL 0 Error */
 262 +#define FALCON_IRQ_ICTRLL0_ERR                 (INT_NUM_IM4_IRL0 + 0)
 263 +/* ICTRLL 1 Error */
 264 +#define FALCON_IRQ_ICTRLL1_ERR                 (INT_NUM_IM4_IRL0 + 1)
 265 +/* ICTRLL 2 Error */
 266 +#define FALCON_IRQ_ICTRLL2_ERR                 (INT_NUM_IM4_IRL0 + 2)
 267 +/* ICTRLL 3 Error */
 268 +#define FALCON_IRQ_ICTRLL3_ERR                 (INT_NUM_IM4_IRL0 + 3)
 269 +/* OCTRLL 0 Error */
 270 +#define FALCON_IRQ_OCTRLL0_ERR                 (INT_NUM_IM4_IRL0 + 4)
 271 +/* OCTRLL 1 Error */
 272 +#define FALCON_IRQ_OCTRLL1_ERR                 (INT_NUM_IM4_IRL0 + 5)
 273 +/* OCTRLL 2 Error */
 274 +#define FALCON_IRQ_OCTRLL2_ERR                 (INT_NUM_IM4_IRL0 + 6)
 275 +/* OCTRLL 3 Error */
 276 +#define FALCON_IRQ_OCTRLL3_ERR                 (INT_NUM_IM4_IRL0 + 7)
 277 +/* ICTRLG Error */
 278 +#define FALCON_IRQ_ICTRLG_ERR                  (INT_NUM_IM4_IRL0 + 8)
 279 +/* OCTRLG Error */
 280 +#define FALCON_IRQ_OCTRLG_ERR                  (INT_NUM_IM4_IRL0 + 9)
 281 +/* IQM Error */
 282 +#define FALCON_IRQ_IQM_ERR                     (INT_NUM_IM4_IRL0 + 10)
 283 +/* FSQM Error */
 284 +#define FALCON_IRQ_FSQM_ERR                    (INT_NUM_IM4_IRL0 + 11)
 285 +/* TMU Error */
 286 +#define FALCON_IRQ_TMU_ERR                     (INT_NUM_IM4_IRL0 + 12)
 287 +/* MPS Status Interrupt #0 (VPE1 to VPE0) */
 288 +#define FALCON_IRQ_MPS_IR0                     (INT_NUM_IM4_IRL0 + 14)
 289 +/* MPS Status Interrupt #1 (VPE1 to VPE0) */
 290 +#define FALCON_IRQ_MPS_IR1                     (INT_NUM_IM4_IRL0 + 15)
 291 +/* MPS Status Interrupt #2 (VPE1 to VPE0) */
 292 +#define FALCON_IRQ_MPS_IR2                     (INT_NUM_IM4_IRL0 + 16)
 293 +/* MPS Status Interrupt #3 (VPE1 to VPE0) */
 294 +#define FALCON_IRQ_MPS_IR3                     (INT_NUM_IM4_IRL0 + 17)
 295 +/* MPS Status Interrupt #4 (VPE1 to VPE0) */
 296 +#define FALCON_IRQ_MPS_IR4                     (INT_NUM_IM4_IRL0 + 18)
 297 +/* MPS Status Interrupt #5 (VPE1 to VPE0) */
 298 +#define FALCON_IRQ_MPS_IR5                     (INT_NUM_IM4_IRL0 + 19)
 299 +/* MPS Status Interrupt #6 (VPE1 to VPE0) */
 300 +#define FALCON_IRQ_MPS_IR6                     (INT_NUM_IM4_IRL0 + 20)
 301 +/* MPS Status Interrupt #7 (VPE1 to VPE0) */
 302 +#define FALCON_IRQ_MPS_IR7                     (INT_NUM_IM4_IRL0 + 21)
 303 +/* MPS Status Interrupt #8 (VPE1 to VPE0) */
 304 +#define FALCON_IRQ_MPS_IR8                     (INT_NUM_IM4_IRL0 + 22)
 305 +/* VPE0 Exception Level Flag Interrupt */
 306 +#define FALCON_IRQ_VPE0_EXL                    (INT_NUM_IM4_IRL0 + 29)
 307 +/* VPE0 Error Level Flag Interrupt */
 308 +#define FALCON_IRQ_VPE0_ERL                    (INT_NUM_IM4_IRL0 + 30)
 309 +/* VPE0 Performance Monitoring Counter Interrupt */
 310 +#define FALCON_IRQ_VPE0_PMCIR                  (INT_NUM_IM4_IRL0 + 31)
 311 +
 312 +#endif /* _FALCON_IRQ__ */
 313 diff --git a/arch/mips/include/asm/mach-lantiq/falcon/irq.h b/arch/mips/include/asm/mach-lantiq/falcon/irq.h
 314 new file mode 100644
 315 index 0000000..2caccd9
 316 --- /dev/null
 317 +++ b/arch/mips/include/asm/mach-lantiq/falcon/irq.h
 318 @@ -0,0 +1,18 @@
 319 +/*
 320 + *  This program is free software; you can redistribute it and/or modify it
 321 + *  under the terms of the GNU General Public License version 2 as published
 322 + *  by the Free Software Foundation.
 323 + *
 324 + *  Copyright (C) 2011 Thomas Langer <thomas.langer@lantiq.com>
 325 + */
 326 +
 327 +#ifndef __FALCON_IRQ_H
 328 +#define __FALCON_IRQ_H
 329 +
 330 +#include <falcon_irq.h>
 331 +
 332 +#define NR_IRQS 328
 333 +
 334 +#include_next <irq.h>
 335 +
 336 +#endif
 337 diff --git a/arch/mips/include/asm/mach-lantiq/falcon/lantiq_soc.h b/arch/mips/include/asm/mach-lantiq/falcon/lantiq_soc.h
 338 new file mode 100644
 339 index 0000000..c092531
 340 --- /dev/null
 341 +++ b/arch/mips/include/asm/mach-lantiq/falcon/lantiq_soc.h
 342 @@ -0,0 +1,140 @@
 343 +/*
 344 + * This program is free software; you can redistribute it and/or modify it
 345 + * under the terms of the GNU General Public License version 2 as published
 346 + * by the Free Software Foundation.
 347 + *
 348 + * Copyright (C) 2010 John Crispin <blogic@openwrt.org>
 349 + */
 350 +
 351 +#ifndef _LTQ_FALCON_H__
 352 +#define _LTQ_FALCON_H__
 353 +
 354 +#ifdef CONFIG_SOC_FALCON
 355 +
 356 +#include <lantiq.h>
 357 +
 358 +/* Chip IDs */
 359 +#define SOC_ID_FALCON          0x01B8
 360 +
 361 +/* SoC Types */
 362 +#define SOC_TYPE_FALCON                0x01
 363 +
 364 +/* ASC0/1 - serial port */
 365 +#define LTQ_ASC0_BASE_ADDR     0x1E100C00
 366 +#define LTQ_ASC1_BASE_ADDR     0x1E100B00
 367 +#define LTQ_ASC_SIZE           0x100
 368 +
 369 +#define LTQ_ASC_TIR(x)          (INT_NUM_IM3_IRL0 + (x * 8))
 370 +#define LTQ_ASC_RIR(x)          (INT_NUM_IM3_IRL0 + (x * 8) + 1)
 371 +#define LTQ_ASC_EIR(x)          (INT_NUM_IM3_IRL0 + (x * 8) + 2)
 372 +
 373 +/* during early_printk no ioremap possible at this early stage
 374 +   lets use KSEG1 instead  */
 375 +#define LTQ_EARLY_ASC          KSEG1ADDR(LTQ_ASC0_BASE_ADDR)
 376 +
 377 +/* ICU - interrupt control unit */
 378 +#define LTQ_ICU_BASE_ADDR      0x1F880200
 379 +#define LTQ_ICU_SIZE           0x100
 380 +
 381 +/* WDT */
 382 +#define LTQ_WDT_BASE_ADDR      0x1F8803F0
 383 +#define LTQ_WDT_SIZE           0x10
 384 +
 385 +#define LTQ_RST_CAUSE_WDTRST   0x0002
 386 +
 387 +/* EBU - external bus unit */
 388 +#define LTQ_EBU_BASE_ADDR       0x18000000
 389 +#define LTQ_EBU_SIZE            0x0100
 390 +
 391 +#define LTQ_EBU_MODCON  0x000C
 392 +
 393 +/* GPIO */
 394 +#define LTQ_GPIO0_BASE_ADDR     0x1D810000
 395 +#define LTQ_GPIO0_SIZE          0x0080
 396 +#define LTQ_GPIO1_BASE_ADDR     0x1E800100
 397 +#define LTQ_GPIO1_SIZE          0x0080
 398 +#define LTQ_GPIO2_BASE_ADDR     0x1D810100
 399 +#define LTQ_GPIO2_SIZE          0x0080
 400 +#define LTQ_GPIO3_BASE_ADDR     0x1E800200
 401 +#define LTQ_GPIO3_SIZE          0x0080
 402 +#define LTQ_GPIO4_BASE_ADDR     0x1E800300
 403 +#define LTQ_GPIO4_SIZE          0x0080
 404 +#define LTQ_PADCTRL0_BASE_ADDR  0x1DB01000
 405 +#define LTQ_PADCTRL0_SIZE       0x0100
 406 +#define LTQ_PADCTRL1_BASE_ADDR  0x1E800400
 407 +#define LTQ_PADCTRL1_SIZE       0x0100
 408 +#define LTQ_PADCTRL2_BASE_ADDR  0x1DB02000
 409 +#define LTQ_PADCTRL2_SIZE       0x0100
 410 +#define LTQ_PADCTRL3_BASE_ADDR  0x1E800500
 411 +#define LTQ_PADCTRL3_SIZE       0x0100
 412 +#define LTQ_PADCTRL4_BASE_ADDR  0x1E800600
 413 +#define LTQ_PADCTRL4_SIZE       0x0100
 414 +
 415 +/* CHIP ID */
 416 +#define LTQ_STATUS_BASE_ADDR   0x1E802000
 417 +
 418 +#define LTQ_FALCON_CHIPID      ((u32 *)(KSEG1 + LTQ_STATUS_BASE_ADDR + 0x0c))
 419 +#define LTQ_FALCON_CHIPCONF    ((u32 *)(KSEG1 + LTQ_STATUS_BASE_ADDR + 0x40))
 420 +
 421 +/* SYSCTL - start/stop/restart/configure/... different parts of the Soc */
 422 +#define LTQ_SYS1_BASE_ADDR      0x1EF00000
 423 +#define LTQ_SYS1_SIZE           0x0100
 424 +#define LTQ_STATUS_BASE_ADDR   0x1E802000
 425 +#define LTQ_STATUS_SIZE                0x0080
 426 +#define LTQ_SYS_ETH_BASE_ADDR  0x1DB00000
 427 +#define LTQ_SYS_ETH_SIZE       0x0100
 428 +#define LTQ_SYS_GPE_BASE_ADDR  0x1D700000
 429 +#define LTQ_SYS_GPE_SIZE       0x0100
 430 +
 431 +#define SYSCTL_SYS1            0
 432 +#define SYSCTL_SYSETH          1
 433 +#define SYSCTL_SYSGPE          2
 434 +
 435 +/* Activation Status Register */
 436 +#define ACTS_ASC1_ACT  0x00000800
 437 +#define ACTS_P0                0x00010000
 438 +#define ACTS_P1                0x00010000
 439 +#define ACTS_P2                0x00020000
 440 +#define ACTS_P3                0x00020000
 441 +#define ACTS_P4                0x00040000
 442 +#define ACTS_PADCTRL0  0x00100000
 443 +#define ACTS_PADCTRL1  0x00100000
 444 +#define ACTS_PADCTRL2  0x00200000
 445 +#define ACTS_PADCTRL3  0x00200000
 446 +#define ACTS_PADCTRL4  0x00400000
 447 +
 448 +extern void ltq_sysctl_activate(int module, unsigned int mask);
 449 +extern void ltq_sysctl_deactivate(int module, unsigned int mask);
 450 +extern void ltq_sysctl_clken(int module, unsigned int mask);
 451 +extern void ltq_sysctl_clkdis(int module, unsigned int mask);
 452 +extern void ltq_sysctl_reboot(int module, unsigned int mask);
 453 +extern int ltq_gpe_is_activated(unsigned int mask);
 454 +
 455 +/* global register ranges */
 456 +extern __iomem void *ltq_ebu_membase;
 457 +extern __iomem void *ltq_sys1_membase;
 458 +#define ltq_ebu_w32(x, y)      ltq_w32((x), ltq_ebu_membase + (y))
 459 +#define ltq_ebu_r32(x)         ltq_r32(ltq_ebu_membase + (x))
 460 +#define ltq_ebu_w32_mask(clear, set, reg)   \
 461 +       ltq_ebu_w32((ltq_ebu_r32(reg) & ~(clear)) | (set), reg)
 462 +
 463 +#define ltq_sys1_w32(x, y)     ltq_w32((x), ltq_sys1_membase + (y))
 464 +#define ltq_sys1_r32(x)                ltq_r32(ltq_sys1_membase + (x))
 465 +#define ltq_sys1_w32_mask(clear, set, reg)   \
 466 +       ltq_sys1_w32((ltq_sys1_r32(reg) & ~(clear)) | (set), reg)
 467 +
 468 +/* gpio_request wrapper to help configure the pin */
 469 +extern int ltq_gpio_request(unsigned int pin, unsigned int val,
 470 +                               unsigned int dir, const char *name);
 471 +extern int ltq_gpio_mux_set(unsigned int pin, unsigned int mux);
 472 +
 473 +/* to keep the irq code generic we need to define these to 0 as falcon
 474 +   has no EIU/EBU */
 475 +#define LTQ_EIU_BASE_ADDR      0
 476 +#define LTQ_EBU_PCC_ISTAT      0
 477 +
 478 +#define ltq_is_ar9()   0
 479 +#define ltq_is_vr9()   0
 480 +
 481 +#endif /* CONFIG_SOC_FALCON */
 482 +#endif /* _LTQ_XWAY_H__ */
 483 diff --git a/arch/mips/include/asm/mach-lantiq/lantiq.h b/arch/mips/include/asm/mach-lantiq/lantiq.h
 484 index 66d7300..188de0f 100644
 485 --- a/arch/mips/include/asm/mach-lantiq/lantiq.h
 486 +++ b/arch/mips/include/asm/mach-lantiq/lantiq.h
 487 @@ -25,6 +25,7 @@ extern unsigned int ltq_get_soc_type(void);
 488  /* clock speeds */
 489  #define CLOCK_60M      60000000
 490  #define CLOCK_83M      83333333
 491 +#define CLOCK_100M     100000000
 492  #define CLOCK_111M     111111111
 493  #define CLOCK_133M     133333333
 494  #define CLOCK_167M     166666667
 495 diff --git a/arch/mips/lantiq/Kconfig b/arch/mips/lantiq/Kconfig
 496 index 3fccf21..cb6b39f 100644
 497 --- a/arch/mips/lantiq/Kconfig
 498 +++ b/arch/mips/lantiq/Kconfig
 499 @@ -16,8 +16,12 @@ config SOC_XWAY
 500         bool "XWAY"
 501         select SOC_TYPE_XWAY
 502         select HW_HAS_PCI
 503 +
 504 +config SOC_FALCON
 505 +       bool "FALCON"
 506  endchoice
 507
 508  source "arch/mips/lantiq/xway/Kconfig"
 509 +source "arch/mips/lantiq/falcon/Kconfig"
 510
 511  endif
 512 diff --git a/arch/mips/lantiq/Makefile b/arch/mips/lantiq/Makefile
 513 index e5dae0e..7e9c69e 100644
 514 --- a/arch/mips/lantiq/Makefile
 515 +++ b/arch/mips/lantiq/Makefile
 516 @@ -9,3 +9,4 @@ obj-y := irq.o setup.o clk.o prom.o devices.o
 517  obj-$(CONFIG_EARLY_PRINTK) += early_printk.o
 518
 519  obj-$(CONFIG_SOC_TYPE_XWAY) += xway/
 520 +obj-$(CONFIG_SOC_FALCON) += falcon/
 521 diff --git a/arch/mips/lantiq/Platform b/arch/mips/lantiq/Platform
 522 index f3dff05..b3ec498 100644
 523 --- a/arch/mips/lantiq/Platform
 524 +++ b/arch/mips/lantiq/Platform
 525 @@ -6,3 +6,4 @@ platform-$(CONFIG_LANTIQ)       += lantiq/
 526  cflags-$(CONFIG_LANTIQ)                += -I$(srctree)/arch/mips/include/asm/mach-lantiq
 527  load-$(CONFIG_LANTIQ)          = 0xffffffff80002000
 528  cflags-$(CONFIG_SOC_TYPE_XWAY) += -I$(srctree)/arch/mips/include/asm/mach-lantiq/xway
 529 +cflags-$(CONFIG_SOC_FALCON)    += -I$(srctree)/arch/mips/include/asm/mach-lantiq/falcon
 530 diff --git a/arch/mips/lantiq/falcon/Makefile b/arch/mips/lantiq/falcon/Makefile
 531 new file mode 100644
 532 index 0000000..e9c7455
 533 --- /dev/null
 534 +++ b/arch/mips/lantiq/falcon/Makefile
 535 @@ -0,0 +1 @@
 536 +obj-y := clk.o prom.o reset.o sysctrl.o devices.o
 537 diff --git a/arch/mips/lantiq/falcon/clk.c b/arch/mips/lantiq/falcon/clk.c
 538 new file mode 100644
 539 index 0000000..1a550ea
 540 --- /dev/null
 541 +++ b/arch/mips/lantiq/falcon/clk.c
 542 @@ -0,0 +1,44 @@
 543 +/*
 544 + * This program is free software; you can redistribute it and/or modify it
 545 + * under the terms of the GNU General Public License version 2 as published
 546 + * by the Free Software Foundation.
 547 + *
 548 + * Copyright (C) 2011 Thomas Langer <thomas.langer@lantiq.com>
 549 + * Copyright (C) 2011 John Crispin <blogic@openwrt.org>
 550 + */
 551 +
 552 +#include <linux/ioport.h>
 553 +#include <linux/module.h>
 554 +
 555 +#include <lantiq_soc.h>
 556 +
 557 +#include "devices.h"
 558 +
 559 +/* CPU0 Clock Control Register */
 560 +#define LTQ_SYS1_CPU0CC                0x0040
 561 +/* clock divider bit */
 562 +#define LTQ_CPU0CC_CPUDIV      0x0001
 563 +
 564 +unsigned int
 565 +ltq_get_io_region_clock(void)
 566 +{
 567 +       return CLOCK_200M;
 568 +}
 569 +EXPORT_SYMBOL(ltq_get_io_region_clock);
 570 +
 571 +unsigned int
 572 +ltq_get_cpu_hz(void)
 573 +{
 574 +       if (ltq_sys1_r32(LTQ_SYS1_CPU0CC) & LTQ_CPU0CC_CPUDIV)
 575 +               return CLOCK_200M;
 576 +       else
 577 +               return CLOCK_400M;
 578 +}
 579 +EXPORT_SYMBOL(ltq_get_cpu_hz);
 580 +
 581 +unsigned int
 582 +ltq_get_fpi_hz(void)
 583 +{
 584 +       return CLOCK_100M;
 585 +}
 586 +EXPORT_SYMBOL(ltq_get_fpi_hz);
 587 diff --git a/arch/mips/lantiq/falcon/devices.c b/arch/mips/lantiq/falcon/devices.c
 588 new file mode 100644
 589 index 0000000..c4606f2
 590 --- /dev/null
 591 +++ b/arch/mips/lantiq/falcon/devices.c
 592 @@ -0,0 +1,87 @@
 593 +/*
 594 + * This program is free software; you can redistribute it and/or modify it
 595 + * under the terms of the GNU General Public License version 2 as published
 596 + * by the Free Software Foundation.
 597 + *
 598 + * Copyright (C) 2011 Thomas Langer <thomas.langer@lantiq.com>
 599 + * Copyright (C) 2011 John Crispin <blogic@openwrt.org>
 600 + */
 601 +
 602 +#include <linux/platform_device.h>
 603 +#include <linux/mtd/nand.h>
 604 +
 605 +#include <lantiq_soc.h>
 606 +
 607 +#include "devices.h"
 608 +
 609 +/* nand flash */
 610 +/* address lines used for NAND control signals */
 611 +#define NAND_ADDR_ALE          0x10000
 612 +#define NAND_ADDR_CLE          0x20000
 613 +/* Ready/Busy Status */
 614 +#define MODCON_STS             0x0002
 615 +/* Ready/Busy Status Edge */
 616 +#define MODCON_STSEDGE         0x0004
 617 +
 618 +static const char *part_probes[] = { "cmdlinepart", NULL };
 619 +
 620 +static int
 621 +falcon_nand_ready(struct mtd_info *mtd)
 622 +{
 623 +       u32 modcon = ltq_ebu_r32(LTQ_EBU_MODCON);
 624 +
 625 +       return (((modcon & (MODCON_STS | MODCON_STSEDGE)) ==
 626 +                                               (MODCON_STS | MODCON_STSEDGE)));
 627 +}
 628 +
 629 +static void
 630 +falcon_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
 631 +{
 632 +       struct nand_chip *this = mtd->priv;
 633 +       unsigned long nandaddr = (unsigned long) this->IO_ADDR_W;
 634 +
 635 +       if (ctrl & NAND_CTRL_CHANGE) {
 636 +               nandaddr &= ~(NAND_ADDR_ALE | NAND_ADDR_CLE);
 637 +
 638 +               if (ctrl & NAND_CLE)
 639 +                       nandaddr |= NAND_ADDR_CLE;
 640 +               if (ctrl & NAND_ALE)
 641 +                       nandaddr |= NAND_ADDR_ALE;
 642 +
 643 +               this->IO_ADDR_W = (void __iomem *) nandaddr;
 644 +       }
 645 +
 646 +       if (cmd != NAND_CMD_NONE)
 647 +               writeb(cmd, this->IO_ADDR_W);
 648 +}
 649 +
 650 +static struct platform_nand_data falcon_flash_nand_data = {
 651 +       .chip = {
 652 +               .nr_chips               = 1,
 653 +               .chip_delay             = 25,
 654 +               .part_probe_types       = part_probes,
 655 +       },
 656 +       .ctrl = {
 657 +               .cmd_ctrl               = falcon_hwcontrol,
 658 +               .dev_ready              = falcon_nand_ready,
 659 +       }
 660 +};
 661 +
 662 +static struct resource ltq_nand_res =
 663 +       MEM_RES("nand", LTQ_FLASH_START, LTQ_FLASH_MAX);
 664 +
 665 +static struct platform_device ltq_flash_nand = {
 666 +       .name           = "gen_nand",
 667 +       .id             = -1,
 668 +       .num_resources  = 1,
 669 +       .resource       = &ltq_nand_res,
 670 +       .dev            = {
 671 +               .platform_data = &falcon_flash_nand_data,
 672 +       },
 673 +};
 674 +
 675 +void __init
 676 +falcon_register_nand(void)
 677 +{
 678 +       platform_device_register(&ltq_flash_nand);
 679 +}
 680 diff --git a/arch/mips/lantiq/falcon/devices.h b/arch/mips/lantiq/falcon/devices.h
 681 new file mode 100644
 682 index 0000000..e802a7c
 683 --- /dev/null
 684 +++ b/arch/mips/lantiq/falcon/devices.h
 685 @@ -0,0 +1,18 @@
 686 +/*
 687 + * This program is free software; you can redistribute it and/or modify
 688 + * it under the terms of the GNU General Public License as published by
 689 + * the Free Software Foundation; either version 2 of the License, or
 690 + * (at your option) any later version.
 691 + *
 692 + * Copyright (C) 2011 Thomas Langer <thomas.langer@lantiq.com>
 693 + * Copyright (C) 2011 John Crispin <blogic@openwrt.org>
 694 + */
 695 +
 696 +#ifndef _FALCON_DEVICES_H__
 697 +#define _FALCON_DEVICES_H__
 698 +
 699 +#include "../devices.h"
 700 +
 701 +extern void falcon_register_nand(void);
 702 +
 703 +#endif
 704 diff --git a/arch/mips/lantiq/falcon/prom.c b/arch/mips/lantiq/falcon/prom.c
 705 new file mode 100644
 706 index 0000000..89367c4
 707 --- /dev/null
 708 +++ b/arch/mips/lantiq/falcon/prom.c
 709 @@ -0,0 +1,72 @@
 710 +/*
 711 + * This program is free software; you can redistribute it and/or modify it
 712 + * under the terms of the GNU General Public License version 2 as published
 713 + * by the Free Software Foundation.
 714 + *
 715 + * Copyright (C) 2011 Thomas Langer <thomas.langer@lantiq.com>
 716 + * Copyright (C) 2011 John Crispin <blogic@openwrt.org>
 717 + */
 718 +
 719 +#include <lantiq_soc.h>
 720 +
 721 +#include "devices.h"
 722 +
 723 +#include "../prom.h"
 724 +
 725 +#define SOC_FALCON             "Falcon"
 726 +
 727 +#define PART_SHIFT     12
 728 +#define PART_MASK      0x0FFFF000
 729 +#define REV_SHIFT      28
 730 +#define REV_MASK       0xF0000000
 731 +#define SREV_SHIFT     22
 732 +#define SREV_MASK      0x03C00000
 733 +
 734 +#define MUXC_SIF_RX_PIN                112
 735 +#define MUXC_SIF_TX_PIN                113
 736 +
 737 +/* this parameter allows us enable/disable asc1 via commandline */
 738 +static int register_asc1;
 739 +static int __init
 740 +ltq_parse_asc1(char *p)
 741 +{
 742 +       register_asc1 = 1;
 743 +       return 0;
 744 +}
 745 +__setup("use_asc1", ltq_parse_asc1);
 746 +
 747 +void __init
 748 +ltq_soc_setup(void)
 749 +{
 750 +       ltq_register_asc(0);
 751 +       ltq_register_wdt();
 752 +       falcon_register_gpio();
 753 +       if (register_asc1) {
 754 +               ltq_register_asc(1);
 755 +               if (ltq_gpio_request(MUXC_SIF_RX_PIN, 3, 0, "asc1-rx"))
 756 +                       pr_err("failed to request asc1-rx");
 757 +               if (ltq_gpio_request(MUXC_SIF_TX_PIN, 3, 1, "asc1-tx"))
 758 +                       pr_err("failed to request asc1-tx");
 759 +               ltq_sysctl_activate(SYSCTL_SYS1, ACTS_ASC1_ACT);
 760 +       }
 761 +}
 762 +
 763 +void __init
 764 +ltq_soc_detect(struct ltq_soc_info *i)
 765 +{
 766 +       i->partnum = (ltq_r32(LTQ_FALCON_CHIPID) & PART_MASK) >> PART_SHIFT;
 767 +       i->rev = (ltq_r32(LTQ_FALCON_CHIPID) & REV_MASK) >> REV_SHIFT;
 768 +       i->srev = (ltq_r32(LTQ_FALCON_CHIPCONF) & SREV_MASK) >> SREV_SHIFT;
 769 +       sprintf(i->rev_type, "%c%d%d", (i->srev & 0x4) ? ('B') : ('A'),
 770 +               i->rev & 0x7, i->srev & 0x3);
 771 +       switch (i->partnum) {
 772 +       case SOC_ID_FALCON:
 773 +               i->name = SOC_FALCON;
 774 +               i->type = SOC_TYPE_FALCON;
 775 +               break;
 776 +
 777 +       default:
 778 +               unreachable();
 779 +               break;
 780 +       }
 781 +}
 782 diff --git a/arch/mips/lantiq/falcon/reset.c b/arch/mips/lantiq/falcon/reset.c
 783 new file mode 100644
 784 index 0000000..d3289ca
 785 --- /dev/null
 786 +++ b/arch/mips/lantiq/falcon/reset.c
 787 @@ -0,0 +1,87 @@
 788 +/*
 789 + * This program is free software; you can redistribute it and/or modify it
 790 + * under the terms of the GNU General Public License version 2 as published
 791 + * by the Free Software Foundation.
 792 + *
 793 + * Copyright (C) 2011 Thomas Langer <thomas.langer@lantiq.com>
 794 + * Copyright (C) 2011 John Crispin <blogic@openwrt.org>
 795 + */
 796 +
 797 +#include <linux/init.h>
 798 +#include <linux/io.h>
 799 +#include <linux/pm.h>
 800 +#include <asm/reboot.h>
 801 +#include <linux/module.h>
 802 +
 803 +#include <lantiq_soc.h>
 804 +
 805 +/* CPU0 Reset Source Register */
 806 +#define LTQ_SYS1_CPU0RS                0x0040
 807 +/* reset cause mask */
 808 +#define LTQ_CPU0RS_MASK                0x0003
 809 +
 810 +int
 811 +ltq_reset_cause(void)
 812 +{
 813 +       return ltq_sys1_r32(LTQ_SYS1_CPU0RS) & LTQ_CPU0RS_MASK;
 814 +}
 815 +EXPORT_SYMBOL_GPL(ltq_reset_cause);
 816 +
 817 +#define BOOT_REG_BASE  (KSEG1 | 0x1F200000)
 818 +#define BOOT_PW1_REG   (BOOT_REG_BASE | 0x20)
 819 +#define BOOT_PW2_REG   (BOOT_REG_BASE | 0x24)
 820 +#define BOOT_PW1       0x4C545100
 821 +#define BOOT_PW2       0x0051544C
 822 +
 823 +#define WDT_REG_BASE   (KSEG1 | 0x1F8803F0)
 824 +#define WDT_PW1                0x00BE0000
 825 +#define WDT_PW2                0x00DC0000
 826 +
 827 +static void
 828 +ltq_machine_restart(char *command)
 829 +{
 830 +       pr_notice("System restart\n");
 831 +       local_irq_disable();
 832 +
 833 +       /* reboot magic */
 834 +       ltq_w32(BOOT_PW1, (void *)BOOT_PW1_REG); /* 'LTQ\0' */
 835 +       ltq_w32(BOOT_PW2, (void *)BOOT_PW2_REG); /* '\0QTL' */
 836 +       ltq_w32(0, (void *)BOOT_REG_BASE); /* reset Bootreg RVEC */
 837 +
 838 +       /* watchdog magic */
 839 +       ltq_w32(WDT_PW1, (void *)WDT_REG_BASE);
 840 +       ltq_w32(WDT_PW2 |
 841 +               (0x3 << 26) | /* PWL */
 842 +               (0x2 << 24) | /* CLKDIV */
 843 +               (0x1 << 31) | /* enable */
 844 +               (1), /* reload */
 845 +               (void *)WDT_REG_BASE);
 846 +       unreachable();
 847 +}
 848 +
 849 +static void
 850 +ltq_machine_halt(void)
 851 +{
 852 +       pr_notice("System halted.\n");
 853 +       local_irq_disable();
 854 +       unreachable();
 855 +}
 856 +
 857 +static void
 858 +ltq_machine_power_off(void)
 859 +{
 860 +       pr_notice("Please turn off the power now.\n");
 861 +       local_irq_disable();
 862 +       unreachable();
 863 +}
 864 +
 865 +static int __init
 866 +mips_reboot_setup(void)
 867 +{
 868 +       _machine_restart = ltq_machine_restart;
 869 +       _machine_halt = ltq_machine_halt;
 870 +       pm_power_off = ltq_machine_power_off;
 871 +       return 0;
 872 +}
 873 +
 874 +arch_initcall(mips_reboot_setup);
 875 diff --git a/arch/mips/lantiq/falcon/sysctrl.c b/arch/mips/lantiq/falcon/sysctrl.c
 876 new file mode 100644
 877 index 0000000..d20b46b
 878 --- /dev/null
 879 +++ b/arch/mips/lantiq/falcon/sysctrl.c
 880 @@ -0,0 +1,181 @@
 881 +/*
 882 + * This program is free software; you can redistribute it and/or modify it
 883 + * under the terms of the GNU General Public License version 2 as published
 884 + * by the Free Software Foundation.
 885 + *
 886 + * Copyright (C) 2011 Thomas Langer <thomas.langer@lantiq.com>
 887 + * Copyright (C) 2011 John Crispin <blogic@openwrt.org>
 888 + */
 889 +
 890 +#include <linux/ioport.h>
 891 +#include <asm/delay.h>
 892 +
 893 +#include <lantiq_soc.h>
 894 +
 895 +#include "devices.h"
 896 +
 897 +/* infrastructure control register */
 898 +#define SYS1_INFRAC            0x00bc
 899 +/* Configuration fuses for drivers and pll */
 900 +#define STATUS_CONFIG          0x0040
 901 +
 902 +/* GPE frequency selection */
 903 +#define GPPC_OFFSET            24
 904 +#define GPEFREQ_MASK           0x00000C0
 905 +#define GPEFREQ_OFFSET         10
 906 +/* Clock status register */
 907 +#define LTQ_SYSCTL_CLKS                0x0000
 908 +/* Clock enable register */
 909 +#define LTQ_SYSCTL_CLKEN       0x0004
 910 +/* Clock clear register */
 911 +#define LTQ_SYSCTL_CLKCLR      0x0008
 912 +/* Activation Status Register */
 913 +#define LTQ_SYSCTL_ACTS                0x0020
 914 +/* Activation Register */
 915 +#define LTQ_SYSCTL_ACT         0x0024
 916 +/* Deactivation Register */
 917 +#define LTQ_SYSCTL_DEACT       0x0028
 918 +/* reboot Register */
 919 +#define LTQ_SYSCTL_RBT         0x002c
 920 +
 921 +static struct resource ltq_sysctl_res[] = {
 922 +       MEM_RES("sys1", LTQ_SYS1_BASE_ADDR, LTQ_SYS1_SIZE),
 923 +       MEM_RES("syseth", LTQ_SYS_ETH_BASE_ADDR, LTQ_SYS_ETH_SIZE),
 924 +       MEM_RES("sysgpe", LTQ_SYS_GPE_BASE_ADDR, LTQ_SYS_GPE_SIZE),
 925 +};
 926 +
 927 +static struct resource ltq_status_res =
 928 +       MEM_RES("status", LTQ_STATUS_BASE_ADDR, LTQ_STATUS_SIZE);
 929 +static struct resource ltq_ebu_res =
 930 +       MEM_RES("ebu", LTQ_EBU_BASE_ADDR, LTQ_EBU_SIZE);
 931 +
 932 +static void __iomem *ltq_sysctl[3];
 933 +static void __iomem *ltq_status_membase;
 934 +void __iomem *ltq_sys1_membase;
 935 +void __iomem *ltq_ebu_membase;
 936 +
 937 +#define ltq_reg_w32(m, x, y)   ltq_w32((x), ltq_sysctl[m] + (y))
 938 +#define ltq_reg_r32(m, x)      ltq_r32(ltq_sysctl[m] + (x))
 939 +#define ltq_reg_w32_mask(m, clear, set, reg)   \
 940 +               ltq_reg_w32(m, (ltq_reg_r32(m, reg) & ~(clear)) | (set), reg)
 941 +
 942 +#define ltq_status_w32(x, y)   ltq_w32((x), ltq_status_membase + (y))
 943 +#define ltq_status_r32(x)      ltq_r32(ltq_status_membase + (x))
 944 +
 945 +static inline void
 946 +ltq_sysctl_wait(int module, unsigned int mask, unsigned int test)
 947 +{
 948 +       int err = 1000000;
 949 +
 950 +       do {} while (--err && ((ltq_reg_r32(module, LTQ_SYSCTL_ACTS)
 951 +                                       & mask) != test));
 952 +       if (!err)
 953 +               pr_err("module de/activation failed %d %08X %08X\n",
 954 +                                                       module, mask, test);
 955 +}
 956 +
 957 +void
 958 +ltq_sysctl_activate(int module, unsigned int mask)
 959 +{
 960 +       if (module > SYSCTL_SYSGPE)
 961 +               return;
 962 +
 963 +       ltq_reg_w32(module, mask, LTQ_SYSCTL_CLKEN);
 964 +       ltq_reg_w32(module, mask, LTQ_SYSCTL_ACT);
 965 +       ltq_sysctl_wait(module, mask, mask);
 966 +}
 967 +EXPORT_SYMBOL(ltq_sysctl_activate);
 968 +
 969 +void
 970 +ltq_sysctl_deactivate(int module, unsigned int mask)
 971 +{
 972 +       if (module > SYSCTL_SYSGPE)
 973 +               return;
 974 +
 975 +       ltq_reg_w32(module, mask, LTQ_SYSCTL_CLKCLR);
 976 +       ltq_reg_w32(module, mask, LTQ_SYSCTL_DEACT);
 977 +       ltq_sysctl_wait(module, mask, 0);
 978 +}
 979 +EXPORT_SYMBOL(ltq_sysctl_deactivate);
 980 +
 981 +void
 982 +ltq_sysctl_clken(int module, unsigned int mask)
 983 +{
 984 +       if (module > SYSCTL_SYSGPE)
 985 +               return;
 986 +
 987 +       ltq_reg_w32(module, mask, LTQ_SYSCTL_CLKEN);
 988 +       ltq_sysctl_wait(module, mask, mask);
 989 +}
 990 +EXPORT_SYMBOL(ltq_sysctl_clken);
 991 +
 992 +void
 993 +ltq_sysctl_clkdis(int module, unsigned int mask)
 994 +{
 995 +       if (module > SYSCTL_SYSGPE)
 996 +               return;
 997 +
 998 +       ltq_reg_w32(module, mask, LTQ_SYSCTL_CLKCLR);
 999 +       ltq_sysctl_wait(module, mask, 0);
1000 +}
1001 +EXPORT_SYMBOL(ltq_sysctl_clkdis);
1002 +
1003 +void
1004 +ltq_sysctl_reboot(int module, unsigned int mask)
1005 +{
1006 +       unsigned int act;
1007 +
1008 +       if (module > SYSCTL_SYSGPE)
1009 +               return;
1010 +
1011 +       act = ltq_reg_r32(module, LTQ_SYSCTL_ACT);
1012 +       if ((~act & mask) != 0)
1013 +               ltq_sysctl_activate(module, ~act & mask);
1014 +       ltq_reg_w32(module, act & mask, LTQ_SYSCTL_RBT);
1015 +       ltq_sysctl_wait(module, mask, mask);
1016 +}
1017 +EXPORT_SYMBOL(ltq_sysctl_reboot);
1018 +
1019 +/* enable the ONU core */
1020 +static void
1021 +ltq_gpe_enable(void)
1022 +{
1023 +       unsigned int freq;
1024 +       unsigned int status;
1025 +
1026 +       /* if if the clock is already enabled */
1027 +       status = ltq_reg_r32(SYSCTL_SYS1, SYS1_INFRAC);
1028 +       if (status & (1 << (GPPC_OFFSET + 1)))
1029 +               return;
1030 +
1031 +       if (ltq_status_r32(STATUS_CONFIG) == 0)
1032 +               freq = 1; /* use 625MHz on unfused chip */
1033 +       else
1034 +               freq = (ltq_status_r32(STATUS_CONFIG) &
1035 +                       GPEFREQ_MASK) >>
1036 +                       GPEFREQ_OFFSET;
1037 +
1038 +       /* apply new frequency */
1039 +       ltq_reg_w32_mask(SYSCTL_SYS1, 7 << (GPPC_OFFSET + 1),
1040 +               freq << (GPPC_OFFSET + 2) , SYS1_INFRAC);
1041 +       udelay(1);
1042 +
1043 +       /* enable new frequency */
1044 +       ltq_reg_w32_mask(SYSCTL_SYS1, 0, 1 << (GPPC_OFFSET + 1), SYS1_INFRAC);
1045 +       udelay(1);
1046 +}
1047 +
1048 +void __init
1049 +ltq_soc_init(void)
1050 +{
1051 +       int i;
1052 +
1053 +       for (i = 0; i < 3; i++)
1054 +               ltq_sysctl[i] = ltq_remap_resource(&ltq_sysctl_res[i]);
1055 +
1056 +       ltq_sys1_membase = ltq_sysctl[0];
1057 +       ltq_status_membase = ltq_remap_resource(&ltq_status_res);
1058 +       ltq_ebu_membase = ltq_remap_resource(&ltq_ebu_res);
1059 +
1060 +       ltq_gpe_enable();
1061 +}
1062 --
1063 1.7.5.4
1064