target/linux/lantiq/patches-2.6.32/0009-SERIAL-Lantiq-Add-driver-for-MIPS-Lantiq-SOCs.patch

   1 From 1d2b44b1afa3ef081cd817dbf947d48eb8f5d21a Mon Sep 17 00:00:00 2001
   2 From: John Crispin <blogic@openwrt.org>
   3 Date: Tue, 5 Apr 2011 14:10:57 +0200
   4 Subject: [PATCH 09/13] SERIAL: Lantiq: Add driver for MIPS Lantiq SOCs.
   5
   6 Signed-off-by: John Crispin <blogic@openwrt.org>
   7 Signed-off-by: Ralph Hempel <ralph.hempel@lantiq.com>
   8 Signed-off-by: Felix Fietkau <nbd@openwrt.org>
   9 Cc: alan@lxorguk.ukuu.org.uk
  10 Cc: linux-mips@linux-mips.org
  11 Cc: linux-serial@vger.kernel.org
  12 Patchwork: https://patchwork.linux-mips.org/patch/2269/
  13 Acked-by: Alan Cox <alan@linux.intel.com>
  14 Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
  15 ---
  16  drivers/tty/serial/Kconfig  |    8 +
  17  drivers/tty/serial/Makefile |    1 +
  18  drivers/tty/serial/lantiq.c |  756 +++++++++++++++++++++++++++++++++++++++++++
  19  3 files changed, 765 insertions(+), 0 deletions(-)
  20  create mode 100644 drivers/tty/serial/lantiq.c
  21
  22 --- /dev/null
  23 +++ b/drivers/serial/lantiq.c
  24 @@ -0,0 +1,756 @@
  25 +/*
  26 + *  Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
  27 + *
  28 + * This program is free software; you can redistribute it and/or modify it
  29 + * under the terms of the GNU General Public License version 2 as published
  30 + * by the Free Software Foundation.
  31 + *
  32 + * This program is distributed in the hope that it will be useful,
  33 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  34 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  35 + * GNU General Public License for more details.
  36 + *
  37 + * You should have received a copy of the GNU General Public License
  38 + * along with this program; if not, write to the Free Software
  39 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  40 + *
  41 + * Copyright (C) 2004 Infineon IFAP DC COM CPE
  42 + * Copyright (C) 2007 Felix Fietkau <nbd@openwrt.org>
  43 + * Copyright (C) 2007 John Crispin <blogic@openwrt.org>
  44 + * Copyright (C) 2010 Thomas Langer, <thomas.langer@lantiq.com>
  45 + */
  46 +
  47 +#include <linux/slab.h>
  48 +#include <linux/module.h>
  49 +#include <linux/ioport.h>
  50 +#include <linux/init.h>
  51 +#include <linux/console.h>
  52 +#include <linux/sysrq.h>
  53 +#include <linux/device.h>
  54 +#include <linux/tty.h>
  55 +#include <linux/tty_flip.h>
  56 +#include <linux/serial_core.h>
  57 +#include <linux/serial.h>
  58 +#include <linux/platform_device.h>
  59 +#include <linux/io.h>
  60 +#include <linux/clk.h>
  61 +
  62 +#include <lantiq_soc.h>
  63 +
  64 +#define PORT_LTQ_ASC           111
  65 +#define MAXPORTS               2
  66 +#define UART_DUMMY_UER_RX      1
  67 +#define DRVNAME                        "ltq_asc"
  68 +#ifdef __BIG_ENDIAN
  69 +#define LTQ_ASC_TBUF           (0x0020 + 3)
  70 +#define LTQ_ASC_RBUF           (0x0024 + 3)
  71 +#else
  72 +#define LTQ_ASC_TBUF           0x0020
  73 +#define LTQ_ASC_RBUF           0x0024
  74 +#endif
  75 +#define LTQ_ASC_FSTAT          0x0048
  76 +#define LTQ_ASC_WHBSTATE       0x0018
  77 +#define LTQ_ASC_STATE          0x0014
  78 +#define LTQ_ASC_IRNCR          0x00F8
  79 +#define LTQ_ASC_CLC            0x0000
  80 +#define LTQ_ASC_ID             0x0008
  81 +#define LTQ_ASC_PISEL          0x0004
  82 +#define LTQ_ASC_TXFCON         0x0044
  83 +#define LTQ_ASC_RXFCON         0x0040
  84 +#define LTQ_ASC_CON            0x0010
  85 +#define LTQ_ASC_BG             0x0050
  86 +#define LTQ_ASC_IRNREN         0x00F4
  87 +
  88 +#define ASC_IRNREN_TX          0x1
  89 +#define ASC_IRNREN_RX          0x2
  90 +#define ASC_IRNREN_ERR         0x4
  91 +#define ASC_IRNREN_TX_BUF      0x8
  92 +#define ASC_IRNCR_TIR          0x1
  93 +#define ASC_IRNCR_RIR          0x2
  94 +#define ASC_IRNCR_EIR          0x4
  95 +
  96 +#define ASCOPT_CSIZE           0x3
  97 +#define TXFIFO_FL              1
  98 +#define RXFIFO_FL              1
  99 +#define ASCCLC_DISS            0x2
 100 +#define ASCCLC_RMCMASK         0x0000FF00
 101 +#define ASCCLC_RMCOFFSET       8
 102 +#define ASCCON_M_8ASYNC                0x0
 103 +#define ASCCON_M_7ASYNC                0x2
 104 +#define ASCCON_ODD             0x00000020
 105 +#define ASCCON_STP             0x00000080
 106 +#define ASCCON_BRS             0x00000100
 107 +#define ASCCON_FDE             0x00000200
 108 +#define ASCCON_R               0x00008000
 109 +#define ASCCON_FEN             0x00020000
 110 +#define ASCCON_ROEN            0x00080000
 111 +#define ASCCON_TOEN            0x00100000
 112 +#define ASCSTATE_PE            0x00010000
 113 +#define ASCSTATE_FE            0x00020000
 114 +#define ASCSTATE_ROE           0x00080000
 115 +#define ASCSTATE_ANY           (ASCSTATE_ROE|ASCSTATE_PE|ASCSTATE_FE)
 116 +#define ASCWHBSTATE_CLRREN     0x00000001
 117 +#define ASCWHBSTATE_SETREN     0x00000002
 118 +#define ASCWHBSTATE_CLRPE      0x00000004
 119 +#define ASCWHBSTATE_CLRFE      0x00000008
 120 +#define ASCWHBSTATE_CLRROE     0x00000020
 121 +#define ASCTXFCON_TXFEN                0x0001
 122 +#define ASCTXFCON_TXFFLU       0x0002
 123 +#define ASCTXFCON_TXFITLMASK   0x3F00
 124 +#define ASCTXFCON_TXFITLOFF    8
 125 +#define ASCRXFCON_RXFEN                0x0001
 126 +#define ASCRXFCON_RXFFLU       0x0002
 127 +#define ASCRXFCON_RXFITLMASK   0x3F00
 128 +#define ASCRXFCON_RXFITLOFF    8
 129 +#define ASCFSTAT_RXFFLMASK     0x003F
 130 +#define ASCFSTAT_TXFFLMASK     0x3F00
 131 +#define ASCFSTAT_TXFREEMASK    0x3F000000
 132 +#define ASCFSTAT_TXFREEOFF     24
 133 +
 134 +static void lqasc_tx_chars(struct uart_port *port);
 135 +static struct ltq_uart_port *lqasc_port[MAXPORTS];
 136 +static struct uart_driver lqasc_reg;
 137 +static DEFINE_SPINLOCK(ltq_asc_lock);
 138 +
 139 +struct ltq_uart_port {
 140 +       struct uart_port        port;
 141 +       struct clk              *clk;
 142 +       unsigned int            tx_irq;
 143 +       unsigned int            rx_irq;
 144 +       unsigned int            err_irq;
 145 +};
 146 +
 147 +static inline struct
 148 +ltq_uart_port *to_ltq_uart_port(struct uart_port *port)
 149 +{
 150 +       return container_of(port, struct ltq_uart_port, port);
 151 +}
 152 +
 153 +static void
 154 +lqasc_stop_tx(struct uart_port *port)
 155 +{
 156 +       return;
 157 +}
 158 +
 159 +static void
 160 +lqasc_start_tx(struct uart_port *port)
 161 +{
 162 +       unsigned long flags;
 163 +       spin_lock_irqsave(&ltq_asc_lock, flags);
 164 +       lqasc_tx_chars(port);
 165 +       spin_unlock_irqrestore(&ltq_asc_lock, flags);
 166 +       return;
 167 +}
 168 +
 169 +static void
 170 +lqasc_stop_rx(struct uart_port *port)
 171 +{
 172 +       ltq_w32(ASCWHBSTATE_CLRREN, port->membase + LTQ_ASC_WHBSTATE);
 173 +}
 174 +
 175 +static void
 176 +lqasc_enable_ms(struct uart_port *port)
 177 +{
 178 +}
 179 +
 180 +static int
 181 +lqasc_rx_chars(struct uart_port *port)
 182 +{
 183 +       struct tty_struct *tty = tty_port_tty_get(&port->state->port);
 184 +       unsigned int ch = 0, rsr = 0, fifocnt;
 185 +
 186 +       if (!tty) {
 187 +               dev_dbg(port->dev, "%s:tty is busy now", __func__);
 188 +               return -EBUSY;
 189 +       }
 190 +       fifocnt =
 191 +               ltq_r32(port->membase + LTQ_ASC_FSTAT) & ASCFSTAT_RXFFLMASK;
 192 +       while (fifocnt--) {
 193 +               u8 flag = TTY_NORMAL;
 194 +               ch = ltq_r8(port->membase + LTQ_ASC_RBUF);
 195 +               rsr = (ltq_r32(port->membase + LTQ_ASC_STATE)
 196 +                       & ASCSTATE_ANY) | UART_DUMMY_UER_RX;
 197 +               tty_flip_buffer_push(tty);
 198 +               port->icount.rx++;
 199 +
 200 +               /*
 201 +                * Note that the error handling code is
 202 +                * out of the main execution path
 203 +                */
 204 +               if (rsr & ASCSTATE_ANY) {
 205 +                       if (rsr & ASCSTATE_PE) {
 206 +                               port->icount.parity++;
 207 +                               ltq_w32_mask(0, ASCWHBSTATE_CLRPE,
 208 +                                       port->membase + LTQ_ASC_WHBSTATE);
 209 +                       } else if (rsr & ASCSTATE_FE) {
 210 +                               port->icount.frame++;
 211 +                               ltq_w32_mask(0, ASCWHBSTATE_CLRFE,
 212 +                                       port->membase + LTQ_ASC_WHBSTATE);
 213 +                       }
 214 +                       if (rsr & ASCSTATE_ROE) {
 215 +                               port->icount.overrun++;
 216 +                               ltq_w32_mask(0, ASCWHBSTATE_CLRROE,
 217 +                                       port->membase + LTQ_ASC_WHBSTATE);
 218 +                       }
 219 +
 220 +                       rsr &= port->read_status_mask;
 221 +
 222 +                       if (rsr & ASCSTATE_PE)
 223 +                               flag = TTY_PARITY;
 224 +                       else if (rsr & ASCSTATE_FE)
 225 +                               flag = TTY_FRAME;
 226 +               }
 227 +
 228 +               if ((rsr & port->ignore_status_mask) == 0)
 229 +                       tty_insert_flip_char(tty, ch, flag);
 230 +
 231 +               if (rsr & ASCSTATE_ROE)
 232 +                       /*
 233 +                        * Overrun is special, since it's reported
 234 +                        * immediately, and doesn't affect the current
 235 +                        * character
 236 +                        */
 237 +                       tty_insert_flip_char(tty, 0, TTY_OVERRUN);
 238 +       }
 239 +       if (ch != 0)
 240 +               tty_flip_buffer_push(tty);
 241 +       tty_kref_put(tty);
 242 +       return 0;
 243 +}
 244 +
 245 +static void
 246 +lqasc_tx_chars(struct uart_port *port)
 247 +{
 248 +       struct circ_buf *xmit = &port->state->xmit;
 249 +       if (uart_tx_stopped(port)) {
 250 +               lqasc_stop_tx(port);
 251 +               return;
 252 +       }
 253 +
 254 +       while (((ltq_r32(port->membase + LTQ_ASC_FSTAT) &
 255 +               ASCFSTAT_TXFREEMASK) >> ASCFSTAT_TXFREEOFF) != 0) {
 256 +               if (port->x_char) {
 257 +                       ltq_w8(port->x_char, port->membase + LTQ_ASC_TBUF);
 258 +                       port->icount.tx++;
 259 +                       port->x_char = 0;
 260 +                       continue;
 261 +               }
 262 +
 263 +               if (uart_circ_empty(xmit))
 264 +                       break;
 265 +
 266 +               ltq_w8(port->state->xmit.buf[port->state->xmit.tail],
 267 +                       port->membase + LTQ_ASC_TBUF);
 268 +               xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
 269 +               port->icount.tx++;
 270 +       }
 271 +
 272 +       if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
 273 +               uart_write_wakeup(port);
 274 +}
 275 +
 276 +static irqreturn_t
 277 +lqasc_tx_int(int irq, void *_port)
 278 +{
 279 +       unsigned long flags;
 280 +       struct uart_port *port = (struct uart_port *)_port;
 281 +       spin_lock_irqsave(&ltq_asc_lock, flags);
 282 +       ltq_w32(ASC_IRNCR_TIR, port->membase + LTQ_ASC_IRNCR);
 283 +       spin_unlock_irqrestore(&ltq_asc_lock, flags);
 284 +       lqasc_start_tx(port);
 285 +       return IRQ_HANDLED;
 286 +}
 287 +
 288 +static irqreturn_t
 289 +lqasc_err_int(int irq, void *_port)
 290 +{
 291 +       unsigned long flags;
 292 +       struct uart_port *port = (struct uart_port *)_port;
 293 +       spin_lock_irqsave(&ltq_asc_lock, flags);
 294 +       /* clear any pending interrupts */
 295 +       ltq_w32_mask(0, ASCWHBSTATE_CLRPE | ASCWHBSTATE_CLRFE |
 296 +               ASCWHBSTATE_CLRROE, port->membase + LTQ_ASC_WHBSTATE);
 297 +       spin_unlock_irqrestore(&ltq_asc_lock, flags);
 298 +       return IRQ_HANDLED;
 299 +}
 300 +
 301 +static irqreturn_t
 302 +lqasc_rx_int(int irq, void *_port)
 303 +{
 304 +       unsigned long flags;
 305 +       struct uart_port *port = (struct uart_port *)_port;
 306 +       spin_lock_irqsave(&ltq_asc_lock, flags);
 307 +       ltq_w32(ASC_IRNCR_RIR, port->membase + LTQ_ASC_IRNCR);
 308 +       lqasc_rx_chars(port);
 309 +       spin_unlock_irqrestore(&ltq_asc_lock, flags);
 310 +       return IRQ_HANDLED;
 311 +}
 312 +
 313 +static unsigned int
 314 +lqasc_tx_empty(struct uart_port *port)
 315 +{
 316 +       int status;
 317 +       status = ltq_r32(port->membase + LTQ_ASC_FSTAT) & ASCFSTAT_TXFFLMASK;
 318 +       return status ? 0 : TIOCSER_TEMT;
 319 +}
 320 +
 321 +static unsigned int
 322 +lqasc_get_mctrl(struct uart_port *port)
 323 +{
 324 +       return TIOCM_CTS | TIOCM_CAR | TIOCM_DSR;
 325 +}
 326 +
 327 +static void
 328 +lqasc_set_mctrl(struct uart_port *port, u_int mctrl)
 329 +{
 330 +}
 331 +
 332 +static void
 333 +lqasc_break_ctl(struct uart_port *port, int break_state)
 334 +{
 335 +}
 336 +
 337 +static int
 338 +lqasc_startup(struct uart_port *port)
 339 +{
 340 +       struct ltq_uart_port *ltq_port = to_ltq_uart_port(port);
 341 +       int retval;
 342 +
 343 +       port->uartclk = clk_get_rate(ltq_port->clk);
 344 +
 345 +       ltq_w32_mask(ASCCLC_DISS | ASCCLC_RMCMASK, (1 << ASCCLC_RMCOFFSET),
 346 +               port->membase + LTQ_ASC_CLC);
 347 +
 348 +       ltq_w32(0, port->membase + LTQ_ASC_PISEL);
 349 +       ltq_w32(
 350 +               ((TXFIFO_FL << ASCTXFCON_TXFITLOFF) & ASCTXFCON_TXFITLMASK) |
 351 +               ASCTXFCON_TXFEN | ASCTXFCON_TXFFLU,
 352 +               port->membase + LTQ_ASC_TXFCON);
 353 +       ltq_w32(
 354 +               ((RXFIFO_FL << ASCRXFCON_RXFITLOFF) & ASCRXFCON_RXFITLMASK)
 355 +               | ASCRXFCON_RXFEN | ASCRXFCON_RXFFLU,
 356 +               port->membase + LTQ_ASC_RXFCON);
 357 +       /* make sure other settings are written to hardware before
 358 +        * setting enable bits
 359 +        */
 360 +       wmb();
 361 +       ltq_w32_mask(0, ASCCON_M_8ASYNC | ASCCON_FEN | ASCCON_TOEN |
 362 +               ASCCON_ROEN, port->membase + LTQ_ASC_CON);
 363 +
 364 +       retval = request_irq(ltq_port->tx_irq, lqasc_tx_int,
 365 +               IRQF_DISABLED, "asc_tx", port);
 366 +       if (retval) {
 367 +               pr_err("failed to request lqasc_tx_int\n");
 368 +               return retval;
 369 +       }
 370 +
 371 +       retval = request_irq(ltq_port->rx_irq, lqasc_rx_int,
 372 +               IRQF_DISABLED, "asc_rx", port);
 373 +       if (retval) {
 374 +               pr_err("failed to request lqasc_rx_int\n");
 375 +               goto err1;
 376 +       }
 377 +
 378 +       retval = request_irq(ltq_port->err_irq, lqasc_err_int,
 379 +               IRQF_DISABLED, "asc_err", port);
 380 +       if (retval) {
 381 +               pr_err("failed to request lqasc_err_int\n");
 382 +               goto err2;
 383 +       }
 384 +
 385 +       ltq_w32(ASC_IRNREN_RX | ASC_IRNREN_ERR | ASC_IRNREN_TX,
 386 +               port->membase + LTQ_ASC_IRNREN);
 387 +       return 0;
 388 +
 389 +err2:
 390 +       free_irq(ltq_port->rx_irq, port);
 391 +err1:
 392 +       free_irq(ltq_port->tx_irq, port);
 393 +       return retval;
 394 +}
 395 +
 396 +static void
 397 +lqasc_shutdown(struct uart_port *port)
 398 +{
 399 +       struct ltq_uart_port *ltq_port = to_ltq_uart_port(port);
 400 +       free_irq(ltq_port->tx_irq, port);
 401 +       free_irq(ltq_port->rx_irq, port);
 402 +       free_irq(ltq_port->err_irq, port);
 403 +
 404 +       ltq_w32(0, port->membase + LTQ_ASC_CON);
 405 +       ltq_w32_mask(ASCRXFCON_RXFEN, ASCRXFCON_RXFFLU,
 406 +               port->membase + LTQ_ASC_RXFCON);
 407 +       ltq_w32_mask(ASCTXFCON_TXFEN, ASCTXFCON_TXFFLU,
 408 +               port->membase + LTQ_ASC_TXFCON);
 409 +}
 410 +
 411 +static void
 412 +lqasc_set_termios(struct uart_port *port,
 413 +       struct ktermios *new, struct ktermios *old)
 414 +{
 415 +       unsigned int cflag;
 416 +       unsigned int iflag;
 417 +       unsigned int divisor;
 418 +       unsigned int baud;
 419 +       unsigned int con = 0;
 420 +       unsigned long flags;
 421 +
 422 +       cflag = new->c_cflag;
 423 +       iflag = new->c_iflag;
 424 +
 425 +       switch (cflag & CSIZE) {
 426 +       case CS7:
 427 +               con = ASCCON_M_7ASYNC;
 428 +               break;
 429 +
 430 +       case CS5:
 431 +       case CS6:
 432 +       default:
 433 +               new->c_cflag &= ~ CSIZE;
 434 +               new->c_cflag |= CS8;
 435 +               con = ASCCON_M_8ASYNC;
 436 +               break;
 437 +       }
 438 +
 439 +       cflag &= ~CMSPAR; /* Mark/Space parity is not supported */
 440 +
 441 +       if (cflag & CSTOPB)
 442 +               con |= ASCCON_STP;
 443 +
 444 +       if (cflag & PARENB) {
 445 +               if (!(cflag & PARODD))
 446 +                       con &= ~ASCCON_ODD;
 447 +               else
 448 +                       con |= ASCCON_ODD;
 449 +       }
 450 +
 451 +       port->read_status_mask = ASCSTATE_ROE;
 452 +       if (iflag & INPCK)
 453 +               port->read_status_mask |= ASCSTATE_FE | ASCSTATE_PE;
 454 +
 455 +       port->ignore_status_mask = 0;
 456 +       if (iflag & IGNPAR)
 457 +               port->ignore_status_mask |= ASCSTATE_FE | ASCSTATE_PE;
 458 +
 459 +       if (iflag & IGNBRK) {
 460 +               /*
 461 +                * If we're ignoring parity and break indicators,
 462 +                * ignore overruns too (for real raw support).
 463 +                */
 464 +               if (iflag & IGNPAR)
 465 +                       port->ignore_status_mask |= ASCSTATE_ROE;
 466 +       }
 467 +
 468 +       if ((cflag & CREAD) == 0)
 469 +               port->ignore_status_mask |= UART_DUMMY_UER_RX;
 470 +
 471 +       /* set error signals  - framing, parity  and overrun, enable receiver */
 472 +       con |= ASCCON_FEN | ASCCON_TOEN | ASCCON_ROEN;
 473 +
 474 +       spin_lock_irqsave(&ltq_asc_lock, flags);
 475 +
 476 +       /* set up CON */
 477 +       ltq_w32_mask(0, con, port->membase + LTQ_ASC_CON);
 478 +
 479 +       /* Set baud rate - take a divider of 2 into account */
 480 +       baud = uart_get_baud_rate(port, new, old, 0, port->uartclk / 16);
 481 +       divisor = uart_get_divisor(port, baud);
 482 +       divisor = divisor / 2 - 1;
 483 +
 484 +       /* disable the baudrate generator */
 485 +       ltq_w32_mask(ASCCON_R, 0, port->membase + LTQ_ASC_CON);
 486 +
 487 +       /* make sure the fractional divider is off */
 488 +       ltq_w32_mask(ASCCON_FDE, 0, port->membase + LTQ_ASC_CON);
 489 +
 490 +       /* set up to use divisor of 2 */
 491 +       ltq_w32_mask(ASCCON_BRS, 0, port->membase + LTQ_ASC_CON);
 492 +
 493 +       /* now we can write the new baudrate into the register */
 494 +       ltq_w32(divisor, port->membase + LTQ_ASC_BG);
 495 +
 496 +       /* turn the baudrate generator back on */
 497 +       ltq_w32_mask(0, ASCCON_R, port->membase + LTQ_ASC_CON);
 498 +
 499 +       /* enable rx */
 500 +       ltq_w32(ASCWHBSTATE_SETREN, port->membase + LTQ_ASC_WHBSTATE);
 501 +
 502 +       spin_unlock_irqrestore(&ltq_asc_lock, flags);
 503 +
 504 +       /* Don't rewrite B0 */
 505 +        if (tty_termios_baud_rate(new))
 506 +               tty_termios_encode_baud_rate(new, baud, baud);
 507 +}
 508 +
 509 +static const char*
 510 +lqasc_type(struct uart_port *port)
 511 +{
 512 +       if (port->type == PORT_LTQ_ASC)
 513 +               return DRVNAME;
 514 +       else
 515 +               return NULL;
 516 +}
 517 +
 518 +static void
 519 +lqasc_release_port(struct uart_port *port)
 520 +{
 521 +       if (port->flags & UPF_IOREMAP) {
 522 +               iounmap(port->membase);
 523 +               port->membase = NULL;
 524 +       }
 525 +}
 526 +
 527 +static int
 528 +lqasc_request_port(struct uart_port *port)
 529 +{
 530 +       struct platform_device *pdev = to_platform_device(port->dev);
 531 +       struct resource *res;
 532 +       int size;
 533 +
 534 +       res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 535 +       if (!res) {
 536 +               dev_err(&pdev->dev, "cannot obtain I/O memory region");
 537 +               return -ENODEV;
 538 +       }
 539 +       size = resource_size(res);
 540 +
 541 +       res = devm_request_mem_region(&pdev->dev, res->start,
 542 +               size, dev_name(&pdev->dev));
 543 +       if (!res) {
 544 +               dev_err(&pdev->dev, "cannot request I/O memory region");
 545 +               return -EBUSY;
 546 +       }
 547 +
 548 +       if (port->flags & UPF_IOREMAP) {
 549 +               port->membase = devm_ioremap_nocache(&pdev->dev,
 550 +                       port->mapbase, size);
 551 +               if (port->membase == NULL)
 552 +                       return -ENOMEM;
 553 +       }
 554 +       return 0;
 555 +}
 556 +
 557 +static void
 558 +lqasc_config_port(struct uart_port *port, int flags)
 559 +{
 560 +       if (flags & UART_CONFIG_TYPE) {
 561 +               port->type = PORT_LTQ_ASC;
 562 +               lqasc_request_port(port);
 563 +       }
 564 +}
 565 +
 566 +static int
 567 +lqasc_verify_port(struct uart_port *port,
 568 +       struct serial_struct *ser)
 569 +{
 570 +       int ret = 0;
 571 +       if (ser->type != PORT_UNKNOWN && ser->type != PORT_LTQ_ASC)
 572 +               ret = -EINVAL;
 573 +       if (ser->irq < 0 || ser->irq >= NR_IRQS)
 574 +               ret = -EINVAL;
 575 +       if (ser->baud_base < 9600)
 576 +               ret = -EINVAL;
 577 +       return ret;
 578 +}
 579 +
 580 +static struct uart_ops lqasc_pops = {
 581 +       .tx_empty =     lqasc_tx_empty,
 582 +       .set_mctrl =    lqasc_set_mctrl,
 583 +       .get_mctrl =    lqasc_get_mctrl,
 584 +       .stop_tx =      lqasc_stop_tx,
 585 +       .start_tx =     lqasc_start_tx,
 586 +       .stop_rx =      lqasc_stop_rx,
 587 +       .enable_ms =    lqasc_enable_ms,
 588 +       .break_ctl =    lqasc_break_ctl,
 589 +       .startup =      lqasc_startup,
 590 +       .shutdown =     lqasc_shutdown,
 591 +       .set_termios =  lqasc_set_termios,
 592 +       .type =         lqasc_type,
 593 +       .release_port = lqasc_release_port,
 594 +       .request_port = lqasc_request_port,
 595 +       .config_port =  lqasc_config_port,
 596 +       .verify_port =  lqasc_verify_port,
 597 +};
 598 +
 599 +static void
 600 +lqasc_console_putchar(struct uart_port *port, int ch)
 601 +{
 602 +       int fifofree;
 603 +
 604 +       if (!port->membase)
 605 +               return;
 606 +
 607 +       do {
 608 +               fifofree = (ltq_r32(port->membase + LTQ_ASC_FSTAT)
 609 +                       & ASCFSTAT_TXFREEMASK) >> ASCFSTAT_TXFREEOFF;
 610 +       } while (fifofree == 0);
 611 +       ltq_w8(ch, port->membase + LTQ_ASC_TBUF);
 612 +}
 613 +
 614 +
 615 +static void
 616 +lqasc_console_write(struct console *co, const char *s, u_int count)
 617 +{
 618 +       struct ltq_uart_port *ltq_port;
 619 +       struct uart_port *port;
 620 +       unsigned long flags;
 621 +
 622 +       if (co->index >= MAXPORTS)
 623 +               return;
 624 +
 625 +       ltq_port = lqasc_port[co->index];
 626 +       if (!ltq_port)
 627 +               return;
 628 +
 629 +       port = &ltq_port->port;
 630 +
 631 +       spin_lock_irqsave(&ltq_asc_lock, flags);
 632 +       uart_console_write(port, s, count, lqasc_console_putchar);
 633 +       spin_unlock_irqrestore(&ltq_asc_lock, flags);
 634 +}
 635 +
 636 +static int __init
 637 +lqasc_console_setup(struct console *co, char *options)
 638 +{
 639 +       struct ltq_uart_port *ltq_port;
 640 +       struct uart_port *port;
 641 +       int baud = 115200;
 642 +       int bits = 8;
 643 +       int parity = 'n';
 644 +       int flow = 'n';
 645 +
 646 +       if (co->index >= MAXPORTS)
 647 +               return -ENODEV;
 648 +
 649 +       ltq_port = lqasc_port[co->index];
 650 +       if (!ltq_port)
 651 +               return -ENODEV;
 652 +
 653 +       port = &ltq_port->port;
 654 +
 655 +       port->uartclk = clk_get_rate(ltq_port->clk);
 656 +
 657 +       if (options)
 658 +               uart_parse_options(options, &baud, &parity, &bits, &flow);
 659 +       return uart_set_options(port, co, baud, parity, bits, flow);
 660 +}
 661 +
 662 +static struct console lqasc_console = {
 663 +       .name =         "ttyLTQ",
 664 +       .write =        lqasc_console_write,
 665 +       .device =       uart_console_device,
 666 +       .setup =        lqasc_console_setup,
 667 +       .flags =        CON_PRINTBUFFER,
 668 +       .index =        -1,
 669 +       .data =         &lqasc_reg,
 670 +};
 671 +
 672 +static int __init
 673 +lqasc_console_init(void)
 674 +{
 675 +       register_console(&lqasc_console);
 676 +       return 0;
 677 +}
 678 +console_initcall(lqasc_console_init);
 679 +
 680 +static struct uart_driver lqasc_reg = {
 681 +       .owner =        THIS_MODULE,
 682 +       .driver_name =  DRVNAME,
 683 +       .dev_name =     "ttyLTQ",
 684 +       .major =        0,
 685 +       .minor =        0,
 686 +       .nr =           MAXPORTS,
 687 +       .cons =         &lqasc_console,
 688 +};
 689 +
 690 +static int __init
 691 +lqasc_probe(struct platform_device *pdev)
 692 +{
 693 +       struct ltq_uart_port *ltq_port;
 694 +       struct uart_port *port;
 695 +       struct resource *mmres, *irqres;
 696 +       int tx_irq, rx_irq, err_irq;
 697 +       struct clk *clk;
 698 +       int ret;
 699 +
 700 +       mmres = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 701 +       irqres = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
 702 +       if (!mmres || !irqres)
 703 +               return -ENODEV;
 704 +
 705 +       if (pdev->id >= MAXPORTS)
 706 +               return -EBUSY;
 707 +
 708 +       if (lqasc_port[pdev->id] != NULL)
 709 +               return -EBUSY;
 710 +
 711 +       clk = clk_get(&pdev->dev, "fpi");
 712 +       if (IS_ERR(clk)) {
 713 +               pr_err("failed to get fpi clk\n");
 714 +               return -ENOENT;
 715 +       }
 716 +
 717 +       tx_irq = platform_get_irq_byname(pdev, "tx");
 718 +       rx_irq = platform_get_irq_byname(pdev, "rx");
 719 +       err_irq = platform_get_irq_byname(pdev, "err");
 720 +       if ((tx_irq < 0) | (rx_irq < 0) | (err_irq < 0))
 721 +               return -ENODEV;
 722 +
 723 +       ltq_port = kzalloc(sizeof(struct ltq_uart_port), GFP_KERNEL);
 724 +       if (!ltq_port)
 725 +               return -ENOMEM;
 726 +
 727 +       port = &ltq_port->port;
 728 +
 729 +       port->iotype    = SERIAL_IO_MEM;
 730 +       port->flags     = ASYNC_BOOT_AUTOCONF | UPF_IOREMAP;
 731 +       port->ops       = &lqasc_pops;
 732 +       port->fifosize  = 16;
 733 +       port->type      = PORT_LTQ_ASC,
 734 +       port->line      = pdev->id;
 735 +       port->dev       = &pdev->dev;
 736 +
 737 +       port->irq       = tx_irq; /* unused, just to be backward-compatibe */
 738 +       port->mapbase   = mmres->start;
 739 +
 740 +       ltq_port->clk   = clk;
 741 +
 742 +       ltq_port->tx_irq = tx_irq;
 743 +       ltq_port->rx_irq = rx_irq;
 744 +       ltq_port->err_irq = err_irq;
 745 +
 746 +       lqasc_port[pdev->id] = ltq_port;
 747 +       platform_set_drvdata(pdev, ltq_port);
 748 +
 749 +       ret = uart_add_one_port(&lqasc_reg, port);
 750 +
 751 +       return ret;
 752 +}
 753 +
 754 +static struct platform_driver lqasc_driver = {
 755 +       .driver         = {
 756 +               .name   = DRVNAME,
 757 +               .owner  = THIS_MODULE,
 758 +       },
 759 +};
 760 +
 761 +int __init
 762 +init_lqasc(void)
 763 +{
 764 +       int ret;
 765 +
 766 +       ret = uart_register_driver(&lqasc_reg);
 767 +       if (ret != 0)
 768 +               return ret;
 769 +
 770 +       ret = platform_driver_probe(&lqasc_driver, lqasc_probe);
 771 +       if (ret != 0)
 772 +               uart_unregister_driver(&lqasc_reg);
 773 +
 774 +       return ret;
 775 +}
 776 +
 777 +module_init(init_lqasc);
 778 +
 779 +MODULE_DESCRIPTION("Lantiq serial port driver");
 780 +MODULE_LICENSE("GPL");
 781 --- a/drivers/serial/Kconfig
 782 +++ b/drivers/serial/Kconfig
 783 @@ -1383,6 +1383,14 @@
 784         help
 785           Support for Console on the NWP serial ports.
 786
 787 +config SERIAL_LANTIQ
 788 +       bool "Lantiq serial driver"
 789 +       depends on LANTIQ
 790 +       select SERIAL_CORE
 791 +       select SERIAL_CORE_CONSOLE
 792 +       help
 793 +         Support for console and UART on Lantiq SoCs.
 794 +
 795  config SERIAL_QE
 796         tristate "Freescale QUICC Engine serial port support"
 797         depends on QUICC_ENGINE
 798 --- a/drivers/serial/Makefile
 799 +++ b/drivers/serial/Makefile
 800 @@ -81,3 +81,4 @@
 801  obj-$(CONFIG_KGDB_SERIAL_CONSOLE) += kgdboc.o
 802  obj-$(CONFIG_SERIAL_QE) += ucc_uart.o
 803  obj-$(CONFIG_SERIAL_TIMBERDALE)        += timbuart.o
 804 +obj-$(CONFIG_SERIAL_LANTIQ)    += lantiq.o