tools/xz: add some upstream patches
[openwrt.git] / target / linux / lantiq / patches / 230-xway_etop.patch
1 --- a/drivers/net/Kconfig
2 +++ b/drivers/net/Kconfig
3 @@ -343,6 +343,12 @@ config MACB
4  
5  source "drivers/net/arm/Kconfig"
6  
7 +config LANTIQ_ETOP
8 +       tristate "Lantiq SoC ETOP driver"
9 +       depends on SOC_LANTIQ_XWAY
10 +       help
11 +         Support for the MII0 inside the Lantiq SoC
12 +
13  config AX88796
14         tristate "ASIX AX88796 NE2000 clone support"
15         depends on ARM || MIPS || SUPERH
16 --- a/drivers/net/Makefile
17 +++ b/drivers/net/Makefile
18 @@ -204,6 +204,7 @@ obj-$(CONFIG_SNI_82596) += sni_82596.o
19  obj-$(CONFIG_MVME16x_NET) += 82596.o
20  obj-$(CONFIG_BVME6000_NET) += 82596.o
21  obj-$(CONFIG_SC92031) += sc92031.o
22 +obj-$(CONFIG_LANTIQ_ETOP) += lantiq_etop.o
23  
24  # This is also a 82596 and should probably be merged
25  obj-$(CONFIG_LP486E) += lp486e.o
26 --- /dev/null
27 +++ b/drivers/net/lantiq_etop.c
28 @@ -0,0 +1,552 @@
29 +/*
30 + *   This program is free software; you can redistribute it and/or modify it
31 + *   under the terms of the GNU General Public License version 2 as published
32 + *   by the Free Software Foundation.
33 + *
34 + *   This program is distributed in the hope that it will be useful,
35 + *   but WITHOUT ANY WARRANTY; without even the implied warranty of
36 + *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
37 + *   GNU General Public License for more details.
38 + *
39 + *   You should have received a copy of the GNU General Public License
40 + *   along with this program; if not, write to the Free Software
41 + *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
42 + *
43 + *   Copyright (C) 2005 Wu Qi Ming <Qi-Ming.Wu@infineon.com>
44 + *   Copyright (C) 2008 John Crispin <blogic@openwrt.org>
45 + */
46 +
47 +#include <linux/kernel.h>
48 +#include <linux/slab.h>
49 +#include <linux/errno.h>
50 +#include <linux/types.h>
51 +#include <linux/interrupt.h>
52 +#include <linux/uaccess.h>
53 +#include <linux/in.h>
54 +#include <linux/netdevice.h>
55 +#include <linux/etherdevice.h>
56 +#include <linux/phy.h>
57 +#include <linux/ip.h>
58 +#include <linux/tcp.h>
59 +#include <linux/skbuff.h>
60 +#include <linux/mm.h>
61 +#include <linux/platform_device.h>
62 +#include <linux/ethtool.h>
63 +#include <linux/init.h>
64 +#include <linux/delay.h>
65 +
66 +#include <asm/checksum.h>
67 +
68 +#include <xway.h>
69 +#include <xway_dma.h>
70 +#include <lantiq_platform.h>
71 +
72 +#define ETHERNET_PACKET_DMA_BUFFER_SIZE                0x600
73 +#define LQ_PPE32_MEM_MAP               ((u32 *)(LQ_PPE32_BASE_ADDR + 0x10000))
74 +#define LQ_PPE32_SRST          ((u32 *)(LQ_PPE32_BASE_ADDR + 0x10080))
75 +
76 +/* mdio access */
77 +#define LQ_PPE32_MDIO_CFG              ((u32 *)(LQ_PPE32_BASE_ADDR + 0x11800))
78 +#define LQ_PPE32_MDIO_ACC              ((u32 *)(LQ_PPE32_BASE_ADDR + 0x11804))
79 +
80 +#define MDIO_ACC_REQUEST               0x80000000
81 +#define MDIO_ACC_READ                  0x40000000
82 +#define MDIO_ACC_ADDR_MASK             0x1f
83 +#define MDIO_ACC_ADDR_OFFSET           0x15
84 +#define MDIO_ACC_REG_MASK              0x1f
85 +#define MDIO_ACC_REG_OFFSET            0x10
86 +#define MDIO_ACC_VAL_MASK              0xffff
87 +
88 +/* configuration */
89 +#define LQ_PPE32_CFG           ((u32 *)(LQ_PPE32_MEM_MAP + 0x1808))
90 +
91 +#define PPE32_MII_MASK                 0xfffffffc
92 +#define PPE32_MII_NORMAL               0x8
93 +#define PPE32_MII_REVERSE              0xe
94 +
95 +/* packet length */
96 +#define LQ_PPE32_IG_PLEN_CTRL  ((u32 *)(LQ_PPE32_MEM_MAP + 0x1820))
97 +
98 +#define PPE32_PLEN_OVER                        0x5ee
99 +#define PPE32_PLEN_UNDER               0x400000
100 +
101 +/* enet */
102 +#define LQ_PPE32_ENET_MAC_CFG  ((u32 *)(LQ_PPE32_MEM_MAP + 0x1840))
103 +
104 +#define PPE32_CGEN                     0x800
105 +
106 +struct lq_mii_priv {
107 +       struct net_device_stats stats;
108 +       struct dma_device_info *dma_device;
109 +       struct sk_buff *skb;
110 +
111 +       struct mii_bus *mii_bus;
112 +       struct phy_device *phydev;
113 +       int oldlink, oldspeed, oldduplex;
114 +};
115 +
116 +static struct net_device *lq_etop_dev;
117 +static unsigned char mac_addr[MAX_ADDR_LEN];
118 +
119 +static int lq_mdiobus_write(struct mii_bus *bus, int phy_addr,
120 +                               int phy_reg, u16 phy_data)
121 +{
122 +       u32 val = MDIO_ACC_REQUEST |
123 +               ((phy_addr & MDIO_ACC_ADDR_MASK) << MDIO_ACC_ADDR_OFFSET) |
124 +               ((phy_reg & MDIO_ACC_REG_MASK) << MDIO_ACC_REG_OFFSET) |
125 +               phy_data;
126 +
127 +       while (lq_r32(LQ_PPE32_MDIO_ACC) & MDIO_ACC_REQUEST)
128 +               ;
129 +       lq_w32(val, LQ_PPE32_MDIO_ACC);
130 +
131 +       return 0;
132 +}
133 +
134 +static int lq_mdiobus_read(struct mii_bus *bus, int phy_addr, int phy_reg)
135 +{
136 +       u32 val = MDIO_ACC_REQUEST | MDIO_ACC_READ |
137 +               ((phy_addr & MDIO_ACC_ADDR_MASK) << MDIO_ACC_ADDR_OFFSET) |
138 +               ((phy_reg & MDIO_ACC_REG_MASK) << MDIO_ACC_REG_OFFSET);
139 +
140 +       while (lq_r32(LQ_PPE32_MDIO_ACC) & MDIO_ACC_REQUEST)
141 +               ;
142 +       lq_w32(val, LQ_PPE32_MDIO_ACC);
143 +       while (lq_r32(LQ_PPE32_MDIO_ACC) & MDIO_ACC_REQUEST)
144 +               ;
145 +       val = lq_r32(LQ_PPE32_MDIO_ACC) & MDIO_ACC_VAL_MASK;
146 +       return val;
147 +}
148 +
149 +int lq_mii_open(struct net_device *dev)
150 +{
151 +       struct lq_mii_priv *priv = (struct lq_mii_priv *)netdev_priv(dev);
152 +       struct dma_device_info *dma_dev = priv->dma_device;
153 +       int i;
154 +
155 +       for (i = 0; i < dma_dev->max_rx_chan_num; i++) {
156 +               if ((dma_dev->rx_chan[i])->control == LQ_DMA_CH_ON)
157 +                       (dma_dev->rx_chan[i])->open(dma_dev->rx_chan[i]);
158 +       }
159 +       netif_start_queue(dev);
160 +       return 0;
161 +}
162 +
163 +int lq_mii_release(struct net_device *dev)
164 +{
165 +       struct lq_mii_priv *priv = (struct lq_mii_priv *)netdev_priv(dev);
166 +       struct dma_device_info *dma_dev = priv->dma_device;
167 +       int i;
168 +
169 +       for (i = 0; i < dma_dev->max_rx_chan_num; i++)
170 +               dma_dev->rx_chan[i]->close(dma_dev->rx_chan[i]);
171 +       netif_stop_queue(dev);
172 +       return 0;
173 +}
174 +
175 +int lq_mii_hw_receive(struct net_device *dev, struct dma_device_info *dma_dev)
176 +{
177 +       struct lq_mii_priv *priv = (struct lq_mii_priv *)netdev_priv(dev);
178 +       unsigned char *buf = NULL;
179 +       struct sk_buff *skb = NULL;
180 +       int len = 0;
181 +
182 +       len = dma_device_read(dma_dev, &buf, (void **)&skb);
183 +
184 +       if (len >= ETHERNET_PACKET_DMA_BUFFER_SIZE) {
185 +               printk(KERN_INFO "lq_etop: packet too large %d\n", len);
186 +               goto lq_mii_hw_receive_err_exit;
187 +       }
188 +
189 +       /* remove CRC */
190 +       len -= 4;
191 +       if (skb == NULL) {
192 +               printk(KERN_INFO "lq_etop: cannot restore pointer\n");
193 +               goto lq_mii_hw_receive_err_exit;
194 +       }
195 +
196 +       if (len > (skb->end - skb->tail)) {
197 +               printk(KERN_INFO "lq_etop: BUG, len:%d end:%p tail:%p\n",
198 +                       (len+4), skb->end, skb->tail);
199 +               goto lq_mii_hw_receive_err_exit;
200 +       }
201 +
202 +       skb_put(skb, len);
203 +       skb->dev = dev;
204 +       skb->protocol = eth_type_trans(skb, dev);
205 +       netif_rx(skb);
206 +
207 +       priv->stats.rx_packets++;
208 +       priv->stats.rx_bytes += len;
209 +       return 0;
210 +
211 +lq_mii_hw_receive_err_exit:
212 +       if (len == 0) {
213 +               if (skb)
214 +                       dev_kfree_skb_any(skb);
215 +               priv->stats.rx_errors++;
216 +               priv->stats.rx_dropped++;
217 +               return -EIO;
218 +       } else {
219 +               return len;
220 +       }
221 +}
222 +
223 +int lq_mii_hw_tx(char *buf, int len, struct net_device *dev)
224 +{
225 +       int ret = 0;
226 +       struct lq_mii_priv *priv = netdev_priv(dev);
227 +       struct dma_device_info *dma_dev = priv->dma_device;
228 +       ret = dma_device_write(dma_dev, buf, len, priv->skb);
229 +       return ret;
230 +}
231 +
232 +int lq_mii_tx(struct sk_buff *skb, struct net_device *dev)
233 +{
234 +       int len;
235 +       char *data;
236 +       struct lq_mii_priv *priv = netdev_priv(dev);
237 +       struct dma_device_info *dma_dev = priv->dma_device;
238 +
239 +       len = skb->len < ETH_ZLEN ? ETH_ZLEN : skb->len;
240 +       data = skb->data;
241 +       priv->skb = skb;
242 +       dev->trans_start = jiffies;
243 +       /* TODO: we got more than 1 dma channel,
244 +          so we should do something intelligent here to select one */
245 +       dma_dev->current_tx_chan = 0;
246 +
247 +       wmb();
248 +
249 +       if (lq_mii_hw_tx(data, len, dev) != len) {
250 +               dev_kfree_skb_any(skb);
251 +               priv->stats.tx_errors++;
252 +               priv->stats.tx_dropped++;
253 +       } else {
254 +               priv->stats.tx_packets++;
255 +               priv->stats.tx_bytes += len;
256 +       }
257 +
258 +       return 0;
259 +}
260 +
261 +void lq_mii_tx_timeout(struct net_device *dev)
262 +{
263 +       int i;
264 +       struct lq_mii_priv *priv = (struct lq_mii_priv *)netdev_priv(dev);
265 +
266 +       priv->stats.tx_errors++;
267 +       for (i = 0; i < priv->dma_device->max_tx_chan_num; i++)
268 +               priv->dma_device->tx_chan[i]->disable_irq(priv->dma_device->tx_chan[i]);
269 +       netif_wake_queue(dev);
270 +       return;
271 +}
272 +
273 +int dma_intr_handler(struct dma_device_info *dma_dev, int status)
274 +{
275 +       int i;
276 +
277 +       switch (status) {
278 +       case RCV_INT:
279 +               lq_mii_hw_receive(lq_etop_dev, dma_dev);
280 +               break;
281 +
282 +       case TX_BUF_FULL_INT:
283 +               printk(KERN_INFO "lq_etop: tx buffer full\n");
284 +               netif_stop_queue(lq_etop_dev);
285 +               for (i = 0; i < dma_dev->max_tx_chan_num; i++) {
286 +                       if ((dma_dev->tx_chan[i])->control == LQ_DMA_CH_ON)
287 +                               dma_dev->tx_chan[i]->enable_irq(dma_dev->tx_chan[i]);
288 +               }
289 +               break;
290 +
291 +       case TRANSMIT_CPT_INT:
292 +               for (i = 0; i < dma_dev->max_tx_chan_num; i++)
293 +                       dma_dev->tx_chan[i]->disable_irq(dma_dev->tx_chan[i]);
294 +
295 +               netif_wake_queue(lq_etop_dev);
296 +               break;
297 +       }
298 +
299 +       return 0;
300 +}
301 +
302 +unsigned char *lq_etop_dma_buffer_alloc(int len, int *byte_offset, void **opt)
303 +{
304 +       unsigned char *buffer = NULL;
305 +       struct sk_buff *skb = NULL;
306 +
307 +       skb = dev_alloc_skb(ETHERNET_PACKET_DMA_BUFFER_SIZE);
308 +       if (skb == NULL)
309 +               return NULL;
310 +
311 +       buffer = (unsigned char *)(skb->data);
312 +       skb_reserve(skb, 2);
313 +       *(int *)opt = (int)skb;
314 +       *byte_offset = 2;
315 +
316 +       return buffer;
317 +}
318 +
319 +void lq_etop_dma_buffer_free(unsigned char *dataptr, void *opt)
320 +{
321 +       struct sk_buff *skb = NULL;
322 +
323 +       if (opt == NULL) {
324 +               kfree(dataptr);
325 +       } else {
326 +               skb = (struct sk_buff *)opt;
327 +               dev_kfree_skb_any(skb);
328 +       }
329 +}
330 +
331 +static void
332 +lq_adjust_link(struct net_device *dev)
333 +{
334 +       struct lq_mii_priv *priv = netdev_priv(dev);
335 +       struct phy_device *phydev = priv->phydev;
336 +       int new_state = 0;
337 +
338 +       /* Did anything change? */
339 +       if (priv->oldlink != phydev->link ||
340 +               priv->oldduplex != phydev->duplex ||
341 +               priv->oldspeed != phydev->speed) {
342 +               /* Yes, so update status and mark as changed */
343 +               new_state = 1;
344 +               priv->oldduplex = phydev->duplex;
345 +               priv->oldspeed = phydev->speed;
346 +               priv->oldlink = phydev->link;
347 +       }
348 +
349 +       /* If link status changed, show new status */
350 +       if (new_state)
351 +               phy_print_status(phydev);
352 +}
353 +
354 +static int mii_probe(struct net_device *dev)
355 +{
356 +       struct lq_mii_priv *priv = netdev_priv(dev);
357 +       struct phy_device *phydev = NULL;
358 +       int phy_addr;
359 +
360 +       priv->oldlink = 0;
361 +       priv->oldspeed = 0;
362 +       priv->oldduplex = -1;
363 +
364 +       /* find the first (lowest address) PHY on the current MAC's MII bus */
365 +       for (phy_addr = 0; phy_addr < PHY_MAX_ADDR; phy_addr++) {
366 +               if (priv->mii_bus->phy_map[phy_addr]) {
367 +                       phydev = priv->mii_bus->phy_map[phy_addr];
368 +                       break; /* break out with first one found */
369 +               }
370 +       }
371 +
372 +       if (!phydev) {
373 +               printk (KERN_ERR "%s: no PHY found\n", dev->name);
374 +               return -ENODEV;
375 +       }
376 +
377 +       /* now we are supposed to have a proper phydev, to attach to... */
378 +       BUG_ON(!phydev);
379 +       BUG_ON(phydev->attached_dev);
380 +
381 +       phydev = phy_connect(dev, dev_name(&phydev->dev), &lq_adjust_link,
382 +                       0, PHY_INTERFACE_MODE_MII);
383 +
384 +       if (IS_ERR(phydev)) {
385 +               printk(KERN_ERR "%s: Could not attach to PHY\n", dev->name);
386 +               return PTR_ERR(phydev);
387 +       }
388 +
389 +       /* mask with MAC supported features */
390 +       phydev->supported &= (SUPPORTED_10baseT_Half
391 +                             | SUPPORTED_10baseT_Full
392 +                             | SUPPORTED_100baseT_Half
393 +                             | SUPPORTED_100baseT_Full
394 +                             | SUPPORTED_Autoneg
395 +                             /* | SUPPORTED_Pause | SUPPORTED_Asym_Pause */
396 +                             | SUPPORTED_MII
397 +                             | SUPPORTED_TP);
398 +
399 +       phydev->advertising = phydev->supported;
400 +
401 +       priv->phydev = phydev;
402 +
403 +       printk(KERN_INFO "%s: attached PHY driver [%s] "
404 +              "(mii_bus:phy_addr=%s, irq=%d)\n",
405 +              dev->name, phydev->drv->name, dev_name(&phydev->dev), phydev->irq);
406 +
407 +       return 0;
408 +}
409 +
410 +
411 +static int lq_mii_dev_init(struct net_device *dev)
412 +{
413 +       int i;
414 +       struct lq_mii_priv *priv = (struct lq_mii_priv *)netdev_priv(dev);
415 +       ether_setup(dev);
416 +       dev->watchdog_timeo = 10 * HZ;
417 +       dev->mtu = 1500;
418 +       memset(priv, 0, sizeof(struct lq_mii_priv));
419 +       priv->dma_device = dma_device_reserve("PPE");
420 +       if (!priv->dma_device) {
421 +               BUG();
422 +               return -ENODEV;
423 +       }
424 +       priv->dma_device->buffer_alloc = &lq_etop_dma_buffer_alloc;
425 +       priv->dma_device->buffer_free = &lq_etop_dma_buffer_free;
426 +       priv->dma_device->intr_handler = &dma_intr_handler;
427 +       priv->dma_device->max_rx_chan_num = 4;
428 +
429 +       for (i = 0; i < priv->dma_device->max_rx_chan_num; i++) {
430 +               priv->dma_device->rx_chan[i]->packet_size = ETHERNET_PACKET_DMA_BUFFER_SIZE;
431 +               priv->dma_device->rx_chan[i]->control = LQ_DMA_CH_ON;
432 +       }
433 +
434 +       for (i = 0; i < priv->dma_device->max_tx_chan_num; i++)
435 +               if (i == 0)
436 +                       priv->dma_device->tx_chan[i]->control = LQ_DMA_CH_ON;
437 +               else
438 +                       priv->dma_device->tx_chan[i]->control = LQ_DMA_CH_OFF;
439 +
440 +       dma_device_register(priv->dma_device);
441 +
442 +       printk(KERN_INFO "%s: using mac=", dev->name);
443 +       for (i = 0; i < 6; i++) {
444 +               dev->dev_addr[i] = mac_addr[i];
445 +               printk("%02X%c", dev->dev_addr[i], (i == 5) ? ('\n') : (':'));
446 +       }
447 +
448 +       priv->mii_bus = mdiobus_alloc();
449 +       if (priv->mii_bus == NULL)
450 +               return -ENOMEM;
451 +
452 +       priv->mii_bus->priv = dev;
453 +       priv->mii_bus->read = lq_mdiobus_read;
454 +       priv->mii_bus->write = lq_mdiobus_write;
455 +       priv->mii_bus->name = "lq_mii";
456 +       snprintf(priv->mii_bus->id, MII_BUS_ID_SIZE, "%x", 0);
457 +       priv->mii_bus->irq = kmalloc(sizeof(int) * PHY_MAX_ADDR, GFP_KERNEL);
458 +       for(i = 0; i < PHY_MAX_ADDR; ++i)
459 +               priv->mii_bus->irq[i] = PHY_POLL;
460 +
461 +       mdiobus_register(priv->mii_bus);
462 +
463 +       return mii_probe(dev);
464 +}
465 +
466 +static void lq_mii_chip_init(int mode)
467 +{
468 +       lq_pmu_enable(PMU_DMA);
469 +       lq_pmu_enable(PMU_PPE);
470 +
471 +       if (mode == REV_MII_MODE)
472 +               lq_w32_mask(PPE32_MII_MASK, PPE32_MII_REVERSE, LQ_PPE32_CFG);
473 +       else if (mode == MII_MODE)
474 +               lq_w32_mask(PPE32_MII_MASK, PPE32_MII_NORMAL, LQ_PPE32_CFG);
475 +       lq_w32(PPE32_PLEN_UNDER | PPE32_PLEN_OVER, LQ_PPE32_IG_PLEN_CTRL);
476 +       lq_w32(PPE32_CGEN, LQ_PPE32_ENET_MAC_CFG);
477 +       wmb();
478 +}
479 +
480 +static int lq_mii_eth_mac_addr(struct net_device *dev, void *p)
481 +{
482 +       int retcode;
483 +
484 +       retcode = eth_mac_addr(dev, p);
485 +
486 +       if (retcode)
487 +               return retcode;
488 +
489 +       // set rx_addr for unicast filter
490 +       lq_w32(((dev->dev_addr[0]<<24)|(dev->dev_addr[1]<<16)|(dev->dev_addr[2]<< 8)|dev->dev_addr[3]), (u32*)(LQ_PPE32_BASE_ADDR|(0x461b<<2)));
491 +       lq_w32(((dev->dev_addr[4]<<24)|(dev->dev_addr[5]<<16)), (u32*)(LQ_PPE32_BASE_ADDR|(0x461c<<2)));
492 +
493 +       return 0;
494 +}
495 +
496 +static void lq_mii_set_rx_mode (struct net_device *dev)
497 +{
498 +       // rx_mode promisc: unset unicast filter
499 +       if ((dev->flags & IFF_PROMISC) || (dev->flags & IFF_ALLMULTI))
500 +               lq_w32(lq_r32((u32*)(LQ_PPE32_BASE_ADDR|(0x4614<<2))) & ~(1<<28), (u32*)(LQ_PPE32_BASE_ADDR|(0x4614<<2)));
501 +       // enable unicast filter
502 +       else
503 +               lq_w32(lq_r32((u32*)(LQ_PPE32_BASE_ADDR|(0x4614<<2))) | (1<<28), (u32*)(LQ_PPE32_BASE_ADDR|(0x4614<<2)));
504 +}
505 +
506 +static const struct net_device_ops lq_eth_netdev_ops = {
507 +       .ndo_init                               = lq_mii_dev_init,
508 +       .ndo_open                               = lq_mii_open,
509 +       .ndo_stop                               = lq_mii_release,
510 +       .ndo_start_xmit                 = lq_mii_tx,
511 +       .ndo_tx_timeout                 = lq_mii_tx_timeout,
512 +       .ndo_change_mtu                 = eth_change_mtu,
513 +       .ndo_set_mac_address    = lq_mii_eth_mac_addr,
514 +       .ndo_validate_addr              = eth_validate_addr,
515 +       .ndo_set_multicast_list = lq_mii_set_rx_mode,
516 +};
517 +
518 +static int
519 +lq_mii_probe(struct platform_device *dev)
520 +{
521 +       int result = 0;
522 +       struct lq_eth_data *eth = (struct lq_eth_data*)dev->dev.platform_data;
523 +       lq_etop_dev = alloc_etherdev(sizeof(struct lq_mii_priv));
524 +       lq_etop_dev->netdev_ops = &lq_eth_netdev_ops;
525 +       memcpy(mac_addr, eth->mac, 6);
526 +       strcpy(lq_etop_dev->name, "eth%d");
527 +       lq_mii_chip_init(eth->mii_mode);
528 +       result = register_netdev(lq_etop_dev);
529 +       if (result) {
530 +               printk(KERN_INFO "lq_etop: error %i registering device \"%s\"\n", result, lq_etop_dev->name);
531 +               goto out;
532 +       }
533 +
534 +       printk(KERN_INFO "lq_etop: driver loaded!\n");
535 +
536 +out:
537 +       return result;
538 +}
539 +
540 +static int lq_mii_remove(struct platform_device *dev)
541 +{
542 +       struct lq_mii_priv *priv = (struct lq_mii_priv *)netdev_priv(lq_etop_dev);
543 +
544 +       printk(KERN_INFO "lq_etop: lq_etop cleanup\n");
545 +
546 +       dma_device_unregister(priv->dma_device);
547 +       dma_device_release(priv->dma_device);
548 +       kfree(priv->dma_device);
549 +       unregister_netdev(lq_etop_dev);
550 +       return 0;
551 +}
552 +
553 +static struct platform_driver lq_mii_driver = {
554 +       .probe = lq_mii_probe,
555 +       .remove = lq_mii_remove,
556 +       .driver = {
557 +               .name = "lq_etop",
558 +               .owner = THIS_MODULE,
559 +       },
560 +};
561 +
562 +int __init lq_mii_init(void)
563 +{
564 +       int ret = platform_driver_register(&lq_mii_driver);
565 +       if (ret)
566 +               printk(KERN_INFO "lq_etop: Error registering platfom driver!");
567 +       return ret;
568 +}
569 +
570 +static void __exit lq_mii_cleanup(void)
571 +{
572 +       platform_driver_unregister(&lq_mii_driver);
573 +}
574 +
575 +module_init(lq_mii_init);
576 +module_exit(lq_mii_cleanup);
577 +
578 +MODULE_LICENSE("GPL");
579 +MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
580 +MODULE_DESCRIPTION("ethernet driver for IFXMIPS boards");