1 /************************************************************************
4 * Infineon Technologies AG
5 * St. Martin Strasse 53; 81669 Muenchen; Germany
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version
10 * 2 of the License, or (at your option) any later version.
12 ************************************************************************/
17 #define LTQ_DMA_CH_ON 1
18 #define LTQ_DMA_CH_OFF 0
19 #define LTQ_DMA_CH_DEFAULT_WEIGHT 100;
26 #define DMA_DESC_OWN_CPU 0x0
27 #define DMA_DESC_OWN_DMA 0x80000000
28 #define DMA_DESC_CPT_SET 0x40000000
29 #define DMA_DESC_SOP_SET 0x20000000
30 #define DMA_DESC_EOP_SET 0x10000000
35 #ifdef CONFIG_CPU_LITTLE_ENDIAN
36 volatile u32 data_length:16;
37 volatile u32 reserve2:7;
38 volatile u32 byte_offset:2;
39 volatile u32 reserve1:3;
49 volatile u32 reserve1:3;
50 volatile u32 byte_offset:2;
51 volatile u32 reserve2:7;
52 volatile u32 data_length:16;
59 volatile u32 data_pointer;
65 #ifdef CONFIG_CPU_LITTLE_ENDIAN
66 volatile u32 data_length:16;
67 volatile u32 reserved:7;
68 volatile u32 byte_offset:5;
78 volatile u32 byte_offset:5;
79 volatile u32 reserved:7;
80 volatile u32 data_length:16;
87 volatile u32 data_pointer;
90 /* DMA pseudo interrupts notified to switch driver */
92 #define TX_BUF_FULL_INT 0x02
93 #define TRANSMIT_CPT_INT 0x04
94 #define CHANNEL_CLOSED 0x10
96 /* Parameters for switch DMA device */
97 #define DEFAULT_SW_CHANNEL_WEIGHT 3
98 #define DEFAULT_SW_PORT_WEIGHT 7
100 #define DEFAULT_SW_TX_BURST_LEN 2 /* 2 words, 4 words, 8 words */
101 #define DEFAULT_SW_RX_BURST_LEN 2 /* 2 words, 4 words, 8 words */
103 #define DEFAULT_SW_TX_CHANNEL_NUM 4
104 #define DEFAULT_SW_RX_CHANNEL_NUM 4
106 #define DEFAULT_SW_TX_CHANNEL_DESCR_NUM 20
107 #define DEFAULT_SW_RX_CHANNEL_DESCR_NUM 20
109 /* Parameters for SSC DMA device */
110 #define DEFAULT_SSC_CHANNEL_WEIGHT 3
111 #define DEFAULT_SSC_PORT_WEIGHT 7
113 #define DEFAULT_SSC_TX_CHANNEL_CLASS 3
114 #define DEFAULT_SSC_RX_CHANNEL_CLASS 0
116 #define DEFAULT_SSC_TX_BURST_LEN 2 /* 2 words, 4 words, 8 words */
117 #define DEFAULT_SSC_RX_BURST_LEN 2 /* 2 words, 4 words, 8 words */
119 #define DEFAULT_SSC0_TX_CHANNEL_NUM 1
120 #define DEFAULT_SSC0_RX_CHANNEL_NUM 1
121 #define DEFAULT_SSC1_TX_CHANNEL_NUM 1
122 #define DEFAULT_SSC1_RX_CHANNEL_NUM 1
124 #define DEFAULT_SSC_TX_CHANNEL_DESCR_NUM 10
125 #define DEFAULT_SSC_RX_CHANNEL_DESCR_NUM 10
127 /* Parameters for memory DMA device */
128 #define DEFAULT_MEM_CHANNEL_WEIGHT 3
129 #define DEFAULT_MEM_PORT_WEIGHT 7
131 #define DEFAULT_MEM_TX_BURST_LEN 4 /* 2 words, 4 words, 8 words */
132 #define DEFAULT_MEM_RX_BURST_LEN 4 /* 2 words, 4 words, 8 words */
134 #define DEFAULT_MEM_TX_CHANNEL_NUM 1
135 #define DEFAULT_MEM_RX_CHANNEL_NUM 1
137 #define DEFAULT_MEM_TX_CHANNEL_DESCR_NUM 2
138 #define DEFAULT_MEM_RX_CHANNEL_DESCR_NUM 2
140 /* Parameters for DEU DMA device */
141 #define DEFAULT_DEU_CHANNEL_WEIGHT 1
142 #define DEFAULT_DEU_PORT_WEIGHT 1
144 #define DEFAULT_DEU_TX_BURST_LEN 4 /* 2 words, 4 words, 8 words */
145 #define DEFAULT_DEU_RX_BURST_LEN 4 /* 2 words, 4 words, 8 words */
147 #define DEFAULT_DEU_TX_CHANNEL_DESCR_NUM 20
148 #define DEFAULT_DEU_RX_CHANNEL_DESCR_NUM 20
150 #define DMA_DESCR_NUM 30 /* number of descriptors per channel */
157 struct dma_device_info;
159 struct dma_channel_info {
160 /*Pointer to the peripheral device who is using this channel*/
161 /*const*/ struct dma_device_info *dma_dev;
163 const enum dma_dir_t dir; /*RX or TX*/
164 /*class for this channel for QoS*/
168 /*relative channel number*/
169 const int rel_chan_no;
170 /*absolute channel number*/
173 /*specify byte_offset*/
177 /*descriptor parameter*/
181 int prev_desc;/*only used if it is a tx channel*/
183 /*weight setting for WFQ algorithm*/
189 /*status of this channel*/
190 int control; /*on or off*/
192 int dur; /*descriptor underrun*/
194 /**optional information for the upper layer devices*/
195 void *opt[DMA_DESCR_NUM];
197 /*channel operations*/
198 int (*open)(struct dma_channel_info *ch);
199 int (*close)(struct dma_channel_info *ch);
200 int (*reset)(struct dma_channel_info *ch);
201 void (*enable_irq)(struct dma_channel_info *ch);
202 void (*disable_irq)(struct dma_channel_info *ch);
206 struct dma_device_info {
207 /*device name of this peripheral*/
208 const char device_name[16];
209 const int max_rx_chan_num;
210 const int max_tx_chan_num;
223 int tx_endianness_mode;
224 int rx_endianness_mode;
225 struct dma_channel_info *tx_chan[4];
226 struct dma_channel_info *rx_chan[4];
228 /*functions, optional*/
229 u8 *(*buffer_alloc)(int len,int *offset, void **opt);
230 void (*buffer_free)(u8 *dataptr, void *opt);
231 int (*intr_handler)(struct dma_device_info *dma_dev, int status);
233 /* used by peripheral driver only */
237 struct dma_device_info *dma_device_reserve(char *dev_name);
238 int dma_device_release(struct dma_device_info *dma_dev);
239 int dma_device_register(struct dma_device_info *dma_dev);
240 int dma_device_unregister(struct dma_device_info *dma_dev);
241 int dma_device_read(struct dma_device_info *dma_dev, u8 **dataptr, void **opt);
242 int dma_device_write(struct dma_device_info *dma_dev, u8 *dataptr,