target/linux/ixp4xx/patches-2.6.25/200-npe_driver.patch

   1 diff --git a/drivers/net/arm/Kconfig b/drivers/net/arm/Kconfig
   2 index f9cc2b6..8eda6ee 100644
   3 --- a/drivers/net/arm/Kconfig
   4 +++ b/drivers/net/arm/Kconfig
   5 @@ -47,3 +47,11 @@ config EP93XX_ETH
   6         help
   7           This is a driver for the ethernet hardware included in EP93xx CPUs.
   8           Say Y if you are building a kernel for EP93xx based devices.
   9 +
  10 +config IXP4XX_ETH
  11 +       tristate "Intel IXP4xx Ethernet support"
  12 +       depends on ARM && ARCH_IXP4XX && IXP4XX_NPE && IXP4XX_QMGR
  13 +       select MII
  14 +       help
  15 +         Say Y here if you want to use built-in Ethernet ports
  16 +         on IXP4xx processor.
  17 diff --git a/drivers/net/arm/Makefile b/drivers/net/arm/Makefile
  18 index a4c8682..7c812ac 100644
  19 --- a/drivers/net/arm/Makefile
  20 +++ b/drivers/net/arm/Makefile
  21 @@ -9,3 +9,4 @@ obj-$(CONFIG_ARM_ETHER3)        += ether3.o
  22  obj-$(CONFIG_ARM_ETHER1)       += ether1.o
  23  obj-$(CONFIG_ARM_AT91_ETHER)   += at91_ether.o
  24  obj-$(CONFIG_EP93XX_ETH)       += ep93xx_eth.o
  25 +obj-$(CONFIG_IXP4XX_ETH)       += ixp4xx_eth.o
  26 diff --git a/drivers/net/arm/ixp4xx_eth.c b/drivers/net/arm/ixp4xx_eth.c
  27 new file mode 100644
  28 index 0000000..c617b64
  29 --- /dev/null
  30 +++ b/drivers/net/arm/ixp4xx_eth.c
  31 @@ -0,0 +1,1265 @@
  32 +/*
  33 + * Intel IXP4xx Ethernet driver for Linux
  34 + *
  35 + * Copyright (C) 2007 Krzysztof Halasa <khc@pm.waw.pl>
  36 + *
  37 + * This program is free software; you can redistribute it and/or modify it
  38 + * under the terms of version 2 of the GNU General Public License
  39 + * as published by the Free Software Foundation.
  40 + *
  41 + * Ethernet port config (0x00 is not present on IXP42X):
  42 + *
  43 + * logical port                0x00            0x10            0x20
  44 + * NPE                 0 (NPE-A)       1 (NPE-B)       2 (NPE-C)
  45 + * physical PortId     2               0               1
  46 + * TX queue            23              24              25
  47 + * RX-free queue       26              27              28
  48 + * TX-done queue is always 31, per-port RX and TX-ready queues are configurable
  49 + *
  50 + *
  51 + * Queue entries:
  52 + * bits 0 -> 1 - NPE ID (RX and TX-done)
  53 + * bits 0 -> 2 - priority (TX, per 802.1D)
  54 + * bits 3 -> 4 - port ID (user-set?)
  55 + * bits 5 -> 31        - physical descriptor address
  56 + */
  57 +
  58 +#include <linux/delay.h>
  59 +#include <linux/dma-mapping.h>
  60 +#include <linux/dmapool.h>
  61 +#include <linux/etherdevice.h>
  62 +#include <linux/io.h>
  63 +#include <linux/kernel.h>
  64 +#include <linux/mii.h>
  65 +#include <linux/platform_device.h>
  66 +#include <asm/arch/npe.h>
  67 +#include <asm/arch/qmgr.h>
  68 +
  69 +#define DEBUG_QUEUES           0
  70 +#define DEBUG_DESC             0
  71 +#define DEBUG_RX               0
  72 +#define DEBUG_TX               0
  73 +#define DEBUG_PKT_BYTES                0
  74 +#define DEBUG_MDIO             0
  75 +#define DEBUG_CLOSE            0
  76 +
  77 +#define DRV_NAME               "ixp4xx_eth"
  78 +
  79 +#define MAX_NPES               3
  80 +
  81 +#define RX_DESCS               64 /* also length of all RX queues */
  82 +#define TX_DESCS               16 /* also length of all TX queues */
  83 +#define TXDONE_QUEUE_LEN       64 /* dwords */
  84 +
  85 +#define POOL_ALLOC_SIZE                (sizeof(struct desc) * (RX_DESCS + TX_DESCS))
  86 +#define REGS_SIZE              0x1000
  87 +#define MAX_MRU                        1536 /* 0x600 */
  88 +#define RX_BUFF_SIZE           ALIGN((NET_IP_ALIGN) + MAX_MRU, 4)
  89 +
  90 +#define NAPI_WEIGHT            16
  91 +#define MDIO_INTERVAL          (3 * HZ)
  92 +#define MAX_MDIO_RETRIES       100 /* microseconds, typically 30 cycles */
  93 +#define MAX_MII_RESET_RETRIES  100 /* mdio_read() cycles, typically 4 */
  94 +#define MAX_CLOSE_WAIT         1000 /* microseconds, typically 2-3 cycles */
  95 +
  96 +#define NPE_ID(port_id)                ((port_id) >> 4)
  97 +#define PHYSICAL_ID(port_id)   ((NPE_ID(port_id) + 2) % 3)
  98 +#define TX_QUEUE(port_id)      (NPE_ID(port_id) + 23)
  99 +#define RXFREE_QUEUE(port_id)  (NPE_ID(port_id) + 26)
 100 +#define TXDONE_QUEUE           31
 101 +
 102 +/* TX Control Registers */
 103 +#define TX_CNTRL0_TX_EN                0x01
 104 +#define TX_CNTRL0_HALFDUPLEX   0x02
 105 +#define TX_CNTRL0_RETRY                0x04
 106 +#define TX_CNTRL0_PAD_EN       0x08
 107 +#define TX_CNTRL0_APPEND_FCS   0x10
 108 +#define TX_CNTRL0_2DEFER       0x20
 109 +#define TX_CNTRL0_RMII         0x40 /* reduced MII */
 110 +#define TX_CNTRL1_RETRIES      0x0F /* 4 bits */
 111 +
 112 +/* RX Control Registers */
 113 +#define RX_CNTRL0_RX_EN                0x01
 114 +#define RX_CNTRL0_PADSTRIP_EN  0x02
 115 +#define RX_CNTRL0_SEND_FCS     0x04
 116 +#define RX_CNTRL0_PAUSE_EN     0x08
 117 +#define RX_CNTRL0_LOOP_EN      0x10
 118 +#define RX_CNTRL0_ADDR_FLTR_EN 0x20
 119 +#define RX_CNTRL0_RX_RUNT_EN   0x40
 120 +#define RX_CNTRL0_BCAST_DIS    0x80
 121 +#define RX_CNTRL1_DEFER_EN     0x01
 122 +
 123 +/* Core Control Register */
 124 +#define CORE_RESET             0x01
 125 +#define CORE_RX_FIFO_FLUSH     0x02
 126 +#define CORE_TX_FIFO_FLUSH     0x04
 127 +#define CORE_SEND_JAM          0x08
 128 +#define CORE_MDC_EN            0x10 /* MDIO using NPE-B ETH-0 only */
 129 +
 130 +#define DEFAULT_TX_CNTRL0      (TX_CNTRL0_TX_EN | TX_CNTRL0_RETRY |    \
 131 +                                TX_CNTRL0_PAD_EN | TX_CNTRL0_APPEND_FCS | \
 132 +                                TX_CNTRL0_2DEFER)
 133 +#define DEFAULT_RX_CNTRL0      RX_CNTRL0_RX_EN
 134 +#define DEFAULT_CORE_CNTRL     CORE_MDC_EN
 135 +
 136 +
 137 +/* NPE message codes */
 138 +#define NPE_GETSTATUS                  0x00
 139 +#define NPE_EDB_SETPORTADDRESS         0x01
 140 +#define NPE_EDB_GETMACADDRESSDATABASE  0x02
 141 +#define NPE_EDB_SETMACADDRESSSDATABASE 0x03
 142 +#define NPE_GETSTATS                   0x04
 143 +#define NPE_RESETSTATS                 0x05
 144 +#define NPE_SETMAXFRAMELENGTHS         0x06
 145 +#define NPE_VLAN_SETRXTAGMODE          0x07
 146 +#define NPE_VLAN_SETDEFAULTRXVID       0x08
 147 +#define NPE_VLAN_SETPORTVLANTABLEENTRY 0x09
 148 +#define NPE_VLAN_SETPORTVLANTABLERANGE 0x0A
 149 +#define NPE_VLAN_SETRXQOSENTRY         0x0B
 150 +#define NPE_VLAN_SETPORTIDEXTRACTIONMODE 0x0C
 151 +#define NPE_STP_SETBLOCKINGSTATE       0x0D
 152 +#define NPE_FW_SETFIREWALLMODE         0x0E
 153 +#define NPE_PC_SETFRAMECONTROLDURATIONID 0x0F
 154 +#define NPE_PC_SETAPMACTABLE           0x11
 155 +#define NPE_SETLOOPBACK_MODE           0x12
 156 +#define NPE_PC_SETBSSIDTABLE           0x13
 157 +#define NPE_ADDRESS_FILTER_CONFIG      0x14
 158 +#define NPE_APPENDFCSCONFIG            0x15
 159 +#define NPE_NOTIFY_MAC_RECOVERY_DONE   0x16
 160 +#define NPE_MAC_RECOVERY_START         0x17
 161 +
 162 +
 163 +#ifdef __ARMEB__
 164 +typedef struct sk_buff buffer_t;
 165 +#define free_buffer dev_kfree_skb
 166 +#define free_buffer_irq dev_kfree_skb_irq
 167 +#else
 168 +typedef void buffer_t;
 169 +#define free_buffer kfree
 170 +#define free_buffer_irq kfree
 171 +#endif
 172 +
 173 +struct eth_regs {
 174 +       u32 tx_control[2], __res1[2];           /* 000 */
 175 +       u32 rx_control[2], __res2[2];           /* 010 */
 176 +       u32 random_seed, __res3[3];             /* 020 */
 177 +       u32 partial_empty_threshold, __res4;    /* 030 */
 178 +       u32 partial_full_threshold, __res5;     /* 038 */
 179 +       u32 tx_start_bytes, __res6[3];          /* 040 */
 180 +       u32 tx_deferral, rx_deferral, __res7[2];/* 050 */
 181 +       u32 tx_2part_deferral[2], __res8[2];    /* 060 */
 182 +       u32 slot_time, __res9[3];               /* 070 */
 183 +       u32 mdio_command[4];                    /* 080 */
 184 +       u32 mdio_status[4];                     /* 090 */
 185 +       u32 mcast_mask[6], __res10[2];          /* 0A0 */
 186 +       u32 mcast_addr[6], __res11[2];          /* 0C0 */
 187 +       u32 int_clock_threshold, __res12[3];    /* 0E0 */
 188 +       u32 hw_addr[6], __res13[61];            /* 0F0 */
 189 +       u32 core_control;                       /* 1FC */
 190 +};
 191 +
 192 +struct port {
 193 +       struct resource *mem_res;
 194 +       struct eth_regs __iomem *regs;
 195 +       struct npe *npe;
 196 +       struct net_device *netdev;
 197 +       struct napi_struct napi;
 198 +       struct net_device_stats stat;
 199 +       struct mii_if_info mii;
 200 +       struct delayed_work mdio_thread;
 201 +       struct eth_plat_info *plat;
 202 +       buffer_t *rx_buff_tab[RX_DESCS], *tx_buff_tab[TX_DESCS];
 203 +       struct desc *desc_tab;  /* coherent */
 204 +       u32 desc_tab_phys;
 205 +       int id;                 /* logical port ID */
 206 +       u16 mii_bmcr;
 207 +};
 208 +
 209 +/* NPE message structure */
 210 +struct msg {
 211 +#ifdef __ARMEB__
 212 +       u8 cmd, eth_id, byte2, byte3;
 213 +       u8 byte4, byte5, byte6, byte7;
 214 +#else
 215 +       u8 byte3, byte2, eth_id, cmd;
 216 +       u8 byte7, byte6, byte5, byte4;
 217 +#endif
 218 +};
 219 +
 220 +/* Ethernet packet descriptor */
 221 +struct desc {
 222 +       u32 next;               /* pointer to next buffer, unused */
 223 +
 224 +#ifdef __ARMEB__
 225 +       u16 buf_len;            /* buffer length */
 226 +       u16 pkt_len;            /* packet length */
 227 +       u32 data;               /* pointer to data buffer in RAM */
 228 +       u8 dest_id;
 229 +       u8 src_id;
 230 +       u16 flags;
 231 +       u8 qos;
 232 +       u8 padlen;
 233 +       u16 vlan_tci;
 234 +#else
 235 +       u16 pkt_len;            /* packet length */
 236 +       u16 buf_len;            /* buffer length */
 237 +       u32 data;               /* pointer to data buffer in RAM */
 238 +       u16 flags;
 239 +       u8 src_id;
 240 +       u8 dest_id;
 241 +       u16 vlan_tci;
 242 +       u8 padlen;
 243 +       u8 qos;
 244 +#endif
 245 +
 246 +#ifdef __ARMEB__
 247 +       u8 dst_mac_0, dst_mac_1, dst_mac_2, dst_mac_3;
 248 +       u8 dst_mac_4, dst_mac_5, src_mac_0, src_mac_1;
 249 +       u8 src_mac_2, src_mac_3, src_mac_4, src_mac_5;
 250 +#else
 251 +       u8 dst_mac_3, dst_mac_2, dst_mac_1, dst_mac_0;
 252 +       u8 src_mac_1, src_mac_0, dst_mac_5, dst_mac_4;
 253 +       u8 src_mac_5, src_mac_4, src_mac_3, src_mac_2;
 254 +#endif
 255 +};
 256 +
 257 +
 258 +#define rx_desc_phys(port, n)  ((port)->desc_tab_phys +                \
 259 +                                (n) * sizeof(struct desc))
 260 +#define rx_desc_ptr(port, n)   (&(port)->desc_tab[n])
 261 +
 262 +#define tx_desc_phys(port, n)  ((port)->desc_tab_phys +                \
 263 +                                ((n) + RX_DESCS) * sizeof(struct desc))
 264 +#define tx_desc_ptr(port, n)   (&(port)->desc_tab[(n) + RX_DESCS])
 265 +
 266 +#ifndef __ARMEB__
 267 +static inline void memcpy_swab32(u32 *dest, u32 *src, int cnt)
 268 +{
 269 +       int i;
 270 +       for (i = 0; i < cnt; i++)
 271 +               dest[i] = swab32(src[i]);
 272 +}
 273 +#endif
 274 +
 275 +static spinlock_t mdio_lock;
 276 +static struct eth_regs __iomem *mdio_regs; /* mdio command and status only */
 277 +static int ports_open;
 278 +static struct port *npe_port_tab[MAX_NPES];
 279 +static struct dma_pool *dma_pool;
 280 +
 281 +
 282 +static u16 mdio_cmd(struct net_device *dev, int phy_id, int location,
 283 +                   int write, u16 cmd)
 284 +{
 285 +       int cycles = 0;
 286 +
 287 +       if (__raw_readl(&mdio_regs->mdio_command[3]) & 0x80) {
 288 +               printk(KERN_ERR "%s: MII not ready to transmit\n", dev->name);
 289 +               return 0;
 290 +       }
 291 +
 292 +       if (write) {
 293 +               __raw_writel(cmd & 0xFF, &mdio_regs->mdio_command[0]);
 294 +               __raw_writel(cmd >> 8, &mdio_regs->mdio_command[1]);
 295 +       }
 296 +       __raw_writel(((phy_id << 5) | location) & 0xFF,
 297 +                    &mdio_regs->mdio_command[2]);
 298 +       __raw_writel((phy_id >> 3) | (write << 2) | 0x80 /* GO */,
 299 +                    &mdio_regs->mdio_command[3]);
 300 +
 301 +       while ((cycles < MAX_MDIO_RETRIES) &&
 302 +              (__raw_readl(&mdio_regs->mdio_command[3]) & 0x80)) {
 303 +               udelay(1);
 304 +               cycles++;
 305 +       }
 306 +
 307 +       if (cycles == MAX_MDIO_RETRIES) {
 308 +               printk(KERN_ERR "%s: MII write failed\n", dev->name);
 309 +               return 0;
 310 +       }
 311 +
 312 +#if DEBUG_MDIO
 313 +       printk(KERN_DEBUG "%s: mdio_cmd() took %i cycles\n", dev->name,
 314 +              cycles);
 315 +#endif
 316 +
 317 +       if (write)
 318 +               return 0;
 319 +
 320 +       if (__raw_readl(&mdio_regs->mdio_status[3]) & 0x80) {
 321 +               printk(KERN_ERR "%s: MII read failed\n", dev->name);
 322 +               return 0;
 323 +       }
 324 +
 325 +       return (__raw_readl(&mdio_regs->mdio_status[0]) & 0xFF) |
 326 +               (__raw_readl(&mdio_regs->mdio_status[1]) << 8);
 327 +}
 328 +
 329 +static int mdio_read(struct net_device *dev, int phy_id, int location)
 330 +{
 331 +       unsigned long flags;
 332 +       u16 val;
 333 +
 334 +       spin_lock_irqsave(&mdio_lock, flags);
 335 +       val = mdio_cmd(dev, phy_id, location, 0, 0);
 336 +       spin_unlock_irqrestore(&mdio_lock, flags);
 337 +       return val;
 338 +}
 339 +
 340 +static void mdio_write(struct net_device *dev, int phy_id, int location,
 341 +                      int val)
 342 +{
 343 +       unsigned long flags;
 344 +
 345 +       spin_lock_irqsave(&mdio_lock, flags);
 346 +       mdio_cmd(dev, phy_id, location, 1, val);
 347 +       spin_unlock_irqrestore(&mdio_lock, flags);
 348 +}
 349 +
 350 +static void phy_reset(struct net_device *dev, int phy_id)
 351 +{
 352 +       struct port *port = netdev_priv(dev);
 353 +       int cycles = 0;
 354 +
 355 +       mdio_write(dev, phy_id, MII_BMCR, port->mii_bmcr | BMCR_RESET);
 356 +
 357 +       while (cycles < MAX_MII_RESET_RETRIES) {
 358 +               if (!(mdio_read(dev, phy_id, MII_BMCR) & BMCR_RESET)) {
 359 +#if DEBUG_MDIO
 360 +                       printk(KERN_DEBUG "%s: phy_reset() took %i cycles\n",
 361 +                              dev->name, cycles);
 362 +#endif
 363 +                       return;
 364 +               }
 365 +               udelay(1);
 366 +               cycles++;
 367 +       }
 368 +
 369 +       printk(KERN_ERR "%s: MII reset failed\n", dev->name);
 370 +}
 371 +
 372 +static void eth_set_duplex(struct port *port)
 373 +{
 374 +       if (port->mii.full_duplex)
 375 +               __raw_writel(DEFAULT_TX_CNTRL0 & ~TX_CNTRL0_HALFDUPLEX,
 376 +                            &port->regs->tx_control[0]);
 377 +       else
 378 +               __raw_writel(DEFAULT_TX_CNTRL0 | TX_CNTRL0_HALFDUPLEX,
 379 +                            &port->regs->tx_control[0]);
 380 +}
 381 +
 382 +
 383 +static void phy_check_media(struct port *port, int init)
 384 +{
 385 +       if (mii_check_media(&port->mii, 1, init))
 386 +               eth_set_duplex(port);
 387 +       if (port->mii.force_media) { /* mii_check_media() doesn't work */
 388 +               struct net_device *dev = port->netdev;
 389 +               int cur_link = mii_link_ok(&port->mii);
 390 +               int prev_link = netif_carrier_ok(dev);
 391 +
 392 +               if (!prev_link && cur_link) {
 393 +                       printk(KERN_INFO "%s: link up\n", dev->name);
 394 +                       netif_carrier_on(dev);
 395 +               } else if (prev_link && !cur_link) {
 396 +                       printk(KERN_INFO "%s: link down\n", dev->name);
 397 +                       netif_carrier_off(dev);
 398 +               }
 399 +       }
 400 +}
 401 +
 402 +
 403 +static void mdio_thread(struct work_struct *work)
 404 +{
 405 +       struct port *port = container_of(work, struct port, mdio_thread.work);
 406 +
 407 +       phy_check_media(port, 0);
 408 +       schedule_delayed_work(&port->mdio_thread, MDIO_INTERVAL);
 409 +}
 410 +
 411 +
 412 +static inline void debug_pkt(struct net_device *dev, const char *func,
 413 +                            u8 *data, int len)
 414 +{
 415 +#if DEBUG_PKT_BYTES
 416 +       int i;
 417 +
 418 +       printk(KERN_DEBUG "%s: %s(%i) ", dev->name, func, len);
 419 +       for (i = 0; i < len; i++) {
 420 +               if (i >= DEBUG_PKT_BYTES)
 421 +                       break;
 422 +               printk("%s%02X",
 423 +                      ((i == 6) || (i == 12) || (i >= 14)) ? " " : "",
 424 +                      data[i]);
 425 +       }
 426 +       printk("\n");
 427 +#endif
 428 +}
 429 +
 430 +
 431 +static inline void debug_desc(u32 phys, struct desc *desc)
 432 +{
 433 +#if DEBUG_DESC
 434 +       printk(KERN_DEBUG "%X: %X %3X %3X %08X %2X < %2X %4X %X"
 435 +              " %X %X %02X%02X%02X%02X%02X%02X < %02X%02X%02X%02X%02X%02X\n",
 436 +              phys, desc->next, desc->buf_len, desc->pkt_len,
 437 +              desc->data, desc->dest_id, desc->src_id, desc->flags,
 438 +              desc->qos, desc->padlen, desc->vlan_tci,
 439 +              desc->dst_mac_0, desc->dst_mac_1, desc->dst_mac_2,
 440 +              desc->dst_mac_3, desc->dst_mac_4, desc->dst_mac_5,
 441 +              desc->src_mac_0, desc->src_mac_1, desc->src_mac_2,
 442 +              desc->src_mac_3, desc->src_mac_4, desc->src_mac_5);
 443 +#endif
 444 +}
 445 +
 446 +static inline void debug_queue(unsigned int queue, int is_get, u32 phys)
 447 +{
 448 +#if DEBUG_QUEUES
 449 +       static struct {
 450 +               int queue;
 451 +               char *name;
 452 +       } names[] = {
 453 +               { TX_QUEUE(0x10), "TX#0 " },
 454 +               { TX_QUEUE(0x20), "TX#1 " },
 455 +               { TX_QUEUE(0x00), "TX#2 " },
 456 +               { RXFREE_QUEUE(0x10), "RX-free#0 " },
 457 +               { RXFREE_QUEUE(0x20), "RX-free#1 " },
 458 +               { RXFREE_QUEUE(0x00), "RX-free#2 " },
 459 +               { TXDONE_QUEUE, "TX-done " },
 460 +       };
 461 +       int i;
 462 +
 463 +       for (i = 0; i < ARRAY_SIZE(names); i++)
 464 +               if (names[i].queue == queue)
 465 +                       break;
 466 +
 467 +       printk(KERN_DEBUG "Queue %i %s%s %X\n", queue,
 468 +              i < ARRAY_SIZE(names) ? names[i].name : "",
 469 +              is_get ? "->" : "<-", phys);
 470 +#endif
 471 +}
 472 +
 473 +static inline u32 queue_get_entry(unsigned int queue)
 474 +{
 475 +       u32 phys = qmgr_get_entry(queue);
 476 +       debug_queue(queue, 1, phys);
 477 +       return phys;
 478 +}
 479 +
 480 +static inline int queue_get_desc(unsigned int queue, struct port *port,
 481 +                                int is_tx)
 482 +{
 483 +       u32 phys, tab_phys, n_desc;
 484 +       struct desc *tab;
 485 +
 486 +       if (!(phys = queue_get_entry(queue)))
 487 +               return -1;
 488 +
 489 +       phys &= ~0x1F; /* mask out non-address bits */
 490 +       tab_phys = is_tx ? tx_desc_phys(port, 0) : rx_desc_phys(port, 0);
 491 +       tab = is_tx ? tx_desc_ptr(port, 0) : rx_desc_ptr(port, 0);
 492 +       n_desc = (phys - tab_phys) / sizeof(struct desc);
 493 +       BUG_ON(n_desc >= (is_tx ? TX_DESCS : RX_DESCS));
 494 +       debug_desc(phys, &tab[n_desc]);
 495 +       BUG_ON(tab[n_desc].next);
 496 +       return n_desc;
 497 +}
 498 +
 499 +static inline void queue_put_desc(unsigned int queue, u32 phys,
 500 +                                 struct desc *desc)
 501 +{
 502 +       debug_queue(queue, 0, phys);
 503 +       debug_desc(phys, desc);
 504 +       BUG_ON(phys & 0x1F);
 505 +       qmgr_put_entry(queue, phys);
 506 +       BUG_ON(qmgr_stat_overflow(queue));
 507 +}
 508 +
 509 +
 510 +static inline void dma_unmap_tx(struct port *port, struct desc *desc)
 511 +{
 512 +#ifdef __ARMEB__
 513 +       dma_unmap_single(&port->netdev->dev, desc->data,
 514 +                        desc->buf_len, DMA_TO_DEVICE);
 515 +#else
 516 +       dma_unmap_single(&port->netdev->dev, desc->data & ~3,
 517 +                        ALIGN((desc->data & 3) + desc->buf_len, 4),
 518 +                        DMA_TO_DEVICE);
 519 +#endif
 520 +}
 521 +
 522 +
 523 +static void eth_rx_irq(void *pdev)
 524 +{
 525 +       struct net_device *dev = pdev;
 526 +       struct port *port = netdev_priv(dev);
 527 +
 528 +#if DEBUG_RX
 529 +       printk(KERN_DEBUG "%s: eth_rx_irq\n", dev->name);
 530 +#endif
 531 +       qmgr_disable_irq(port->plat->rxq);
 532 +       netif_rx_schedule(dev, &port->napi);
 533 +}
 534 +
 535 +static int eth_poll(struct napi_struct *napi, int budget)
 536 +{
 537 +       struct port *port = container_of(napi, struct port, napi);
 538 +       struct net_device *dev = port->netdev;
 539 +       unsigned int rxq = port->plat->rxq, rxfreeq = RXFREE_QUEUE(port->id);
 540 +       int received = 0;
 541 +
 542 +#if DEBUG_RX
 543 +       printk(KERN_DEBUG "%s: eth_poll\n", dev->name);
 544 +#endif
 545 +
 546 +       while (received < budget) {
 547 +               struct sk_buff *skb;
 548 +               struct desc *desc;
 549 +               int n;
 550 +#ifdef __ARMEB__
 551 +               struct sk_buff *temp;
 552 +               u32 phys;
 553 +#endif
 554 +
 555 +               if ((n = queue_get_desc(rxq, port, 0)) < 0) {
 556 +                       received = 0; /* No packet received */
 557 +#if DEBUG_RX
 558 +                       printk(KERN_DEBUG "%s: eth_poll netif_rx_complete\n",
 559 +                              dev->name);
 560 +#endif
 561 +                       netif_rx_complete(dev, napi);
 562 +                       qmgr_enable_irq(rxq);
 563 +                       if (!qmgr_stat_empty(rxq) &&
 564 +                           netif_rx_reschedule(dev, napi)) {
 565 +#if DEBUG_RX
 566 +                               printk(KERN_DEBUG "%s: eth_poll"
 567 +                                      " netif_rx_reschedule successed\n",
 568 +                                      dev->name);
 569 +#endif
 570 +                               qmgr_disable_irq(rxq);
 571 +                               continue;
 572 +                       }
 573 +#if DEBUG_RX
 574 +                       printk(KERN_DEBUG "%s: eth_poll all done\n",
 575 +                              dev->name);
 576 +#endif
 577 +                       return 0; /* all work done */
 578 +               }
 579 +
 580 +               desc = rx_desc_ptr(port, n);
 581 +
 582 +#ifdef __ARMEB__
 583 +               if ((skb = netdev_alloc_skb(dev, RX_BUFF_SIZE))) {
 584 +                       phys = dma_map_single(&dev->dev, skb->data,
 585 +                                             RX_BUFF_SIZE, DMA_FROM_DEVICE);
 586 +                       if (dma_mapping_error(phys)) {
 587 +                               dev_kfree_skb(skb);
 588 +                               skb = NULL;
 589 +                       }
 590 +               }
 591 +#else
 592 +               skb = netdev_alloc_skb(dev,
 593 +                                      ALIGN(NET_IP_ALIGN + desc->pkt_len, 4));
 594 +#endif
 595 +
 596 +               if (!skb) {
 597 +                       port->stat.rx_dropped++;
 598 +                       /* put the desc back on RX-ready queue */
 599 +                       desc->buf_len = MAX_MRU;
 600 +                       desc->pkt_len = 0;
 601 +                       queue_put_desc(rxfreeq, rx_desc_phys(port, n), desc);
 602 +                       continue;
 603 +               }
 604 +
 605 +               /* process received frame */
 606 +#ifdef __ARMEB__
 607 +               temp = skb;
 608 +               skb = port->rx_buff_tab[n];
 609 +               dma_unmap_single(&dev->dev, desc->data - NET_IP_ALIGN,
 610 +                                RX_BUFF_SIZE, DMA_FROM_DEVICE);
 611 +#else
 612 +               dma_sync_single(&dev->dev, desc->data - NET_IP_ALIGN,
 613 +                               RX_BUFF_SIZE, DMA_FROM_DEVICE);
 614 +               memcpy_swab32((u32 *)skb->data, (u32 *)port->rx_buff_tab[n],
 615 +                             ALIGN(NET_IP_ALIGN + desc->pkt_len, 4) / 4);
 616 +#endif
 617 +               skb_reserve(skb, NET_IP_ALIGN);
 618 +               skb_put(skb, desc->pkt_len);
 619 +
 620 +               debug_pkt(dev, "eth_poll", skb->data, skb->len);
 621 +
 622 +               skb->protocol = eth_type_trans(skb, dev);
 623 +               dev->last_rx = jiffies;
 624 +               port->stat.rx_packets++;
 625 +               port->stat.rx_bytes += skb->len;
 626 +               netif_receive_skb(skb);
 627 +
 628 +               /* put the new buffer on RX-free queue */
 629 +#ifdef __ARMEB__
 630 +               port->rx_buff_tab[n] = temp;
 631 +               desc->data = phys + NET_IP_ALIGN;
 632 +#endif
 633 +               desc->buf_len = MAX_MRU;
 634 +               desc->pkt_len = 0;
 635 +               queue_put_desc(rxfreeq, rx_desc_phys(port, n), desc);
 636 +               received++;
 637 +       }
 638 +
 639 +#if DEBUG_RX
 640 +       printk(KERN_DEBUG "eth_poll(): end, not all work done\n");
 641 +#endif
 642 +       return received;                /* not all work done */
 643 +}
 644 +
 645 +
 646 +static void eth_txdone_irq(void *unused)
 647 +{
 648 +       u32 phys;
 649 +
 650 +#if DEBUG_TX
 651 +       printk(KERN_DEBUG DRV_NAME ": eth_txdone_irq\n");
 652 +#endif
 653 +       while ((phys = queue_get_entry(TXDONE_QUEUE)) != 0) {
 654 +               u32 npe_id, n_desc;
 655 +               struct port *port;
 656 +               struct desc *desc;
 657 +               int start;
 658 +
 659 +               npe_id = phys & 3;
 660 +               BUG_ON(npe_id >= MAX_NPES);
 661 +               port = npe_port_tab[npe_id];
 662 +               BUG_ON(!port);
 663 +               phys &= ~0x1F; /* mask out non-address bits */
 664 +               n_desc = (phys - tx_desc_phys(port, 0)) / sizeof(struct desc);
 665 +               BUG_ON(n_desc >= TX_DESCS);
 666 +               desc = tx_desc_ptr(port, n_desc);
 667 +               debug_desc(phys, desc);
 668 +
 669 +               if (port->tx_buff_tab[n_desc]) { /* not the draining packet */
 670 +                       port->stat.tx_packets++;
 671 +                       port->stat.tx_bytes += desc->pkt_len;
 672 +
 673 +                       dma_unmap_tx(port, desc);
 674 +#if DEBUG_TX
 675 +                       printk(KERN_DEBUG "%s: eth_txdone_irq free %p\n",
 676 +                              port->netdev->name, port->tx_buff_tab[n_desc]);
 677 +#endif
 678 +                       free_buffer_irq(port->tx_buff_tab[n_desc]);
 679 +                       port->tx_buff_tab[n_desc] = NULL;
 680 +               }
 681 +
 682 +               start = qmgr_stat_empty(port->plat->txreadyq);
 683 +               queue_put_desc(port->plat->txreadyq, phys, desc);
 684 +               if (start) {
 685 +#if DEBUG_TX
 686 +                       printk(KERN_DEBUG "%s: eth_txdone_irq xmit ready\n",
 687 +                              port->netdev->name);
 688 +#endif
 689 +                       netif_wake_queue(port->netdev);
 690 +               }
 691 +       }
 692 +}
 693 +
 694 +static int eth_xmit(struct sk_buff *skb, struct net_device *dev)
 695 +{
 696 +       struct port *port = netdev_priv(dev);
 697 +       unsigned int txreadyq = port->plat->txreadyq;
 698 +       int len, offset, bytes, n;
 699 +       void *mem;
 700 +       u32 phys;
 701 +       struct desc *desc;
 702 +
 703 +#if DEBUG_TX
 704 +       printk(KERN_DEBUG "%s: eth_xmit\n", dev->name);
 705 +#endif
 706 +
 707 +       if (unlikely(skb->len > MAX_MRU)) {
 708 +               dev_kfree_skb(skb);
 709 +               port->stat.tx_errors++;
 710 +               return NETDEV_TX_OK;
 711 +       }
 712 +
 713 +       debug_pkt(dev, "eth_xmit", skb->data, skb->len);
 714 +
 715 +       len = skb->len;
 716 +#ifdef __ARMEB__
 717 +       offset = 0; /* no need to keep alignment */
 718 +       bytes = len;
 719 +       mem = skb->data;
 720 +#else
 721 +       offset = (int)skb->data & 3; /* keep 32-bit alignment */
 722 +       bytes = ALIGN(offset + len, 4);
 723 +       if (!(mem = kmalloc(bytes, GFP_ATOMIC))) {
 724 +               dev_kfree_skb(skb);
 725 +               port->stat.tx_dropped++;
 726 +               return NETDEV_TX_OK;
 727 +       }
 728 +       memcpy_swab32(mem, (u32 *)((int)skb->data & ~3), bytes / 4);
 729 +       dev_kfree_skb(skb);
 730 +#endif
 731 +
 732 +       phys = dma_map_single(&dev->dev, mem, bytes, DMA_TO_DEVICE);
 733 +       if (dma_mapping_error(phys)) {
 734 +#ifdef __ARMEB__
 735 +               dev_kfree_skb(skb);
 736 +#else
 737 +               kfree(mem);
 738 +#endif
 739 +               port->stat.tx_dropped++;
 740 +               return NETDEV_TX_OK;
 741 +       }
 742 +
 743 +       n = queue_get_desc(txreadyq, port, 1);
 744 +       BUG_ON(n < 0);
 745 +       desc = tx_desc_ptr(port, n);
 746 +
 747 +#ifdef __ARMEB__
 748 +       port->tx_buff_tab[n] = skb;
 749 +#else
 750 +       port->tx_buff_tab[n] = mem;
 751 +#endif
 752 +       desc->data = phys + offset;
 753 +       desc->buf_len = desc->pkt_len = len;
 754 +
 755 +       /* NPE firmware pads short frames with zeros internally */
 756 +       wmb();
 757 +       queue_put_desc(TX_QUEUE(port->id), tx_desc_phys(port, n), desc);
 758 +       dev->trans_start = jiffies;
 759 +
 760 +       if (qmgr_stat_empty(txreadyq)) {
 761 +#if DEBUG_TX
 762 +               printk(KERN_DEBUG "%s: eth_xmit queue full\n", dev->name);
 763 +#endif
 764 +               netif_stop_queue(dev);
 765 +               /* we could miss TX ready interrupt */
 766 +               if (!qmgr_stat_empty(txreadyq)) {
 767 +#if DEBUG_TX
 768 +                       printk(KERN_DEBUG "%s: eth_xmit ready again\n",
 769 +                              dev->name);
 770 +#endif
 771 +                       netif_wake_queue(dev);
 772 +               }
 773 +       }
 774 +
 775 +#if DEBUG_TX
 776 +       printk(KERN_DEBUG "%s: eth_xmit end\n", dev->name);
 777 +#endif
 778 +       return NETDEV_TX_OK;
 779 +}
 780 +
 781 +
 782 +static struct net_device_stats *eth_stats(struct net_device *dev)
 783 +{
 784 +       struct port *port = netdev_priv(dev);
 785 +       return &port->stat;
 786 +}
 787 +
 788 +static void eth_set_mcast_list(struct net_device *dev)
 789 +{
 790 +       struct port *port = netdev_priv(dev);
 791 +       struct dev_mc_list *mclist = dev->mc_list;
 792 +       u8 diffs[ETH_ALEN], *addr;
 793 +       int cnt = dev->mc_count, i;
 794 +
 795 +       if ((dev->flags & IFF_PROMISC) || !mclist || !cnt) {
 796 +               __raw_writel(DEFAULT_RX_CNTRL0 & ~RX_CNTRL0_ADDR_FLTR_EN,
 797 +                            &port->regs->rx_control[0]);
 798 +               return;
 799 +       }
 800 +
 801 +       memset(diffs, 0, ETH_ALEN);
 802 +       addr = mclist->dmi_addr; /* first MAC address */
 803 +
 804 +       while (--cnt && (mclist = mclist->next))
 805 +               for (i = 0; i < ETH_ALEN; i++)
 806 +                       diffs[i] |= addr[i] ^ mclist->dmi_addr[i];
 807 +
 808 +       for (i = 0; i < ETH_ALEN; i++) {
 809 +               __raw_writel(addr[i], &port->regs->mcast_addr[i]);
 810 +               __raw_writel(~diffs[i], &port->regs->mcast_mask[i]);
 811 +       }
 812 +
 813 +       __raw_writel(DEFAULT_RX_CNTRL0 | RX_CNTRL0_ADDR_FLTR_EN,
 814 +                    &port->regs->rx_control[0]);
 815 +}
 816 +
 817 +
 818 +static int eth_ioctl(struct net_device *dev, struct ifreq *req, int cmd)
 819 +{
 820 +       struct port *port = netdev_priv(dev);
 821 +       unsigned int duplex_chg;
 822 +       int err;
 823 +
 824 +       if (!netif_running(dev))
 825 +               return -EINVAL;
 826 +       err = generic_mii_ioctl(&port->mii, if_mii(req), cmd, &duplex_chg);
 827 +       if (duplex_chg)
 828 +               eth_set_duplex(port);
 829 +       return err;
 830 +}
 831 +
 832 +
 833 +static int request_queues(struct port *port)
 834 +{
 835 +       int err;
 836 +
 837 +       err = qmgr_request_queue(RXFREE_QUEUE(port->id), RX_DESCS, 0, 0);
 838 +       if (err)
 839 +               return err;
 840 +
 841 +       err = qmgr_request_queue(port->plat->rxq, RX_DESCS, 0, 0);
 842 +       if (err)
 843 +               goto rel_rxfree;
 844 +
 845 +       err = qmgr_request_queue(TX_QUEUE(port->id), TX_DESCS, 0, 0);
 846 +       if (err)
 847 +               goto rel_rx;
 848 +
 849 +       err = qmgr_request_queue(port->plat->txreadyq, TX_DESCS, 0, 0);
 850 +       if (err)
 851 +               goto rel_tx;
 852 +
 853 +       /* TX-done queue handles skbs sent out by the NPEs */
 854 +       if (!ports_open) {
 855 +               err = qmgr_request_queue(TXDONE_QUEUE, TXDONE_QUEUE_LEN, 0, 0);
 856 +               if (err)
 857 +                       goto rel_txready;
 858 +       }
 859 +       return 0;
 860 +
 861 +rel_txready:
 862 +       qmgr_release_queue(port->plat->txreadyq);
 863 +rel_tx:
 864 +       qmgr_release_queue(TX_QUEUE(port->id));
 865 +rel_rx:
 866 +       qmgr_release_queue(port->plat->rxq);
 867 +rel_rxfree:
 868 +       qmgr_release_queue(RXFREE_QUEUE(port->id));
 869 +       printk(KERN_DEBUG "%s: unable to request hardware queues\n",
 870 +              port->netdev->name);
 871 +       return err;
 872 +}
 873 +
 874 +static void release_queues(struct port *port)
 875 +{
 876 +       qmgr_release_queue(RXFREE_QUEUE(port->id));
 877 +       qmgr_release_queue(port->plat->rxq);
 878 +       qmgr_release_queue(TX_QUEUE(port->id));
 879 +       qmgr_release_queue(port->plat->txreadyq);
 880 +
 881 +       if (!ports_open)
 882 +               qmgr_release_queue(TXDONE_QUEUE);
 883 +}
 884 +
 885 +static int init_queues(struct port *port)
 886 +{
 887 +       int i;
 888 +
 889 +       if (!ports_open)
 890 +               if (!(dma_pool = dma_pool_create(DRV_NAME, NULL,
 891 +                                                POOL_ALLOC_SIZE, 32, 0)))
 892 +                       return -ENOMEM;
 893 +
 894 +       if (!(port->desc_tab = dma_pool_alloc(dma_pool, GFP_KERNEL,
 895 +                                             &port->desc_tab_phys)))
 896 +               return -ENOMEM;
 897 +       memset(port->desc_tab, 0, POOL_ALLOC_SIZE);
 898 +       memset(port->rx_buff_tab, 0, sizeof(port->rx_buff_tab)); /* tables */
 899 +       memset(port->tx_buff_tab, 0, sizeof(port->tx_buff_tab));
 900 +
 901 +       /* Setup RX buffers */
 902 +       for (i = 0; i < RX_DESCS; i++) {
 903 +               struct desc *desc = rx_desc_ptr(port, i);
 904 +               buffer_t *buff; /* skb or kmalloc()ated memory */
 905 +               void *data;
 906 +#ifdef __ARMEB__
 907 +               if (!(buff = netdev_alloc_skb(port->netdev, RX_BUFF_SIZE)))
 908 +                       return -ENOMEM;
 909 +               data = buff->data;
 910 +#else
 911 +               if (!(buff = kmalloc(RX_BUFF_SIZE, GFP_KERNEL)))
 912 +                       return -ENOMEM;
 913 +               data = buff;
 914 +#endif
 915 +               desc->buf_len = MAX_MRU;
 916 +               desc->data = dma_map_single(&port->netdev->dev, data,
 917 +                                           RX_BUFF_SIZE, DMA_FROM_DEVICE);
 918 +               if (dma_mapping_error(desc->data)) {
 919 +                       free_buffer(buff);
 920 +                       return -EIO;
 921 +               }
 922 +               desc->data += NET_IP_ALIGN;
 923 +               port->rx_buff_tab[i] = buff;
 924 +       }
 925 +
 926 +       return 0;
 927 +}
 928 +
 929 +static void destroy_queues(struct port *port)
 930 +{
 931 +       int i;
 932 +
 933 +       if (port->desc_tab) {
 934 +               for (i = 0; i < RX_DESCS; i++) {
 935 +                       struct desc *desc = rx_desc_ptr(port, i);
 936 +                       buffer_t *buff = port->rx_buff_tab[i];
 937 +                       if (buff) {
 938 +                               dma_unmap_single(&port->netdev->dev,
 939 +                                                desc->data - NET_IP_ALIGN,
 940 +                                                RX_BUFF_SIZE, DMA_FROM_DEVICE);
 941 +                               free_buffer(buff);
 942 +                       }
 943 +               }
 944 +               for (i = 0; i < TX_DESCS; i++) {
 945 +                       struct desc *desc = tx_desc_ptr(port, i);
 946 +                       buffer_t *buff = port->tx_buff_tab[i];
 947 +                       if (buff) {
 948 +                               dma_unmap_tx(port, desc);
 949 +                               free_buffer(buff);
 950 +                       }
 951 +               }
 952 +               dma_pool_free(dma_pool, port->desc_tab, port->desc_tab_phys);
 953 +               port->desc_tab = NULL;
 954 +       }
 955 +
 956 +       if (!ports_open && dma_pool) {
 957 +               dma_pool_destroy(dma_pool);
 958 +               dma_pool = NULL;
 959 +       }
 960 +}
 961 +
 962 +static int eth_open(struct net_device *dev)
 963 +{
 964 +       struct port *port = netdev_priv(dev);
 965 +       struct npe *npe = port->npe;
 966 +       struct msg msg;
 967 +       int i, err;
 968 +
 969 +       if (!npe_running(npe)) {
 970 +               err = npe_load_firmware(npe, npe_name(npe), &dev->dev);
 971 +               if (err)
 972 +                       return err;
 973 +
 974 +               if (npe_recv_message(npe, &msg, "ETH_GET_STATUS")) {
 975 +                       printk(KERN_ERR "%s: %s not responding\n", dev->name,
 976 +                              npe_name(npe));
 977 +                       return -EIO;
 978 +               }
 979 +       }
 980 +
 981 +       mdio_write(dev, port->plat->phy, MII_BMCR, port->mii_bmcr);
 982 +
 983 +       memset(&msg, 0, sizeof(msg));
 984 +       msg.cmd = NPE_VLAN_SETRXQOSENTRY;
 985 +       msg.eth_id = port->id;
 986 +       msg.byte5 = port->plat->rxq | 0x80;
 987 +       msg.byte7 = port->plat->rxq << 4;
 988 +       for (i = 0; i < 8; i++) {
 989 +               msg.byte3 = i;
 990 +               if (npe_send_recv_message(port->npe, &msg, "ETH_SET_RXQ"))
 991 +                       return -EIO;
 992 +       }
 993 +
 994 +       msg.cmd = NPE_EDB_SETPORTADDRESS;
 995 +       msg.eth_id = PHYSICAL_ID(port->id);
 996 +       msg.byte2 = dev->dev_addr[0];
 997 +       msg.byte3 = dev->dev_addr[1];
 998 +       msg.byte4 = dev->dev_addr[2];
 999 +       msg.byte5 = dev->dev_addr[3];
1000 +       msg.byte6 = dev->dev_addr[4];
1001 +       msg.byte7 = dev->dev_addr[5];
1002 +       if (npe_send_recv_message(port->npe, &msg, "ETH_SET_MAC"))
1003 +               return -EIO;
1004 +
1005 +       memset(&msg, 0, sizeof(msg));
1006 +       msg.cmd = NPE_FW_SETFIREWALLMODE;
1007 +       msg.eth_id = port->id;
1008 +       if (npe_send_recv_message(port->npe, &msg, "ETH_SET_FIREWALL_MODE"))
1009 +               return -EIO;
1010 +
1011 +       if ((err = request_queues(port)) != 0)
1012 +               return err;
1013 +
1014 +       if ((err = init_queues(port)) != 0) {
1015 +               destroy_queues(port);
1016 +               release_queues(port);
1017 +               return err;
1018 +       }
1019 +
1020 +       for (i = 0; i < ETH_ALEN; i++)
1021 +               __raw_writel(dev->dev_addr[i], &port->regs->hw_addr[i]);
1022 +       __raw_writel(0x08, &port->regs->random_seed);
1023 +       __raw_writel(0x12, &port->regs->partial_empty_threshold);
1024 +       __raw_writel(0x30, &port->regs->partial_full_threshold);
1025 +       __raw_writel(0x08, &port->regs->tx_start_bytes);
1026 +       __raw_writel(0x15, &port->regs->tx_deferral);
1027 +       __raw_writel(0x08, &port->regs->tx_2part_deferral[0]);
1028 +       __raw_writel(0x07, &port->regs->tx_2part_deferral[1]);
1029 +       __raw_writel(0x80, &port->regs->slot_time);
1030 +       __raw_writel(0x01, &port->regs->int_clock_threshold);
1031 +
1032 +       /* Populate queues with buffers, no failure after this point */
1033 +       for (i = 0; i < TX_DESCS; i++)
1034 +               queue_put_desc(port->plat->txreadyq,
1035 +                              tx_desc_phys(port, i), tx_desc_ptr(port, i));
1036 +
1037 +       for (i = 0; i < RX_DESCS; i++)
1038 +               queue_put_desc(RXFREE_QUEUE(port->id),
1039 +                              rx_desc_phys(port, i), rx_desc_ptr(port, i));
1040 +
1041 +       __raw_writel(TX_CNTRL1_RETRIES, &port->regs->tx_control[1]);
1042 +       __raw_writel(DEFAULT_TX_CNTRL0, &port->regs->tx_control[0]);
1043 +       __raw_writel(0, &port->regs->rx_control[1]);
1044 +       __raw_writel(DEFAULT_RX_CNTRL0, &port->regs->rx_control[0]);
1045 +
1046 +       napi_enable(&port->napi);
1047 +       phy_check_media(port, 1);
1048 +       eth_set_mcast_list(dev);
1049 +       netif_start_queue(dev);
1050 +       schedule_delayed_work(&port->mdio_thread, MDIO_INTERVAL);
1051 +
1052 +       qmgr_set_irq(port->plat->rxq, QUEUE_IRQ_SRC_NOT_EMPTY,
1053 +                    eth_rx_irq, dev);
1054 +       if (!ports_open) {
1055 +               qmgr_set_irq(TXDONE_QUEUE, QUEUE_IRQ_SRC_NOT_EMPTY,
1056 +                            eth_txdone_irq, NULL);
1057 +               qmgr_enable_irq(TXDONE_QUEUE);
1058 +       }
1059 +       ports_open++;
1060 +       /* we may already have RX data, enables IRQ */
1061 +       netif_rx_schedule(dev, &port->napi);
1062 +       return 0;
1063 +}
1064 +
1065 +static int eth_close(struct net_device *dev)
1066 +{
1067 +       struct port *port = netdev_priv(dev);
1068 +       struct msg msg;
1069 +       int buffs = RX_DESCS; /* allocated RX buffers */
1070 +       int i;
1071 +
1072 +       ports_open--;
1073 +       qmgr_disable_irq(port->plat->rxq);
1074 +       napi_disable(&port->napi);
1075 +       netif_stop_queue(dev);
1076 +
1077 +       while (queue_get_desc(RXFREE_QUEUE(port->id), port, 0) >= 0)
1078 +               buffs--;
1079 +
1080 +       memset(&msg, 0, sizeof(msg));
1081 +       msg.cmd = NPE_SETLOOPBACK_MODE;
1082 +       msg.eth_id = port->id;
1083 +       msg.byte3 = 1;
1084 +       if (npe_send_recv_message(port->npe, &msg, "ETH_ENABLE_LOOPBACK"))
1085 +               printk(KERN_CRIT "%s: unable to enable loopback\n", dev->name);
1086 +
1087 +       i = 0;
1088 +       do {                    /* drain RX buffers */
1089 +               while (queue_get_desc(port->plat->rxq, port, 0) >= 0)
1090 +                       buffs--;
1091 +               if (!buffs)
1092 +                       break;
1093 +               if (qmgr_stat_empty(TX_QUEUE(port->id))) {
1094 +                       /* we have to inject some packet */
1095 +                       struct desc *desc;
1096 +                       u32 phys;
1097 +                       int n = queue_get_desc(port->plat->txreadyq, port, 1);
1098 +                       BUG_ON(n < 0);
1099 +                       desc = tx_desc_ptr(port, n);
1100 +                       phys = tx_desc_phys(port, n);
1101 +                       desc->buf_len = desc->pkt_len = 1;
1102 +                       wmb();
1103 +                       queue_put_desc(TX_QUEUE(port->id), phys, desc);
1104 +               }
1105 +               udelay(1);
1106 +       } while (++i < MAX_CLOSE_WAIT);
1107 +
1108 +       if (buffs)
1109 +               printk(KERN_CRIT "%s: unable to drain RX queue, %i buffer(s)"
1110 +                      " left in NPE\n", dev->name, buffs);
1111 +#if DEBUG_CLOSE
1112 +       if (!buffs)
1113 +               printk(KERN_DEBUG "Draining RX queue took %i cycles\n", i);
1114 +#endif
1115 +
1116 +       buffs = TX_DESCS;
1117 +       while (queue_get_desc(TX_QUEUE(port->id), port, 1) >= 0)
1118 +               buffs--; /* cancel TX */
1119 +
1120 +       i = 0;
1121 +       do {
1122 +               while (queue_get_desc(port->plat->txreadyq, port, 1) >= 0)
1123 +                       buffs--;
1124 +               if (!buffs)
1125 +                       break;
1126 +       } while (++i < MAX_CLOSE_WAIT);
1127 +
1128 +       if (buffs)
1129 +               printk(KERN_CRIT "%s: unable to drain TX queue, %i buffer(s) "
1130 +                      "left in NPE\n", dev->name, buffs);
1131 +#if DEBUG_CLOSE
1132 +       if (!buffs)
1133 +               printk(KERN_DEBUG "Draining TX queues took %i cycles\n", i);
1134 +#endif
1135 +
1136 +       msg.byte3 = 0;
1137 +       if (npe_send_recv_message(port->npe, &msg, "ETH_DISABLE_LOOPBACK"))
1138 +               printk(KERN_CRIT "%s: unable to disable loopback\n",
1139 +                      dev->name);
1140 +
1141 +       port->mii_bmcr = mdio_read(dev, port->plat->phy, MII_BMCR) &
1142 +               ~(BMCR_RESET | BMCR_PDOWN); /* may have been altered */
1143 +       mdio_write(dev, port->plat->phy, MII_BMCR,
1144 +                  port->mii_bmcr | BMCR_PDOWN);
1145 +
1146 +       if (!ports_open)
1147 +               qmgr_disable_irq(TXDONE_QUEUE);
1148 +       cancel_rearming_delayed_work(&port->mdio_thread);
1149 +       destroy_queues(port);
1150 +       release_queues(port);
1151 +       return 0;
1152 +}
1153 +
1154 +static int __devinit eth_init_one(struct platform_device *pdev)
1155 +{
1156 +       struct port *port;
1157 +       struct net_device *dev;
1158 +       struct eth_plat_info *plat = pdev->dev.platform_data;
1159 +       u32 regs_phys;
1160 +       int err;
1161 +
1162 +       if (!(dev = alloc_etherdev(sizeof(struct port))))
1163 +               return -ENOMEM;
1164 +
1165 +       SET_NETDEV_DEV(dev, &pdev->dev);
1166 +       port = netdev_priv(dev);
1167 +       port->netdev = dev;
1168 +       port->id = pdev->id;
1169 +
1170 +       switch (port->id) {
1171 +       case IXP4XX_ETH_NPEA:
1172 +               port->regs = (struct eth_regs __iomem *)IXP4XX_EthA_BASE_VIRT;
1173 +               regs_phys  = IXP4XX_EthA_BASE_PHYS;
1174 +               break;
1175 +       case IXP4XX_ETH_NPEB:
1176 +               port->regs = (struct eth_regs __iomem *)IXP4XX_EthB_BASE_VIRT;
1177 +               regs_phys  = IXP4XX_EthB_BASE_PHYS;
1178 +               break;
1179 +       case IXP4XX_ETH_NPEC:
1180 +               port->regs = (struct eth_regs __iomem *)IXP4XX_EthC_BASE_VIRT;
1181 +               regs_phys  = IXP4XX_EthC_BASE_PHYS;
1182 +               break;
1183 +       default:
1184 +               err = -ENOSYS;
1185 +               goto err_free;
1186 +       }
1187 +
1188 +       dev->open = eth_open;
1189 +       dev->hard_start_xmit = eth_xmit;
1190 +       dev->stop = eth_close;
1191 +       dev->get_stats = eth_stats;
1192 +       dev->do_ioctl = eth_ioctl;
1193 +       dev->set_multicast_list = eth_set_mcast_list;
1194 +       dev->tx_queue_len = 100;
1195 +
1196 +       netif_napi_add(dev, &port->napi, eth_poll, NAPI_WEIGHT);
1197 +
1198 +       if (!(port->npe = npe_request(NPE_ID(port->id)))) {
1199 +               err = -EIO;
1200 +               goto err_free;
1201 +       }
1202 +
1203 +       if (register_netdev(dev)) {
1204 +               err = -EIO;
1205 +               goto err_npe_rel;
1206 +       }
1207 +
1208 +       port->mem_res = request_mem_region(regs_phys, REGS_SIZE, dev->name);
1209 +       if (!port->mem_res) {
1210 +               err = -EBUSY;
1211 +               goto err_unreg;
1212 +       }
1213 +
1214 +       port->plat = plat;
1215 +       npe_port_tab[NPE_ID(port->id)] = port;
1216 +       memcpy(dev->dev_addr, plat->hwaddr, ETH_ALEN);
1217 +
1218 +       platform_set_drvdata(pdev, dev);
1219 +
1220 +       __raw_writel(DEFAULT_CORE_CNTRL | CORE_RESET,
1221 +                    &port->regs->core_control);
1222 +       udelay(50);
1223 +       __raw_writel(DEFAULT_CORE_CNTRL, &port->regs->core_control);
1224 +       udelay(50);
1225 +
1226 +       port->mii.dev = dev;
1227 +       port->mii.mdio_read = mdio_read;
1228 +       port->mii.mdio_write = mdio_write;
1229 +       port->mii.phy_id = plat->phy;
1230 +       port->mii.phy_id_mask = 0x1F;
1231 +       port->mii.reg_num_mask = 0x1F;
1232 +
1233 +       printk(KERN_INFO "%s: MII PHY %i on %s\n", dev->name, plat->phy,
1234 +              npe_name(port->npe));
1235 +
1236 +       phy_reset(dev, plat->phy);
1237 +       port->mii_bmcr = mdio_read(dev, plat->phy, MII_BMCR) &
1238 +               ~(BMCR_RESET | BMCR_PDOWN);
1239 +       mdio_write(dev, plat->phy, MII_BMCR, port->mii_bmcr | BMCR_PDOWN);
1240 +
1241 +       INIT_DELAYED_WORK(&port->mdio_thread, mdio_thread);
1242 +       return 0;
1243 +
1244 +err_unreg:
1245 +       unregister_netdev(dev);
1246 +err_npe_rel:
1247 +       npe_release(port->npe);
1248 +err_free:
1249 +       free_netdev(dev);
1250 +       return err;
1251 +}
1252 +
1253 +static int __devexit eth_remove_one(struct platform_device *pdev)
1254 +{
1255 +       struct net_device *dev = platform_get_drvdata(pdev);
1256 +       struct port *port = netdev_priv(dev);
1257 +
1258 +       unregister_netdev(dev);
1259 +       npe_port_tab[NPE_ID(port->id)] = NULL;
1260 +       platform_set_drvdata(pdev, NULL);
1261 +       npe_release(port->npe);
1262 +       release_resource(port->mem_res);
1263 +       free_netdev(dev);
1264 +       return 0;
1265 +}
1266 +
1267 +static struct platform_driver drv = {
1268 +       .driver.name    = DRV_NAME,
1269 +       .probe          = eth_init_one,
1270 +       .remove         = eth_remove_one,
1271 +};
1272 +
1273 +static int __init eth_init_module(void)
1274 +{
1275 +       if (!(ixp4xx_read_feature_bits() & IXP4XX_FEATURE_NPEB_ETH0))
1276 +               return -ENOSYS;
1277 +
1278 +       /* All MII PHY accesses use NPE-B Ethernet registers */
1279 +       spin_lock_init(&mdio_lock);
1280 +       mdio_regs = (struct eth_regs __iomem *)IXP4XX_EthB_BASE_VIRT;
1281 +       __raw_writel(DEFAULT_CORE_CNTRL, &mdio_regs->core_control);
1282 +
1283 +       return platform_driver_register(&drv);
1284 +}
1285 +
1286 +static void __exit eth_cleanup_module(void)
1287 +{
1288 +       platform_driver_unregister(&drv);
1289 +}
1290 +
1291 +MODULE_AUTHOR("Krzysztof Halasa");
1292 +MODULE_DESCRIPTION("Intel IXP4xx Ethernet driver");
1293 +MODULE_LICENSE("GPL v2");
1294 +MODULE_ALIAS("platform:ixp4xx_eth");
1295 +module_init(eth_init_module);
1296 +module_exit(eth_cleanup_module);
1297 diff --git a/arch/arm/mach-ixp4xx/ixp4xx_npe.c b/arch/arm/mach-ixp4xx/ixp4xx_npe.c
1298 index 83c137e..63a23fa 100644
1299 --- a/arch/arm/mach-ixp4xx/ixp4xx_npe.c
1300 +++ b/arch/arm/mach-ixp4xx/ixp4xx_npe.c
1301 @@ -448,7 +448,9 @@ int npe_send_message(struct npe *npe, const void *msg, const char *what)
1302                 return -ETIMEDOUT;
1303         }
1304
1305 +#if DEBUG_MSG > 1
1306         debug_msg(npe, "Sending a message took %i cycles\n", cycles);
1307 +#endif
1308         return 0;
1309  }
1310
1311 @@ -484,7 +486,9 @@ int npe_recv_message(struct npe *npe, void *msg, const char *what)
1312                 return -ETIMEDOUT;
1313         }
1314
1315 +#if DEBUG_MSG > 1
1316         debug_msg(npe, "Receiving a message took %i cycles\n", cycles);
1317 +#endif
1318         return 0;
1319  }
1320
1321 diff --git a/arch/arm/mach-ixp4xx/ixp4xx_qmgr.c b/arch/arm/mach-ixp4xx/ixp4xx_qmgr.c
1322 index e833013..fab94ea 100644
1323 --- a/arch/arm/mach-ixp4xx/ixp4xx_qmgr.c
1324 +++ b/arch/arm/mach-ixp4xx/ixp4xx_qmgr.c
1325 @@ -184,6 +184,8 @@ void qmgr_release_queue(unsigned int queue)
1326         case 3: mask[0] = 0xFF; break;
1327         }
1328
1329 +       mask[1] = mask[2] = mask[3] = 0;
1330 +
1331         while (addr--)
1332                 shift_mask(mask);
1333