target/linux/ipq806x/patches-4.0/705-net-stmmac-ipq806x-document-device-tree-bindings.patch

   1 From 0f9605d9409b77a89daef91cc68239fc2ff50457 Mon Sep 17 00:00:00 2001
   2 From: Mathieu Olivari <mathieu@codeaurora.org>
   3 Date: Fri, 8 May 2015 16:51:25 -0700
   4 Subject: [PATCH 5/8] net: stmmac: ipq806x: document device tree bindings
   5
   6 Add the device tree bindings documentation for the QCA IPQ806x
   7 variant of the Synopsys DesignWare MAC.
   8
   9 Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
  10 ---
  11  .../devicetree/bindings/net/ipq806x-dwmac.txt      | 35 ++++++++++++++++++++++
  12  1 file changed, 35 insertions(+)
  13  create mode 100644 Documentation/devicetree/bindings/net/ipq806x-dwmac.txt
  14
  15 --- /dev/null
  16 +++ b/Documentation/devicetree/bindings/net/ipq806x-dwmac.txt
  17 @@ -0,0 +1,35 @@
  18 +* IPQ806x DWMAC Ethernet controller
  19 +
  20 +The device inherits all the properties of the dwmac/stmmac devices
  21 +described in the file net/stmmac.txt with the following changes.
  22 +
  23 +Required properties:
  24 +
  25 +- compatible: should be "qcom,ipq806x-gmac" along with "snps,dwmac"
  26 +             and any applicable more detailed version number
  27 +             described in net/stmmac.txt
  28 +
  29 +- qcom,nss-common: should contain a phandle to a syscon device mapping the
  30 +                  nss-common registers.
  31 +
  32 +- qcom,qsgmii-csr: should contain a phandle to a syscon device mapping the
  33 +                  qsgmii-csr registers.
  34 +
  35 +Example:
  36 +
  37 +       gmac: ethernet@37000000 {
  38 +               device_type = "network";
  39 +               compatible = "qcom,ipq806x-gmac";
  40 +               reg = <0x37000000 0x200000>;
  41 +               interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
  42 +               interrupt-names = "macirq";
  43 +
  44 +               qcom,nss-common = <&nss_common>;
  45 +               qcom,qsgmii-csr = <&qsgmii_csr>;
  46 +
  47 +               clocks = <&gcc GMAC_CORE1_CLK>;
  48 +               clock-names = "stmmaceth";
  49 +
  50 +               resets = <&gcc GMAC_CORE1_RESET>;
  51 +               reset-names = "stmmaceth";
  52 +       };