target/linux/ipq806x/patches-4.0/138-clk-qcom-Add-HFPLL-driver.patch

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   4 Subject: [v3,06/13] clk: qcom: Add HFPLL driver
   5 From: Stephen Boyd <sboyd@codeaurora.org>
   6 X-Patchwork-Id: 6063231
   7 Message-Id: <1426920332-9340-7-git-send-email-sboyd@codeaurora.org>
   8 To: Mike Turquette <mturquette@linaro.org>, Stephen Boyd <sboyd@codeaurora.org>
   9 Cc: linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org,
  10         linux-pm@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
  11         Viresh Kumar <viresh.kumar@linaro.org>, <devicetree@vger.kernel.org>
  12 Date: Fri, 20 Mar 2015 23:45:25 -0700
  13
  14 On some devices (MSM8974 for example), the HFPLLs are
  15 instantiated within the Krait processor subsystem as separate
  16 register regions. Add a driver for these PLLs so that we can
  17 provide HFPLL clocks for use by the system.
  18
  19 Cc: <devicetree@vger.kernel.org>
  20 Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
  21
  22 ---
  23 .../devicetree/bindings/clock/qcom,hfpll.txt       |  40 ++++++++
  24  drivers/clk/qcom/Kconfig                           |   8 ++
  25  drivers/clk/qcom/Makefile                          |   1 +
  26  drivers/clk/qcom/hfpll.c                           | 109 +++++++++++++++++++++
  27  4 files changed, 158 insertions(+)
  28  create mode 100644 Documentation/devicetree/bindings/clock/qcom,hfpll.txt
  29  create mode 100644 drivers/clk/qcom/hfpll.c
  30
  31 --- /dev/null
  32 +++ b/Documentation/devicetree/bindings/clock/qcom,hfpll.txt
  33 @@ -0,0 +1,40 @@
  34 +High-Frequency PLL (HFPLL)
  35 +
  36 +PROPERTIES
  37 +
  38 +- compatible:
  39 +       Usage: required
  40 +       Value type: <string>
  41 +       Definition: must be "qcom,hfpll"
  42 +
  43 +- reg:
  44 +       Usage: required
  45 +       Value type: <prop-encoded-array>
  46 +       Definition: address and size of HPLL registers. An optional second
  47 +                   element specifies the address and size of the alias
  48 +                   register region.
  49 +
  50 +- clock-output-names:
  51 +       Usage: required
  52 +       Value type: <string>
  53 +       Definition: Name of the PLL. Typically hfpllX where X is a CPU number
  54 +                   starting at 0. Otherwise hfpll_Y where Y is more specific
  55 +                   such as "l2".
  56 +
  57 +Example:
  58 +
  59 +1) An HFPLL for the L2 cache.
  60 +
  61 +       clock-controller@f9016000 {
  62 +               compatible = "qcom,hfpll";
  63 +               reg = <0xf9016000 0x30>;
  64 +               clock-output-names = "hfpll_l2";
  65 +       };
  66 +
  67 +2) An HFPLL for CPU0. This HFPLL has the alias register region.
  68 +
  69 +       clock-controller@f908a000 {
  70 +               compatible = "qcom,hfpll";
  71 +               reg = <0xf908a000 0x30>, <0xf900a000 0x30>;
  72 +               clock-output-names = "hfpll0";
  73 +       };
  74 --- a/drivers/clk/qcom/Kconfig
  75 +++ b/drivers/clk/qcom/Kconfig
  76 @@ -88,3 +88,11 @@ config MSM_MMCC_8974
  77           Support for the multimedia clock controller on msm8974 devices.
  78           Say Y if you want to support multimedia devices such as display,
  79           graphics, video encode/decode, camera, etc.
  80 +
  81 +config QCOM_HFPLL
  82 +       tristate "High-Frequency PLL (HFPLL) Clock Controller"
  83 +       depends on COMMON_CLK_QCOM
  84 +       help
  85 +         Support for the high-frequency PLLs present on Qualcomm devices.
  86 +         Say Y if you want to support CPU frequency scaling on devices
  87 +         such as MSM8974, APQ8084, etc.
  88 --- a/drivers/clk/qcom/Makefile
  89 +++ b/drivers/clk/qcom/Makefile
  90 @@ -21,3 +21,4 @@ obj-$(CONFIG_MSM_LCC_8960) += lcc-msm896
  91  obj-$(CONFIG_MSM_GCC_8974) += gcc-msm8974.o
  92  obj-$(CONFIG_MSM_MMCC_8960) += mmcc-msm8960.o
  93  obj-$(CONFIG_MSM_MMCC_8974) += mmcc-msm8974.o
  94 +obj-$(CONFIG_QCOM_HFPLL) += hfpll.o
  95 --- /dev/null
  96 +++ b/drivers/clk/qcom/hfpll.c
  97 @@ -0,0 +1,109 @@
  98 +/*
  99 + * Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
 100 + *
 101 + * This program is free software; you can redistribute it and/or modify
 102 + * it under the terms of the GNU General Public License version 2 and
 103 + * only version 2 as published by the Free Software Foundation.
 104 + *
 105 + * This program is distributed in the hope that it will be useful,
 106 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
 107 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 108 + * GNU General Public License for more details.
 109 + */
 110 +
 111 +#include <linux/kernel.h>
 112 +#include <linux/init.h>
 113 +#include <linux/module.h>
 114 +#include <linux/platform_device.h>
 115 +#include <linux/of.h>
 116 +#include <linux/clk.h>
 117 +#include <linux/clk-provider.h>
 118 +#include <linux/regmap.h>
 119 +
 120 +#include "clk-regmap.h"
 121 +#include "clk-hfpll.h"
 122 +
 123 +static const struct hfpll_data hdata = {
 124 +       .mode_reg = 0x00,
 125 +       .l_reg = 0x04,
 126 +       .m_reg = 0x08,
 127 +       .n_reg = 0x0c,
 128 +       .user_reg = 0x10,
 129 +       .config_reg = 0x14,
 130 +       .config_val = 0x430405d,
 131 +       .status_reg = 0x1c,
 132 +       .lock_bit = 16,
 133 +
 134 +       .user_val = 0x8,
 135 +       .user_vco_mask = 0x100000,
 136 +       .low_vco_max_rate = 1248000000,
 137 +       .min_rate = 537600000UL,
 138 +       .max_rate = 2900000000UL,
 139 +};
 140 +
 141 +static const struct of_device_id qcom_hfpll_match_table[] = {
 142 +       { .compatible = "qcom,hfpll" },
 143 +       { }
 144 +};
 145 +MODULE_DEVICE_TABLE(of, qcom_hfpll_match_table);
 146 +
 147 +static const struct regmap_config hfpll_regmap_config = {
 148 +       .reg_bits       = 32,
 149 +       .reg_stride     = 4,
 150 +       .val_bits       = 32,
 151 +       .max_register   = 0x30,
 152 +       .fast_io        = true,
 153 +};
 154 +
 155 +static int qcom_hfpll_probe(struct platform_device *pdev)
 156 +{
 157 +       struct clk *clk;
 158 +       struct resource *res;
 159 +       struct device *dev = &pdev->dev;
 160 +       void __iomem *base;
 161 +       struct regmap *regmap;
 162 +       struct clk_hfpll *h;
 163 +       struct clk_init_data init = {
 164 +               .parent_names = (const char *[]){ "xo" },
 165 +               .num_parents = 1,
 166 +               .ops = &clk_ops_hfpll,
 167 +       };
 168 +
 169 +       h = devm_kzalloc(dev, sizeof(*h), GFP_KERNEL);
 170 +       if (!h)
 171 +               return -ENOMEM;
 172 +
 173 +       res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 174 +       base = devm_ioremap_resource(dev, res);
 175 +       if (IS_ERR(base))
 176 +               return PTR_ERR(base);
 177 +
 178 +       regmap = devm_regmap_init_mmio(&pdev->dev, base, &hfpll_regmap_config);
 179 +       if (IS_ERR(regmap))
 180 +               return PTR_ERR(regmap);
 181 +
 182 +       if (of_property_read_string_index(dev->of_node, "clock-output-names",
 183 +                                                 0, &init.name))
 184 +               return -ENODEV;
 185 +
 186 +       h->d = &hdata;
 187 +       h->clkr.hw.init = &init;
 188 +       spin_lock_init(&h->lock);
 189 +
 190 +       clk = devm_clk_register_regmap(&pdev->dev, &h->clkr);
 191 +
 192 +       return PTR_ERR_OR_ZERO(clk);
 193 +}
 194 +
 195 +static struct platform_driver qcom_hfpll_driver = {
 196 +       .probe          = qcom_hfpll_probe,
 197 +       .driver         = {
 198 +               .name   = "qcom-hfpll",
 199 +               .of_match_table = qcom_hfpll_match_table,
 200 +       },
 201 +};
 202 +module_platform_driver(qcom_hfpll_driver);
 203 +
 204 +MODULE_DESCRIPTION("QCOM HFPLL Clock Driver");
 205 +MODULE_LICENSE("GPL v2");
 206 +MODULE_ALIAS("platform:qcom-hfpll");