1 From 1fb18acab2d71e7e4efd9c10492edb1baf84dcc0 Mon Sep 17 00:00:00 2001
2 From: Andy Gross <agross@codeaurora.org>
3 Date: Wed, 20 May 2015 15:41:07 +0530
4 Subject: [PATCH] ARM: DT: ipq8064: Add ADM device node
6 This patch adds support for the ADM DMA on the IPQ8064 SOC
8 Signed-off-by: Andy Gross <agross@codeaurora.org>
10 arch/arm/boot/dts/qcom-ipq8064-ap148.dts | 4 ++++
11 arch/arm/boot/dts/qcom-ipq8064.dtsi | 21 +++++++++++++++++++++
12 2 files changed, 25 insertions(+)
14 --- a/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
15 +++ b/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
18 cs-gpios = <&qcom_pinmux 20 0>;
20 + dmas = <&adm_dma 6>,
22 + dma-names = "rx", "tx";
25 compatible = "s25fl256s1";
27 --- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
28 +++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
33 + adm_dma: dma@18300000 {
34 + compatible = "qcom,adm";
35 + reg = <0x18300000 0x100000>;
36 + interrupts = <0 170 0>;
39 + clocks = <&gcc ADM0_CLK>, <&gcc ADM0_PBUS_CLK>;
40 + clock-names = "core", "iface";
42 + resets = <&gcc ADM0_RESET>,
43 + <&gcc ADM0_PBUS_RESET>,
44 + <&gcc ADM0_C0_RESET>,
45 + <&gcc ADM0_C1_RESET>,
46 + <&gcc ADM0_C2_RESET>;
47 + reset-names = "clk", "pbus", "c0", "c1", "c2";
50 + status = "disabled";