5fed04123ea7a553ce21870756f8845c4b6f606d
[openwrt.git] / target / linux / ipq806x / patches / 0180-ARM-dts-Add-ADM-DMA-nodes-and-SPI-linkage.patch
1 From c78ae23b6c174c9f2e0973a247942b6b4adb7e82 Mon Sep 17 00:00:00 2001
2 From: Andy Gross <agross@codeaurora.org>
3 Date: Thu, 26 Jun 2014 13:02:59 -0500
4 Subject: [PATCH 180/182] ARM: dts: Add ADM DMA nodes and SPI linkage
5
6 This patch adds the ADM DMA controller DT nodes and also enables the use of dma
7 in SPI.
8
9 Signed-off-by: Andy Gross <agross@codeaurora.org>
10 ---
11  arch/arm/boot/dts/qcom-ipq8064-ap148.dts |   11 +++++++++++
12  arch/arm/boot/dts/qcom-ipq8064.dtsi      |    8 +++++---
13  2 files changed, 16 insertions(+), 3 deletions(-)
14
15 diff --git a/arch/arm/boot/dts/qcom-ipq8064-ap148.dts b/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
16 index 2b2d63c..c54a3ee 100644
17 --- a/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
18 +++ b/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
19 @@ -44,6 +44,10 @@
20                                         drive-strength = <10>;
21                                         bias-none;
22                                 };
23 +                               cs {
24 +                                       pins = "gpio20";
25 +                                       drive-strength = <12>;
26 +                               };
27                         };
28                         nand_pins: nand_pins {
29                                 mux {
30 @@ -100,12 +104,17 @@
31  
32                                 cs-gpios = <&qcom_pinmux 20 0>;
33  
34 +                               dmas = <&adm_dma 6 9>,
35 +                                       <&adm_dma 5 10>;
36 +                               dma-names = "rx", "tx";
37 +
38                                 flash: m25p80@0 {
39                                         compatible = "s25fl256s1";
40                                         #address-cells = <1>;
41                                         #size-cells = <1>;
42                                         spi-max-frequency = <50000000>;
43                                         reg = <0>;
44 +                                       m25p,fast-read;
45  
46                                         partition@0 {
47                                                 label = "rootfs";
48 @@ -140,8 +149,10 @@
49                         ranges = <0x00000000 0 0x00000000 0x31f00000 0 0x00100000   /* configuration space */
50                                   0x81000000 0 0          0x31e00000 0 0x00100000   /* downstream I/O */
51                                   0x82000000 0 0x00000000 0x2e000000 0 0x03e00000>; /* non-prefetchable memory */
52 +
53                 };
54  
55 +
56                 sata-phy@1b400000 {
57                         status = "ok";
58                 };
59 diff --git a/arch/arm/boot/dts/qcom-ipq8064.dtsi b/arch/arm/boot/dts/qcom-ipq8064.dtsi
60 index 97e4c3d..f74e923 100644
61 --- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
62 +++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
63 @@ -421,19 +421,21 @@
64                         compatible = "qcom,adm";
65                         reg = <0x18300000 0x100000>;
66                         interrupts = <0 170 0>;
67 +                       #dma-cells = <2>;
68  
69                         clocks = <&gcc ADM0_CLK>, <&gcc ADM0_PBUS_CLK>;
70 -                       clock-names = "core_clk", "iface_clk";
71 +                       clock-names = "core", "iface";
72  
73                         resets = <&gcc ADM0_RESET>,
74                                 <&gcc ADM0_PBUS_RESET>,
75                                 <&gcc ADM0_C0_RESET>,
76                                 <&gcc ADM0_C1_RESET>,
77                                 <&gcc ADM0_C2_RESET>;
78 -
79 -                       reset-names = "adm", "pbus", "c0", "c1", "c2";
80 +                       reset-names = "clk", "pbus", "c0", "c1", "c2";
81 +                       qcom,ee = <0>;
82  
83                         status = "disabled";
84 +
85                 };
86  
87                 nand@0x1ac00000 {
88 -- 
89 1.7.10.4
90