1 From c78ae23b6c174c9f2e0973a247942b6b4adb7e82 Mon Sep 17 00:00:00 2001
2 From: Andy Gross <agross@codeaurora.org>
3 Date: Thu, 26 Jun 2014 13:02:59 -0500
4 Subject: [PATCH 180/182] ARM: dts: Add ADM DMA nodes and SPI linkage
6 This patch adds the ADM DMA controller DT nodes and also enables the use of dma
9 Signed-off-by: Andy Gross <agross@codeaurora.org>
11 arch/arm/boot/dts/qcom-ipq8064-ap148.dts | 11 +++++++++++
12 arch/arm/boot/dts/qcom-ipq8064.dtsi | 8 +++++---
13 2 files changed, 16 insertions(+), 3 deletions(-)
15 --- a/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
16 +++ b/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
18 drive-strength = <10>;
23 + drive-strength = <12>;
26 nand_pins: nand_pins {
30 cs-gpios = <&qcom_pinmux 20 0>;
32 + dmas = <&adm_dma 6 9>,
34 + dma-names = "rx", "tx";
37 compatible = "s25fl256s1";
40 spi-max-frequency = <50000000>;
47 ranges = <0x00000000 0 0x00000000 0x31f00000 0 0x00100000 /* configuration space */
48 0x81000000 0 0 0x31e00000 0 0x00100000 /* downstream I/O */
49 0x82000000 0 0x00000000 0x2e000000 0 0x03e00000>; /* non-prefetchable memory */
57 --- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
58 +++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
60 compatible = "qcom,adm";
61 reg = <0x18300000 0x100000>;
62 interrupts = <0 170 0>;
65 clocks = <&gcc ADM0_CLK>, <&gcc ADM0_PBUS_CLK>;
66 - clock-names = "core_clk", "iface_clk";
67 + clock-names = "core", "iface";
69 resets = <&gcc ADM0_RESET>,
70 <&gcc ADM0_PBUS_RESET>,
75 - reset-names = "adm", "pbus", "c0", "c1", "c2";
76 + reset-names = "clk", "pbus", "c0", "c1", "c2";