target/linux/ipq806x/patches/0174-clk-qcom-Add-HFPLLs-to-IPQ806X-driver.patch

   1 From b9b3815f2a71af88ca68d3524ee4d9b6b4739257 Mon Sep 17 00:00:00 2001
   2 From: Stephen Boyd <sboyd@codeaurora.org>
   3 Date: Wed, 18 Jun 2014 15:57:06 -0700
   4 Subject: [PATCH 174/182] clk: qcom: Add HFPLLs to IPQ806X driver
   5
   6 Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
   7 ---
   8  drivers/clk/qcom/gcc-ipq806x.c |   83 ++++++++++++++++++++++++++++++++++++++++
   9  1 file changed, 83 insertions(+)
  10
  11 diff --git a/drivers/clk/qcom/gcc-ipq806x.c b/drivers/clk/qcom/gcc-ipq806x.c
  12 index d80dc69..83a73cb 100644
  13 --- a/drivers/clk/qcom/gcc-ipq806x.c
  14 +++ b/drivers/clk/qcom/gcc-ipq806x.c
  15 @@ -30,6 +30,7 @@
  16  #include "clk-pll.h"
  17  #include "clk-rcg.h"
  18  #include "clk-branch.h"
  19 +#include "clk-hfpll.h"
  20  #include "reset.h"
  21
  22  static struct clk_pll pll0 = {
  23 @@ -102,6 +103,85 @@ static struct clk_regmap pll8_vote = {
  24         },
  25  };
  26
  27 +static struct hfpll_data hfpll0_data = {
  28 +       .mode_reg = 0x3200,
  29 +       .l_reg = 0x3208,
  30 +       .m_reg = 0x320c,
  31 +       .n_reg = 0x3210,
  32 +       .config_reg = 0x3204,
  33 +       .status_reg = 0x321c,
  34 +        .config_val = 0x7845c665,
  35 +        .droop_reg = 0x3214,
  36 +        .droop_val = 0x0108c000,
  37 +       .min_rate = 600000000UL,
  38 +       .max_rate = 1800000000UL,
  39 +};
  40 +
  41 +static struct clk_hfpll hfpll0 = {
  42 +       .d = &hfpll0_data,
  43 +       .clkr.hw.init = &(struct clk_init_data){
  44 +               .parent_names = (const char *[]){ "pxo" },
  45 +               .num_parents = 1,
  46 +               .name = "hfpll0",
  47 +               .ops = &clk_ops_hfpll,
  48 +               .flags = CLK_IGNORE_UNUSED,
  49 +       },
  50 +       .lock = __SPIN_LOCK_UNLOCKED(hfpll0.lock),
  51 +};
  52 +
  53 +static struct hfpll_data hfpll1_data = {
  54 +       .mode_reg = 0x3240,
  55 +       .l_reg = 0x3248,
  56 +       .m_reg = 0x324c,
  57 +       .n_reg = 0x3250,
  58 +       .config_reg = 0x3244,
  59 +       .status_reg = 0x325c,
  60 +        .config_val = 0x7845c665,
  61 +        .droop_reg = 0x3314,
  62 +        .droop_val = 0x0108c000,
  63 +       .min_rate = 600000000UL,
  64 +       .max_rate = 1800000000UL,
  65 +};
  66 +
  67 +static struct clk_hfpll hfpll1 = {
  68 +       .d = &hfpll1_data,
  69 +       .clkr.hw.init = &(struct clk_init_data){
  70 +               .parent_names = (const char *[]){ "pxo" },
  71 +               .num_parents = 1,
  72 +               .name = "hfpll1",
  73 +               .ops = &clk_ops_hfpll,
  74 +               .flags = CLK_IGNORE_UNUSED,
  75 +       },
  76 +       .lock = __SPIN_LOCK_UNLOCKED(hfpll1.lock),
  77 +};
  78 +
  79 +static struct hfpll_data hfpll_l2_data = {
  80 +       .mode_reg = 0x3300,
  81 +       .l_reg = 0x3308,
  82 +       .m_reg = 0x330c,
  83 +       .n_reg = 0x3310,
  84 +       .config_reg = 0x3304,
  85 +       .status_reg = 0x331c,
  86 +        .config_val = 0x7845c665,
  87 +        .droop_reg = 0x3314,
  88 +        .droop_val = 0x0108c000,
  89 +       .min_rate = 600000000UL,
  90 +       .max_rate = 1800000000UL,
  91 +};
  92 +
  93 +static struct clk_hfpll hfpll_l2 = {
  94 +       .d = &hfpll_l2_data,
  95 +       .clkr.hw.init = &(struct clk_init_data){
  96 +               .parent_names = (const char *[]){ "pxo" },
  97 +               .num_parents = 1,
  98 +               .name = "hfpll_l2",
  99 +               .ops = &clk_ops_hfpll,
 100 +               .flags = CLK_IGNORE_UNUSED,
 101 +       },
 102 +       .lock = __SPIN_LOCK_UNLOCKED(hfpll_l2.lock),
 103 +};
 104 +
 105 +
 106  static struct clk_pll pll14 = {
 107         .l_reg = 0x31c4,
 108         .m_reg = 0x31c8,
 109 @@ -2878,6 +2958,9 @@ static struct clk_regmap *gcc_ipq806x_clks[] = {
 110         [NSSTCM_CLK_SRC] = &nss_tcm_src.clkr,
 111         [NSSTCM_CLK] = &nss_tcm_clk.clkr,
 112         [NSS_CORE_CLK] = &nss_core_clk,
 113 +       [PLL9] = &hfpll0.clkr,
 114 +       [PLL10] = &hfpll1.clkr,
 115 +       [PLL12] = &hfpll_l2.clkr,
 116  };
 117
 118  static const struct qcom_reset_map gcc_ipq806x_resets[] = {
 119 --
 120 1.7.10.4
 121