1 From 63ecfef8560631a15ee13129b2778cd4dffbcfe2 Mon Sep 17 00:00:00 2001
2 From: Stephen Boyd <sboyd@codeaurora.org>
3 Date: Wed, 18 Jun 2014 14:18:31 -0700
4 Subject: [PATCH 169/182] clk: qcom: Add support for Krait clocks
6 The Krait clocks are made up of a series of muxes and a divider
7 that choose between a fixed rate clock and dedicated HFPLLs for
8 each CPU. Instead of using mmio accesses to remux parents, the
9 Krait implementation exposes the remux control via cp15
10 registers. Support these clocks.
12 Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
14 drivers/clk/qcom/Kconfig | 4 ++
15 drivers/clk/qcom/Makefile | 1 +
16 drivers/clk/qcom/clk-krait.c | 121 ++++++++++++++++++++++++++++++++++++++++++
17 drivers/clk/qcom/clk-krait.h | 22 ++++++++
18 4 files changed, 148 insertions(+)
19 create mode 100644 drivers/clk/qcom/clk-krait.c
20 create mode 100644 drivers/clk/qcom/clk-krait.h
22 --- a/drivers/clk/qcom/Kconfig
23 +++ b/drivers/clk/qcom/Kconfig
24 @@ -61,3 +61,7 @@ config QCOM_HFPLL
25 Support for the high-frequency PLLs present on Qualcomm devices.
26 Say Y if you want to support CPU frequency scaling on devices
27 such as MSM8974, APQ8084, etc.
31 + select KRAIT_L2_ACCESSORS
32 --- a/drivers/clk/qcom/Makefile
33 +++ b/drivers/clk/qcom/Makefile
34 @@ -7,6 +7,7 @@ clk-qcom-y += clk-rcg.o
35 clk-qcom-y += clk-rcg2.o
36 clk-qcom-y += clk-branch.o
37 clk-qcom-y += clk-generic.o
38 +clk-qcom-$(CONFIG_KRAIT_CLOCKS) += clk-krait.o
39 clk-qcom-y += clk-hfpll.o
43 +++ b/drivers/clk/qcom/clk-krait.c
46 + * Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
48 + * This program is free software; you can redistribute it and/or modify
49 + * it under the terms of the GNU General Public License version 2 and
50 + * only version 2 as published by the Free Software Foundation.
52 + * This program is distributed in the hope that it will be useful,
53 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
54 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
55 + * GNU General Public License for more details.
58 +#include <linux/kernel.h>
59 +#include <linux/module.h>
60 +#include <linux/init.h>
61 +#include <linux/io.h>
62 +#include <linux/delay.h>
63 +#include <linux/err.h>
64 +#include <linux/clk-provider.h>
65 +#include <linux/spinlock.h>
67 +#include <asm/krait-l2-accessors.h>
69 +#include "clk-krait.h"
71 +/* Secondary and primary muxes share the same cp15 register */
72 +static DEFINE_SPINLOCK(kpss_clock_reg_lock);
75 +static void __kpss_mux_set_sel(struct mux_clk *mux, int sel)
77 + unsigned long flags;
80 + spin_lock_irqsave(&kpss_clock_reg_lock, flags);
81 + regval = krait_get_l2_indirect_reg(mux->offset);
82 + regval &= ~(mux->mask << mux->shift);
83 + regval |= (sel & mux->mask) << mux->shift;
85 + regval &= ~(mux->mask << (mux->shift + LPL_SHIFT));
86 + regval |= (sel & mux->mask) << (mux->shift + LPL_SHIFT);
88 + krait_set_l2_indirect_reg(mux->offset, regval);
89 + spin_unlock_irqrestore(&kpss_clock_reg_lock, flags);
91 + /* Wait for switch to complete. */
96 +static int kpss_mux_set_sel(struct mux_clk *mux, int sel)
99 + /* Don't touch mux if CPU is off as it won't work */
100 + if (__clk_is_enabled(mux->hw.clk))
101 + __kpss_mux_set_sel(mux, sel);
105 +static int kpss_mux_get_sel(struct mux_clk *mux)
109 + sel = krait_get_l2_indirect_reg(mux->offset);
110 + sel >>= mux->shift;
112 + mux->en_mask = sel;
117 +static int kpss_mux_enable(struct mux_clk *mux)
119 + __kpss_mux_set_sel(mux, mux->en_mask);
123 +static void kpss_mux_disable(struct mux_clk *mux)
125 + __kpss_mux_set_sel(mux, mux->safe_sel);
128 +const struct clk_mux_ops clk_mux_ops_kpss = {
129 + .enable = kpss_mux_enable,
130 + .disable = kpss_mux_disable,
131 + .set_mux_sel = kpss_mux_set_sel,
132 + .get_mux_sel = kpss_mux_get_sel,
134 +EXPORT_SYMBOL_GPL(clk_mux_ops_kpss);
137 + * The divider can divide by 2, 4, 6 and 8. But we only really need div-2. So
138 + * force it to div-2 during handoff and treat it like a fixed div-2 clock.
140 +static int kpss_div2_get_div(struct div_clk *div)
142 + unsigned long flags;
146 + spin_lock_irqsave(&kpss_clock_reg_lock, flags);
147 + regval = krait_get_l2_indirect_reg(div->offset);
148 + val = (regval >> div->shift) & div->mask;
149 + regval &= ~(div->mask << div->shift);
151 + regval &= ~(div->mask << (div->shift + LPL_SHIFT));
152 + krait_set_l2_indirect_reg(div->offset, regval);
153 + spin_unlock_irqrestore(&kpss_clock_reg_lock, flags);
155 + val = (val + 1) * 2;
156 + WARN(val != 2, "Divider %s was configured to div-%d instead of 2!\n",
157 + __clk_get_name(div->hw.clk), val);
162 +const struct clk_div_ops clk_div_ops_kpss_div2 = {
163 + .get_div = kpss_div2_get_div,
165 +EXPORT_SYMBOL_GPL(clk_div_ops_kpss_div2);
167 +++ b/drivers/clk/qcom/clk-krait.h
170 + * Copyright (c) 2013, The Linux Foundation. All rights reserved.
172 + * This program is free software; you can redistribute it and/or modify
173 + * it under the terms of the GNU General Public License version 2 and
174 + * only version 2 as published by the Free Software Foundation.
176 + * This program is distributed in the hope that it will be useful,
177 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
178 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
179 + * GNU General Public License for more details.
182 +#ifndef __SOC_QCOM_CLOCK_KRAIT_H
183 +#define __SOC_QCOM_CLOCK_KRAIT_H
185 +#include <linux/clk/msm-clk-generic.h>
187 +extern const struct clk_mux_ops clk_mux_ops_kpss;
188 +extern const struct clk_div_ops clk_div_ops_kpss_div2;