target/linux/ipq806x/patches/0139-ARM-dts-msm-Add-PCIe-related-nodes-for-IPQ8064-AP148.patch

   1 From 7c6525a0d5cf88f9244187fbe8ee293fa4ee43c1 Mon Sep 17 00:00:00 2001
   2 From: Kumar Gala <galak@codeaurora.org>
   3 Date: Mon, 12 May 2014 19:36:23 -0500
   4 Subject: [PATCH 139/182] ARM: dts: msm: Add PCIe related nodes for
   5  IPQ8064/AP148
   6
   7 ---
   8  arch/arm/boot/dts/qcom-ipq8064-ap148.dts |   38 ++++++++++++
   9  arch/arm/boot/dts/qcom-ipq8064.dtsi      |   93 ++++++++++++++++++++++++++++++
  10  2 files changed, 131 insertions(+)
  11
  12 diff --git a/arch/arm/boot/dts/qcom-ipq8064-ap148.dts b/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
  13 index 158a09f..11f7a77 100644
  14 --- a/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
  15 +++ b/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
  16 @@ -21,6 +21,22 @@
  17                                 bias-disable;
  18                         };
  19
  20 +                       pcie1_pins: pcie1_pinmux {
  21 +                               mux {
  22 +                                       pins = "gpio3";
  23 +                                       drive-strength = <2>;
  24 +                                       bias-disable;
  25 +                               };
  26 +                       };
  27 +
  28 +                       pcie2_pins: pcie2_pinmux {
  29 +                               mux {
  30 +                                       pins = "gpio48";
  31 +                                       drive-strength = <2>;
  32 +                                       bias-disable;
  33 +                               };
  34 +                       };
  35 +
  36                         spi_pins: spi_pins {
  37                                 mux {
  38                                         pins = "gpio18", "gpio19", "gpio21";
  39 @@ -80,5 +96,27 @@
  40                                 };
  41                         };
  42                 };
  43 +
  44 +               pci@1b500000 {
  45 +                       status = "ok";
  46 +                       reset-gpio = <&qcom_pinmux 3 0>;
  47 +                       pinctrl-0 = <&pcie1_pins>;
  48 +                       pinctrl-names = "default";
  49 +
  50 +                       ranges = <0x00000000 0 0x00000000 0x0ff00000 0 0x00100000   /* configuration space */
  51 +                                 0x81000000 0 0          0x0fe00000 0 0x00100000   /* downstream I/O */
  52 +                                 0x82000000 0 0x00000000 0x08000000 0 0x07e00000>; /* non-prefetchable memory */
  53 +               };
  54 +
  55 +               pci@1b700000 {
  56 +                       status = "ok";
  57 +                       reset-gpio = <&qcom_pinmux 48 0>;
  58 +                       pinctrl-0 = <&pcie2_pins>;
  59 +                       pinctrl-names = "default";
  60 +
  61 +                       ranges = <0x00000000 0 0x00000000 0x31f00000 0 0x00100000   /* configuration space */
  62 +                                 0x81000000 0 0          0x31e00000 0 0x00100000   /* downstream I/O */
  63 +                                 0x82000000 0 0x00000000 0x2e000000 0 0x03e00000>; /* non-prefetchable memory */
  64 +               };
  65         };
  66  };
  67 diff --git a/arch/arm/boot/dts/qcom-ipq8064.dtsi b/arch/arm/boot/dts/qcom-ipq8064.dtsi
  68 index 244f857..42a651f 100644
  69 --- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
  70 +++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
  71 @@ -2,6 +2,7 @@
  72
  73  #include "skeleton.dtsi"
  74  #include <dt-bindings/clock/qcom,gcc-ipq806x.h>
  75 +#include <dt-bindings/reset/qcom,gcc-ipq806x.h>
  76  #include <dt-bindings/soc/qcom,gsbi.h>
  77
  78  / {
  79 @@ -246,5 +247,97 @@
  80                         #clock-cells = <1>;
  81                         #reset-cells = <1>;
  82                 };
  83 +
  84 +               pci@1b500000 {
  85 +                       compatible = "qcom,pcie-ipq8064";
  86 +                       reg = <0x1b500000 0x1000
  87 +                              0x1b502000 0x80
  88 +                              0x1b600000 0x100
  89 +                               >;
  90 +                       reg-names = "base", "elbi", "parf";
  91 +
  92 +                       #address-cells = <3>;
  93 +                       #size-cells = <2>;
  94 +                       device_type = "pci";
  95 +                       interrupts = <0 35 0x0
  96 +                                     0 36 0x0
  97 +                                     0 37 0x0
  98 +                                     0 38 0x0
  99 +                                     0 39 0x0>;
 100 +                       resets = <&gcc PCIE_ACLK_RESET>,
 101 +                                <&gcc PCIE_HCLK_RESET>,
 102 +                                <&gcc PCIE_POR_RESET>,
 103 +                                <&gcc PCIE_PCI_RESET>,
 104 +                                <&gcc PCIE_PHY_RESET>;
 105 +                       reset-names = "axi", "ahb", "por", "pci", "phy";
 106 +
 107 +                       clocks = <&gcc PCIE_A_CLK>,
 108 +                                <&gcc PCIE_H_CLK>,
 109 +                                <&gcc PCIE_PHY_CLK>;
 110 +                       clock-names = "core", "iface", "phy";
 111 +                       status = "disabled";
 112 +               };
 113 +
 114 +               pci@1b700000 {
 115 +                       compatible = "qcom,pcie-ipq8064";
 116 +                       reg = <0x1b700000 0x1000
 117 +                              0x1b702000 0x80
 118 +                              0x1b800000 0x100
 119 +                               >;
 120 +                       reg-names = "base", "elbi", "parf";
 121 +
 122 +                       #address-cells = <3>;
 123 +                       #size-cells = <2>;
 124 +                       device_type = "pci";
 125 +
 126 +                       interrupts = <0 57 0x0
 127 +                                     0 58 0x0
 128 +                                     0 59 0x0
 129 +                                     0 60 0x0
 130 +                                     0 61 0x0>;
 131 +                       resets = <&gcc PCIE_1_ACLK_RESET>,
 132 +                                <&gcc PCIE_1_HCLK_RESET>,
 133 +                                <&gcc PCIE_1_POR_RESET>,
 134 +                                <&gcc PCIE_1_PCI_RESET>,
 135 +                                <&gcc PCIE_1_PHY_RESET>;
 136 +                       reset-names = "axi", "ahb", "por", "pci", "phy";
 137 +
 138 +                       clocks = <&gcc PCIE_1_A_CLK>,
 139 +                                <&gcc PCIE_1_H_CLK>,
 140 +                                <&gcc PCIE_1_PHY_CLK>;
 141 +                       clock-names = "core", "iface", "phy";
 142 +                       status = "disabled";
 143 +               };
 144 +
 145 +               pci@1b900000 {
 146 +                       compatible = "qcom,pcie-ipq8064";
 147 +                       reg = <0x1b900000 0x1000
 148 +                              0x1b902000 0x80
 149 +                              0x1ba00000 0x100
 150 +                               >;
 151 +                       reg-names = "base", "elbi", "parf";
 152 +
 153 +                       #address-cells = <3>;
 154 +                       #size-cells = <2>;
 155 +                       device_type = "pci";
 156 +
 157 +                       interrupts = <0 71 0x0
 158 +                                     0 72 0x0
 159 +                                     0 73 0x0
 160 +                                     0 74 0x0
 161 +                                     0 75 0x0>;
 162 +                       resets = <&gcc PCIE_2_ACLK_RESET>,
 163 +                                <&gcc PCIE_2_HCLK_RESET>,
 164 +                                <&gcc PCIE_2_POR_RESET>,
 165 +                                <&gcc PCIE_2_PCI_RESET>,
 166 +                                <&gcc PCIE_2_PHY_RESET>;
 167 +                       reset-names = "axi", "ahb", "por", "pci", "phy";
 168 +
 169 +                       clocks = <&gcc PCIE_2_A_CLK>,
 170 +                                <&gcc PCIE_2_H_CLK>,
 171 +                                <&gcc PCIE_2_PHY_CLK>;
 172 +                       clock-names = "core", "iface", "phy";
 173 +                       status = "disabled";
 174 +               };
 175         };
 176  };
 177 --
 178 1.7.10.4
 179