1 From b9eaa80146abb09bcc7e6d8b33fca476453c839c Mon Sep 17 00:00:00 2001
2 From: Andy Gross <agross@codeaurora.org>
3 Date: Wed, 14 May 2014 22:01:16 -0500
4 Subject: [PATCH 137/182] ARM: qcom-ipq8064-ap148: Add SPI related bindings
6 Signed-off-by: Andy Gross <agross@codeaurora.org>
8 arch/arm/boot/dts/qcom-ipq8064-ap148.dts | 42 ++++++++++++++++++++++++++
9 arch/arm/boot/dts/qcom-ipq8064.dtsi | 47 ++++++++++++++++++++++++++++++
10 2 files changed, 89 insertions(+)
12 --- a/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
13 +++ b/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
19 + spi_pins: spi_pins {
21 + pins = "gpio18", "gpio19", "gpio21";
23 + drive-strength = <10>;
31 pinctrl-names = "default";
35 + gsbi5: gsbi@1a200000 {
36 + qcom,mode = <GSBI_PROT_SPI>;
39 + spi4: spi@1a280000 {
41 + spi-max-frequency = <50000000>;
43 + pinctrl-0 = <&spi_pins>;
44 + pinctrl-names = "default";
46 + cs-gpios = <&qcom_pinmux 20 0>;
49 + compatible = "s25fl256s1";
50 + #address-cells = <1>;
52 + spi-max-frequency = <50000000>;
57 + reg = <0x0 0x1000000>;
62 + reg = <0x1000000 0x1000000>;
69 --- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
70 +++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
75 + gsbi5: gsbi@1a200000 {
76 + compatible = "qcom,gsbi-v1.0.0";
77 + reg = <0x1a200000 0x100>;
78 + clocks = <&gcc GSBI5_H_CLK>;
79 + clock-names = "iface";
80 + #address-cells = <1>;
83 + status = "disabled";
86 + compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
87 + reg = <0x1a240000 0x1000>,
88 + <0x1a200000 0x1000>;
89 + interrupts = <0 154 0x0>;
90 + clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>;
91 + clock-names = "core", "iface";
92 + status = "disabled";
96 + compatible = "qcom,i2c-qup-v1.1.1";
97 + reg = <0x1a280000 0x1000>;
98 + interrupts = <0 155 0>;
100 + clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>;
101 + clock-names = "core", "iface";
102 + status = "disabled";
104 + #address-cells = <1>;
109 + compatible = "qcom,spi-qup-v1.1.1";
110 + reg = <0x1a280000 0x1000>;
111 + interrupts = <0 155 0>;
113 + clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>;
114 + clock-names = "core", "iface";
115 + status = "disabled";
117 + #address-cells = <1>;
123 compatible = "qcom,ssbi";
124 reg = <0x00500000 0x1000>;