target/linux/ipq806x/patches/0130-ARM-qcom-Add-initial-IPQ8064-SoC-and-AP148-device-tr.patch

   1 From 1c6e51ffb10f5bf93a3018c7c1e04d7ed93f944e Mon Sep 17 00:00:00 2001
   2 From: Kumar Gala <galak@codeaurora.org>
   3 Date: Fri, 7 Mar 2014 10:56:59 -0600
   4 Subject: [PATCH 130/182] ARM: qcom: Add initial IPQ8064 SoC and AP148 device
   5  trees
   6
   7 Add basic IPQ8064 SoC include device tree and support for basic booting on
   8 the AP148 Reference board.
   9
  10 Signed-off-by: Kumar Gala <galak@codeaurora.org>
  11 ---
  12  arch/arm/boot/dts/Makefile               |    1 +
  13  arch/arm/boot/dts/qcom-ipq8064-ap148.dts |   25 +++++
  14  arch/arm/boot/dts/qcom-ipq8064-v1.0.dtsi |    1 +
  15  arch/arm/boot/dts/qcom-ipq8064.dtsi      |  176 ++++++++++++++++++++++++++++++
  16  arch/arm/mach-qcom/board.c               |    2 +
  17  5 files changed, 205 insertions(+)
  18  create mode 100644 arch/arm/boot/dts/qcom-ipq8064-ap148.dts
  19  create mode 100644 arch/arm/boot/dts/qcom-ipq8064-v1.0.dtsi
  20  create mode 100644 arch/arm/boot/dts/qcom-ipq8064.dtsi
  21
  22 --- a/arch/arm/boot/dts/Makefile
  23 +++ b/arch/arm/boot/dts/Makefile
  24 @@ -235,6 +235,7 @@ dtb-$(CONFIG_ARCH_QCOM) += \
  25         qcom-apq8064-ifc6410.dtb \
  26         qcom-apq8074-dragonboard.dtb \
  27         qcom-apq8084-mtp.dtb \
  28 +       qcom-ipq8064-ap148.dtb \
  29         qcom-msm8660-surf.dtb \
  30         qcom-msm8960-cdp.dtb
  31  dtb-$(CONFIG_ARCH_U8500) += ste-snowball.dtb \
  32 --- /dev/null
  33 +++ b/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
  34 @@ -0,0 +1,25 @@
  35 +#include "qcom-ipq8064-v1.0.dtsi"
  36 +
  37 +/ {
  38 +       model = "Qualcomm IPQ8064/AP148";
  39 +       compatible = "qcom,ipq8064-ap148", "qcom,ipq8064";
  40 +
  41 +       reserved-memory {
  42 +               #address-cells = <1>;
  43 +               #size-cells = <1>;
  44 +               rsvd@41200000 {
  45 +                       reg = <0x41200000 0x300000>;
  46 +                       no-map;
  47 +               };
  48 +       };
  49 +
  50 +       soc {
  51 +               gsbi@16300000 {
  52 +                       qcom,mode = <GSBI_PROT_I2C_UART>;
  53 +                       status = "ok";
  54 +                       serial@16340000 {
  55 +                               status = "ok";
  56 +                       };
  57 +               };
  58 +       };
  59 +};
  60 --- /dev/null
  61 +++ b/arch/arm/boot/dts/qcom-ipq8064-v1.0.dtsi
  62 @@ -0,0 +1 @@
  63 +#include "qcom-ipq8064.dtsi"
  64 --- /dev/null
  65 +++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
  66 @@ -0,0 +1,176 @@
  67 +/dts-v1/;
  68 +
  69 +#include "skeleton.dtsi"
  70 +#include <dt-bindings/clock/qcom,gcc-ipq806x.h>
  71 +#include <dt-bindings/soc/qcom,gsbi.h>
  72 +
  73 +/ {
  74 +       model = "Qualcomm IPQ8064";
  75 +       compatible = "qcom,ipq8064";
  76 +       interrupt-parent = <&intc>;
  77 +
  78 +       cpus {
  79 +               #address-cells = <1>;
  80 +               #size-cells = <0>;
  81 +
  82 +               cpu@0 {
  83 +                       compatible = "qcom,krait";
  84 +                       enable-method = "qcom,kpss-acc-v1";
  85 +                       device_type = "cpu";
  86 +                       reg = <0>;
  87 +                       next-level-cache = <&L2>;
  88 +                       qcom,acc = <&acc0>;
  89 +                       qcom,saw = <&saw0>;
  90 +               };
  91 +
  92 +               cpu@1 {
  93 +                       compatible = "qcom,krait";
  94 +                       enable-method = "qcom,kpss-acc-v1";
  95 +                       device_type = "cpu";
  96 +                       reg = <1>;
  97 +                       next-level-cache = <&L2>;
  98 +                       qcom,acc = <&acc1>;
  99 +                       qcom,saw = <&saw1>;
 100 +               };
 101 +
 102 +               L2: l2-cache {
 103 +                       compatible = "cache";
 104 +                       cache-level = <2>;
 105 +               };
 106 +       };
 107 +
 108 +       cpu-pmu {
 109 +               compatible = "qcom,krait-pmu";
 110 +               interrupts = <1 10 0x304>;
 111 +       };
 112 +
 113 +       reserved-memory {
 114 +               #address-cells = <1>;
 115 +               #size-cells = <1>;
 116 +               ranges;
 117 +
 118 +               nss@40000000 {
 119 +                       reg = <0x40000000 0x1000000>;
 120 +                       no-map;
 121 +               };
 122 +
 123 +               smem@41000000 {
 124 +                       reg = <0x41000000 0x200000>;
 125 +                       no-map;
 126 +               };
 127 +       };
 128 +
 129 +       soc: soc {
 130 +               #address-cells = <1>;
 131 +               #size-cells = <1>;
 132 +               ranges;
 133 +               compatible = "simple-bus";
 134 +
 135 +               qcom_pinmux: pinmux@800000 {
 136 +                       compatible = "qcom,ipq8064-pinctrl";
 137 +                       reg = <0x800000 0x4000>;
 138 +
 139 +                       gpio-controller;
 140 +                       #gpio-cells = <2>;
 141 +                       interrupt-controller;
 142 +                       #interrupt-cells = <2>;
 143 +                       interrupts = <0 32 0x4>;
 144 +               };
 145 +
 146 +               intc: interrupt-controller@2000000 {
 147 +                       compatible = "qcom,msm-qgic2";
 148 +                       interrupt-controller;
 149 +                       #interrupt-cells = <3>;
 150 +                       reg = <0x02000000 0x1000>,
 151 +                             <0x02002000 0x1000>;
 152 +               };
 153 +
 154 +               timer@200a000 {
 155 +                       compatible = "qcom,kpss-timer", "qcom,msm-timer";
 156 +                       interrupts = <1 1 0x301>,
 157 +                                    <1 2 0x301>,
 158 +                                    <1 3 0x301>;
 159 +                       reg = <0x0200a000 0x100>;
 160 +                       clock-frequency = <25000000>,
 161 +                                         <32768>;
 162 +                       cpu-offset = <0x80000>;
 163 +               };
 164 +
 165 +               acc0: clock-controller@2088000 {
 166 +                       compatible = "qcom,kpss-acc-v1";
 167 +                       reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
 168 +               };
 169 +
 170 +               acc1: clock-controller@2098000 {
 171 +                       compatible = "qcom,kpss-acc-v1";
 172 +                       reg = <0x02098000 0x1000>, <0x02008000 0x1000>;
 173 +               };
 174 +
 175 +               saw0: regulator@2089000 {
 176 +                       compatible = "qcom,saw2";
 177 +                       reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
 178 +                       regulator;
 179 +               };
 180 +
 181 +               saw1: regulator@2099000 {
 182 +                       compatible = "qcom,saw2";
 183 +                       reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
 184 +                       regulator;
 185 +               };
 186 +
 187 +               gsbi2: gsbi@12480000 {
 188 +                       compatible = "qcom,gsbi-v1.0.0";
 189 +                       reg = <0x12480000 0x100>;
 190 +                       clocks = <&gcc GSBI2_H_CLK>;
 191 +                       clock-names = "iface";
 192 +                       #address-cells = <1>;
 193 +                       #size-cells = <1>;
 194 +                       ranges;
 195 +                       status = "disabled";
 196 +
 197 +                       serial@12490000 {
 198 +                               compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
 199 +                               reg = <0x12490000 0x1000>,
 200 +                                     <0x12480000 0x1000>;
 201 +                               interrupts = <0 195 0x0>;
 202 +                               clocks = <&gcc GSBI2_UART_CLK>, <&gcc GSBI2_H_CLK>;
 203 +                               clock-names = "core", "iface";
 204 +                               status = "disabled";
 205 +                       };
 206 +               };
 207 +
 208 +               gsbi4: gsbi@16300000 {
 209 +                       compatible = "qcom,gsbi-v1.0.0";
 210 +                       reg = <0x16300000 0x100>;
 211 +                       clocks = <&gcc GSBI4_H_CLK>;
 212 +                       clock-names = "iface";
 213 +                       #address-cells = <1>;
 214 +                       #size-cells = <1>;
 215 +                       ranges;
 216 +                       status = "disabled";
 217 +
 218 +                       serial@16340000 {
 219 +                               compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
 220 +                               reg = <0x16340000 0x1000>,
 221 +                                     <0x16300000 0x1000>;
 222 +                               interrupts = <0 152 0x0>;
 223 +                               clocks = <&gcc GSBI4_UART_CLK>, <&gcc GSBI4_H_CLK>;
 224 +                               clock-names = "core", "iface";
 225 +                               status = "disabled";
 226 +                       };
 227 +               };
 228 +
 229 +               qcom,ssbi@500000 {
 230 +                       compatible = "qcom,ssbi";
 231 +                       reg = <0x00500000 0x1000>;
 232 +                       qcom,controller-type = "pmic-arbiter";
 233 +               };
 234 +
 235 +               gcc: clock-controller@900000 {
 236 +                       compatible = "qcom,gcc-ipq8064";
 237 +                       reg = <0x00900000 0x4000>;
 238 +                       #clock-cells = <1>;
 239 +                       #reset-cells = <1>;
 240 +               };
 241 +       };
 242 +};
 243 --- a/arch/arm/mach-qcom/board.c
 244 +++ b/arch/arm/mach-qcom/board.c
 245 @@ -18,6 +18,8 @@ static const char * const qcom_dt_match[
 246         "qcom,apq8064",
 247         "qcom,apq8074-dragonboard",
 248         "qcom,apq8084",
 249 +       "qcom,ipq8062",
 250 +       "qcom,ipq8064",
 251         "qcom,msm8660-surf",
 252         "qcom,msm8960-cdp",
 253         NULL