1 From 5a58dbf4d82c29f7e6d89abc3520bed1aa2af05c Mon Sep 17 00:00:00 2001
2 From: Andy Gross <agross@codeaurora.org>
3 Date: Thu, 24 Apr 2014 11:31:20 -0500
4 Subject: [PATCH 088/182] soc: qcom: Add device tree binding for GSBI
6 Add device tree binding support for the QCOM GSBI driver.
8 Signed-off-by: Andy Gross <agross@codeaurora.org>
9 Signed-off-by: Kumar Gala <galak@codeaurora.org>
11 .../devicetree/bindings/soc/qcom/qcom,gsbi.txt | 78 ++++++++++++++++++++
12 include/dt-bindings/soc/qcom,gsbi.h | 26 +++++++
13 2 files changed, 104 insertions(+)
14 create mode 100644 Documentation/devicetree/bindings/soc/qcom/qcom,gsbi.txt
15 create mode 100644 include/dt-bindings/soc/qcom,gsbi.h
18 +++ b/Documentation/devicetree/bindings/soc/qcom/qcom,gsbi.txt
20 +QCOM GSBI (General Serial Bus Interface) Driver
22 +The GSBI controller is modeled as a node with zero or more child nodes, each
23 +representing a serial sub-node device that is mux'd as part of the GSBI
24 +configuration settings. The mode setting will govern the input/output mode of
28 +- compatible: must contain "qcom,gsbi-v1.0.0" for APQ8064/IPQ8064
29 +- reg: Address range for GSBI registers
30 +- clocks: required clock
31 +- clock-names: must contain "iface" entry
32 +- qcom,mode : indicates MUX value for configuration of the serial interface.
33 + Please reference dt-bindings/soc/qcom,gsbi.h for valid mux values.
36 +- qcom,crci : indicates CRCI MUX value for QUP CRCI ports. Please reference
37 + dt-bindings/soc/qcom,gsbi.h for valid CRCI mux values.
39 +Required properties if child node exists:
40 +- #address-cells: Must be 1
41 +- #size-cells: Must be 1
42 +- ranges: Must be present
44 +Properties for children:
46 +A GSBI controller node can contain 0 or more child nodes representing serial
47 +devices. These serial devices can be a QCOM UART, I2C controller, spi
48 +controller, or some combination of aforementioned devices.
50 +See the following for child node definitions:
51 +Documentation/devicetree/bindings/i2c/qcom,i2c-qup.txt
52 +Documentation/devicetree/bindings/spi/qcom,spi-qup.txt
53 +Documentation/devicetree/bindings/serial/qcom,msm-uartdm.txt
57 +#include <dt-bindings/soc/qcom,gsbi.h>
60 + compatible = "qcom,gsbi-v1.0.0";
61 + reg = <0x16300000 0x100>;
62 + clocks = <&gcc GSBI4_H_CLK>;
63 + clock-names = "iface";
64 + #address-cells = <1>;
67 + qcom,mode = <GSBI_PROT_I2C_UART>;
68 + qcom,crci = <GSBI_CRCI_QUP>;
70 + /* child nodes go under here */
72 + i2c_qup4: i2c@16380000 {
73 + compatible = "qcom,i2c-qup-v1.1.1";
74 + reg = <0x16380000 0x1000>;
75 + interrupts = <0 153 0>;
77 + clocks = <&gcc GSBI4_QUP_CLK>, <&gcc GSBI4_H_CLK>;
78 + clock-names = "core", "iface";
80 + clock-frequency = <200000>;
82 + #address-cells = <1>;
87 + uart4: serial@16340000 {
88 + compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
89 + reg = <0x16340000 0x1000>,
90 + <0x16300000 0x1000>;
91 + interrupts = <0 152 0x0>;
92 + clocks = <&gcc GSBI4_UART_CLK>, <&gcc GSBI4_H_CLK>;
93 + clock-names = "core", "iface";
99 +++ b/include/dt-bindings/soc/qcom,gsbi.h
101 +/* Copyright (c) 2013, The Linux Foundation. All rights reserved.
103 + * This program is free software; you can redistribute it and/or modify
104 + * it under the terms of the GNU General Public License version 2 and
105 + * only version 2 as published by the Free Software Foundation.
107 + * This program is distributed in the hope that it will be useful,
108 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
109 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
110 + * GNU General Public License for more details.
112 +#ifndef __DT_BINDINGS_QCOM_GSBI_H
113 +#define __DT_BINDINGS_QCOM_GSBI_H
115 +#define GSBI_PROT_IDLE 0
116 +#define GSBI_PROT_I2C_UIM 1
117 +#define GSBI_PROT_I2C 2
118 +#define GSBI_PROT_SPI 3
119 +#define GSBI_PROT_UART_W_FC 4
120 +#define GSBI_PROT_UIM 5
121 +#define GSBI_PROT_I2C_UART 6
123 +#define GSBI_CRCI_QUP 0
124 +#define GSBI_CRCI_UART 1