target/linux/ipq806x/patches/0057-spmi-pmic_arb-add-support-for-interrupt-handling.patch

   1 From b5bc51d44485c7ce0ca180a8c5de11a206f686e8 Mon Sep 17 00:00:00 2001
   2 From: Josh Cartwright <joshc@codeaurora.org>
   3 Date: Wed, 12 Feb 2014 13:44:25 -0600
   4 Subject: [PATCH 057/182] spmi: pmic_arb: add support for interrupt handling
   5
   6 The Qualcomm PMIC Arbiter, in addition to being a basic SPMI controller,
   7 also implements interrupt handling for slave devices.  Note, this is
   8 outside the scope of SPMI, as SPMI leaves interrupt handling completely
   9 unspecified.
  10
  11 Extend the driver to provide a irq_chip implementation and chained irq
  12 handling which allows for these interrupts to be used.
  13
  14 Cc: Thomas Gleixner <tglx@linutronix.de>
  15 Signed-off-by: Josh Cartwright <joshc@codeaurora.org>
  16 Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
  17 ---
  18  drivers/spmi/Kconfig         |    1 +
  19  drivers/spmi/spmi-pmic-arb.c |  377 +++++++++++++++++++++++++++++++++++++++++-
  20  2 files changed, 376 insertions(+), 2 deletions(-)
  21
  22 --- a/drivers/spmi/Kconfig
  23 +++ b/drivers/spmi/Kconfig
  24 @@ -13,6 +13,7 @@ if SPMI
  25  config SPMI_MSM_PMIC_ARB
  26         tristate "Qualcomm MSM SPMI Controller (PMIC Arbiter)"
  27         depends on ARM
  28 +       depends on IRQ_DOMAIN
  29         depends on ARCH_MSM || COMPILE_TEST
  30         default ARCH_MSM
  31         help
  32 --- a/drivers/spmi/spmi-pmic-arb.c
  33 +++ b/drivers/spmi/spmi-pmic-arb.c
  34 @@ -13,6 +13,9 @@
  35  #include <linux/err.h>
  36  #include <linux/interrupt.h>
  37  #include <linux/io.h>
  38 +#include <linux/irqchip/chained_irq.h>
  39 +#include <linux/irqdomain.h>
  40 +#include <linux/irq.h>
  41  #include <linux/kernel.h>
  42  #include <linux/module.h>
  43  #include <linux/of.h>
  44 @@ -103,6 +106,14 @@ enum pmic_arb_cmd_op_code {
  45   * @cnfg:              address of the PMIC Arbiter configuration registers.
  46   * @lock:              lock to synchronize accesses.
  47   * @channel:           which channel to use for accesses.
  48 + * @irq:               PMIC ARB interrupt.
  49 + * @ee:                        the current Execution Environment
  50 + * @min_apid:          minimum APID (used for bounding IRQ search)
  51 + * @max_apid:          maximum APID
  52 + * @mapping_table:     in-memory copy of PPID -> APID mapping table.
  53 + * @domain:            irq domain object for PMIC IRQ domain
  54 + * @spmic:             SPMI controller object
  55 + * @apid_to_ppid:      cached mapping from APID to PPID
  56   */
  57  struct spmi_pmic_arb_dev {
  58         void __iomem            *base;
  59 @@ -110,6 +121,14 @@ struct spmi_pmic_arb_dev {
  60         void __iomem            *cnfg;
  61         raw_spinlock_t          lock;
  62         u8                      channel;
  63 +       int                     irq;
  64 +       u8                      ee;
  65 +       u8                      min_apid;
  66 +       u8                      max_apid;
  67 +       u32                     mapping_table[SPMI_MAPPING_TABLE_LEN];
  68 +       struct irq_domain       *domain;
  69 +       struct spmi_controller  *spmic;
  70 +       u16                     apid_to_ppid[256];
  71  };
  72
  73  static inline u32 pmic_arb_base_read(struct spmi_pmic_arb_dev *dev, u32 offset)
  74 @@ -306,12 +325,316 @@ static int pmic_arb_write_cmd(struct spm
  75         return rc;
  76  }
  77
  78 +enum qpnpint_regs {
  79 +       QPNPINT_REG_RT_STS              = 0x10,
  80 +       QPNPINT_REG_SET_TYPE            = 0x11,
  81 +       QPNPINT_REG_POLARITY_HIGH       = 0x12,
  82 +       QPNPINT_REG_POLARITY_LOW        = 0x13,
  83 +       QPNPINT_REG_LATCHED_CLR         = 0x14,
  84 +       QPNPINT_REG_EN_SET              = 0x15,
  85 +       QPNPINT_REG_EN_CLR              = 0x16,
  86 +       QPNPINT_REG_LATCHED_STS         = 0x18,
  87 +};
  88 +
  89 +struct spmi_pmic_arb_qpnpint_type {
  90 +       u8 type; /* 1 -> edge */
  91 +       u8 polarity_high;
  92 +       u8 polarity_low;
  93 +} __packed;
  94 +
  95 +/* Simplified accessor functions for irqchip callbacks */
  96 +static void qpnpint_spmi_write(struct irq_data *d, u8 reg, void *buf,
  97 +                              size_t len)
  98 +{
  99 +       struct spmi_pmic_arb_dev *pa = irq_data_get_irq_chip_data(d);
 100 +       u8 sid = d->hwirq >> 24;
 101 +       u8 per = d->hwirq >> 16;
 102 +
 103 +       if (pmic_arb_write_cmd(pa->spmic, SPMI_CMD_EXT_WRITEL, sid,
 104 +                              (per << 8) + reg, buf, len))
 105 +               dev_err_ratelimited(&pa->spmic->dev,
 106 +                               "failed irqchip transaction on %x\n",
 107 +                                   d->irq);
 108 +}
 109 +
 110 +static void qpnpint_spmi_read(struct irq_data *d, u8 reg, void *buf, size_t len)
 111 +{
 112 +       struct spmi_pmic_arb_dev *pa = irq_data_get_irq_chip_data(d);
 113 +       u8 sid = d->hwirq >> 24;
 114 +       u8 per = d->hwirq >> 16;
 115 +
 116 +       if (pmic_arb_read_cmd(pa->spmic, SPMI_CMD_EXT_READL, sid,
 117 +                             (per << 8) + reg, buf, len))
 118 +               dev_err_ratelimited(&pa->spmic->dev,
 119 +                               "failed irqchip transaction on %x\n",
 120 +                                   d->irq);
 121 +}
 122 +
 123 +static void periph_interrupt(struct spmi_pmic_arb_dev *pa, u8 apid)
 124 +{
 125 +       unsigned int irq;
 126 +       u32 status;
 127 +       int id;
 128 +
 129 +       status = readl_relaxed(pa->intr + SPMI_PIC_IRQ_STATUS(apid));
 130 +       while (status) {
 131 +               id = ffs(status) - 1;
 132 +               status &= ~(1 << id);
 133 +               irq = irq_find_mapping(pa->domain,
 134 +                                      pa->apid_to_ppid[apid] << 16
 135 +                                    | id << 8
 136 +                                    | apid);
 137 +               generic_handle_irq(irq);
 138 +       }
 139 +}
 140 +
 141 +static void pmic_arb_chained_irq(unsigned int irq, struct irq_desc *desc)
 142 +{
 143 +       struct spmi_pmic_arb_dev *pa = irq_get_handler_data(irq);
 144 +       struct irq_chip *chip = irq_get_chip(irq);
 145 +       void __iomem *intr = pa->intr;
 146 +       int first = pa->min_apid >> 5;
 147 +       int last = pa->max_apid >> 5;
 148 +       u32 status;
 149 +       int i, id;
 150 +
 151 +       chained_irq_enter(chip, desc);
 152 +
 153 +       for (i = first; i <= last; ++i) {
 154 +               status = readl_relaxed(intr +
 155 +                                      SPMI_PIC_OWNER_ACC_STATUS(pa->ee, i));
 156 +               while (status) {
 157 +                       id = ffs(status) - 1;
 158 +                       status &= ~(1 << id);
 159 +                       periph_interrupt(pa, id + i * 32);
 160 +               }
 161 +       }
 162 +
 163 +       chained_irq_exit(chip, desc);
 164 +}
 165 +
 166 +static void qpnpint_irq_ack(struct irq_data *d)
 167 +{
 168 +       struct spmi_pmic_arb_dev *pa = irq_data_get_irq_chip_data(d);
 169 +       u8 irq  = d->hwirq >> 8;
 170 +       u8 apid = d->hwirq;
 171 +       unsigned long flags;
 172 +       u8 data;
 173 +
 174 +       raw_spin_lock_irqsave(&pa->lock, flags);
 175 +       writel_relaxed(1 << irq, pa->intr + SPMI_PIC_IRQ_CLEAR(apid));
 176 +       raw_spin_unlock_irqrestore(&pa->lock, flags);
 177 +
 178 +       data = 1 << irq;
 179 +       qpnpint_spmi_write(d, QPNPINT_REG_LATCHED_CLR, &data, 1);
 180 +}
 181 +
 182 +static void qpnpint_irq_mask(struct irq_data *d)
 183 +{
 184 +       struct spmi_pmic_arb_dev *pa = irq_data_get_irq_chip_data(d);
 185 +       u8 irq  = d->hwirq >> 8;
 186 +       u8 apid = d->hwirq;
 187 +       unsigned long flags;
 188 +       u32 status;
 189 +       u8 data;
 190 +
 191 +       raw_spin_lock_irqsave(&pa->lock, flags);
 192 +       status = readl_relaxed(pa->intr + SPMI_PIC_ACC_ENABLE(apid));
 193 +       if (status & SPMI_PIC_ACC_ENABLE_BIT) {
 194 +               status = status & ~SPMI_PIC_ACC_ENABLE_BIT;
 195 +               writel_relaxed(status, pa->intr + SPMI_PIC_ACC_ENABLE(apid));
 196 +       }
 197 +       raw_spin_unlock_irqrestore(&pa->lock, flags);
 198 +
 199 +       data = 1 << irq;
 200 +       qpnpint_spmi_write(d, QPNPINT_REG_EN_CLR, &data, 1);
 201 +}
 202 +
 203 +static void qpnpint_irq_unmask(struct irq_data *d)
 204 +{
 205 +       struct spmi_pmic_arb_dev *pa = irq_data_get_irq_chip_data(d);
 206 +       u8 irq  = d->hwirq >> 8;
 207 +       u8 apid = d->hwirq;
 208 +       unsigned long flags;
 209 +       u32 status;
 210 +       u8 data;
 211 +
 212 +       raw_spin_lock_irqsave(&pa->lock, flags);
 213 +       status = readl_relaxed(pa->intr + SPMI_PIC_ACC_ENABLE(apid));
 214 +       if (!(status & SPMI_PIC_ACC_ENABLE_BIT)) {
 215 +               writel_relaxed(status | SPMI_PIC_ACC_ENABLE_BIT,
 216 +                               pa->intr + SPMI_PIC_ACC_ENABLE(apid));
 217 +       }
 218 +       raw_spin_unlock_irqrestore(&pa->lock, flags);
 219 +
 220 +       data = 1 << irq;
 221 +       qpnpint_spmi_write(d, QPNPINT_REG_EN_SET, &data, 1);
 222 +}
 223 +
 224 +static void qpnpint_irq_enable(struct irq_data *d)
 225 +{
 226 +       u8 irq  = d->hwirq >> 8;
 227 +       u8 data;
 228 +
 229 +       qpnpint_irq_unmask(d);
 230 +
 231 +       data = 1 << irq;
 232 +       qpnpint_spmi_write(d, QPNPINT_REG_LATCHED_CLR, &data, 1);
 233 +}
 234 +
 235 +static int qpnpint_irq_set_type(struct irq_data *d, unsigned int flow_type)
 236 +{
 237 +       struct spmi_pmic_arb_qpnpint_type type;
 238 +       u8 irq = d->hwirq >> 8;
 239 +
 240 +       qpnpint_spmi_read(d, QPNPINT_REG_SET_TYPE, &type, sizeof(type));
 241 +
 242 +       if (flow_type & (IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING)) {
 243 +               type.type |= 1 << irq;
 244 +               if (flow_type & IRQF_TRIGGER_RISING)
 245 +                       type.polarity_high |= 1 << irq;
 246 +               if (flow_type & IRQF_TRIGGER_FALLING)
 247 +                       type.polarity_low  |= 1 << irq;
 248 +       } else {
 249 +               if ((flow_type & (IRQF_TRIGGER_HIGH)) &&
 250 +                   (flow_type & (IRQF_TRIGGER_LOW)))
 251 +                       return -EINVAL;
 252 +
 253 +               type.type &= ~(1 << irq); /* level trig */
 254 +               if (flow_type & IRQF_TRIGGER_HIGH)
 255 +                       type.polarity_high |= 1 << irq;
 256 +               else
 257 +                       type.polarity_low  |= 1 << irq;
 258 +       }
 259 +
 260 +       qpnpint_spmi_write(d, QPNPINT_REG_SET_TYPE, &type, sizeof(type));
 261 +       return 0;
 262 +}
 263 +
 264 +static struct irq_chip pmic_arb_irqchip = {
 265 +       .name           = "pmic_arb",
 266 +       .irq_enable     = qpnpint_irq_enable,
 267 +       .irq_ack        = qpnpint_irq_ack,
 268 +       .irq_mask       = qpnpint_irq_mask,
 269 +       .irq_unmask     = qpnpint_irq_unmask,
 270 +       .irq_set_type   = qpnpint_irq_set_type,
 271 +       .flags          = IRQCHIP_MASK_ON_SUSPEND
 272 +                       | IRQCHIP_SKIP_SET_WAKE,
 273 +};
 274 +
 275 +struct spmi_pmic_arb_irq_spec {
 276 +       unsigned slave:4;
 277 +       unsigned per:8;
 278 +       unsigned irq:3;
 279 +};
 280 +
 281 +static int search_mapping_table(struct spmi_pmic_arb_dev *pa,
 282 +                               struct spmi_pmic_arb_irq_spec *spec,
 283 +                               u8 *apid)
 284 +{
 285 +       u16 ppid = spec->slave << 8 | spec->per;
 286 +       u32 *mapping_table = pa->mapping_table;
 287 +       int index = 0, i;
 288 +       u32 data;
 289 +
 290 +       for (i = 0; i < SPMI_MAPPING_TABLE_TREE_DEPTH; ++i) {
 291 +               data = mapping_table[index];
 292 +
 293 +               if (ppid & (1 << SPMI_MAPPING_BIT_INDEX(data))) {
 294 +                       if (SPMI_MAPPING_BIT_IS_1_FLAG(data)) {
 295 +                               index = SPMI_MAPPING_BIT_IS_1_RESULT(data);
 296 +                       } else {
 297 +                               *apid = SPMI_MAPPING_BIT_IS_1_RESULT(data);
 298 +                               return 0;
 299 +                       }
 300 +               } else {
 301 +                       if (SPMI_MAPPING_BIT_IS_0_FLAG(data)) {
 302 +                               index = SPMI_MAPPING_BIT_IS_0_RESULT(data);
 303 +                       } else {
 304 +                               *apid = SPMI_MAPPING_BIT_IS_0_RESULT(data);
 305 +                               return 0;
 306 +                       }
 307 +               }
 308 +       }
 309 +
 310 +       return -ENODEV;
 311 +}
 312 +
 313 +static int qpnpint_irq_domain_dt_translate(struct irq_domain *d,
 314 +                                          struct device_node *controller,
 315 +                                          const u32 *intspec,
 316 +                                          unsigned int intsize,
 317 +                                          unsigned long *out_hwirq,
 318 +                                          unsigned int *out_type)
 319 +{
 320 +       struct spmi_pmic_arb_dev *pa = d->host_data;
 321 +       struct spmi_pmic_arb_irq_spec spec;
 322 +       int err;
 323 +       u8 apid;
 324 +
 325 +       dev_dbg(&pa->spmic->dev,
 326 +               "intspec[0] 0x%1x intspec[1] 0x%02x intspec[2] 0x%02x\n",
 327 +               intspec[0], intspec[1], intspec[2]);
 328 +
 329 +       if (d->of_node != controller)
 330 +               return -EINVAL;
 331 +       if (intsize != 4)
 332 +               return -EINVAL;
 333 +       if (intspec[0] > 0xF || intspec[1] > 0xFF || intspec[2] > 0x7)
 334 +               return -EINVAL;
 335 +
 336 +       spec.slave = intspec[0];
 337 +       spec.per   = intspec[1];
 338 +       spec.irq   = intspec[2];
 339 +
 340 +       err = search_mapping_table(pa, &spec, &apid);
 341 +       if (err)
 342 +               return err;
 343 +
 344 +       pa->apid_to_ppid[apid] = spec.slave << 8 | spec.per;
 345 +
 346 +       /* Keep track of {max,min}_apid for bounding search during interrupt */
 347 +       if (apid > pa->max_apid)
 348 +               pa->max_apid = apid;
 349 +       if (apid < pa->min_apid)
 350 +               pa->min_apid = apid;
 351 +
 352 +       *out_hwirq = spec.slave << 24
 353 +                  | spec.per   << 16
 354 +                  | spec.irq   << 8
 355 +                  | apid;
 356 +       *out_type  = intspec[3] & IRQ_TYPE_SENSE_MASK;
 357 +
 358 +       dev_dbg(&pa->spmic->dev, "out_hwirq = %lu\n", *out_hwirq);
 359 +
 360 +       return 0;
 361 +}
 362 +
 363 +static int qpnpint_irq_domain_map(struct irq_domain *d,
 364 +                                 unsigned int virq,
 365 +                                 irq_hw_number_t hwirq)
 366 +{
 367 +       struct spmi_pmic_arb_dev *pa = d->host_data;
 368 +
 369 +       dev_dbg(&pa->spmic->dev, "virq = %u, hwirq = %lu\n", virq, hwirq);
 370 +
 371 +       irq_set_chip_and_handler(virq, &pmic_arb_irqchip, handle_level_irq);
 372 +       irq_set_chip_data(virq, d->host_data);
 373 +       irq_set_noprobe(virq);
 374 +       return 0;
 375 +}
 376 +
 377 +static const struct irq_domain_ops pmic_arb_irq_domain_ops = {
 378 +       .map    = qpnpint_irq_domain_map,
 379 +       .xlate  = qpnpint_irq_domain_dt_translate,
 380 +};
 381 +
 382  static int spmi_pmic_arb_probe(struct platform_device *pdev)
 383  {
 384         struct spmi_pmic_arb_dev *pa;
 385         struct spmi_controller *ctrl;
 386         struct resource *res;
 387 -       u32 channel;
 388 +       u32 channel, ee;
 389         int err, i;
 390
 391         ctrl = spmi_controller_alloc(&pdev->dev, sizeof(*pa));
 392 @@ -319,6 +642,7 @@ static int spmi_pmic_arb_probe(struct pl
 393                 return -ENOMEM;
 394
 395         pa = spmi_controller_get_drvdata(ctrl);
 396 +       pa->spmic = ctrl;
 397
 398         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "core");
 399         pa->base = devm_ioremap_resource(&ctrl->dev, res);
 400 @@ -341,6 +665,12 @@ static int spmi_pmic_arb_probe(struct pl
 401                 goto err_put_ctrl;
 402         }
 403
 404 +       pa->irq = platform_get_irq_byname(pdev, "periph_irq");
 405 +       if (pa->irq < 0) {
 406 +               err = pa->irq;
 407 +               goto err_put_ctrl;
 408 +       }
 409 +
 410         err = of_property_read_u32(pdev->dev.of_node, "qcom,channel", &channel);
 411         if (err) {
 412                 dev_err(&pdev->dev, "channel unspecified.\n");
 413 @@ -355,6 +685,29 @@ static int spmi_pmic_arb_probe(struct pl
 414
 415         pa->channel = channel;
 416
 417 +       err = of_property_read_u32(pdev->dev.of_node, "qcom,ee", &ee);
 418 +       if (err) {
 419 +               dev_err(&pdev->dev, "EE unspecified.\n");
 420 +               goto err_put_ctrl;
 421 +       }
 422 +
 423 +       if (ee > 5) {
 424 +               dev_err(&pdev->dev, "invalid EE (%u) specified\n", ee);
 425 +               err = -EINVAL;
 426 +               goto err_put_ctrl;
 427 +       }
 428 +
 429 +       pa->ee = ee;
 430 +
 431 +       for (i = 0; i < ARRAY_SIZE(pa->mapping_table); ++i)
 432 +               pa->mapping_table[i] = readl_relaxed(
 433 +                               pa->cnfg + SPMI_MAPPING_TABLE_REG(i));
 434 +
 435 +       /* Initialize max_apid/min_apid to the opposite bounds, during
 436 +        * the irq domain translation, we are sure to update these */
 437 +       pa->max_apid = 0;
 438 +       pa->min_apid = PMIC_ARB_MAX_PERIPHS - 1;
 439 +
 440         platform_set_drvdata(pdev, ctrl);
 441         raw_spin_lock_init(&pa->lock);
 442
 443 @@ -362,15 +715,31 @@ static int spmi_pmic_arb_probe(struct pl
 444         ctrl->read_cmd = pmic_arb_read_cmd;
 445         ctrl->write_cmd = pmic_arb_write_cmd;
 446
 447 +       dev_dbg(&pdev->dev, "adding irq domain\n");
 448 +       pa->domain = irq_domain_add_tree(pdev->dev.of_node,
 449 +                                        &pmic_arb_irq_domain_ops, pa);
 450 +       if (!pa->domain) {
 451 +               dev_err(&pdev->dev, "unable to create irq_domain\n");
 452 +               err = -ENOMEM;
 453 +               goto err_put_ctrl;
 454 +       }
 455 +
 456 +       irq_set_handler_data(pa->irq, pa);
 457 +       irq_set_chained_handler(pa->irq, pmic_arb_chained_irq);
 458 +
 459         err = spmi_controller_add(ctrl);
 460         if (err)
 461 -               goto err_put_ctrl;
 462 +               goto err_domain_remove;
 463
 464         dev_dbg(&ctrl->dev, "PMIC Arb Version 0x%x\n",
 465                 pmic_arb_base_read(pa, PMIC_ARB_VERSION));
 466
 467         return 0;
 468
 469 +err_domain_remove:
 470 +       irq_set_chained_handler(pa->irq, NULL);
 471 +       irq_set_handler_data(pa->irq, NULL);
 472 +       irq_domain_remove(pa->domain);
 473  err_put_ctrl:
 474         spmi_controller_put(ctrl);
 475         return err;
 476 @@ -379,7 +748,11 @@ err_put_ctrl:
 477  static int spmi_pmic_arb_remove(struct platform_device *pdev)
 478  {
 479         struct spmi_controller *ctrl = platform_get_drvdata(pdev);
 480 +       struct spmi_pmic_arb_dev *pa = spmi_controller_get_drvdata(ctrl);
 481         spmi_controller_remove(ctrl);
 482 +       irq_set_chained_handler(pa->irq, NULL);
 483 +       irq_set_handler_data(pa->irq, NULL);
 484 +       irq_domain_remove(pa->domain);
 485         spmi_controller_put(ctrl);
 486         return 0;
 487  }