1 From: Richard Zhu <r65037@freescale.com>
2 Subject: [PATCH] ahci_imx: add ahci sata support on imx platforms
4 imx6q contains one Synopsys AHCI SATA controller, But it can't share
5 ahci_platform driver with other controllers because there are some
6 misalignments of the generic AHCI controller - the bits definitions of
7 the HBA registers, the Vendor Specific registers, the AHCI PHY clock
8 and the AHCI signals adjustment window(GPR13 register).
10 - CAP_SSS(bit20) of the HOST_CAP is writable, default value is '0',
11 should be configured to be '1'
13 - bit0 (only one AHCI SATA port on imx6q) of the HOST_PORTS_IMPL
14 should be set to be '1'.(default 0)
16 - One Vendor Specific register HOST_TIMER1MS(offset:0xe0) should be
17 configured regarding to the frequency of AHB bus clock.
19 - Configurations of the AHCI PHY clock, and the signal parameters of
22 Setup its own ahci sata driver, contained the imx6q specific
23 initialized codes, re-use the generic ahci_platform driver, and keep
24 the generic ahci_platform driver clean as much as possible.
26 tj: patch description reformatted
28 Signed-off-by: Richard Zhu <r65037@freescale.com>
29 Reviewed-by: Shawn Guo <shawn.guo@linaro.org>
30 Signed-off-by: Tejun Heo <tj@kernel.org>
32 drivers/ata/Kconfig | 9 ++
33 drivers/ata/Makefile | 1 +
34 drivers/ata/ahci_imx.c | 236 +++++++++++++++++++++++++++++++++++++++++++++++++
35 3 files changed, 246 insertions(+)
36 create mode 100644 drivers/ata/ahci_imx.c
38 --- a/drivers/ata/Kconfig
39 +++ b/drivers/ata/Kconfig
40 @@ -97,6 +97,15 @@ config SATA_AHCI_PLATFORM
45 + tristate "Freescale i.MX AHCI SATA support"
46 + depends on SATA_AHCI_PLATFORM
48 + This option enables support for the Freescale i.MX SoC's
54 tristate "Freescale 3.0Gbps SATA support"
56 --- a/drivers/ata/Makefile
57 +++ b/drivers/ata/Makefile
58 @@ -10,6 +10,7 @@ obj-$(CONFIG_SATA_INIC162X) += sata_inic
59 obj-$(CONFIG_SATA_SIL24) += sata_sil24.o
60 obj-$(CONFIG_SATA_DWC) += sata_dwc_460ex.o
61 obj-$(CONFIG_SATA_HIGHBANK) += sata_highbank.o libahci.o
62 +obj-$(CONFIG_AHCI_IMX) += ahci_imx.o
65 obj-$(CONFIG_PDC_ADMA) += pdc_adma.o
67 +++ b/drivers/ata/ahci_imx.c
70 + * Freescale IMX AHCI SATA platform driver
71 + * Copyright 2013 Freescale Semiconductor, Inc.
73 + * based on the AHCI SATA platform driver by Jeff Garzik and Anton Vorontsov
75 + * This program is free software; you can redistribute it and/or modify it
76 + * under the terms and conditions of the GNU General Public License,
77 + * version 2, as published by the Free Software Foundation.
79 + * This program is distributed in the hope it will be useful, but WITHOUT
80 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
81 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
84 + * You should have received a copy of the GNU General Public License along with
85 + * this program. If not, see <http://www.gnu.org/licenses/>.
88 +#include <linux/kernel.h>
89 +#include <linux/module.h>
90 +#include <linux/platform_device.h>
91 +#include <linux/regmap.h>
92 +#include <linux/ahci_platform.h>
93 +#include <linux/of_device.h>
94 +#include <linux/mfd/syscon.h>
95 +#include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
99 + HOST_TIMER1MS = 0xe0, /* Timer 1-ms */
102 +struct imx_ahci_priv {
103 + struct platform_device *ahci_pdev;
104 + struct clk *sata_ref_clk;
105 + struct clk *ahb_clk;
106 + struct regmap *gpr;
109 +static int imx6q_sata_init(struct device *dev, void __iomem *mmio)
112 + unsigned int reg_val;
113 + struct imx_ahci_priv *imxpriv = dev_get_drvdata(dev->parent);
116 + syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr");
117 + if (IS_ERR(imxpriv->gpr)) {
118 + dev_err(dev, "failed to find fsl,imx6q-iomux-gpr regmap\n");
119 + return PTR_ERR(imxpriv->gpr);
122 + ret = clk_prepare_enable(imxpriv->sata_ref_clk);
124 + dev_err(dev, "prepare-enable sata_ref clock err:%d\n", ret);
129 + * set PHY Paremeters, two steps to configure the GPR13,
130 + * one write for rest of parameters, mask of first write
131 + * is 0x07fffffd, and the other one write for setting
134 + regmap_update_bits(imxpriv->gpr, 0x34, IMX6Q_GPR13_SATA_RX_EQ_VAL_MASK
135 + | IMX6Q_GPR13_SATA_RX_LOS_LVL_MASK
136 + | IMX6Q_GPR13_SATA_RX_DPLL_MODE_MASK
137 + | IMX6Q_GPR13_SATA_SPD_MODE_MASK
138 + | IMX6Q_GPR13_SATA_MPLL_SS_EN
139 + | IMX6Q_GPR13_SATA_TX_ATTEN_MASK
140 + | IMX6Q_GPR13_SATA_TX_BOOST_MASK
141 + | IMX6Q_GPR13_SATA_TX_LVL_MASK
142 + | IMX6Q_GPR13_SATA_TX_EDGE_RATE
143 + , IMX6Q_GPR13_SATA_RX_EQ_VAL_3_0_DB
144 + | IMX6Q_GPR13_SATA_RX_LOS_LVL_SATA2M
145 + | IMX6Q_GPR13_SATA_RX_DPLL_MODE_2P_4F
146 + | IMX6Q_GPR13_SATA_SPD_MODE_3P0G
147 + | IMX6Q_GPR13_SATA_MPLL_SS_EN
148 + | IMX6Q_GPR13_SATA_TX_ATTEN_9_16
149 + | IMX6Q_GPR13_SATA_TX_BOOST_3_33_DB
150 + | IMX6Q_GPR13_SATA_TX_LVL_1_025_V);
151 + regmap_update_bits(imxpriv->gpr, 0x34, IMX6Q_GPR13_SATA_MPLL_CLK_EN,
152 + IMX6Q_GPR13_SATA_MPLL_CLK_EN);
153 + usleep_range(100, 200);
156 + * Configure the HWINIT bits of the HOST_CAP and HOST_PORTS_IMPL,
157 + * and IP vendor specific register HOST_TIMER1MS.
158 + * Configure CAP_SSS (support stagered spin up).
159 + * Implement the port0.
160 + * Get the ahb clock rate, and configure the TIMER1MS register.
162 + reg_val = readl(mmio + HOST_CAP);
163 + if (!(reg_val & HOST_CAP_SSS)) {
164 + reg_val |= HOST_CAP_SSS;
165 + writel(reg_val, mmio + HOST_CAP);
167 + reg_val = readl(mmio + HOST_PORTS_IMPL);
168 + if (!(reg_val & 0x1)) {
170 + writel(reg_val, mmio + HOST_PORTS_IMPL);
173 + reg_val = clk_get_rate(imxpriv->ahb_clk) / 1000;
174 + writel(reg_val, mmio + HOST_TIMER1MS);
179 +static void imx6q_sata_exit(struct device *dev)
181 + struct imx_ahci_priv *imxpriv = dev_get_drvdata(dev->parent);
183 + regmap_update_bits(imxpriv->gpr, 0x34, IMX6Q_GPR13_SATA_MPLL_CLK_EN,
184 + !IMX6Q_GPR13_SATA_MPLL_CLK_EN);
185 + clk_disable_unprepare(imxpriv->sata_ref_clk);
188 +static struct ahci_platform_data imx6q_sata_pdata = {
189 + .init = imx6q_sata_init,
190 + .exit = imx6q_sata_exit,
193 +static const struct of_device_id imx_ahci_of_match[] = {
194 + { .compatible = "fsl,imx6q-ahci", .data = &imx6q_sata_pdata},
197 +MODULE_DEVICE_TABLE(of, imx_ahci_of_match);
199 +static int imx_ahci_probe(struct platform_device *pdev)
201 + struct device *dev = &pdev->dev;
202 + struct resource *mem, *irq, res[2];
203 + const struct of_device_id *of_id;
204 + const struct ahci_platform_data *pdata = NULL;
205 + struct imx_ahci_priv *imxpriv;
206 + struct device *ahci_dev;
207 + struct platform_device *ahci_pdev;
210 + imxpriv = devm_kzalloc(dev, sizeof(*imxpriv), GFP_KERNEL);
212 + dev_err(dev, "can't alloc ahci_host_priv\n");
216 + ahci_pdev = platform_device_alloc("ahci", -1);
220 + ahci_dev = &ahci_pdev->dev;
221 + ahci_dev->parent = dev;
223 + imxpriv->ahb_clk = devm_clk_get(dev, "ahb");
224 + if (IS_ERR(imxpriv->ahb_clk)) {
225 + dev_err(dev, "can't get ahb clock.\n");
226 + ret = PTR_ERR(imxpriv->ahb_clk);
230 + imxpriv->sata_ref_clk = devm_clk_get(dev, "sata_ref");
231 + if (IS_ERR(imxpriv->sata_ref_clk)) {
232 + dev_err(dev, "can't get sata_ref clock.\n");
233 + ret = PTR_ERR(imxpriv->sata_ref_clk);
237 + imxpriv->ahci_pdev = ahci_pdev;
238 + platform_set_drvdata(pdev, imxpriv);
240 + of_id = of_match_device(imx_ahci_of_match, dev);
242 + pdata = of_id->data;
248 + mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
249 + irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
250 + if (!mem || !irq) {
251 + dev_err(dev, "no mmio/irq resource\n");
259 + ahci_dev->coherent_dma_mask = DMA_BIT_MASK(32);
260 + ahci_dev->dma_mask = &ahci_dev->coherent_dma_mask;
261 + ahci_dev->of_node = dev->of_node;
263 + ret = platform_device_add_resources(ahci_pdev, res, 2);
267 + ret = platform_device_add_data(ahci_pdev, pdata, sizeof(*pdata));
271 + ret = platform_device_add(ahci_pdev);
274 + platform_device_put(ahci_pdev);
281 +static int imx_ahci_remove(struct platform_device *pdev)
283 + struct imx_ahci_priv *imxpriv = platform_get_drvdata(pdev);
284 + struct platform_device *ahci_pdev = imxpriv->ahci_pdev;
286 + platform_device_unregister(ahci_pdev);
290 +static struct platform_driver imx_ahci_driver = {
291 + .probe = imx_ahci_probe,
292 + .remove = imx_ahci_remove,
294 + .name = "ahci-imx",
295 + .owner = THIS_MODULE,
296 + .of_match_table = imx_ahci_of_match,
299 +module_platform_driver(imx_ahci_driver);
301 +MODULE_DESCRIPTION("Freescale i.MX AHCI SATA platform driver");
302 +MODULE_AUTHOR("Richard Zhu <Hong-Xing.Zhu@freescale.com>");
303 +MODULE_LICENSE("GPL");
304 +MODULE_ALIAS("ahci:imx");