target/linux/ifxmips/files/arch/mips/ifxmips/timer.c

   1 #include <linux/kernel.h>
   2 #include <linux/module.h>
   3 #include <linux/version.h>
   4 #include <linux/types.h>
   5 #include <linux/fs.h>
   6 #include <linux/miscdevice.h>
   7 #include <linux/init.h>
   8 #include <linux/uaccess.h>
   9 #include <linux/unistd.h>
  10 #include <linux/errno.h>
  11 #include <linux/interrupt.h>
  12
  13 #include <asm/irq.h>
  14 #include <asm/div64.h>
  15
  16 #include <ifxmips.h>
  17 #include <ifxmips_irq.h>
  18 #include <ifxmips_cgu.h>
  19 #include <ifxmips_gptu.h>
  20 #include <ifxmips_pmu.h>
  21
  22 #define MAX_NUM_OF_32BIT_TIMER_BLOCKS   6
  23
  24 #ifdef TIMER1A
  25 #define FIRST_TIMER                     TIMER1A
  26 #else
  27 #define FIRST_TIMER                     2
  28 #endif
  29
  30 /*
  31  *  GPTC divider is set or not.
  32  */
  33 #define GPTU_CLC_RMC_IS_SET             0
  34
  35 /*
  36  *  Timer Interrupt (IRQ)
  37  */
  38 /*  Must be adjusted when ICU driver is available */
  39 #define TIMER_INTERRUPT                 (INT_NUM_IM3_IRL0 + 22)
  40
  41 /*
  42  *  Bits Operation
  43  */
  44 #define GET_BITS(x, msb, lsb)           \
  45         (((x) & ((1 << ((msb) + 1)) - 1)) >> (lsb))
  46 #define SET_BITS(x, msb, lsb, value)    \
  47         (((x) & ~(((1 << ((msb) + 1)) - 1) ^ ((1 << (lsb)) - 1))) | \
  48         (((value) & ((1 << (1 + (msb) - (lsb))) - 1)) << (lsb)))
  49
  50 /*
  51  *  GPTU Register Mapping
  52  */
  53 #define IFXMIPS_GPTU                    (KSEG1 + 0x1E100A00)
  54 #define IFXMIPS_GPTU_CLC                ((volatile u32 *)(IFXMIPS_GPTU + 0x0000))
  55 #define IFXMIPS_GPTU_ID                 ((volatile u32 *)(IFXMIPS_GPTU + 0x0008))
  56 #define IFXMIPS_GPTU_CON(n, X)          ((volatile u32 *)(IFXMIPS_GPTU + 0x0010 + ((X) * 4) + ((n) - 1) * 0x0020))      /* X must be either A or B */
  57 #define IFXMIPS_GPTU_RUN(n, X)          ((volatile u32 *)(IFXMIPS_GPTU + 0x0018 + ((X) * 4) + ((n) - 1) * 0x0020))      /* X must be either A or B */
  58 #define IFXMIPS_GPTU_RELOAD(n, X)       ((volatile u32 *)(IFXMIPS_GPTU + 0x0020 + ((X) * 4) + ((n) - 1) * 0x0020))      /* X must be either A or B */
  59 #define IFXMIPS_GPTU_COUNT(n, X)        ((volatile u32 *)(IFXMIPS_GPTU + 0x0028 + ((X) * 4) + ((n) - 1) * 0x0020))      /* X must be either A or B */
  60 #define IFXMIPS_GPTU_IRNEN              ((volatile u32 *)(IFXMIPS_GPTU + 0x00F4))
  61 #define IFXMIPS_GPTU_IRNICR             ((volatile u32 *)(IFXMIPS_GPTU + 0x00F8))
  62 #define IFXMIPS_GPTU_IRNCR              ((volatile u32 *)(IFXMIPS_GPTU + 0x00FC))
  63
  64 /*
  65  *  Clock Control Register
  66  */
  67 #define GPTU_CLC_SMC                    GET_BITS(*IFXMIPS_GPTU_CLC, 23, 16)
  68 #define GPTU_CLC_RMC                    GET_BITS(*IFXMIPS_GPTU_CLC, 15, 8)
  69 #define GPTU_CLC_FSOE                   (*IFXMIPS_GPTU_CLC & (1 << 5))
  70 #define GPTU_CLC_EDIS                   (*IFXMIPS_GPTU_CLC & (1 << 3))
  71 #define GPTU_CLC_SPEN                   (*IFXMIPS_GPTU_CLC & (1 << 2))
  72 #define GPTU_CLC_DISS                   (*IFXMIPS_GPTU_CLC & (1 << 1))
  73 #define GPTU_CLC_DISR                   (*IFXMIPS_GPTU_CLC & (1 << 0))
  74
  75 #define GPTU_CLC_SMC_SET(value)         SET_BITS(0, 23, 16, (value))
  76 #define GPTU_CLC_RMC_SET(value)         SET_BITS(0, 15, 8, (value))
  77 #define GPTU_CLC_FSOE_SET(value)        ((value) ? (1 << 5) : 0)
  78 #define GPTU_CLC_SBWE_SET(value)        ((value) ? (1 << 4) : 0)
  79 #define GPTU_CLC_EDIS_SET(value)        ((value) ? (1 << 3) : 0)
  80 #define GPTU_CLC_SPEN_SET(value)        ((value) ? (1 << 2) : 0)
  81 #define GPTU_CLC_DISR_SET(value)        ((value) ? (1 << 0) : 0)
  82
  83 /*
  84  *  ID Register
  85  */
  86 #define GPTU_ID_ID                      GET_BITS(*IFXMIPS_GPTU_ID, 15, 8)
  87 #define GPTU_ID_CFG                     GET_BITS(*IFXMIPS_GPTU_ID, 7, 5)
  88 #define GPTU_ID_REV                     GET_BITS(*IFXMIPS_GPTU_ID, 4, 0)
  89
  90 /*
  91  *  Control Register of Timer/Counter nX
  92  *    n is the index of block (1 based index)
  93  *    X is either A or B
  94  */
  95 #define GPTU_CON_SRC_EG(n, X)           (*IFXMIPS_GPTU_CON(n, X) & (1 << 10))
  96 #define GPTU_CON_SRC_EXT(n, X)          (*IFXMIPS_GPTU_CON(n, X) & (1 << 9))
  97 #define GPTU_CON_SYNC(n, X)             (*IFXMIPS_GPTU_CON(n, X) & (1 << 8))
  98 #define GPTU_CON_EDGE(n, X)             GET_BITS(*IFXMIPS_GPTU_CON(n, X), 7, 6)
  99 #define GPTU_CON_INV(n, X)              (*IFXMIPS_GPTU_CON(n, X) & (1 << 5))
 100 #define GPTU_CON_EXT(n, X)              (*IFXMIPS_GPTU_CON(n, A) & (1 << 4))    /* Timer/Counter B does not have this bit */
 101 #define GPTU_CON_STP(n, X)              (*IFXMIPS_GPTU_CON(n, X) & (1 << 3))
 102 #define GPTU_CON_CNT(n, X)              (*IFXMIPS_GPTU_CON(n, X) & (1 << 2))
 103 #define GPTU_CON_DIR(n, X)              (*IFXMIPS_GPTU_CON(n, X) & (1 << 1))
 104 #define GPTU_CON_EN(n, X)               (*IFXMIPS_GPTU_CON(n, X) & (1 << 0))
 105
 106 #define GPTU_CON_SRC_EG_SET(value)      ((value) ? 0 : (1 << 10))
 107 #define GPTU_CON_SRC_EXT_SET(value)     ((value) ? (1 << 9) : 0)
 108 #define GPTU_CON_SYNC_SET(value)        ((value) ? (1 << 8) : 0)
 109 #define GPTU_CON_EDGE_SET(value)        SET_BITS(0, 7, 6, (value))
 110 #define GPTU_CON_INV_SET(value)         ((value) ? (1 << 5) : 0)
 111 #define GPTU_CON_EXT_SET(value)         ((value) ? (1 << 4) : 0)
 112 #define GPTU_CON_STP_SET(value)         ((value) ? (1 << 3) : 0)
 113 #define GPTU_CON_CNT_SET(value)         ((value) ? (1 << 2) : 0)
 114 #define GPTU_CON_DIR_SET(value)         ((value) ? (1 << 1) : 0)
 115
 116 #define GPTU_RUN_RL_SET(value)          ((value) ? (1 << 2) : 0)
 117 #define GPTU_RUN_CEN_SET(value)         ((value) ? (1 << 1) : 0)
 118 #define GPTU_RUN_SEN_SET(value)         ((value) ? (1 << 0) : 0)
 119
 120 #define GPTU_IRNEN_TC_SET(n, X, value)  ((value) ? (1 << (((n) - 1) * 2 + (X))) : 0)
 121 #define GPTU_IRNCR_TC_SET(n, X, value)  ((value) ? (1 << (((n) - 1) * 2 + (X))) : 0)
 122
 123 #define TIMER_FLAG_MASK_SIZE(x)         (x & 0x0001)
 124 #define TIMER_FLAG_MASK_TYPE(x)         (x & 0x0002)
 125 #define TIMER_FLAG_MASK_STOP(x)         (x & 0x0004)
 126 #define TIMER_FLAG_MASK_DIR(x)          (x & 0x0008)
 127 #define TIMER_FLAG_NONE_EDGE            0x0000
 128 #define TIMER_FLAG_MASK_EDGE(x)         (x & 0x0030)
 129 #define TIMER_FLAG_REAL                 0x0000
 130 #define TIMER_FLAG_INVERT               0x0040
 131 #define TIMER_FLAG_MASK_INVERT(x)       (x & 0x0040)
 132 #define TIMER_FLAG_MASK_TRIGGER(x)      (x & 0x0070)
 133 #define TIMER_FLAG_MASK_SYNC(x)         (x & 0x0080)
 134 #define TIMER_FLAG_CALLBACK_IN_HB       0x0200
 135 #define TIMER_FLAG_MASK_HANDLE(x)       (x & 0x0300)
 136 #define TIMER_FLAG_MASK_SRC(x)          (x & 0x1000)
 137
 138 struct timer_dev_timer {
 139         unsigned int f_irq_on;
 140         unsigned int irq;
 141         unsigned int flag;
 142         unsigned long arg1;
 143         unsigned long arg2;
 144 };
 145
 146 struct timer_dev {
 147         struct mutex gptu_mutex;
 148         unsigned int number_of_timers;
 149         unsigned int occupation;
 150         unsigned int f_gptu_on;
 151         struct timer_dev_timer timer[MAX_NUM_OF_32BIT_TIMER_BLOCKS * 2];
 152 };
 153
 154 static int gptu_ioctl(struct inode *, struct file *, unsigned int, unsigned long);
 155 static int gptu_open(struct inode *, struct file *);
 156 static int gptu_release(struct inode *, struct file *);
 157
 158 static struct file_operations gptu_fops = {
 159         .owner = THIS_MODULE,
 160         .ioctl = gptu_ioctl,
 161         .open = gptu_open,
 162         .release = gptu_release
 163 };
 164
 165 static struct miscdevice gptu_miscdev = {
 166         .minor = MISC_DYNAMIC_MINOR,
 167         .name = "gptu",
 168         .fops = &gptu_fops,
 169 };
 170
 171 static struct timer_dev timer_dev;
 172
 173 static irqreturn_t timer_irq_handler(int irq, void *p)
 174 {
 175         unsigned int timer;
 176         unsigned int flag;
 177         struct timer_dev_timer *dev_timer = (struct timer_dev_timer *)p;
 178
 179         timer = irq - TIMER_INTERRUPT;
 180         if (timer < timer_dev.number_of_timers
 181                 && dev_timer == &timer_dev.timer[timer]) {
 182                 /*  Clear interrupt.    */
 183                 ifxmips_w32(1 << timer, IFXMIPS_GPTU_IRNCR);
 184
 185                 /*  Call user hanler or signal. */
 186                 flag = dev_timer->flag;
 187                 if (!(timer & 0x01)
 188                         || TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT) {
 189                         /* 16-bit timer or timer A of 32-bit timer  */
 190                         switch (TIMER_FLAG_MASK_HANDLE(flag)) {
 191                         case TIMER_FLAG_CALLBACK_IN_IRQ:
 192                         case TIMER_FLAG_CALLBACK_IN_HB:
 193                                 if (dev_timer->arg1)
 194                                         (*(timer_callback)dev_timer->arg1)(dev_timer->arg2);
 195                                 break;
 196                         case TIMER_FLAG_SIGNAL:
 197                                 send_sig((int)dev_timer->arg2, (struct task_struct *)dev_timer->arg1, 0);
 198                                 break;
 199                         }
 200                 }
 201         }
 202         return IRQ_HANDLED;
 203 }
 204
 205 static inline void ifxmips_enable_gptu(void)
 206 {
 207         ifxmips_pmu_enable(IFXMIPS_PMU_PWDCR_GPT);
 208
 209         /*  Set divider as 1, disable write protection for SPEN, enable module. */
 210         *IFXMIPS_GPTU_CLC =
 211                 GPTU_CLC_SMC_SET(0x00) |
 212                 GPTU_CLC_RMC_SET(0x01) |
 213                 GPTU_CLC_FSOE_SET(0) |
 214                 GPTU_CLC_SBWE_SET(1) |
 215                 GPTU_CLC_EDIS_SET(0) |
 216                 GPTU_CLC_SPEN_SET(0) |
 217                 GPTU_CLC_DISR_SET(0);
 218 }
 219
 220 static inline void ifxmips_disable_gptu(void)
 221 {
 222         ifxmips_w32(0x00, IFXMIPS_GPTU_IRNEN);
 223         ifxmips_w32(0xfff, IFXMIPS_GPTU_IRNCR);
 224
 225         /*  Set divider as 0, enable write protection for SPEN, disable module. */
 226         *IFXMIPS_GPTU_CLC =
 227                 GPTU_CLC_SMC_SET(0x00) |
 228                 GPTU_CLC_RMC_SET(0x00) |
 229                 GPTU_CLC_FSOE_SET(0) |
 230                 GPTU_CLC_SBWE_SET(0) |
 231                 GPTU_CLC_EDIS_SET(0) |
 232                 GPTU_CLC_SPEN_SET(0) |
 233                 GPTU_CLC_DISR_SET(1);
 234
 235         ifxmips_pmu_disable(IFXMIPS_PMU_PWDCR_GPT);
 236 }
 237
 238 int ifxmips_request_timer(unsigned int timer, unsigned int flag,
 239         unsigned long value, unsigned long arg1, unsigned long arg2)
 240 {
 241         int ret = 0;
 242         unsigned int con_reg, irnen_reg;
 243         int n, X;
 244
 245         if (timer >= FIRST_TIMER + timer_dev.number_of_timers)
 246                 return -EINVAL;
 247
 248         printk(KERN_INFO "request_timer(%d, 0x%08X, %lu)...",
 249                 timer, flag, value);
 250
 251         if (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT)
 252                 value &= 0xFFFF;
 253         else
 254                 timer &= ~0x01;
 255
 256         mutex_lock(&timer_dev.gptu_mutex);
 257
 258         /*
 259          *  Allocate timer.
 260          */
 261         if (timer < FIRST_TIMER) {
 262                 unsigned int mask;
 263                 unsigned int shift;
 264                 /* This takes care of TIMER1B which is the only choice for Voice TAPI system */
 265                 unsigned int offset = TIMER2A;
 266
 267                 /*
 268                  *  Pick up a free timer.
 269                  */
 270                 if (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT) {
 271                         mask = 1 << offset;
 272                         shift = 1;
 273                 } else {
 274                         mask = 3 << offset;
 275                         shift = 2;
 276                 }
 277                 for (timer = offset;
 278                      timer < offset + timer_dev.number_of_timers;
 279                      timer += shift, mask <<= shift)
 280                         if (!(timer_dev.occupation & mask)) {
 281                                 timer_dev.occupation |= mask;
 282                                 break;
 283                         }
 284                 if (timer >= offset + timer_dev.number_of_timers) {
 285                         printk("failed![%d]\n", __LINE__);
 286                         mutex_unlock(&timer_dev.gptu_mutex);
 287                         return -EINVAL;
 288                 } else
 289                         ret = timer;
 290         } else {
 291                 register unsigned int mask;
 292
 293                 /*
 294                  *  Check if the requested timer is free.
 295                  */
 296                 mask = (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT ? 1 : 3) << timer;
 297                 if ((timer_dev.occupation & mask)) {
 298                         printk("failed![%d] mask %#x, timer_dev.occupation %#x\n",
 299                                 __LINE__, mask, timer_dev.occupation);
 300                         mutex_unlock(&timer_dev.gptu_mutex);
 301                         return -EBUSY;
 302                 } else {
 303                         timer_dev.occupation |= mask;
 304                         ret = 0;
 305                 }
 306         }
 307
 308         /*
 309          *  Prepare control register value.
 310          */
 311         switch (TIMER_FLAG_MASK_EDGE(flag)) {
 312         default:
 313         case TIMER_FLAG_NONE_EDGE:
 314                 con_reg = GPTU_CON_EDGE_SET(0x00);
 315                 break;
 316         case TIMER_FLAG_RISE_EDGE:
 317                 con_reg = GPTU_CON_EDGE_SET(0x01);
 318                 break;
 319         case TIMER_FLAG_FALL_EDGE:
 320                 con_reg = GPTU_CON_EDGE_SET(0x02);
 321                 break;
 322         case TIMER_FLAG_ANY_EDGE:
 323                 con_reg = GPTU_CON_EDGE_SET(0x03);
 324                 break;
 325         }
 326         if (TIMER_FLAG_MASK_TYPE(flag) == TIMER_FLAG_TIMER)
 327                 con_reg |=
 328                         TIMER_FLAG_MASK_SRC(flag) ==
 329                         TIMER_FLAG_EXT_SRC ? GPTU_CON_SRC_EXT_SET(1) :
 330                         GPTU_CON_SRC_EXT_SET(0);
 331         else
 332                 con_reg |=
 333                         TIMER_FLAG_MASK_SRC(flag) ==
 334                         TIMER_FLAG_EXT_SRC ? GPTU_CON_SRC_EG_SET(1) :
 335                         GPTU_CON_SRC_EG_SET(0);
 336         con_reg |=
 337                 TIMER_FLAG_MASK_SYNC(flag) ==
 338                 TIMER_FLAG_UNSYNC ? GPTU_CON_SYNC_SET(0) :
 339                 GPTU_CON_SYNC_SET(1);
 340         con_reg |=
 341                 TIMER_FLAG_MASK_INVERT(flag) ==
 342                 TIMER_FLAG_REAL ? GPTU_CON_INV_SET(0) : GPTU_CON_INV_SET(1);
 343         con_reg |=
 344                 TIMER_FLAG_MASK_SIZE(flag) ==
 345                 TIMER_FLAG_16BIT ? GPTU_CON_EXT_SET(0) :
 346                 GPTU_CON_EXT_SET(1);
 347         con_reg |=
 348                 TIMER_FLAG_MASK_STOP(flag) ==
 349                 TIMER_FLAG_ONCE ? GPTU_CON_STP_SET(1) : GPTU_CON_STP_SET(0);
 350         con_reg |=
 351                 TIMER_FLAG_MASK_TYPE(flag) ==
 352                 TIMER_FLAG_TIMER ? GPTU_CON_CNT_SET(0) :
 353                 GPTU_CON_CNT_SET(1);
 354         con_reg |=
 355                 TIMER_FLAG_MASK_DIR(flag) ==
 356                 TIMER_FLAG_UP ? GPTU_CON_DIR_SET(1) : GPTU_CON_DIR_SET(0);
 357
 358         /*
 359          *  Fill up running data.
 360          */
 361         timer_dev.timer[timer - FIRST_TIMER].flag = flag;
 362         timer_dev.timer[timer - FIRST_TIMER].arg1 = arg1;
 363         timer_dev.timer[timer - FIRST_TIMER].arg2 = arg2;
 364         if (TIMER_FLAG_MASK_SIZE(flag) != TIMER_FLAG_16BIT)
 365                 timer_dev.timer[timer - FIRST_TIMER + 1].flag = flag;
 366
 367         /*
 368          *  Enable GPTU module.
 369          */
 370         if (!timer_dev.f_gptu_on) {
 371                 ifxmips_enable_gptu();
 372                 timer_dev.f_gptu_on = 1;
 373         }
 374
 375         /*
 376          *  Enable IRQ.
 377          */
 378         if (TIMER_FLAG_MASK_HANDLE(flag) != TIMER_FLAG_NO_HANDLE) {
 379                 if (TIMER_FLAG_MASK_HANDLE(flag) == TIMER_FLAG_SIGNAL)
 380                         timer_dev.timer[timer - FIRST_TIMER].arg1 =
 381                                 (unsigned long) find_task_by_vpid((int) arg1);
 382
 383                 irnen_reg = 1 << (timer - FIRST_TIMER);
 384
 385                 if (TIMER_FLAG_MASK_HANDLE(flag) == TIMER_FLAG_SIGNAL
 386                     || (TIMER_FLAG_MASK_HANDLE(flag) ==
 387                         TIMER_FLAG_CALLBACK_IN_IRQ
 388                         && timer_dev.timer[timer - FIRST_TIMER].arg1)) {
 389                         enable_irq(timer_dev.timer[timer - FIRST_TIMER].irq);
 390                         timer_dev.timer[timer - FIRST_TIMER].f_irq_on = 1;
 391                 }
 392         } else
 393                 irnen_reg = 0;
 394
 395         /*
 396          *  Write config register, reload value and enable interrupt.
 397          */
 398         n = timer >> 1;
 399         X = timer & 0x01;
 400         *IFXMIPS_GPTU_CON(n, X) = con_reg;
 401         *IFXMIPS_GPTU_RELOAD(n, X) = value;
 402         /* printk("reload value = %d\n", (u32)value); */
 403         *IFXMIPS_GPTU_IRNEN |= irnen_reg;
 404
 405         mutex_unlock(&timer_dev.gptu_mutex);
 406         printk("successful!\n");
 407         return ret;
 408 }
 409 EXPORT_SYMBOL(ifxmips_request_timer);
 410
 411 int ifxmips_free_timer(unsigned int timer)
 412 {
 413         unsigned int flag;
 414         unsigned int mask;
 415         int n, X;
 416
 417         if (!timer_dev.f_gptu_on)
 418                 return -EINVAL;
 419
 420         if (timer < FIRST_TIMER || timer >= FIRST_TIMER + timer_dev.number_of_timers)
 421                 return -EINVAL;
 422
 423         mutex_lock(&timer_dev.gptu_mutex);
 424
 425         flag = timer_dev.timer[timer - FIRST_TIMER].flag;
 426         if (TIMER_FLAG_MASK_SIZE(flag) != TIMER_FLAG_16BIT)
 427                 timer &= ~0x01;
 428
 429         mask = (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT ? 1 : 3) << timer;
 430         if (((timer_dev.occupation & mask) ^ mask)) {
 431                 mutex_unlock(&timer_dev.gptu_mutex);
 432                 return -EINVAL;
 433         }
 434
 435         n = timer >> 1;
 436         X = timer & 0x01;
 437
 438         if (GPTU_CON_EN(n, X))
 439                 *IFXMIPS_GPTU_RUN(n, X) = GPTU_RUN_CEN_SET(1);
 440
 441         *IFXMIPS_GPTU_IRNEN &= ~GPTU_IRNEN_TC_SET(n, X, 1);
 442         *IFXMIPS_GPTU_IRNCR |= GPTU_IRNCR_TC_SET(n, X, 1);
 443
 444         if (timer_dev.timer[timer - FIRST_TIMER].f_irq_on) {
 445                 disable_irq(timer_dev.timer[timer - FIRST_TIMER].irq);
 446                 timer_dev.timer[timer - FIRST_TIMER].f_irq_on = 0;
 447         }
 448
 449         timer_dev.occupation &= ~mask;
 450         if (!timer_dev.occupation && timer_dev.f_gptu_on) {
 451                 ifxmips_disable_gptu();
 452                 timer_dev.f_gptu_on = 0;
 453         }
 454
 455         mutex_unlock(&timer_dev.gptu_mutex);
 456
 457         return 0;
 458 }
 459 EXPORT_SYMBOL(ifxmips_free_timer);
 460
 461 int ifxmips_start_timer(unsigned int timer, int is_resume)
 462 {
 463         unsigned int flag;
 464         unsigned int mask;
 465         int n, X;
 466
 467         if (!timer_dev.f_gptu_on)
 468                 return -EINVAL;
 469
 470         if (timer < FIRST_TIMER || timer >= FIRST_TIMER + timer_dev.number_of_timers)
 471                 return -EINVAL;
 472
 473         mutex_lock(&timer_dev.gptu_mutex);
 474
 475         flag = timer_dev.timer[timer - FIRST_TIMER].flag;
 476         if (TIMER_FLAG_MASK_SIZE(flag) != TIMER_FLAG_16BIT)
 477                 timer &= ~0x01;
 478
 479         mask = (TIMER_FLAG_MASK_SIZE(flag) ==
 480         TIMER_FLAG_16BIT ? 1 : 3) << timer;
 481         if (((timer_dev.occupation & mask) ^ mask)) {
 482                 mutex_unlock(&timer_dev.gptu_mutex);
 483                 return -EINVAL;
 484         }
 485
 486         n = timer >> 1;
 487         X = timer & 0x01;
 488
 489         *IFXMIPS_GPTU_RUN(n, X) = GPTU_RUN_RL_SET(!is_resume) | GPTU_RUN_SEN_SET(1);
 490
 491         mutex_unlock(&timer_dev.gptu_mutex);
 492
 493         return 0;
 494 }
 495 EXPORT_SYMBOL(ifxmips_start_timer);
 496
 497 int ifxmips_stop_timer(unsigned int timer)
 498 {
 499         unsigned int flag;
 500         unsigned int mask;
 501         int n, X;
 502
 503         if (!timer_dev.f_gptu_on)
 504                 return -EINVAL;
 505
 506         if (timer < FIRST_TIMER
 507             || timer >= FIRST_TIMER + timer_dev.number_of_timers)
 508                 return -EINVAL;
 509
 510         mutex_lock(&timer_dev.gptu_mutex);
 511
 512         flag = timer_dev.timer[timer - FIRST_TIMER].flag;
 513         if (TIMER_FLAG_MASK_SIZE(flag) != TIMER_FLAG_16BIT)
 514                 timer &= ~0x01;
 515
 516         mask = (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT ? 1 : 3) << timer;
 517         if (((timer_dev.occupation & mask) ^ mask)) {
 518                 mutex_unlock(&timer_dev.gptu_mutex);
 519                 return -EINVAL;
 520         }
 521
 522         n = timer >> 1;
 523         X = timer & 0x01;
 524
 525         *IFXMIPS_GPTU_RUN(n, X) = GPTU_RUN_CEN_SET(1);
 526
 527         mutex_unlock(&timer_dev.gptu_mutex);
 528
 529         return 0;
 530 }
 531 EXPORT_SYMBOL(ifxmips_stop_timer);
 532
 533 int ifxmips_reset_counter_flags(u32 timer, u32 flags)
 534 {
 535         unsigned int oflag;
 536         unsigned int mask, con_reg;
 537         int n, X;
 538
 539         if (!timer_dev.f_gptu_on)
 540                 return -EINVAL;
 541
 542         if (timer < FIRST_TIMER || timer >= FIRST_TIMER + timer_dev.number_of_timers)
 543                 return -EINVAL;
 544
 545         mutex_lock(&timer_dev.gptu_mutex);
 546
 547         oflag = timer_dev.timer[timer - FIRST_TIMER].flag;
 548         if (TIMER_FLAG_MASK_SIZE(oflag) != TIMER_FLAG_16BIT)
 549                 timer &= ~0x01;
 550
 551         mask = (TIMER_FLAG_MASK_SIZE(oflag) == TIMER_FLAG_16BIT ? 1 : 3) << timer;
 552         if (((timer_dev.occupation & mask) ^ mask)) {
 553                 mutex_unlock(&timer_dev.gptu_mutex);
 554                 return -EINVAL;
 555         }
 556
 557         switch (TIMER_FLAG_MASK_EDGE(flags)) {
 558         default:
 559         case TIMER_FLAG_NONE_EDGE:
 560                 con_reg = GPTU_CON_EDGE_SET(0x00);
 561                 break;
 562         case TIMER_FLAG_RISE_EDGE:
 563                 con_reg = GPTU_CON_EDGE_SET(0x01);
 564                 break;
 565         case TIMER_FLAG_FALL_EDGE:
 566                 con_reg = GPTU_CON_EDGE_SET(0x02);
 567                 break;
 568         case TIMER_FLAG_ANY_EDGE:
 569                 con_reg = GPTU_CON_EDGE_SET(0x03);
 570                 break;
 571         }
 572         if (TIMER_FLAG_MASK_TYPE(flags) == TIMER_FLAG_TIMER)
 573                 con_reg |= TIMER_FLAG_MASK_SRC(flags) == TIMER_FLAG_EXT_SRC ? GPTU_CON_SRC_EXT_SET(1) : GPTU_CON_SRC_EXT_SET(0);
 574         else
 575                 con_reg |= TIMER_FLAG_MASK_SRC(flags) == TIMER_FLAG_EXT_SRC ? GPTU_CON_SRC_EG_SET(1) : GPTU_CON_SRC_EG_SET(0);
 576         con_reg |= TIMER_FLAG_MASK_SYNC(flags) == TIMER_FLAG_UNSYNC ? GPTU_CON_SYNC_SET(0) : GPTU_CON_SYNC_SET(1);
 577         con_reg |= TIMER_FLAG_MASK_INVERT(flags) == TIMER_FLAG_REAL ? GPTU_CON_INV_SET(0) : GPTU_CON_INV_SET(1);
 578         con_reg |= TIMER_FLAG_MASK_SIZE(flags) == TIMER_FLAG_16BIT ? GPTU_CON_EXT_SET(0) : GPTU_CON_EXT_SET(1);
 579         con_reg |= TIMER_FLAG_MASK_STOP(flags) == TIMER_FLAG_ONCE ? GPTU_CON_STP_SET(1) : GPTU_CON_STP_SET(0);
 580         con_reg |= TIMER_FLAG_MASK_TYPE(flags) == TIMER_FLAG_TIMER ? GPTU_CON_CNT_SET(0) : GPTU_CON_CNT_SET(1);
 581         con_reg |= TIMER_FLAG_MASK_DIR(flags) == TIMER_FLAG_UP ? GPTU_CON_DIR_SET(1) : GPTU_CON_DIR_SET(0);
 582
 583         timer_dev.timer[timer - FIRST_TIMER].flag = flags;
 584         if (TIMER_FLAG_MASK_SIZE(flags) != TIMER_FLAG_16BIT)
 585                 timer_dev.timer[timer - FIRST_TIMER + 1].flag = flags;
 586
 587         n = timer >> 1;
 588         X = timer & 0x01;
 589
 590         *IFXMIPS_GPTU_CON(n, X) = con_reg;
 591         smp_wmb();
 592         printk(KERN_INFO "[%s]: counter%d oflags %#x, nflags %#x, GPTU_CON %#x\n", __func__, timer, oflag, flags, *IFXMIPS_GPTU_CON(n, X));
 593         mutex_unlock(&timer_dev.gptu_mutex);
 594         return 0;
 595 }
 596 EXPORT_SYMBOL(ifxmips_reset_counter_flags);
 597
 598 int ifxmips_get_count_value(unsigned int timer, unsigned long *value)
 599 {
 600         unsigned int flag;
 601         unsigned int mask;
 602         int n, X;
 603
 604         if (!timer_dev.f_gptu_on)
 605                 return -EINVAL;
 606
 607         if (timer < FIRST_TIMER
 608             || timer >= FIRST_TIMER + timer_dev.number_of_timers)
 609                 return -EINVAL;
 610
 611         mutex_lock(&timer_dev.gptu_mutex);
 612
 613         flag = timer_dev.timer[timer - FIRST_TIMER].flag;
 614         if (TIMER_FLAG_MASK_SIZE(flag) != TIMER_FLAG_16BIT)
 615                 timer &= ~0x01;
 616
 617         mask = (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT ? 1 : 3) << timer;
 618         if (((timer_dev.occupation & mask) ^ mask)) {
 619                 mutex_unlock(&timer_dev.gptu_mutex);
 620                 return -EINVAL;
 621         }
 622
 623         n = timer >> 1;
 624         X = timer & 0x01;
 625
 626         *value = *IFXMIPS_GPTU_COUNT(n, X);
 627
 628         mutex_unlock(&timer_dev.gptu_mutex);
 629
 630         return 0;
 631 }
 632 EXPORT_SYMBOL(ifxmips_get_count_value);
 633
 634 u32 ifxmips_cal_divider(unsigned long freq)
 635 {
 636         u64 module_freq, fpi = cgu_get_fpi_bus_clock(2);
 637         u32 clock_divider = 1;
 638         module_freq = fpi * 1000;
 639         do_div(module_freq, clock_divider * freq);
 640         return module_freq;
 641 }
 642 EXPORT_SYMBOL(ifxmips_cal_divider);
 643
 644 int ifxmips_set_timer(unsigned int timer, unsigned int freq, int is_cyclic,
 645         int is_ext_src, unsigned int handle_flag, unsigned long arg1,
 646         unsigned long arg2)
 647 {
 648         unsigned long divider;
 649         unsigned int flag;
 650
 651         divider = ifxmips_cal_divider(freq);
 652         if (divider == 0)
 653                 return -EINVAL;
 654         flag = ((divider & ~0xFFFF) ? TIMER_FLAG_32BIT : TIMER_FLAG_16BIT)
 655                 | (is_cyclic ? TIMER_FLAG_CYCLIC : TIMER_FLAG_ONCE)
 656                 | (is_ext_src ? TIMER_FLAG_EXT_SRC : TIMER_FLAG_INT_SRC)
 657                 | TIMER_FLAG_TIMER | TIMER_FLAG_DOWN
 658                 | TIMER_FLAG_MASK_HANDLE(handle_flag);
 659
 660         printk(KERN_INFO "ifxmips_set_timer(%d, %d), divider = %lu\n",
 661                 timer, freq, divider);
 662         return ifxmips_request_timer(timer, flag, divider, arg1, arg2);
 663 }
 664 EXPORT_SYMBOL(ifxmips_set_timer);
 665
 666 int ifxmips_set_counter(unsigned int timer, unsigned int flag, u32 reload,
 667         unsigned long arg1, unsigned long arg2)
 668 {
 669         printk(KERN_INFO "ifxmips_set_counter(%d, %#x, %d)\n", timer, flag, reload);
 670         return ifxmips_request_timer(timer, flag, reload, arg1, arg2);
 671 }
 672 EXPORT_SYMBOL(ifxmips_set_counter);
 673
 674 static int gptu_ioctl(struct inode *inode, struct file *file, unsigned int cmd,
 675         unsigned long arg)
 676 {
 677         int ret;
 678         struct gptu_ioctl_param param;
 679
 680         if (!access_ok(VERIFY_READ, arg, sizeof(struct gptu_ioctl_param)))
 681                 return -EFAULT;
 682         copy_from_user(&param, (void *) arg, sizeof(param));
 683
 684         if ((((cmd == GPTU_REQUEST_TIMER || cmd == GPTU_SET_TIMER
 685                || GPTU_SET_COUNTER) && param.timer < 2)
 686              || cmd == GPTU_GET_COUNT_VALUE || cmd == GPTU_CALCULATE_DIVIDER)
 687             && !access_ok(VERIFY_WRITE, arg,
 688                            sizeof(struct gptu_ioctl_param)))
 689                 return -EFAULT;
 690
 691         switch (cmd) {
 692         case GPTU_REQUEST_TIMER:
 693                 ret = ifxmips_request_timer(param.timer, param.flag, param.value,
 694                                      (unsigned long) param.pid,
 695                                      (unsigned long) param.sig);
 696                 if (ret > 0) {
 697                         copy_to_user(&((struct gptu_ioctl_param *) arg)->
 698                                       timer, &ret, sizeof(&ret));
 699                         ret = 0;
 700                 }
 701                 break;
 702         case GPTU_FREE_TIMER:
 703                 ret = ifxmips_free_timer(param.timer);
 704                 break;
 705         case GPTU_START_TIMER:
 706                 ret = ifxmips_start_timer(param.timer, param.flag);
 707                 break;
 708         case GPTU_STOP_TIMER:
 709                 ret = ifxmips_stop_timer(param.timer);
 710                 break;
 711         case GPTU_GET_COUNT_VALUE:
 712                 ret = ifxmips_get_count_value(param.timer, &param.value);
 713                 if (!ret)
 714                         copy_to_user(&((struct gptu_ioctl_param *) arg)->
 715                                       value, &param.value,
 716                                       sizeof(param.value));
 717                 break;
 718         case GPTU_CALCULATE_DIVIDER:
 719                 param.value = ifxmips_cal_divider(param.value);
 720                 if (param.value == 0)
 721                         ret = -EINVAL;
 722                 else {
 723                         copy_to_user(&((struct gptu_ioctl_param *) arg)->
 724                                       value, &param.value,
 725                                       sizeof(param.value));
 726                         ret = 0;
 727                 }
 728                 break;
 729         case GPTU_SET_TIMER:
 730                 ret = ifxmips_set_timer(param.timer, param.value,
 731                                  TIMER_FLAG_MASK_STOP(param.flag) !=
 732                                  TIMER_FLAG_ONCE ? 1 : 0,
 733                                  TIMER_FLAG_MASK_SRC(param.flag) ==
 734                                  TIMER_FLAG_EXT_SRC ? 1 : 0,
 735                                  TIMER_FLAG_MASK_HANDLE(param.flag) ==
 736                                  TIMER_FLAG_SIGNAL ? TIMER_FLAG_SIGNAL :
 737                                  TIMER_FLAG_NO_HANDLE,
 738                                  (unsigned long) param.pid,
 739                                  (unsigned long) param.sig);
 740                 if (ret > 0) {
 741                         copy_to_user(&((struct gptu_ioctl_param *) arg)->
 742                                       timer, &ret, sizeof(&ret));
 743                         ret = 0;
 744                 }
 745                 break;
 746         case GPTU_SET_COUNTER:
 747                 ifxmips_set_counter(param.timer, param.flag, param.value, 0, 0);
 748                 if (ret > 0) {
 749                         copy_to_user(&((struct gptu_ioctl_param *) arg)->
 750                                       timer, &ret, sizeof(&ret));
 751                         ret = 0;
 752                 }
 753                 break;
 754         default:
 755                 ret = -ENOTTY;
 756         }
 757
 758         return ret;
 759 }
 760
 761 static int gptu_open(struct inode *inode, struct file *file)
 762 {
 763         return 0;
 764 }
 765
 766 static int gptu_release(struct inode *inode, struct file *file)
 767 {
 768         return 0;
 769 }
 770
 771 int __init ifxmips_gptu_init(void)
 772 {
 773         int ret;
 774         unsigned int i;
 775
 776         ifxmips_w32(0, IFXMIPS_GPTU_IRNEN);
 777         ifxmips_w32(0xfff, IFXMIPS_GPTU_IRNCR);
 778
 779         memset(&timer_dev, 0, sizeof(timer_dev));
 780         mutex_init(&timer_dev.gptu_mutex);
 781
 782         ifxmips_enable_gptu();
 783         timer_dev.number_of_timers = GPTU_ID_CFG * 2;
 784         ifxmips_disable_gptu();
 785         if (timer_dev.number_of_timers > MAX_NUM_OF_32BIT_TIMER_BLOCKS * 2)
 786                 timer_dev.number_of_timers = MAX_NUM_OF_32BIT_TIMER_BLOCKS * 2;
 787         printk(KERN_INFO "gptu: totally %d 16-bit timers/counters\n", timer_dev.number_of_timers);
 788
 789         ret = misc_register(&gptu_miscdev);
 790         if (ret) {
 791                 printk(KERN_ERR "gptu: can't misc_register, get error %d\n", -ret);
 792                 return ret;
 793         } else {
 794                 printk(KERN_INFO "gptu: misc_register on minor %d\n", gptu_miscdev.minor);
 795         }
 796
 797         for (i = 0; i < timer_dev.number_of_timers; i++) {
 798                 ret = request_irq(TIMER_INTERRUPT + i, timer_irq_handler, IRQF_TIMER, gptu_miscdev.name, &timer_dev.timer[i]);
 799                 if (ret) {
 800                         for (; i >= 0; i--)
 801                                 free_irq(TIMER_INTERRUPT + i, &timer_dev.timer[i]);
 802                         misc_deregister(&gptu_miscdev);
 803                         printk(KERN_ERR "gptu: failed in requesting irq (%d), get error %d\n", i, -ret);
 804                         return ret;
 805                 } else {
 806                         timer_dev.timer[i].irq = TIMER_INTERRUPT + i;
 807                         disable_irq(timer_dev.timer[i].irq);
 808                         printk(KERN_INFO "gptu: succeeded to request irq %d\n", timer_dev.timer[i].irq);
 809                 }
 810         }
 811
 812         return 0;
 813 }
 814
 815 void __exit ifxmips_gptu_exit(void)
 816 {
 817         unsigned int i;
 818
 819         for (i = 0; i < timer_dev.number_of_timers; i++) {
 820                 if (timer_dev.timer[i].f_irq_on)
 821                         disable_irq(timer_dev.timer[i].irq);
 822                 free_irq(timer_dev.timer[i].irq, &timer_dev.timer[i]);
 823         }
 824         ifxmips_disable_gptu();
 825         misc_deregister(&gptu_miscdev);
 826 }
 827
 828 module_init(ifxmips_gptu_init);
 829 module_exit(ifxmips_gptu_exit);