2 * Sonics Silicon Backplane
3 * Broadcom PCI-core driver
5 * Copyright 2005, Broadcom Corporation
6 * Copyright 2006, 2007, Michael Buesch <mb@bu3sch.de>
8 * Licensed under the GNU/GPL. See COPYING for details.
11 #include <linux/ssb/ssb.h>
12 #include <linux/pci.h>
13 #include <linux/delay.h>
15 #include "ssb_private.h"
19 u32 pcicore_read32(struct ssb_pcicore *pc, u16 offset)
21 return ssb_read32(pc->dev, offset);
25 void pcicore_write32(struct ssb_pcicore *pc, u16 offset, u32 value)
27 ssb_write32(pc->dev, offset, value);
30 /**************************************************
31 * Code for hostmode operation.
32 **************************************************/
34 #ifdef CONFIG_SSB_PCICORE_HOSTMODE
36 #include <asm/paccess.h>
37 /* Read the bus and catch bus exceptions. This is MIPS specific. */
38 #define mips_busprobe(val, addr) get_dbe((val), (addr))
40 /* Assume one-hot slot wiring */
41 #define SSB_PCI_SLOT_MAX 16
43 /* Global lock is OK, as we won't have more than one extpci anyway. */
44 static DEFINE_SPINLOCK(cfgspace_lock);
45 /* Core to access the external PCI config space. Can only have one. */
46 static struct ssb_pcicore *extpci_core;
48 u32 pci_iobase = 0x100;
49 u32 pci_membase = SSB_PCI_DMA;
51 int pcibios_plat_dev_init(struct pci_dev *d)
57 printk("PCI: Fixing up device %s\n", pci_name(d));
59 /* Fix up resource bases */
60 for (pos = 0; pos < 6; pos++) {
61 res = &d->resource[pos];
62 base = ((res->flags & IORESOURCE_IO) ? &pci_iobase : &pci_membase);
64 size = res->end - res->start + 1;
65 if (*base & (size - 1))
66 *base = (*base + size) & ~(size - 1);
68 res->end = res->start + size - 1;
70 pci_write_config_dword(d, PCI_BASE_ADDRESS_0 + (pos << 2), res->start);
72 /* Fix up PCI bridge BAR0 only */
73 if (d->bus->number == 0 && PCI_SLOT(d->devfn) == 0)
76 /* Fix up interrupt lines */
77 d->irq = ssb_mips_irq(extpci_core->dev) + 2;
78 pci_write_config_byte(d, PCI_INTERRUPT_LINE, d->irq);
83 static void __init ssb_fixup_pcibridge(struct pci_dev *dev)
85 if (dev->bus->number != 0 || PCI_SLOT(dev->devfn) != 0)
88 printk("PCI: fixing up bridge\n");
90 /* Enable PCI bridge bus mastering and memory space */
92 pcibios_enable_device(dev, ~0);
94 /* Enable PCI bridge BAR1 prefetch and burst */
95 pci_write_config_dword(dev, SSB_BAR1_CONTROL, 3);
97 /* Make sure our latency is high enough to handle the devices behind us */
98 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0xa8);
100 DECLARE_PCI_FIXUP_EARLY(PCI_ANY_ID, PCI_ANY_ID, ssb_fixup_pcibridge);
102 int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
104 return ssb_mips_irq(extpci_core->dev) + 2;
107 static u32 get_cfgspace_addr(struct ssb_pcicore *pc,
108 unsigned int bus, unsigned int dev,
109 unsigned int func, unsigned int off)
114 if (unlikely(pc->cardbusmode && dev > 1))
116 if (bus == 0) {//FIXME busnumber ok?
117 /* Type 0 transaction */
118 if (unlikely(dev >= SSB_PCI_SLOT_MAX))
120 /* Slide the window */
121 tmp = SSB_PCICORE_SBTOPCI_CFG0;
122 tmp |= ((1 << (dev + 16)) & SSB_PCICORE_SBTOPCI1_MASK);
123 pcicore_write32(pc, SSB_PCICORE_SBTOPCI1, tmp);
124 /* Calculate the address */
126 addr |= ((1 << (dev + 16)) & ~SSB_PCICORE_SBTOPCI1_MASK);
130 /* Type 1 transaction */
131 pcicore_write32(pc, SSB_PCICORE_SBTOPCI1,
132 SSB_PCICORE_SBTOPCI_CFG1);
133 /* Calculate the address */
144 static int ssb_extpci_read_config(struct ssb_pcicore *pc,
145 unsigned int bus, unsigned int dev,
146 unsigned int func, unsigned int off,
153 assert(pc->hostmode);
154 if (unlikely(len != 1 && len != 2 && len != 4))
156 addr = get_cfgspace_addr(pc, bus, dev, func, off);
160 mmio = ioremap_nocache(addr, len);
164 if (mips_busprobe(val, (u32 *) mmio)) {
170 val >>= (8 * (off & 3));
174 *((u8 *)buf) = (u8)val;
177 *((u16 *)buf) = (u16)val;
180 *((u32 *)buf) = (u32)val;
190 static int ssb_extpci_write_config(struct ssb_pcicore *pc,
191 unsigned int bus, unsigned int dev,
192 unsigned int func, unsigned int off,
193 const void *buf, int len)
199 assert(pc->hostmode);
200 if (unlikely(len != 1 && len != 2 && len != 4))
202 addr = get_cfgspace_addr(pc, bus, dev, func, off);
206 mmio = ioremap_nocache(addr, len);
210 if (mips_busprobe(val, (u32 *) mmio)) {
218 val &= ~(0xFF << (8 * (off & 3)));
219 val |= *((const u8 *)buf) << (8 * (off & 3));
223 val &= ~(0xFFFF << (8 * (off & 3)));
224 val |= *((const u16 *)buf) << (8 * (off & 3));
227 val = *((const u32 *)buf);
239 static int ssb_pcicore_read_config(struct pci_bus *bus, unsigned int devfn,
240 int reg, int size, u32 *val)
245 spin_lock_irqsave(&cfgspace_lock, flags);
246 err = ssb_extpci_read_config(extpci_core, bus->number, PCI_SLOT(devfn),
247 PCI_FUNC(devfn), reg, val, size);
248 spin_unlock_irqrestore(&cfgspace_lock, flags);
250 return err ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
253 static int ssb_pcicore_write_config(struct pci_bus *bus, unsigned int devfn,
254 int reg, int size, u32 val)
259 spin_lock_irqsave(&cfgspace_lock, flags);
260 err = ssb_extpci_write_config(extpci_core, bus->number, PCI_SLOT(devfn),
261 PCI_FUNC(devfn), reg, &val, size);
262 spin_unlock_irqrestore(&cfgspace_lock, flags);
264 return err ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
267 static struct pci_ops ssb_pcicore_pciops = {
268 .read = ssb_pcicore_read_config,
269 .write = ssb_pcicore_write_config,
272 static struct resource ssb_pcicore_mem_resource = {
273 .name = "SSB PCIcore external memory",
274 .start = SSB_PCI_DMA,
275 .end = (u32)SSB_PCI_DMA + (u32)SSB_PCI_DMA_SZ - 1,
276 .flags = IORESOURCE_MEM,
279 static struct resource ssb_pcicore_io_resource = {
280 .name = "SSB PCIcore external I/O",
283 .flags = IORESOURCE_IO,
286 static struct pci_controller ssb_pcicore_controller = {
287 .pci_ops = &ssb_pcicore_pciops,
288 .io_resource = &ssb_pcicore_io_resource,
289 .mem_resource = &ssb_pcicore_mem_resource,
290 .mem_offset = 0x24000000,
293 static void ssb_pcicore_init_hostmode(struct ssb_pcicore *pc)
303 ssb_dprintk(KERN_INFO PFX "PCIcore in host mode found\n");
304 /* Reset devices on the external PCI bus */
305 val = SSB_PCICORE_CTL_RST_OE;
306 val |= SSB_PCICORE_CTL_CLK_OE;
307 pcicore_write32(pc, SSB_PCICORE_CTL, val);
308 val |= SSB_PCICORE_CTL_CLK; /* Clock on */
309 pcicore_write32(pc, SSB_PCICORE_CTL, val);
311 val |= SSB_PCICORE_CTL_RST; /* Deassert RST# */
312 pcicore_write32(pc, SSB_PCICORE_CTL, val);
313 val = SSB_PCICORE_ARBCTL_INTERN;
314 pcicore_write32(pc, SSB_PCICORE_ARBCTL, val);
319 /* 64MB I/O window */
320 pcicore_write32(pc, SSB_PCICORE_SBTOPCI0,
321 SSB_PCICORE_SBTOPCI_IO);
322 /* 64MB config space */
323 pcicore_write32(pc, SSB_PCICORE_SBTOPCI1,
324 SSB_PCICORE_SBTOPCI_CFG0);
325 /* 1GB memory window */
326 pcicore_write32(pc, SSB_PCICORE_SBTOPCI2,
327 SSB_PCICORE_SBTOPCI_MEM | SSB_PCI_DMA);
329 /* Enable PCI bridge BAR0 prefetch and burst */
330 val = PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
331 ssb_extpci_write_config(pc, 0, 0, 0, PCI_COMMAND, &val, 2);
332 /* Clear error conditions */
334 ssb_extpci_write_config(pc, 0, 0, 0, PCI_STATUS, &val, 2);
336 /* Enable PCI interrupts */
337 pcicore_write32(pc, SSB_PCICORE_IMASK,
338 SSB_PCICORE_IMASK_INTA);
340 /* Ok, ready to run, register it to the system.
341 * The following needs change, if we want to port hostmode
342 * to non-MIPS platform. */
343 set_io_port_base((unsigned long)ioremap_nocache(SSB_PCI_MEM, 0x04000000));
345 register_pci_controller(&ssb_pcicore_controller);
348 static int pcicore_is_in_hostmode(struct ssb_pcicore *pc)
350 struct ssb_bus *bus = pc->dev->bus;
354 chipid_top = (bus->chip_id & 0xFF00);
355 if (chipid_top != 0x4700 &&
356 chipid_top != 0x5300)
359 if (bus->sprom.r1.boardflags_lo & SSB_PCICORE_BFL_NOPCI)
362 /* The 200-pin BCM4712 package does not bond out PCI. Even when
363 * PCI is bonded out, some boards may leave the pins floating. */
364 if (bus->chip_id == 0x4712) {
365 if (bus->chip_package == SSB_CHIPPACK_BCM4712S)
367 if (bus->chip_package == SSB_CHIPPACK_BCM4712M)
370 if (bus->chip_id == 0x5350)
373 return !mips_busprobe(tmp, (u32 *) (bus->mmio + (pc->dev->core_index * SSB_CORE_SIZE)));
375 #endif /* CONFIG_SSB_PCICORE_HOSTMODE */
378 /**************************************************
379 * Generic and Clientmode operation code.
380 **************************************************/
382 static void ssb_pcicore_init_clientmode(struct ssb_pcicore *pc)
384 /* Disable PCI interrupts. */
385 ssb_write32(pc->dev, SSB_INTVEC, 0);
388 void ssb_pcicore_init(struct ssb_pcicore *pc)
390 struct ssb_device *dev = pc->dev;
396 if (!ssb_device_is_enabled(dev))
397 ssb_device_enable(dev, 0);
399 #ifdef CONFIG_SSB_PCICORE_HOSTMODE
400 pc->hostmode = pcicore_is_in_hostmode(pc);
402 ssb_pcicore_init_hostmode(pc);
403 #endif /* CONFIG_SSB_PCICORE_HOSTMODE */
405 ssb_pcicore_init_clientmode(pc);
408 static u32 ssb_pcie_read(struct ssb_pcicore *pc, u32 address)
410 pcicore_write32(pc, 0x130, address);
411 return pcicore_read32(pc, 0x134);
414 static void ssb_pcie_write(struct ssb_pcicore *pc, u32 address, u32 data)
416 pcicore_write32(pc, 0x130, address);
417 pcicore_write32(pc, 0x134, data);
420 static void ssb_pcie_mdio_write(struct ssb_pcicore *pc, u8 device,
421 u8 address, u16 data)
423 const u16 mdio_control = 0x128;
424 const u16 mdio_data = 0x12C;
428 v = 0x80; /* Enable Preamble Sequence */
429 v |= 0x2; /* MDIO Clock Divisor */
430 pcicore_write32(pc, mdio_control, v);
432 v = (1 << 30); /* Start of Transaction */
433 v |= (1 << 28); /* Write Transaction */
434 v |= (1 << 17); /* Turnaround */
435 v |= (u32)device << 22;
436 v |= (u32)address << 18;
438 pcicore_write32(pc, mdio_data, v);
440 for (i = 0; i < 10; i++) {
441 v = pcicore_read32(pc, mdio_control);
442 if (v & 0x100 /* Trans complete */)
446 pcicore_write32(pc, mdio_control, 0);
449 static void ssb_broadcast_value(struct ssb_device *dev,
450 u32 address, u32 data)
452 /* This is used for both, PCI and ChipCommon core, so be careful. */
453 BUILD_BUG_ON(SSB_PCICORE_BCAST_ADDR != SSB_CHIPCO_BCAST_ADDR);
454 BUILD_BUG_ON(SSB_PCICORE_BCAST_DATA != SSB_CHIPCO_BCAST_DATA);
456 ssb_write32(dev, SSB_PCICORE_BCAST_ADDR, address);
457 ssb_read32(dev, SSB_PCICORE_BCAST_ADDR); /* flush */
458 ssb_write32(dev, SSB_PCICORE_BCAST_DATA, data);
459 ssb_read32(dev, SSB_PCICORE_BCAST_DATA); /* flush */
462 static void ssb_commit_settings(struct ssb_bus *bus)
464 struct ssb_device *dev;
466 dev = bus->chipco.dev ? bus->chipco.dev : bus->pcicore.dev;
468 /* This forces an update of the cached registers. */
469 ssb_broadcast_value(dev, 0xFD8, 0);
472 int ssb_pcicore_dev_irqvecs_enable(struct ssb_pcicore *pc,
473 struct ssb_device *dev)
475 struct ssb_device *pdev = pc->dev;
486 /* Enable interrupts for this device. */
488 ((pdev->id.revision >= 6) || (pdev->id.coreid == SSB_DEV_PCIE))) {
491 /* Calculate the "coremask" for the device. */
492 coremask = (1 << dev->core_index);
494 err = pci_read_config_dword(bus->host_pci, SSB_PCI_IRQMASK, &tmp);
497 tmp |= coremask << 8;
498 err = pci_write_config_dword(bus->host_pci, SSB_PCI_IRQMASK, tmp);
504 intvec = ssb_read32(pdev, SSB_INTVEC);
505 tmp = ssb_read32(dev, SSB_TPSFLAG);
506 tmp &= SSB_TPSFLAG_BPFLAG;
508 ssb_write32(pdev, SSB_INTVEC, intvec);
511 /* Setup PCIcore operation. */
514 if (pdev->id.coreid == SSB_DEV_PCI) {
515 tmp = pcicore_read32(pc, SSB_PCICORE_SBTOPCI2);
516 tmp |= SSB_PCICORE_SBTOPCI_PREF;
517 tmp |= SSB_PCICORE_SBTOPCI_BURST;
518 pcicore_write32(pc, SSB_PCICORE_SBTOPCI2, tmp);
520 if (pdev->id.revision < 5) {
521 tmp = ssb_read32(pdev, SSB_IMCFGLO);
522 tmp &= ~SSB_IMCFGLO_SERTO;
524 tmp &= ~SSB_IMCFGLO_REQTO;
525 tmp |= 3 << SSB_IMCFGLO_REQTO_SHIFT;
526 ssb_write32(pdev, SSB_IMCFGLO, tmp);
527 ssb_commit_settings(bus);
528 } else if (pdev->id.revision >= 11) {
529 tmp = pcicore_read32(pc, SSB_PCICORE_SBTOPCI2);
530 tmp |= SSB_PCICORE_SBTOPCI_MRM;
531 pcicore_write32(pc, SSB_PCICORE_SBTOPCI2, tmp);
534 assert(pdev->id.coreid == SSB_DEV_PCIE);
535 //TODO: Better make defines for all these magic PCIE values.
536 if ((pdev->id.revision == 0) || (pdev->id.revision == 1)) {
537 /* TLP Workaround register. */
538 tmp = ssb_pcie_read(pc, 0x4);
540 ssb_pcie_write(pc, 0x4, tmp);
542 if (pdev->id.revision == 0) {
543 const u8 serdes_rx_device = 0x1F;
545 ssb_pcie_mdio_write(pc, serdes_rx_device,
546 2 /* Timer */, 0x8128);
547 ssb_pcie_mdio_write(pc, serdes_rx_device,
548 6 /* CDR */, 0x0100);
549 ssb_pcie_mdio_write(pc, serdes_rx_device,
550 7 /* CDR BW */, 0x1466);
551 } else if (pdev->id.revision == 1) {
552 /* DLLP Link Control register. */
553 tmp = ssb_pcie_read(pc, 0x100);
555 ssb_pcie_write(pc, 0x100, tmp);
562 EXPORT_SYMBOL(ssb_pcicore_dev_irqvecs_enable);