1 --- a/drivers/bcma/Kconfig
2 +++ b/drivers/bcma/Kconfig
3 @@ -65,6 +65,14 @@ config BCMA_DRIVER_GMAC_CMN
7 +config BCMA_DRIVER_GPIO
8 + bool "BCMA GPIO driver"
9 + depends on BCMA && GPIOLIB
11 + Driver to provide access to the GPIO pins of the bcma bus.
18 --- a/drivers/bcma/Makefile
19 +++ b/drivers/bcma/Makefile
20 @@ -6,6 +6,7 @@ bcma-y += driver_pci.o
21 bcma-$(CONFIG_BCMA_DRIVER_PCI_HOSTMODE) += driver_pci_host.o
22 bcma-$(CONFIG_BCMA_DRIVER_MIPS) += driver_mips.o
23 bcma-$(CONFIG_BCMA_DRIVER_GMAC_CMN) += driver_gmac_cmn.o
24 +bcma-$(CONFIG_BCMA_DRIVER_GPIO) += driver_gpio.o
25 bcma-$(CONFIG_BCMA_HOST_PCI) += host_pci.o
26 bcma-$(CONFIG_BCMA_HOST_SOC) += host_soc.o
27 obj-$(CONFIG_BCMA) += bcma.o
28 --- a/drivers/bcma/bcma_private.h
29 +++ b/drivers/bcma/bcma_private.h
30 @@ -31,6 +31,8 @@ int __init bcma_bus_early_register(struc
31 int bcma_bus_suspend(struct bcma_bus *bus);
32 int bcma_bus_resume(struct bcma_bus *bus);
34 +struct bcma_device *bcma_find_core_unit(struct bcma_bus *bus, u16 coreid,
38 int bcma_bus_scan(struct bcma_bus *bus);
39 @@ -48,8 +50,8 @@ void bcma_chipco_serial_init(struct bcma
40 #endif /* CONFIG_BCMA_DRIVER_MIPS */
42 /* driver_chipcommon_pmu.c */
43 -u32 bcma_pmu_alp_clock(struct bcma_drv_cc *cc);
44 -u32 bcma_pmu_get_clockcpu(struct bcma_drv_cc *cc);
45 +u32 bcma_pmu_get_alp_clock(struct bcma_drv_cc *cc);
46 +u32 bcma_pmu_get_cpu_clock(struct bcma_drv_cc *cc);
48 #ifdef CONFIG_BCMA_SFLASH
49 /* driver_chipcommon_sflash.c */
50 @@ -84,9 +86,21 @@ extern void __exit bcma_host_pci_exit(vo
52 u32 bcma_pcie_read(struct bcma_drv_pci *pc, u32 address);
54 +extern int bcma_chipco_watchdog_register(struct bcma_drv_cc *cc);
56 #ifdef CONFIG_BCMA_DRIVER_PCI_HOSTMODE
57 bool __devinit bcma_core_pci_is_in_hostmode(struct bcma_drv_pci *pc);
58 void __devinit bcma_core_pci_hostmode_init(struct bcma_drv_pci *pc);
59 #endif /* CONFIG_BCMA_DRIVER_PCI_HOSTMODE */
61 +#ifdef CONFIG_BCMA_DRIVER_GPIO
63 +int bcma_gpio_init(struct bcma_drv_cc *cc);
65 +static inline int bcma_gpio_init(struct bcma_drv_cc *cc)
69 +#endif /* CONFIG_BCMA_DRIVER_GPIO */
72 --- a/drivers/bcma/driver_chipcommon.c
73 +++ b/drivers/bcma/driver_chipcommon.c
76 * Copyright 2005, Broadcom Corporation
77 * Copyright 2006, 2007, Michael Buesch <m@bues.ch>
78 + * Copyright 2012, Hauke Mehrtens <hauke@hauke-m.de>
80 * Licensed under the GNU/GPL. See COPYING for details.
83 #include "bcma_private.h"
84 +#include <linux/bcm47xx_wdt.h>
85 #include <linux/export.h>
86 +#include <linux/platform_device.h>
87 #include <linux/bcma/bcma.h>
89 static inline u32 bcma_cc_write32_masked(struct bcma_drv_cc *cc, u16 offset,
90 @@ -22,20 +25,119 @@ static inline u32 bcma_cc_write32_masked
94 -void bcma_core_chipcommon_init(struct bcma_drv_cc *cc)
95 +static u32 bcma_chipco_get_alp_clock(struct bcma_drv_cc *cc)
99 + if (cc->capabilities & BCMA_CC_CAP_PMU)
100 + return bcma_pmu_get_alp_clock(cc);
102 - if (cc->setup_done)
106 +static u32 bcma_chipco_watchdog_get_max_timer(struct bcma_drv_cc *cc)
108 + struct bcma_bus *bus = cc->core->bus;
111 + if (cc->capabilities & BCMA_CC_CAP_PMU) {
112 + if (bus->chipinfo.id == BCMA_CHIP_ID_BCM4706)
114 + else if (cc->core->id.rev < 26)
117 + nb = (cc->core->id.rev >= 37) ? 32 : 24;
124 + return (1 << nb) - 1;
127 +static u32 bcma_chipco_watchdog_timer_set_wdt(struct bcm47xx_wdt *wdt,
130 + struct bcma_drv_cc *cc = bcm47xx_wdt_get_drvdata(wdt);
132 + return bcma_chipco_watchdog_timer_set(cc, ticks);
135 +static u32 bcma_chipco_watchdog_timer_set_ms_wdt(struct bcm47xx_wdt *wdt,
138 + struct bcma_drv_cc *cc = bcm47xx_wdt_get_drvdata(wdt);
141 + ticks = bcma_chipco_watchdog_timer_set(cc, cc->ticks_per_ms * ms);
142 + return ticks / cc->ticks_per_ms;
145 +static int bcma_chipco_watchdog_ticks_per_ms(struct bcma_drv_cc *cc)
147 + struct bcma_bus *bus = cc->core->bus;
149 + if (cc->capabilities & BCMA_CC_CAP_PMU) {
150 + if (bus->chipinfo.id == BCMA_CHIP_ID_BCM4706)
151 + /* 4706 CC and PMU watchdogs are clocked at 1/4 of ALP clock */
152 + return bcma_chipco_get_alp_clock(cc) / 4000;
154 + /* based on 32KHz ILP clock */
157 + return bcma_chipco_get_alp_clock(cc) / 1000;
161 +int bcma_chipco_watchdog_register(struct bcma_drv_cc *cc)
163 + struct bcm47xx_wdt wdt = {};
164 + struct platform_device *pdev;
166 + wdt.driver_data = cc;
167 + wdt.timer_set = bcma_chipco_watchdog_timer_set_wdt;
168 + wdt.timer_set_ms = bcma_chipco_watchdog_timer_set_ms_wdt;
169 + wdt.max_timer_ms = bcma_chipco_watchdog_get_max_timer(cc) / cc->ticks_per_ms;
171 + pdev = platform_device_register_data(NULL, "bcm47xx-wdt",
172 + cc->core->bus->num, &wdt,
175 + return PTR_ERR(pdev);
177 + cc->watchdog = pdev;
182 +void bcma_core_chipcommon_early_init(struct bcma_drv_cc *cc)
184 + if (cc->early_setup_done)
187 + spin_lock_init(&cc->gpio_lock);
189 if (cc->core->id.rev >= 11)
190 cc->status = bcma_cc_read32(cc, BCMA_CC_CHIPSTAT);
191 cc->capabilities = bcma_cc_read32(cc, BCMA_CC_CAP);
192 if (cc->core->id.rev >= 35)
193 cc->capabilities_ext = bcma_cc_read32(cc, BCMA_CC_CAP_EXT);
195 + if (cc->capabilities & BCMA_CC_CAP_PMU)
196 + bcma_pmu_early_init(cc);
198 + cc->early_setup_done = true;
201 +void bcma_core_chipcommon_init(struct bcma_drv_cc *cc)
204 + u32 leddc_off = 90;
206 + if (cc->setup_done)
209 + bcma_core_chipcommon_early_init(cc);
211 if (cc->core->id.rev >= 20) {
212 bcma_cc_write32(cc, BCMA_CC_GPIOPULLUP, 0);
213 bcma_cc_write32(cc, BCMA_CC_GPIOPULLDOWN, 0);
214 @@ -56,15 +158,33 @@ void bcma_core_chipcommon_init(struct bc
215 ((leddc_on << BCMA_CC_GPIOTIMER_ONTIME_SHIFT) |
216 (leddc_off << BCMA_CC_GPIOTIMER_OFFTIME_SHIFT)));
218 + cc->ticks_per_ms = bcma_chipco_watchdog_ticks_per_ms(cc);
220 cc->setup_done = true;
223 /* Set chip watchdog reset timer to fire in 'ticks' backplane cycles */
224 -void bcma_chipco_watchdog_timer_set(struct bcma_drv_cc *cc, u32 ticks)
225 +u32 bcma_chipco_watchdog_timer_set(struct bcma_drv_cc *cc, u32 ticks)
228 - bcma_cc_write32(cc, BCMA_CC_WATCHDOG, ticks);
230 + enum bcma_clkmode clkmode;
232 + maxt = bcma_chipco_watchdog_get_max_timer(cc);
233 + if (cc->capabilities & BCMA_CC_CAP_PMU) {
236 + else if (ticks > maxt)
238 + bcma_cc_write32(cc, BCMA_CC_PMU_WATCHDOG, ticks);
240 + clkmode = ticks ? BCMA_CLKMODE_FAST : BCMA_CLKMODE_DYNAMIC;
241 + bcma_core_set_clockmode(cc->core, clkmode);
245 + bcma_cc_write32(cc, BCMA_CC_WATCHDOG, ticks);
250 void bcma_chipco_irq_mask(struct bcma_drv_cc *cc, u32 mask, u32 value)
251 @@ -84,28 +204,97 @@ u32 bcma_chipco_gpio_in(struct bcma_drv_
253 u32 bcma_chipco_gpio_out(struct bcma_drv_cc *cc, u32 mask, u32 value)
255 - return bcma_cc_write32_masked(cc, BCMA_CC_GPIOOUT, mask, value);
256 + unsigned long flags;
259 + spin_lock_irqsave(&cc->gpio_lock, flags);
260 + res = bcma_cc_write32_masked(cc, BCMA_CC_GPIOOUT, mask, value);
261 + spin_unlock_irqrestore(&cc->gpio_lock, flags);
266 u32 bcma_chipco_gpio_outen(struct bcma_drv_cc *cc, u32 mask, u32 value)
268 - return bcma_cc_write32_masked(cc, BCMA_CC_GPIOOUTEN, mask, value);
269 + unsigned long flags;
272 + spin_lock_irqsave(&cc->gpio_lock, flags);
273 + res = bcma_cc_write32_masked(cc, BCMA_CC_GPIOOUTEN, mask, value);
274 + spin_unlock_irqrestore(&cc->gpio_lock, flags);
280 + * If the bit is set to 0, chipcommon controlls this GPIO,
281 + * if the bit is set to 1, it is used by some part of the chip and not our code.
283 u32 bcma_chipco_gpio_control(struct bcma_drv_cc *cc, u32 mask, u32 value)
285 - return bcma_cc_write32_masked(cc, BCMA_CC_GPIOCTL, mask, value);
286 + unsigned long flags;
289 + spin_lock_irqsave(&cc->gpio_lock, flags);
290 + res = bcma_cc_write32_masked(cc, BCMA_CC_GPIOCTL, mask, value);
291 + spin_unlock_irqrestore(&cc->gpio_lock, flags);
295 EXPORT_SYMBOL_GPL(bcma_chipco_gpio_control);
297 u32 bcma_chipco_gpio_intmask(struct bcma_drv_cc *cc, u32 mask, u32 value)
299 - return bcma_cc_write32_masked(cc, BCMA_CC_GPIOIRQ, mask, value);
300 + unsigned long flags;
303 + spin_lock_irqsave(&cc->gpio_lock, flags);
304 + res = bcma_cc_write32_masked(cc, BCMA_CC_GPIOIRQ, mask, value);
305 + spin_unlock_irqrestore(&cc->gpio_lock, flags);
310 u32 bcma_chipco_gpio_polarity(struct bcma_drv_cc *cc, u32 mask, u32 value)
312 - return bcma_cc_write32_masked(cc, BCMA_CC_GPIOPOL, mask, value);
313 + unsigned long flags;
316 + spin_lock_irqsave(&cc->gpio_lock, flags);
317 + res = bcma_cc_write32_masked(cc, BCMA_CC_GPIOPOL, mask, value);
318 + spin_unlock_irqrestore(&cc->gpio_lock, flags);
323 +u32 bcma_chipco_gpio_pullup(struct bcma_drv_cc *cc, u32 mask, u32 value)
325 + unsigned long flags;
328 + if (cc->core->id.rev < 20)
331 + spin_lock_irqsave(&cc->gpio_lock, flags);
332 + res = bcma_cc_write32_masked(cc, BCMA_CC_GPIOPULLUP, mask, value);
333 + spin_unlock_irqrestore(&cc->gpio_lock, flags);
338 +u32 bcma_chipco_gpio_pulldown(struct bcma_drv_cc *cc, u32 mask, u32 value)
340 + unsigned long flags;
343 + if (cc->core->id.rev < 20)
346 + spin_lock_irqsave(&cc->gpio_lock, flags);
347 + res = bcma_cc_write32_masked(cc, BCMA_CC_GPIOPULLDOWN, mask, value);
348 + spin_unlock_irqrestore(&cc->gpio_lock, flags);
353 #ifdef CONFIG_BCMA_DRIVER_MIPS
354 @@ -118,8 +307,7 @@ void bcma_chipco_serial_init(struct bcma
355 struct bcma_serial_port *ports = cc->serial_ports;
357 if (ccrev >= 11 && ccrev != 15) {
358 - /* Fixed ALP clock */
359 - baud_base = bcma_pmu_alp_clock(cc);
360 + baud_base = bcma_chipco_get_alp_clock(cc);
362 /* Turn off UART clock before switching clocksource. */
363 bcma_cc_write32(cc, BCMA_CC_CORECTL,
364 --- a/drivers/bcma/driver_chipcommon_nflash.c
365 +++ b/drivers/bcma/driver_chipcommon_nflash.c
366 @@ -32,6 +32,9 @@ int bcma_nflash_init(struct bcma_drv_cc
369 cc->nflash.present = true;
370 + if (cc->core->id.rev == 38 &&
371 + (cc->status & BCMA_CC_CHIPST_5357_NAND_BOOT))
372 + cc->nflash.boot = true;
374 /* Prepare platform device, but don't register it yet. It's too early,
375 * malloc (required by device_private_init) is not available yet. */
376 --- a/drivers/bcma/driver_chipcommon_pmu.c
377 +++ b/drivers/bcma/driver_chipcommon_pmu.c
379 #include <linux/export.h>
380 #include <linux/bcma/bcma.h>
382 -static u32 bcma_chipco_pll_read(struct bcma_drv_cc *cc, u32 offset)
383 +u32 bcma_chipco_pll_read(struct bcma_drv_cc *cc, u32 offset)
385 bcma_cc_write32(cc, BCMA_CC_PLLCTL_ADDR, offset);
386 bcma_cc_read32(cc, BCMA_CC_PLLCTL_ADDR);
387 return bcma_cc_read32(cc, BCMA_CC_PLLCTL_DATA);
389 +EXPORT_SYMBOL_GPL(bcma_chipco_pll_read);
391 void bcma_chipco_pll_write(struct bcma_drv_cc *cc, u32 offset, u32 value)
393 @@ -144,7 +145,7 @@ static void bcma_pmu_workarounds(struct
397 -void bcma_pmu_init(struct bcma_drv_cc *cc)
398 +void bcma_pmu_early_init(struct bcma_drv_cc *cc)
402 @@ -153,7 +154,10 @@ void bcma_pmu_init(struct bcma_drv_cc *c
404 bcma_debug(cc->core->bus, "Found rev %u PMU (capabilities 0x%08X)\n",
405 cc->pmu.rev, pmucap);
408 +void bcma_pmu_init(struct bcma_drv_cc *cc)
410 if (cc->pmu.rev == 1)
411 bcma_cc_mask32(cc, BCMA_CC_PMU_CTL,
412 ~BCMA_CC_PMU_CTL_NOILPONW);
413 @@ -165,7 +169,7 @@ void bcma_pmu_init(struct bcma_drv_cc *c
414 bcma_pmu_workarounds(cc);
417 -u32 bcma_pmu_alp_clock(struct bcma_drv_cc *cc)
418 +u32 bcma_pmu_get_alp_clock(struct bcma_drv_cc *cc)
420 struct bcma_bus *bus = cc->core->bus;
422 @@ -193,7 +197,7 @@ u32 bcma_pmu_alp_clock(struct bcma_drv_c
423 /* Find the output of the "m" pll divider given pll controls that start with
424 * pllreg "pll0" i.e. 12 for main 6 for phy, 0 for misc.
426 -static u32 bcma_pmu_clock(struct bcma_drv_cc *cc, u32 pll0, u32 m)
427 +static u32 bcma_pmu_pll_clock(struct bcma_drv_cc *cc, u32 pll0, u32 m)
429 u32 tmp, div, ndiv, p1, p2, fc;
430 struct bcma_bus *bus = cc->core->bus;
431 @@ -222,14 +226,14 @@ static u32 bcma_pmu_clock(struct bcma_dr
432 ndiv = (tmp & BCMA_CC_PPL_NDIV_MASK) >> BCMA_CC_PPL_NDIV_SHIFT;
434 /* Do calculation in Mhz */
435 - fc = bcma_pmu_alp_clock(cc) / 1000000;
436 + fc = bcma_pmu_get_alp_clock(cc) / 1000000;
437 fc = (p1 * ndiv * fc) / p2;
439 /* Return clock in Hertz */
440 return (fc / div) * 1000000;
443 -static u32 bcma_pmu_clock_bcm4706(struct bcma_drv_cc *cc, u32 pll0, u32 m)
444 +static u32 bcma_pmu_pll_clock_bcm4706(struct bcma_drv_cc *cc, u32 pll0, u32 m)
446 u32 tmp, ndiv, p1div, p2div;
448 @@ -260,7 +264,7 @@ static u32 bcma_pmu_clock_bcm4706(struct
451 /* query bus clock frequency for PMU-enabled chipcommon */
452 -static u32 bcma_pmu_get_clockcontrol(struct bcma_drv_cc *cc)
453 +static u32 bcma_pmu_get_bus_clock(struct bcma_drv_cc *cc)
455 struct bcma_bus *bus = cc->core->bus;
457 @@ -268,40 +272,42 @@ static u32 bcma_pmu_get_clockcontrol(str
458 case BCMA_CHIP_ID_BCM4716:
459 case BCMA_CHIP_ID_BCM4748:
460 case BCMA_CHIP_ID_BCM47162:
461 - return bcma_pmu_clock(cc, BCMA_CC_PMU4716_MAINPLL_PLL0,
462 - BCMA_CC_PMU5_MAINPLL_SSB);
463 + return bcma_pmu_pll_clock(cc, BCMA_CC_PMU4716_MAINPLL_PLL0,
464 + BCMA_CC_PMU5_MAINPLL_SSB);
465 case BCMA_CHIP_ID_BCM5356:
466 - return bcma_pmu_clock(cc, BCMA_CC_PMU5356_MAINPLL_PLL0,
467 - BCMA_CC_PMU5_MAINPLL_SSB);
468 + return bcma_pmu_pll_clock(cc, BCMA_CC_PMU5356_MAINPLL_PLL0,
469 + BCMA_CC_PMU5_MAINPLL_SSB);
470 case BCMA_CHIP_ID_BCM5357:
471 case BCMA_CHIP_ID_BCM4749:
472 - return bcma_pmu_clock(cc, BCMA_CC_PMU5357_MAINPLL_PLL0,
473 - BCMA_CC_PMU5_MAINPLL_SSB);
474 + return bcma_pmu_pll_clock(cc, BCMA_CC_PMU5357_MAINPLL_PLL0,
475 + BCMA_CC_PMU5_MAINPLL_SSB);
476 case BCMA_CHIP_ID_BCM4706:
477 - return bcma_pmu_clock_bcm4706(cc, BCMA_CC_PMU4706_MAINPLL_PLL0,
478 - BCMA_CC_PMU5_MAINPLL_SSB);
479 + return bcma_pmu_pll_clock_bcm4706(cc,
480 + BCMA_CC_PMU4706_MAINPLL_PLL0,
481 + BCMA_CC_PMU5_MAINPLL_SSB);
482 case BCMA_CHIP_ID_BCM53572:
485 - bcma_warn(bus, "No backplane clock specified for %04X device, pmu rev. %d, using default %d Hz\n",
486 + bcma_warn(bus, "No bus clock specified for %04X device, pmu rev. %d, using default %d Hz\n",
487 bus->chipinfo.id, cc->pmu.rev, BCMA_CC_PMU_HT_CLOCK);
489 return BCMA_CC_PMU_HT_CLOCK;
492 /* query cpu clock frequency for PMU-enabled chipcommon */
493 -u32 bcma_pmu_get_clockcpu(struct bcma_drv_cc *cc)
494 +u32 bcma_pmu_get_cpu_clock(struct bcma_drv_cc *cc)
496 struct bcma_bus *bus = cc->core->bus;
498 if (bus->chipinfo.id == BCMA_CHIP_ID_BCM53572)
501 + /* New PMUs can have different clock for bus and CPU */
502 if (cc->pmu.rev >= 5) {
504 switch (bus->chipinfo.id) {
505 case BCMA_CHIP_ID_BCM4706:
506 - return bcma_pmu_clock_bcm4706(cc,
507 + return bcma_pmu_pll_clock_bcm4706(cc,
508 BCMA_CC_PMU4706_MAINPLL_PLL0,
509 BCMA_CC_PMU5_MAINPLL_CPU);
510 case BCMA_CHIP_ID_BCM5356:
511 @@ -316,10 +322,11 @@ u32 bcma_pmu_get_clockcpu(struct bcma_dr
515 - return bcma_pmu_clock(cc, pll, BCMA_CC_PMU5_MAINPLL_CPU);
516 + return bcma_pmu_pll_clock(cc, pll, BCMA_CC_PMU5_MAINPLL_CPU);
519 - return bcma_pmu_get_clockcontrol(cc);
520 + /* On old PMUs CPU has the same clock as the bus */
521 + return bcma_pmu_get_bus_clock(cc);
524 static void bcma_pmu_spuravoid_pll_write(struct bcma_drv_cc *cc, u32 offset,
525 --- a/drivers/bcma/driver_chipcommon_sflash.c
526 +++ b/drivers/bcma/driver_chipcommon_sflash.c
529 static struct resource bcma_sflash_resource = {
530 .name = "bcma_sflash",
531 - .start = BCMA_SFLASH,
532 + .start = BCMA_SOC_FLASH2,
534 .flags = IORESOURCE_MEM | IORESOURCE_READONLY,
536 @@ -31,15 +31,42 @@ struct bcma_sflash_tbl_e {
539 static struct bcma_sflash_tbl_e bcma_sflash_st_tbl[] = {
540 - { "", 0x14, 0x10000, 32, },
541 + { "M25P20", 0x11, 0x10000, 4, },
542 + { "M25P40", 0x12, 0x10000, 8, },
544 + { "M25P16", 0x14, 0x10000, 32, },
545 + { "M25P32", 0x15, 0x10000, 64, },
546 + { "M25P64", 0x16, 0x10000, 128, },
547 + { "M25FL128", 0x17, 0x10000, 256, },
551 static struct bcma_sflash_tbl_e bcma_sflash_sst_tbl[] = {
552 + { "SST25WF512", 1, 0x1000, 16, },
553 + { "SST25VF512", 0x48, 0x1000, 16, },
554 + { "SST25WF010", 2, 0x1000, 32, },
555 + { "SST25VF010", 0x49, 0x1000, 32, },
556 + { "SST25WF020", 3, 0x1000, 64, },
557 + { "SST25VF020", 0x43, 0x1000, 64, },
558 + { "SST25WF040", 4, 0x1000, 128, },
559 + { "SST25VF040", 0x44, 0x1000, 128, },
560 + { "SST25VF040B", 0x8d, 0x1000, 128, },
561 + { "SST25WF080", 5, 0x1000, 256, },
562 + { "SST25VF080B", 0x8e, 0x1000, 256, },
563 + { "SST25VF016", 0x41, 0x1000, 512, },
564 + { "SST25VF032", 0x4a, 0x1000, 1024, },
565 + { "SST25VF064", 0x4b, 0x1000, 2048, },
569 static struct bcma_sflash_tbl_e bcma_sflash_at_tbl[] = {
570 + { "AT45DB011", 0xc, 256, 512, },
571 + { "AT45DB021", 0x14, 256, 1024, },
572 + { "AT45DB041", 0x1c, 256, 2048, },
573 + { "AT45DB081", 0x24, 256, 4096, },
574 + { "AT45DB161", 0x2c, 512, 4096, },
575 + { "AT45DB321", 0x34, 512, 8192, },
576 + { "AT45DB642", 0x3c, 1024, 8192, },
580 @@ -84,6 +111,8 @@ int bcma_sflash_init(struct bcma_drv_cc
587 for (e = bcma_sflash_st_tbl; e->name; e++) {
589 @@ -116,7 +145,7 @@ int bcma_sflash_init(struct bcma_drv_cc
593 - sflash->window = BCMA_SFLASH;
594 + sflash->window = BCMA_SOC_FLASH2;
595 sflash->blocksize = e->blocksize;
596 sflash->numblocks = e->numblocks;
597 sflash->size = sflash->blocksize * sflash->numblocks;
599 +++ b/drivers/bcma/driver_gpio.c
602 + * Broadcom specific AMBA
605 + * Copyright 2011, Broadcom Corporation
606 + * Copyright 2012, Hauke Mehrtens <hauke@hauke-m.de>
608 + * Licensed under the GNU/GPL. See COPYING for details.
611 +#include <linux/gpio.h>
612 +#include <linux/export.h>
613 +#include <linux/bcma/bcma.h>
615 +#include "bcma_private.h"
617 +static inline struct bcma_drv_cc *bcma_gpio_get_cc(struct gpio_chip *chip)
619 + return container_of(chip, struct bcma_drv_cc, gpio);
622 +static int bcma_gpio_get_value(struct gpio_chip *chip, unsigned gpio)
624 + struct bcma_drv_cc *cc = bcma_gpio_get_cc(chip);
626 + return !!bcma_chipco_gpio_in(cc, 1 << gpio);
629 +static void bcma_gpio_set_value(struct gpio_chip *chip, unsigned gpio,
632 + struct bcma_drv_cc *cc = bcma_gpio_get_cc(chip);
634 + bcma_chipco_gpio_out(cc, 1 << gpio, value ? 1 << gpio : 0);
637 +static int bcma_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
639 + struct bcma_drv_cc *cc = bcma_gpio_get_cc(chip);
641 + bcma_chipco_gpio_outen(cc, 1 << gpio, 0);
645 +static int bcma_gpio_direction_output(struct gpio_chip *chip, unsigned gpio,
648 + struct bcma_drv_cc *cc = bcma_gpio_get_cc(chip);
650 + bcma_chipco_gpio_outen(cc, 1 << gpio, 1 << gpio);
651 + bcma_chipco_gpio_out(cc, 1 << gpio, value ? 1 << gpio : 0);
655 +static int bcma_gpio_request(struct gpio_chip *chip, unsigned gpio)
657 + struct bcma_drv_cc *cc = bcma_gpio_get_cc(chip);
659 + bcma_chipco_gpio_control(cc, 1 << gpio, 0);
660 + /* clear pulldown */
661 + bcma_chipco_gpio_pulldown(cc, 1 << gpio, 0);
663 + bcma_chipco_gpio_pullup(cc, 1 << gpio, 1 << gpio);
668 +static void bcma_gpio_free(struct gpio_chip *chip, unsigned gpio)
670 + struct bcma_drv_cc *cc = bcma_gpio_get_cc(chip);
673 + bcma_chipco_gpio_pullup(cc, 1 << gpio, 0);
676 +int bcma_gpio_init(struct bcma_drv_cc *cc)
678 + struct gpio_chip *chip = &cc->gpio;
680 + chip->label = "bcma_gpio";
681 + chip->owner = THIS_MODULE;
682 + chip->request = bcma_gpio_request;
683 + chip->free = bcma_gpio_free;
684 + chip->get = bcma_gpio_get_value;
685 + chip->set = bcma_gpio_set_value;
686 + chip->direction_input = bcma_gpio_direction_input;
687 + chip->direction_output = bcma_gpio_direction_output;
689 + /* There is just one SoC in one device and its GPIO addresses should be
690 + * deterministic to address them more easily. The other buses could get
691 + * a random base number. */
692 + if (cc->core->bus->hosttype == BCMA_HOSTTYPE_SOC)
697 + return gpiochip_add(chip);
699 --- a/drivers/bcma/driver_mips.c
700 +++ b/drivers/bcma/driver_mips.c
701 @@ -74,11 +74,16 @@ static u32 bcma_core_mips_irqflag(struct
702 return dev->core_index;
703 flag = bcma_aread32(dev, BCMA_MIPS_OOBSELOUTA30);
705 - return flag & 0x1F;
707 + return flag & 0x1F;
712 /* Get the MIPS IRQ assignment for a specified device.
713 * If unassigned, 0 is returned.
714 + * If disabled, 5 is returned.
715 + * If not supported, 6 is returned.
717 unsigned int bcma_core_mips_irq(struct bcma_device *dev)
719 @@ -87,13 +92,15 @@ unsigned int bcma_core_mips_irq(struct b
722 irqflag = bcma_core_mips_irqflag(dev);
723 + if (irqflag == 0x3f)
726 - for (irq = 1; irq <= 4; irq++)
727 + for (irq = 0; irq <= 4; irq++)
728 if (bcma_read32(mdev, BCMA_MIPS_MIPS74K_INTMASK(irq)) &
735 EXPORT_SYMBOL(bcma_core_mips_irq);
737 @@ -114,7 +121,7 @@ static void bcma_core_mips_set_irq(struc
738 bcma_write32(mdev, BCMA_MIPS_MIPS74K_INTMASK(0),
739 bcma_read32(mdev, BCMA_MIPS_MIPS74K_INTMASK(0)) &
742 + else if (oldirq != 5)
743 bcma_write32(mdev, BCMA_MIPS_MIPS74K_INTMASK(oldirq), 0);
745 /* assign the new one */
746 @@ -123,9 +130,9 @@ static void bcma_core_mips_set_irq(struc
747 bcma_read32(mdev, BCMA_MIPS_MIPS74K_INTMASK(0)) |
750 - u32 oldirqflag = bcma_read32(mdev,
751 - BCMA_MIPS_MIPS74K_INTMASK(irq));
753 + u32 irqinitmask = bcma_read32(mdev,
754 + BCMA_MIPS_MIPS74K_INTMASK(irq));
756 struct bcma_device *core;
758 /* backplane irq line is in use, find out who uses
759 @@ -133,7 +140,7 @@ static void bcma_core_mips_set_irq(struc
761 list_for_each_entry(core, &bus->cores, list) {
762 if ((1 << bcma_core_mips_irqflag(core)) ==
765 bcma_core_mips_set_irq(core, 0);
768 @@ -143,15 +150,31 @@ static void bcma_core_mips_set_irq(struc
772 - bcma_info(bus, "set_irq: core 0x%04x, irq %d => %d\n",
773 - dev->id.id, oldirq + 2, irq + 2);
774 + bcma_debug(bus, "set_irq: core 0x%04x, irq %d => %d\n",
775 + dev->id.id, oldirq <= 4 ? oldirq + 2 : 0, irq + 2);
778 +static void bcma_core_mips_set_irq_name(struct bcma_bus *bus, unsigned int irq,
779 + u16 coreid, u8 unit)
781 + struct bcma_device *core;
783 + core = bcma_find_core_unit(bus, coreid, unit);
786 + "Can not find core (id: 0x%x, unit %i) for IRQ configuration.\n",
791 + bcma_core_mips_set_irq(core, irq);
794 static void bcma_core_mips_print_irq(struct bcma_device *dev, unsigned int irq)
797 static const char *irq_name[] = {"2(S)", "3", "4", "5", "6", "D", "I"};
798 - printk(KERN_INFO KBUILD_MODNAME ": core 0x%04x, irq :", dev->id.id);
799 + printk(KERN_DEBUG KBUILD_MODNAME ": core 0x%04x, irq :", dev->id.id);
800 for (i = 0; i <= 6; i++)
801 printk(" %s%s", irq_name[i], i == irq ? "*" : " ");
803 @@ -171,7 +194,7 @@ u32 bcma_cpu_clock(struct bcma_drv_mips
804 struct bcma_bus *bus = mcore->core->bus;
806 if (bus->drv_cc.capabilities & BCMA_CC_CAP_PMU)
807 - return bcma_pmu_get_clockcpu(&bus->drv_cc);
808 + return bcma_pmu_get_cpu_clock(&bus->drv_cc);
810 bcma_err(bus, "No PMU available, need this to get the cpu clock\n");
812 @@ -181,85 +204,109 @@ EXPORT_SYMBOL(bcma_cpu_clock);
813 static void bcma_core_mips_flash_detect(struct bcma_drv_mips *mcore)
815 struct bcma_bus *bus = mcore->core->bus;
816 + struct bcma_drv_cc *cc = &bus->drv_cc;
818 - switch (bus->drv_cc.capabilities & BCMA_CC_CAP_FLASHT) {
819 + switch (cc->capabilities & BCMA_CC_CAP_FLASHT) {
820 case BCMA_CC_FLASHT_STSER:
821 case BCMA_CC_FLASHT_ATSER:
822 bcma_debug(bus, "Found serial flash\n");
823 - bcma_sflash_init(&bus->drv_cc);
824 + bcma_sflash_init(cc);
826 case BCMA_CC_FLASHT_PARA:
827 bcma_debug(bus, "Found parallel flash\n");
828 - bus->drv_cc.pflash.window = 0x1c000000;
829 - bus->drv_cc.pflash.window_size = 0x02000000;
830 + cc->pflash.present = true;
831 + cc->pflash.window = BCMA_SOC_FLASH2;
832 + cc->pflash.window_size = BCMA_SOC_FLASH2_SZ;
834 - if ((bcma_read32(bus->drv_cc.core, BCMA_CC_FLASH_CFG) &
835 + if ((bcma_read32(cc->core, BCMA_CC_FLASH_CFG) &
836 BCMA_CC_FLASH_CFG_DS) == 0)
837 - bus->drv_cc.pflash.buswidth = 1;
838 + cc->pflash.buswidth = 1;
840 - bus->drv_cc.pflash.buswidth = 2;
841 + cc->pflash.buswidth = 2;
844 bcma_err(bus, "Flash type not supported\n");
847 - if (bus->drv_cc.core->id.rev == 38 ||
848 + if (cc->core->id.rev == 38 ||
849 bus->chipinfo.id == BCMA_CHIP_ID_BCM4706) {
850 - if (bus->drv_cc.capabilities & BCMA_CC_CAP_NFLASH) {
851 + if (cc->capabilities & BCMA_CC_CAP_NFLASH) {
852 bcma_debug(bus, "Found NAND flash\n");
853 - bcma_nflash_init(&bus->drv_cc);
854 + bcma_nflash_init(cc);
859 +void bcma_core_mips_early_init(struct bcma_drv_mips *mcore)
861 + struct bcma_bus *bus = mcore->core->bus;
863 + if (mcore->early_setup_done)
866 + bcma_chipco_serial_init(&bus->drv_cc);
867 + bcma_core_mips_flash_detect(mcore);
869 + mcore->early_setup_done = true;
872 void bcma_core_mips_init(struct bcma_drv_mips *mcore)
874 struct bcma_bus *bus;
875 struct bcma_device *core;
876 bus = mcore->core->bus;
878 - bcma_info(bus, "Initializing MIPS core...\n");
879 + if (mcore->setup_done)
882 - if (!mcore->setup_done)
883 - mcore->assigned_irqs = 1;
884 + bcma_debug(bus, "Initializing MIPS core...\n");
886 - /* Assign IRQs to all cores on the bus */
887 - list_for_each_entry(core, &bus->cores, list) {
892 - mips_irq = bcma_core_mips_irq(core);
896 - core->irq = mips_irq + 2;
899 - switch (core->id.id) {
900 - case BCMA_CORE_PCI:
901 - case BCMA_CORE_PCIE:
902 - case BCMA_CORE_ETHERNET:
903 - case BCMA_CORE_ETHERNET_GBIT:
904 - case BCMA_CORE_MAC_GBIT:
905 - case BCMA_CORE_80211:
906 - case BCMA_CORE_USB20_HOST:
907 - /* These devices get their own IRQ line if available,
908 - * the rest goes on IRQ0
910 - if (mcore->assigned_irqs <= 4)
911 - bcma_core_mips_set_irq(core,
912 - mcore->assigned_irqs++);
914 + bcma_core_mips_early_init(mcore);
916 + switch (bus->chipinfo.id) {
917 + case BCMA_CHIP_ID_BCM4716:
918 + case BCMA_CHIP_ID_BCM4748:
919 + bcma_core_mips_set_irq_name(bus, 1, BCMA_CORE_80211, 0);
920 + bcma_core_mips_set_irq_name(bus, 2, BCMA_CORE_MAC_GBIT, 0);
921 + bcma_core_mips_set_irq_name(bus, 3, BCMA_CORE_USB20_HOST, 0);
922 + bcma_core_mips_set_irq_name(bus, 4, BCMA_CORE_PCIE, 0);
923 + bcma_core_mips_set_irq_name(bus, 0, BCMA_CORE_CHIPCOMMON, 0);
924 + bcma_core_mips_set_irq_name(bus, 0, BCMA_CORE_I2S, 0);
926 + case BCMA_CHIP_ID_BCM5356:
927 + case BCMA_CHIP_ID_BCM47162:
928 + case BCMA_CHIP_ID_BCM53572:
929 + bcma_core_mips_set_irq_name(bus, 1, BCMA_CORE_80211, 0);
930 + bcma_core_mips_set_irq_name(bus, 2, BCMA_CORE_MAC_GBIT, 0);
931 + bcma_core_mips_set_irq_name(bus, 0, BCMA_CORE_CHIPCOMMON, 0);
933 + case BCMA_CHIP_ID_BCM5357:
934 + case BCMA_CHIP_ID_BCM4749:
935 + bcma_core_mips_set_irq_name(bus, 1, BCMA_CORE_80211, 0);
936 + bcma_core_mips_set_irq_name(bus, 2, BCMA_CORE_MAC_GBIT, 0);
937 + bcma_core_mips_set_irq_name(bus, 3, BCMA_CORE_USB20_HOST, 0);
938 + bcma_core_mips_set_irq_name(bus, 0, BCMA_CORE_CHIPCOMMON, 0);
939 + bcma_core_mips_set_irq_name(bus, 0, BCMA_CORE_I2S, 0);
941 + case BCMA_CHIP_ID_BCM4706:
942 + bcma_core_mips_set_irq_name(bus, 1, BCMA_CORE_PCIE, 0);
943 + bcma_core_mips_set_irq_name(bus, 2, BCMA_CORE_4706_MAC_GBIT,
945 + bcma_core_mips_set_irq_name(bus, 3, BCMA_CORE_PCIE, 1);
946 + bcma_core_mips_set_irq_name(bus, 4, BCMA_CORE_USB20_HOST, 0);
947 + bcma_core_mips_set_irq_name(bus, 0, BCMA_CORE_4706_CHIPCOMMON,
951 + list_for_each_entry(core, &bus->cores, list) {
952 + core->irq = bcma_core_mips_irq(core) + 2;
955 + "Unknown device (0x%x) found, can not configure IRQs\n",
958 - bcma_info(bus, "IRQ reconfiguration done\n");
959 + bcma_debug(bus, "IRQ reconfiguration done\n");
960 bcma_core_mips_dump_irq(bus);
962 - if (mcore->setup_done)
965 - bcma_chipco_serial_init(&bus->drv_cc);
966 - bcma_core_mips_flash_detect(mcore);
967 mcore->setup_done = true;
969 --- a/drivers/bcma/driver_pci_host.c
970 +++ b/drivers/bcma/driver_pci_host.c
971 @@ -35,11 +35,6 @@ bool __devinit bcma_core_pci_is_in_hostm
972 chipid_top != 0x5300)
975 - if (bus->sprom.boardflags_lo & BCMA_CORE_PCI_BFL_NOPCI) {
976 - bcma_info(bus, "This PCI core is disabled and not working\n");
980 bcma_core_enable(pc->core, 0);
982 return !mips_busprobe32(tmp, pc->core->io_addr);
983 @@ -396,6 +391,11 @@ void __devinit bcma_core_pci_hostmode_in
985 bcma_info(bus, "PCIEcore in host mode found\n");
987 + if (bus->sprom.boardflags_lo & BCMA_CORE_PCI_BFL_NOPCI) {
988 + bcma_info(bus, "This PCIE core is disabled and not working\n");
992 pc_host = kzalloc(sizeof(*pc_host), GFP_KERNEL);
994 bcma_err(bus, "can not allocate memory");
995 @@ -452,6 +452,8 @@ void __devinit bcma_core_pci_hostmode_in
996 pc_host->mem_resource.start = BCMA_SOC_PCI_MEM;
997 pc_host->mem_resource.end = BCMA_SOC_PCI_MEM +
998 BCMA_SOC_PCI_MEM_SZ - 1;
999 + pc_host->io_resource.start = 0x100;
1000 + pc_host->io_resource.end = 0x47F;
1001 pci_membase_1G = BCMA_SOC_PCIE_DMA_H32;
1002 pcicore_write32(pc, BCMA_CORE_PCI_SBTOPCI0,
1003 tmp | BCMA_SOC_PCI_MEM);
1004 @@ -459,6 +461,8 @@ void __devinit bcma_core_pci_hostmode_in
1005 pc_host->mem_resource.start = BCMA_SOC_PCI1_MEM;
1006 pc_host->mem_resource.end = BCMA_SOC_PCI1_MEM +
1007 BCMA_SOC_PCI_MEM_SZ - 1;
1008 + pc_host->io_resource.start = 0x480;
1009 + pc_host->io_resource.end = 0x7FF;
1010 pci_membase_1G = BCMA_SOC_PCIE1_DMA_H32;
1011 pc_host->host_cfg_addr = BCMA_SOC_PCI1_CFG;
1012 pcicore_write32(pc, BCMA_CORE_PCI_SBTOPCI0,
1013 @@ -534,7 +538,7 @@ DECLARE_PCI_FIXUP_EARLY(PCI_ANY_ID, PCI_
1014 static void bcma_core_pci_fixup_addresses(struct pci_dev *dev)
1016 struct resource *res;
1020 if (dev->bus->ops->read != bcma_core_pci_hostmode_read_config) {
1021 /* This is not a device on the PCI-core bridge. */
1022 @@ -547,8 +551,12 @@ static void bcma_core_pci_fixup_addresse
1024 for (pos = 0; pos < 6; pos++) {
1025 res = &dev->resource[pos];
1026 - if (res->flags & (IORESOURCE_IO | IORESOURCE_MEM))
1027 - pci_assign_resource(dev, pos);
1028 + if (res->flags & (IORESOURCE_IO | IORESOURCE_MEM)) {
1029 + err = pci_assign_resource(dev, pos);
1031 + pr_err("PCI: Problem fixing up the addresses on %s\n",
1036 DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, bcma_core_pci_fixup_addresses);
1037 --- a/drivers/bcma/host_pci.c
1038 +++ b/drivers/bcma/host_pci.c
1039 @@ -238,7 +238,7 @@ static void __devexit bcma_host_pci_remo
1040 pci_set_drvdata(dev, NULL);
1044 +#ifdef CONFIG_PM_SLEEP
1045 static int bcma_host_pci_suspend(struct device *dev)
1047 struct pci_dev *pdev = to_pci_dev(dev);
1048 @@ -261,11 +261,11 @@ static SIMPLE_DEV_PM_OPS(bcma_pm_ops, bc
1049 bcma_host_pci_resume);
1050 #define BCMA_PM_OPS (&bcma_pm_ops)
1052 -#else /* CONFIG_PM */
1053 +#else /* CONFIG_PM_SLEEP */
1055 #define BCMA_PM_OPS NULL
1057 -#endif /* CONFIG_PM */
1058 +#endif /* CONFIG_PM_SLEEP */
1060 static DEFINE_PCI_DEVICE_TABLE(bcma_pci_bridge_tbl) = {
1061 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x0576) },
1062 --- a/drivers/bcma/main.c
1063 +++ b/drivers/bcma/main.c
1064 @@ -81,6 +81,18 @@ struct bcma_device *bcma_find_core(struc
1066 EXPORT_SYMBOL_GPL(bcma_find_core);
1068 +struct bcma_device *bcma_find_core_unit(struct bcma_bus *bus, u16 coreid,
1071 + struct bcma_device *core;
1073 + list_for_each_entry(core, &bus->cores, list) {
1074 + if (core->id.id == coreid && core->core_unit == unit)
1080 static void bcma_release_core_dev(struct device *dev)
1082 struct bcma_device *core = container_of(dev, struct bcma_device, dev);
1083 @@ -152,6 +164,17 @@ static int bcma_register_cores(struct bc
1084 bcma_err(bus, "Error registering NAND flash\n");
1087 + err = bcma_gpio_init(&bus->drv_cc);
1088 + if (err == -ENOTSUPP)
1089 + bcma_debug(bus, "GPIO driver not activated\n");
1091 + bcma_err(bus, "Error registering GPIO driver: %i\n", err);
1093 + if (bus->hosttype == BCMA_HOSTTYPE_SOC) {
1094 + err = bcma_chipco_watchdog_register(&bus->drv_cc);
1096 + bcma_err(bus, "Error registering watchdog driver\n");
1101 @@ -165,6 +188,8 @@ static void bcma_unregister_cores(struct
1102 if (core->dev_registered)
1103 device_unregister(&core->dev);
1105 + if (bus->hosttype == BCMA_HOSTTYPE_SOC)
1106 + platform_device_unregister(bus->drv_cc.watchdog);
1109 int __devinit bcma_bus_register(struct bcma_bus *bus)
1110 @@ -183,6 +208,20 @@ int __devinit bcma_bus_register(struct b
1114 + /* Early init CC core */
1115 + core = bcma_find_core(bus, bcma_cc_core_id(bus));
1117 + bus->drv_cc.core = core;
1118 + bcma_core_chipcommon_early_init(&bus->drv_cc);
1121 + /* Try to get SPROM */
1122 + err = bcma_sprom_get(bus);
1123 + if (err == -ENOENT) {
1124 + bcma_err(bus, "No SPROM available\n");
1126 + bcma_err(bus, "Failed to get SPROM: %d\n", err);
1129 core = bcma_find_core(bus, bcma_cc_core_id(bus));
1131 @@ -198,10 +237,17 @@ int __devinit bcma_bus_register(struct b
1134 /* Init PCIE core */
1135 - core = bcma_find_core(bus, BCMA_CORE_PCIE);
1136 + core = bcma_find_core_unit(bus, BCMA_CORE_PCIE, 0);
1138 - bus->drv_pci.core = core;
1139 - bcma_core_pci_init(&bus->drv_pci);
1140 + bus->drv_pci[0].core = core;
1141 + bcma_core_pci_init(&bus->drv_pci[0]);
1144 + /* Init PCIE core */
1145 + core = bcma_find_core_unit(bus, BCMA_CORE_PCIE, 1);
1147 + bus->drv_pci[1].core = core;
1148 + bcma_core_pci_init(&bus->drv_pci[1]);
1151 /* Init GBIT MAC COMMON core */
1152 @@ -211,13 +257,6 @@ int __devinit bcma_bus_register(struct b
1153 bcma_core_gmac_cmn_init(&bus->drv_gmac_cmn);
1156 - /* Try to get SPROM */
1157 - err = bcma_sprom_get(bus);
1158 - if (err == -ENOENT) {
1159 - bcma_err(bus, "No SPROM available\n");
1161 - bcma_err(bus, "Failed to get SPROM: %d\n", err);
1163 /* Register found cores */
1164 bcma_register_cores(bus);
1166 @@ -275,18 +314,18 @@ int __init bcma_bus_early_register(struc
1170 - /* Init CC core */
1171 + /* Early init CC core */
1172 core = bcma_find_core(bus, bcma_cc_core_id(bus));
1174 bus->drv_cc.core = core;
1175 - bcma_core_chipcommon_init(&bus->drv_cc);
1176 + bcma_core_chipcommon_early_init(&bus->drv_cc);
1179 - /* Init MIPS core */
1180 + /* Early init MIPS core */
1181 core = bcma_find_core(bus, BCMA_CORE_MIPS_74K);
1183 bus->drv_mips.core = core;
1184 - bcma_core_mips_init(&bus->drv_mips);
1185 + bcma_core_mips_early_init(&bus->drv_mips);
1188 bcma_info(bus, "Early bus registered\n");
1189 --- a/drivers/bcma/sprom.c
1190 +++ b/drivers/bcma/sprom.c
1191 @@ -595,8 +595,11 @@ int bcma_sprom_get(struct bcma_bus *bus)
1192 bcma_chipco_bcm4331_ext_pa_lines_ctl(&bus->drv_cc, true);
1194 err = bcma_sprom_valid(sprom);
1197 + bcma_warn(bus, "invalid sprom read from the PCIe card, try to use fallback sprom\n");
1198 + err = bcma_fill_sprom_with_fallback(bus, &bus->sprom);
1202 bcma_sprom_extract_r8(bus, sprom);
1204 --- a/include/linux/bcma/bcma.h
1205 +++ b/include/linux/bcma/bcma.h
1206 @@ -157,6 +157,7 @@ struct bcma_host_ops {
1208 /* Chip IDs of SoCs */
1209 #define BCMA_CHIP_ID_BCM4706 0x5300
1210 +#define BCMA_PKG_ID_BCM4706L 1
1211 #define BCMA_CHIP_ID_BCM4716 0x4716
1212 #define BCMA_PKG_ID_BCM4716 8
1213 #define BCMA_PKG_ID_BCM4717 9
1214 @@ -166,7 +167,11 @@ struct bcma_host_ops {
1215 #define BCMA_CHIP_ID_BCM4749 0x4749
1216 #define BCMA_CHIP_ID_BCM5356 0x5356
1217 #define BCMA_CHIP_ID_BCM5357 0x5357
1218 +#define BCMA_PKG_ID_BCM5358 9
1219 +#define BCMA_PKG_ID_BCM47186 10
1220 +#define BCMA_PKG_ID_BCM5357 11
1221 #define BCMA_CHIP_ID_BCM53572 53572
1222 +#define BCMA_PKG_ID_BCM47188 9
1224 struct bcma_device {
1225 struct bcma_bus *bus;
1226 @@ -251,7 +256,7 @@ struct bcma_bus {
1229 struct bcma_drv_cc drv_cc;
1230 - struct bcma_drv_pci drv_pci;
1231 + struct bcma_drv_pci drv_pci[2];
1232 struct bcma_drv_mips drv_mips;
1233 struct bcma_drv_gmac_cmn drv_gmac_cmn;
1235 @@ -345,6 +350,7 @@ extern void bcma_core_set_clockmode(stru
1236 enum bcma_clkmode clkmode);
1237 extern void bcma_core_pll_ctl(struct bcma_device *core, u32 req, u32 status,
1239 +extern u32 bcma_chipco_pll_read(struct bcma_drv_cc *cc, u32 offset);
1240 #define BCMA_DMA_TRANSLATION_MASK 0xC0000000
1241 #define BCMA_DMA_TRANSLATION_NONE 0x00000000
1242 #define BCMA_DMA_TRANSLATION_DMA32_CMT 0x40000000 /* Client Mode Translation for 32-bit DMA */
1243 --- a/include/linux/bcma/bcma_driver_chipcommon.h
1244 +++ b/include/linux/bcma/bcma_driver_chipcommon.h
1246 #ifndef LINUX_BCMA_DRIVER_CC_H_
1247 #define LINUX_BCMA_DRIVER_CC_H_
1249 +#include <linux/platform_device.h>
1250 +#include <linux/gpio.h>
1252 /** ChipCommon core registers. **/
1253 #define BCMA_CC_ID 0x0000
1254 #define BCMA_CC_ID_ID 0x0000FFFF
1255 @@ -510,6 +513,7 @@ struct bcma_chipcommon_pmu {
1257 #ifdef CONFIG_BCMA_DRIVER_MIPS
1258 struct bcma_pflash {
1263 @@ -532,6 +536,7 @@ struct mtd_info;
1265 struct bcma_nflash {
1267 + bool boot; /* This is the flash the SoC boots from */
1269 struct mtd_info *mtd;
1271 @@ -552,6 +557,7 @@ struct bcma_drv_cc {
1273 u32 capabilities_ext;
1275 + u8 early_setup_done:1;
1276 /* Fast Powerup Delay constant */
1277 u16 fast_pwrup_delay;
1278 struct bcma_chipcommon_pmu pmu;
1279 @@ -567,6 +573,14 @@ struct bcma_drv_cc {
1280 int nr_serial_ports;
1281 struct bcma_serial_port serial_ports[4];
1282 #endif /* CONFIG_BCMA_DRIVER_MIPS */
1284 + struct platform_device *watchdog;
1286 + /* Lock for GPIO register access. */
1287 + spinlock_t gpio_lock;
1288 +#ifdef CONFIG_BCMA_DRIVER_GPIO
1289 + struct gpio_chip gpio;
1293 /* Register access */
1294 @@ -583,14 +597,14 @@ struct bcma_drv_cc {
1295 bcma_cc_write32(cc, offset, (bcma_cc_read32(cc, offset) & (mask)) | (set))
1297 extern void bcma_core_chipcommon_init(struct bcma_drv_cc *cc);
1298 +extern void bcma_core_chipcommon_early_init(struct bcma_drv_cc *cc);
1300 extern void bcma_chipco_suspend(struct bcma_drv_cc *cc);
1301 extern void bcma_chipco_resume(struct bcma_drv_cc *cc);
1303 void bcma_chipco_bcm4331_ext_pa_lines_ctl(struct bcma_drv_cc *cc, bool enable);
1305 -extern void bcma_chipco_watchdog_timer_set(struct bcma_drv_cc *cc,
1307 +extern u32 bcma_chipco_watchdog_timer_set(struct bcma_drv_cc *cc, u32 ticks);
1309 void bcma_chipco_irq_mask(struct bcma_drv_cc *cc, u32 mask, u32 value);
1311 @@ -603,9 +617,12 @@ u32 bcma_chipco_gpio_outen(struct bcma_d
1312 u32 bcma_chipco_gpio_control(struct bcma_drv_cc *cc, u32 mask, u32 value);
1313 u32 bcma_chipco_gpio_intmask(struct bcma_drv_cc *cc, u32 mask, u32 value);
1314 u32 bcma_chipco_gpio_polarity(struct bcma_drv_cc *cc, u32 mask, u32 value);
1315 +u32 bcma_chipco_gpio_pullup(struct bcma_drv_cc *cc, u32 mask, u32 value);
1316 +u32 bcma_chipco_gpio_pulldown(struct bcma_drv_cc *cc, u32 mask, u32 value);
1319 extern void bcma_pmu_init(struct bcma_drv_cc *cc);
1320 +extern void bcma_pmu_early_init(struct bcma_drv_cc *cc);
1322 extern void bcma_chipco_pll_write(struct bcma_drv_cc *cc, u32 offset,
1324 --- a/include/linux/bcma/bcma_driver_mips.h
1325 +++ b/include/linux/bcma/bcma_driver_mips.h
1326 @@ -35,13 +35,15 @@ struct bcma_device;
1327 struct bcma_drv_mips {
1328 struct bcma_device *core;
1330 - unsigned int assigned_irqs;
1331 + u8 early_setup_done:1;
1334 #ifdef CONFIG_BCMA_DRIVER_MIPS
1335 extern void bcma_core_mips_init(struct bcma_drv_mips *mcore);
1336 +extern void bcma_core_mips_early_init(struct bcma_drv_mips *mcore);
1338 static inline void bcma_core_mips_init(struct bcma_drv_mips *mcore) { }
1339 +static inline void bcma_core_mips_early_init(struct bcma_drv_mips *mcore) { }
1342 extern u32 bcma_cpu_clock(struct bcma_drv_mips *mcore);
1343 --- a/include/linux/bcma/bcma_regs.h
1344 +++ b/include/linux/bcma/bcma_regs.h
1346 * (2 ZettaBytes), high 32 bits
1349 -#define BCMA_SFLASH 0x1c000000
1350 +#define BCMA_SOC_FLASH1 0x1fc00000 /* MIPS Flash Region 1 */
1351 +#define BCMA_SOC_FLASH1_SZ 0x00400000 /* MIPS Size of Flash Region 1 */
1352 +#define BCMA_SOC_FLASH2 0x1c000000 /* Flash Region 2 (region 1 shadowed here) */
1353 +#define BCMA_SOC_FLASH2_SZ 0x02000000 /* Size of Flash Region 2 */
1355 #endif /* LINUX_BCMA_REGS_H_ */
1356 --- a/drivers/net/wireless/b43/main.c
1357 +++ b/drivers/net/wireless/b43/main.c
1358 @@ -4684,7 +4684,7 @@ static int b43_wireless_core_init(struct
1359 switch (dev->dev->bus_type) {
1360 #ifdef CONFIG_B43_BCMA
1362 - bcma_core_pci_irq_ctl(&dev->dev->bdev->bus->drv_pci,
1363 + bcma_core_pci_irq_ctl(&dev->dev->bdev->bus->drv_pci[0],
1364 dev->dev->bdev, true);
1367 --- a/drivers/net/wireless/brcm80211/brcmsmac/aiutils.c
1368 +++ b/drivers/net/wireless/brcm80211/brcmsmac/aiutils.c
1369 @@ -692,7 +692,7 @@ void ai_pci_up(struct si_pub *sih)
1370 sii = container_of(sih, struct si_info, pub);
1372 if (sii->icbus->hosttype == BCMA_HOSTTYPE_PCI)
1373 - bcma_core_pci_extend_L1timer(&sii->icbus->drv_pci, true);
1374 + bcma_core_pci_extend_L1timer(&sii->icbus->drv_pci[0], true);
1377 /* Unconfigure and/or apply various WARs when going down */
1378 @@ -703,7 +703,7 @@ void ai_pci_down(struct si_pub *sih)
1379 sii = container_of(sih, struct si_info, pub);
1381 if (sii->icbus->hosttype == BCMA_HOSTTYPE_PCI)
1382 - bcma_core_pci_extend_L1timer(&sii->icbus->drv_pci, false);
1383 + bcma_core_pci_extend_L1timer(&sii->icbus->drv_pci[0], false);
1386 /* Enable BT-COEX & Ex-PA for 4313 */
1387 --- a/drivers/net/wireless/brcm80211/brcmsmac/main.c
1388 +++ b/drivers/net/wireless/brcm80211/brcmsmac/main.c
1389 @@ -5077,7 +5077,7 @@ static int brcms_b_up_prep(struct brcms_
1390 * Configure pci/pcmcia here instead of in brcms_c_attach()
1391 * to allow mfg hotswap: down, hotswap (chip power cycle), up.
1393 - bcma_core_pci_irq_ctl(&wlc_hw->d11core->bus->drv_pci, wlc_hw->d11core,
1394 + bcma_core_pci_irq_ctl(&wlc_hw->d11core->bus->drv_pci[0], wlc_hw->d11core,