1 --- a/arch/mips/bcm47xx/nvram.c
2 +++ b/arch/mips/bcm47xx/nvram.c
3 @@ -43,8 +43,8 @@ static void early_nvram_init(void)
4 #ifdef CONFIG_BCM47XX_SSB
5 case BCM47XX_BUS_TYPE_SSB:
6 mcore_ssb = &bcm47xx_bus.ssb.mipscore;
7 - base = mcore_ssb->flash_window;
8 - lim = mcore_ssb->flash_window_size;
9 + base = mcore_ssb->pflash.window;
10 + lim = mcore_ssb->pflash.window_size;
13 #ifdef CONFIG_BCM47XX_BCMA
14 --- a/arch/mips/bcm47xx/wgt634u.c
15 +++ b/arch/mips/bcm47xx/wgt634u.c
16 @@ -156,10 +156,10 @@ static int __init wgt634u_init(void)
20 - wgt634u_flash_data.width = mcore->flash_buswidth;
21 - wgt634u_flash_resource.start = mcore->flash_window;
22 - wgt634u_flash_resource.end = mcore->flash_window
23 - + mcore->flash_window_size
24 + wgt634u_flash_data.width = mcore->pflash.buswidth;
25 + wgt634u_flash_resource.start = mcore->pflash.window;
26 + wgt634u_flash_resource.end = mcore->pflash.window
27 + + mcore->pflash.window_size
29 return platform_add_devices(wgt634u_devices,
30 ARRAY_SIZE(wgt634u_devices));
31 --- a/drivers/ssb/Kconfig
32 +++ b/drivers/ssb/Kconfig
33 @@ -136,6 +136,11 @@ config SSB_DRIVER_MIPS
38 + bool "SSB serial flash support"
39 + depends on SSB_DRIVER_MIPS && BROKEN
42 # Assumption: We are on embedded, if we compile the MIPS core.
45 @@ -160,4 +165,12 @@ config SSB_DRIVER_GIGE
49 +config SSB_DRIVER_GPIO
50 + bool "SSB GPIO driver"
51 + depends on SSB && GPIOLIB
53 + Driver to provide access to the GPIO pins on the bus.
58 --- a/drivers/ssb/Makefile
59 +++ b/drivers/ssb/Makefile
60 @@ -11,10 +11,12 @@ ssb-$(CONFIG_SSB_SDIOHOST) += sdio.o
62 ssb-y += driver_chipcommon.o
63 ssb-y += driver_chipcommon_pmu.o
64 +ssb-$(CONFIG_SSB_SFLASH) += driver_chipcommon_sflash.o
65 ssb-$(CONFIG_SSB_DRIVER_MIPS) += driver_mipscore.o
66 ssb-$(CONFIG_SSB_DRIVER_EXTIF) += driver_extif.o
67 ssb-$(CONFIG_SSB_DRIVER_PCICORE) += driver_pcicore.o
68 ssb-$(CONFIG_SSB_DRIVER_GIGE) += driver_gige.o
69 +ssb-$(CONFIG_SSB_DRIVER_GPIO) += driver_gpio.o
71 # b43 pci-ssb-bridge driver
72 # Not strictly a part of SSB, but kept here for convenience
73 --- a/drivers/ssb/b43_pci_bridge.c
74 +++ b/drivers/ssb/b43_pci_bridge.c
75 @@ -37,6 +37,7 @@ static const struct pci_device_id b43_pc
76 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4329) },
77 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x432b) },
78 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x432c) },
79 + { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4350) },
82 MODULE_DEVICE_TABLE(pci, b43_pci_bridge_tbl);
83 --- a/drivers/ssb/driver_chipcommon.c
84 +++ b/drivers/ssb/driver_chipcommon.c
87 * Copyright 2005, Broadcom Corporation
88 * Copyright 2006, 2007, Michael Buesch <m@bues.ch>
89 + * Copyright 2012, Hauke Mehrtens <hauke@hauke-m.de>
91 * Licensed under the GNU/GPL. See COPYING for details.
94 #include <linux/ssb/ssb_regs.h>
95 #include <linux/export.h>
96 #include <linux/pci.h>
97 +#include <linux/bcm47xx_wdt.h>
99 #include "ssb_private.h"
101 @@ -280,10 +282,76 @@ static void calc_fast_powerup_delay(stru
102 cc->fast_pwrup_delay = tmp;
105 +static u32 ssb_chipco_alp_clock(struct ssb_chipcommon *cc)
107 + if (cc->capabilities & SSB_CHIPCO_CAP_PMU)
108 + return ssb_pmu_get_alp_clock(cc);
113 +static u32 ssb_chipco_watchdog_get_max_timer(struct ssb_chipcommon *cc)
117 + if (cc->capabilities & SSB_CHIPCO_CAP_PMU) {
118 + if (cc->dev->id.revision < 26)
121 + nb = (cc->dev->id.revision >= 37) ? 32 : 24;
128 + return (1 << nb) - 1;
131 +u32 ssb_chipco_watchdog_timer_set_wdt(struct bcm47xx_wdt *wdt, u32 ticks)
133 + struct ssb_chipcommon *cc = bcm47xx_wdt_get_drvdata(wdt);
135 + if (cc->dev->bus->bustype != SSB_BUSTYPE_SSB)
138 + return ssb_chipco_watchdog_timer_set(cc, ticks);
141 +u32 ssb_chipco_watchdog_timer_set_ms(struct bcm47xx_wdt *wdt, u32 ms)
143 + struct ssb_chipcommon *cc = bcm47xx_wdt_get_drvdata(wdt);
146 + if (cc->dev->bus->bustype != SSB_BUSTYPE_SSB)
149 + ticks = ssb_chipco_watchdog_timer_set(cc, cc->ticks_per_ms * ms);
150 + return ticks / cc->ticks_per_ms;
153 +static int ssb_chipco_watchdog_ticks_per_ms(struct ssb_chipcommon *cc)
155 + struct ssb_bus *bus = cc->dev->bus;
157 + if (cc->capabilities & SSB_CHIPCO_CAP_PMU) {
158 + /* based on 32KHz ILP clock */
161 + if (cc->dev->id.revision < 18)
162 + return ssb_clockspeed(bus) / 1000;
164 + return ssb_chipco_alp_clock(cc) / 1000;
168 void ssb_chipcommon_init(struct ssb_chipcommon *cc)
171 return; /* We don't have a ChipCommon */
173 + spin_lock_init(&cc->gpio_lock);
175 if (cc->dev->id.revision >= 11)
176 cc->status = chipco_read32(cc, SSB_CHIPCO_CHIPSTAT);
177 ssb_dprintk(KERN_INFO PFX "chipcommon status is 0x%x\n", cc->status);
178 @@ -297,6 +365,11 @@ void ssb_chipcommon_init(struct ssb_chip
179 chipco_powercontrol_init(cc);
180 ssb_chipco_set_clockmode(cc, SSB_CLKMODE_FAST);
181 calc_fast_powerup_delay(cc);
183 + if (cc->dev->bus->bustype == SSB_BUSTYPE_SSB) {
184 + cc->ticks_per_ms = ssb_chipco_watchdog_ticks_per_ms(cc);
185 + cc->max_timer_ms = ssb_chipco_watchdog_get_max_timer(cc) / cc->ticks_per_ms;
189 void ssb_chipco_suspend(struct ssb_chipcommon *cc)
190 @@ -395,10 +468,27 @@ void ssb_chipco_timing_init(struct ssb_c
193 /* Set chip watchdog reset timer to fire in 'ticks' backplane cycles */
194 -void ssb_chipco_watchdog_timer_set(struct ssb_chipcommon *cc, u32 ticks)
195 +u32 ssb_chipco_watchdog_timer_set(struct ssb_chipcommon *cc, u32 ticks)
198 - chipco_write32(cc, SSB_CHIPCO_WATCHDOG, ticks);
200 + enum ssb_clkmode clkmode;
202 + maxt = ssb_chipco_watchdog_get_max_timer(cc);
203 + if (cc->capabilities & SSB_CHIPCO_CAP_PMU) {
206 + else if (ticks > maxt)
208 + chipco_write32(cc, SSB_CHIPCO_PMU_WATCHDOG, ticks);
210 + clkmode = ticks ? SSB_CLKMODE_FAST : SSB_CLKMODE_DYNAMIC;
211 + ssb_chipco_set_clockmode(cc, clkmode);
215 + chipco_write32(cc, SSB_CHIPCO_WATCHDOG, ticks);
220 void ssb_chipco_irq_mask(struct ssb_chipcommon *cc, u32 mask, u32 value)
221 @@ -418,28 +508,93 @@ u32 ssb_chipco_gpio_in(struct ssb_chipco
223 u32 ssb_chipco_gpio_out(struct ssb_chipcommon *cc, u32 mask, u32 value)
225 - return chipco_write32_masked(cc, SSB_CHIPCO_GPIOOUT, mask, value);
226 + unsigned long flags;
229 + spin_lock_irqsave(&cc->gpio_lock, flags);
230 + res = chipco_write32_masked(cc, SSB_CHIPCO_GPIOOUT, mask, value);
231 + spin_unlock_irqrestore(&cc->gpio_lock, flags);
236 u32 ssb_chipco_gpio_outen(struct ssb_chipcommon *cc, u32 mask, u32 value)
238 - return chipco_write32_masked(cc, SSB_CHIPCO_GPIOOUTEN, mask, value);
239 + unsigned long flags;
242 + spin_lock_irqsave(&cc->gpio_lock, flags);
243 + res = chipco_write32_masked(cc, SSB_CHIPCO_GPIOOUTEN, mask, value);
244 + spin_unlock_irqrestore(&cc->gpio_lock, flags);
249 u32 ssb_chipco_gpio_control(struct ssb_chipcommon *cc, u32 mask, u32 value)
251 - return chipco_write32_masked(cc, SSB_CHIPCO_GPIOCTL, mask, value);
252 + unsigned long flags;
255 + spin_lock_irqsave(&cc->gpio_lock, flags);
256 + res = chipco_write32_masked(cc, SSB_CHIPCO_GPIOCTL, mask, value);
257 + spin_unlock_irqrestore(&cc->gpio_lock, flags);
261 EXPORT_SYMBOL(ssb_chipco_gpio_control);
263 u32 ssb_chipco_gpio_intmask(struct ssb_chipcommon *cc, u32 mask, u32 value)
265 - return chipco_write32_masked(cc, SSB_CHIPCO_GPIOIRQ, mask, value);
266 + unsigned long flags;
269 + spin_lock_irqsave(&cc->gpio_lock, flags);
270 + res = chipco_write32_masked(cc, SSB_CHIPCO_GPIOIRQ, mask, value);
271 + spin_unlock_irqrestore(&cc->gpio_lock, flags);
276 u32 ssb_chipco_gpio_polarity(struct ssb_chipcommon *cc, u32 mask, u32 value)
278 - return chipco_write32_masked(cc, SSB_CHIPCO_GPIOPOL, mask, value);
279 + unsigned long flags;
282 + spin_lock_irqsave(&cc->gpio_lock, flags);
283 + res = chipco_write32_masked(cc, SSB_CHIPCO_GPIOPOL, mask, value);
284 + spin_unlock_irqrestore(&cc->gpio_lock, flags);
289 +u32 ssb_chipco_gpio_pullup(struct ssb_chipcommon *cc, u32 mask, u32 value)
291 + unsigned long flags;
294 + if (cc->dev->id.revision < 20)
297 + spin_lock_irqsave(&cc->gpio_lock, flags);
298 + res = chipco_write32_masked(cc, SSB_CHIPCO_GPIOPULLUP, mask, value);
299 + spin_unlock_irqrestore(&cc->gpio_lock, flags);
304 +u32 ssb_chipco_gpio_pulldown(struct ssb_chipcommon *cc, u32 mask, u32 value)
306 + unsigned long flags;
309 + if (cc->dev->id.revision < 20)
312 + spin_lock_irqsave(&cc->gpio_lock, flags);
313 + res = chipco_write32_masked(cc, SSB_CHIPCO_GPIOPULLDOWN, mask, value);
314 + spin_unlock_irqrestore(&cc->gpio_lock, flags);
319 #ifdef CONFIG_SSB_SERIAL
320 @@ -473,12 +628,7 @@ int ssb_chipco_serial_init(struct ssb_ch
321 chipco_read32(cc, SSB_CHIPCO_CORECTL)
322 | SSB_CHIPCO_CORECTL_UARTCLK0);
323 } else if ((ccrev >= 11) && (ccrev != 15)) {
324 - /* Fixed ALP clock */
325 - baud_base = 20000000;
326 - if (cc->capabilities & SSB_CHIPCO_CAP_PMU) {
327 - /* FIXME: baud_base is different for devices with a PMU */
330 + baud_base = ssb_chipco_alp_clock(cc);
333 /* Turn off UART clock before switching clocksource. */
334 --- a/drivers/ssb/driver_chipcommon_pmu.c
335 +++ b/drivers/ssb/driver_chipcommon_pmu.c
336 @@ -346,6 +346,8 @@ static void ssb_pmu_pll_init(struct ssb_
337 chipco_write32(cc, SSB_CHIPCO_PLLCTL_DATA, 0x380005C0);
343 ssb_printk(KERN_ERR PFX
344 "ERROR: PLL init unknown for device %04X\n",
345 @@ -434,6 +436,7 @@ static void ssb_pmu_resources_init(struc
350 /* We keep the default settings:
353 @@ -615,6 +618,33 @@ void ssb_pmu_set_ldo_paref(struct ssb_ch
354 EXPORT_SYMBOL(ssb_pmu_set_ldo_voltage);
355 EXPORT_SYMBOL(ssb_pmu_set_ldo_paref);
357 +static u32 ssb_pmu_get_alp_clock_clk0(struct ssb_chipcommon *cc)
360 + const struct pmu0_plltab_entry *e = NULL;
362 + crystalfreq = chipco_read32(cc, SSB_CHIPCO_PMU_CTL) &
363 + SSB_CHIPCO_PMU_CTL_XTALFREQ >> SSB_CHIPCO_PMU_CTL_XTALFREQ_SHIFT;
364 + e = pmu0_plltab_find_entry(crystalfreq);
366 + return e->freq * 1000;
369 +u32 ssb_pmu_get_alp_clock(struct ssb_chipcommon *cc)
371 + struct ssb_bus *bus = cc->dev->bus;
373 + switch (bus->chip_id) {
375 + ssb_pmu_get_alp_clock_clk0(cc);
377 + ssb_printk(KERN_ERR PFX
378 + "ERROR: PMU alp clock unknown for device %04X\n",
384 u32 ssb_pmu_get_cpu_clock(struct ssb_chipcommon *cc)
386 struct ssb_bus *bus = cc->dev->bus;
388 +++ b/drivers/ssb/driver_chipcommon_sflash.c
391 + * Sonics Silicon Backplane
392 + * ChipCommon serial flash interface
394 + * Licensed under the GNU/GPL. See COPYING for details.
397 +#include <linux/ssb/ssb.h>
399 +#include "ssb_private.h"
401 +/* Initialize serial flash access */
402 +int ssb_sflash_init(struct ssb_chipcommon *cc)
404 + pr_err("Serial flash support is not implemented yet!\n");
408 --- a/drivers/ssb/driver_extif.c
409 +++ b/drivers/ssb/driver_extif.c
410 @@ -112,10 +112,37 @@ void ssb_extif_get_clockcontrol(struct s
411 *m = extif_read32(extif, SSB_EXTIF_CLOCK_SB);
414 -void ssb_extif_watchdog_timer_set(struct ssb_extif *extif,
416 +u32 ssb_extif_watchdog_timer_set_wdt(struct bcm47xx_wdt *wdt, u32 ticks)
418 + struct ssb_extif *extif = bcm47xx_wdt_get_drvdata(wdt);
420 + return ssb_extif_watchdog_timer_set(extif, ticks);
423 +u32 ssb_extif_watchdog_timer_set_ms(struct bcm47xx_wdt *wdt, u32 ms)
425 + struct ssb_extif *extif = bcm47xx_wdt_get_drvdata(wdt);
426 + u32 ticks = (SSB_EXTIF_WATCHDOG_CLK / 1000) * ms;
428 + ticks = ssb_extif_watchdog_timer_set(extif, ticks);
430 + return (ticks * 1000) / SSB_EXTIF_WATCHDOG_CLK;
433 +u32 ssb_extif_watchdog_timer_set(struct ssb_extif *extif, u32 ticks)
435 + if (ticks > SSB_EXTIF_WATCHDOG_MAX_TIMER)
436 + ticks = SSB_EXTIF_WATCHDOG_MAX_TIMER;
437 extif_write32(extif, SSB_EXTIF_WATCHDOG, ticks);
442 +void ssb_extif_init(struct ssb_extif *extif)
445 + return; /* We don't have a Extif core */
446 + spin_lock_init(&extif->gpio_lock);
449 u32 ssb_extif_gpio_in(struct ssb_extif *extif, u32 mask)
450 @@ -125,22 +152,50 @@ u32 ssb_extif_gpio_in(struct ssb_extif *
452 u32 ssb_extif_gpio_out(struct ssb_extif *extif, u32 mask, u32 value)
454 - return extif_write32_masked(extif, SSB_EXTIF_GPIO_OUT(0),
455 + unsigned long flags;
458 + spin_lock_irqsave(&extif->gpio_lock, flags);
459 + res = extif_write32_masked(extif, SSB_EXTIF_GPIO_OUT(0),
461 + spin_unlock_irqrestore(&extif->gpio_lock, flags);
466 u32 ssb_extif_gpio_outen(struct ssb_extif *extif, u32 mask, u32 value)
468 - return extif_write32_masked(extif, SSB_EXTIF_GPIO_OUTEN(0),
469 + unsigned long flags;
472 + spin_lock_irqsave(&extif->gpio_lock, flags);
473 + res = extif_write32_masked(extif, SSB_EXTIF_GPIO_OUTEN(0),
475 + spin_unlock_irqrestore(&extif->gpio_lock, flags);
480 u32 ssb_extif_gpio_polarity(struct ssb_extif *extif, u32 mask, u32 value)
482 - return extif_write32_masked(extif, SSB_EXTIF_GPIO_INTPOL, mask, value);
483 + unsigned long flags;
486 + spin_lock_irqsave(&extif->gpio_lock, flags);
487 + res = extif_write32_masked(extif, SSB_EXTIF_GPIO_INTPOL, mask, value);
488 + spin_unlock_irqrestore(&extif->gpio_lock, flags);
493 u32 ssb_extif_gpio_intmask(struct ssb_extif *extif, u32 mask, u32 value)
495 - return extif_write32_masked(extif, SSB_EXTIF_GPIO_INTMASK, mask, value);
496 + unsigned long flags;
499 + spin_lock_irqsave(&extif->gpio_lock, flags);
500 + res = extif_write32_masked(extif, SSB_EXTIF_GPIO_INTMASK, mask, value);
501 + spin_unlock_irqrestore(&extif->gpio_lock, flags);
506 +++ b/drivers/ssb/driver_gpio.c
509 + * Sonics Silicon Backplane
512 + * Copyright 2011, Broadcom Corporation
513 + * Copyright 2012, Hauke Mehrtens <hauke@hauke-m.de>
515 + * Licensed under the GNU/GPL. See COPYING for details.
518 +#include <linux/gpio.h>
519 +#include <linux/export.h>
520 +#include <linux/ssb/ssb.h>
522 +#include "ssb_private.h"
524 +static struct ssb_bus *ssb_gpio_get_bus(struct gpio_chip *chip)
526 + return container_of(chip, struct ssb_bus, gpio);
529 +static int ssb_gpio_chipco_get_value(struct gpio_chip *chip, unsigned gpio)
531 + struct ssb_bus *bus = ssb_gpio_get_bus(chip);
533 + return !!ssb_chipco_gpio_in(&bus->chipco, 1 << gpio);
536 +static void ssb_gpio_chipco_set_value(struct gpio_chip *chip, unsigned gpio,
539 + struct ssb_bus *bus = ssb_gpio_get_bus(chip);
541 + ssb_chipco_gpio_out(&bus->chipco, 1 << gpio, value ? 1 << gpio : 0);
544 +static int ssb_gpio_chipco_direction_input(struct gpio_chip *chip,
547 + struct ssb_bus *bus = ssb_gpio_get_bus(chip);
549 + ssb_chipco_gpio_outen(&bus->chipco, 1 << gpio, 0);
553 +static int ssb_gpio_chipco_direction_output(struct gpio_chip *chip,
554 + unsigned gpio, int value)
556 + struct ssb_bus *bus = ssb_gpio_get_bus(chip);
558 + ssb_chipco_gpio_outen(&bus->chipco, 1 << gpio, 1 << gpio);
559 + ssb_chipco_gpio_out(&bus->chipco, 1 << gpio, value ? 1 << gpio : 0);
563 +static int ssb_gpio_chipco_request(struct gpio_chip *chip, unsigned gpio)
565 + struct ssb_bus *bus = ssb_gpio_get_bus(chip);
567 + ssb_chipco_gpio_control(&bus->chipco, 1 << gpio, 0);
568 + /* clear pulldown */
569 + ssb_chipco_gpio_pulldown(&bus->chipco, 1 << gpio, 0);
571 + ssb_chipco_gpio_pullup(&bus->chipco, 1 << gpio, 1 << gpio);
576 +static void ssb_gpio_chipco_free(struct gpio_chip *chip, unsigned gpio)
578 + struct ssb_bus *bus = ssb_gpio_get_bus(chip);
581 + ssb_chipco_gpio_pullup(&bus->chipco, 1 << gpio, 0);
584 +static int ssb_gpio_chipco_init(struct ssb_bus *bus)
586 + struct gpio_chip *chip = &bus->gpio;
588 + chip->label = "ssb_chipco_gpio";
589 + chip->owner = THIS_MODULE;
590 + chip->request = ssb_gpio_chipco_request;
591 + chip->free = ssb_gpio_chipco_free;
592 + chip->get = ssb_gpio_chipco_get_value;
593 + chip->set = ssb_gpio_chipco_set_value;
594 + chip->direction_input = ssb_gpio_chipco_direction_input;
595 + chip->direction_output = ssb_gpio_chipco_direction_output;
597 + /* There is just one SoC in one device and its GPIO addresses should be
598 + * deterministic to address them more easily. The other buses could get
599 + * a random base number. */
600 + if (bus->bustype == SSB_BUSTYPE_SSB)
605 + return gpiochip_add(chip);
608 +#ifdef CONFIG_SSB_DRIVER_EXTIF
610 +static int ssb_gpio_extif_get_value(struct gpio_chip *chip, unsigned gpio)
612 + struct ssb_bus *bus = ssb_gpio_get_bus(chip);
614 + return !!ssb_extif_gpio_in(&bus->extif, 1 << gpio);
617 +static void ssb_gpio_extif_set_value(struct gpio_chip *chip, unsigned gpio,
620 + struct ssb_bus *bus = ssb_gpio_get_bus(chip);
622 + ssb_extif_gpio_out(&bus->extif, 1 << gpio, value ? 1 << gpio : 0);
625 +static int ssb_gpio_extif_direction_input(struct gpio_chip *chip,
628 + struct ssb_bus *bus = ssb_gpio_get_bus(chip);
630 + ssb_extif_gpio_outen(&bus->extif, 1 << gpio, 0);
634 +static int ssb_gpio_extif_direction_output(struct gpio_chip *chip,
635 + unsigned gpio, int value)
637 + struct ssb_bus *bus = ssb_gpio_get_bus(chip);
639 + ssb_extif_gpio_outen(&bus->extif, 1 << gpio, 1 << gpio);
640 + ssb_extif_gpio_out(&bus->extif, 1 << gpio, value ? 1 << gpio : 0);
644 +static int ssb_gpio_extif_init(struct ssb_bus *bus)
646 + struct gpio_chip *chip = &bus->gpio;
648 + chip->label = "ssb_extif_gpio";
649 + chip->owner = THIS_MODULE;
650 + chip->get = ssb_gpio_extif_get_value;
651 + chip->set = ssb_gpio_extif_set_value;
652 + chip->direction_input = ssb_gpio_extif_direction_input;
653 + chip->direction_output = ssb_gpio_extif_direction_output;
655 + /* There is just one SoC in one device and its GPIO addresses should be
656 + * deterministic to address them more easily. The other buses could get
657 + * a random base number. */
658 + if (bus->bustype == SSB_BUSTYPE_SSB)
663 + return gpiochip_add(chip);
667 +static int ssb_gpio_extif_init(struct ssb_bus *bus)
673 +int ssb_gpio_init(struct ssb_bus *bus)
675 + if (ssb_chipco_available(&bus->chipco))
676 + return ssb_gpio_chipco_init(bus);
677 + else if (ssb_extif_available(&bus->extif))
678 + return ssb_gpio_extif_init(bus);
684 --- a/drivers/ssb/driver_mipscore.c
685 +++ b/drivers/ssb/driver_mipscore.c
686 @@ -178,9 +178,9 @@ static void ssb_mips_serial_init(struct
688 struct ssb_bus *bus = mcore->dev->bus;
690 - if (bus->extif.dev)
691 + if (ssb_extif_available(&bus->extif))
692 mcore->nr_serial_ports = ssb_extif_serial_init(&bus->extif, mcore->serial_ports);
693 - else if (bus->chipco.dev)
694 + else if (ssb_chipco_available(&bus->chipco))
695 mcore->nr_serial_ports = ssb_chipco_serial_init(&bus->chipco, mcore->serial_ports);
697 mcore->nr_serial_ports = 0;
698 @@ -191,10 +191,11 @@ static void ssb_mips_flash_detect(struct
699 struct ssb_bus *bus = mcore->dev->bus;
701 /* When there is no chipcommon on the bus there is 4MB flash */
702 - if (!bus->chipco.dev) {
703 - mcore->flash_buswidth = 2;
704 - mcore->flash_window = SSB_FLASH1;
705 - mcore->flash_window_size = SSB_FLASH1_SZ;
706 + if (!ssb_chipco_available(&bus->chipco)) {
707 + mcore->pflash.present = true;
708 + mcore->pflash.buswidth = 2;
709 + mcore->pflash.window = SSB_FLASH1;
710 + mcore->pflash.window_size = SSB_FLASH1_SZ;
714 @@ -202,17 +203,19 @@ static void ssb_mips_flash_detect(struct
715 switch (bus->chipco.capabilities & SSB_CHIPCO_CAP_FLASHT) {
716 case SSB_CHIPCO_FLASHT_STSER:
717 case SSB_CHIPCO_FLASHT_ATSER:
718 - pr_err("Serial flash not supported\n");
719 + pr_debug("Found serial flash\n");
720 + ssb_sflash_init(&bus->chipco);
722 case SSB_CHIPCO_FLASHT_PARA:
723 pr_debug("Found parallel flash\n");
724 - mcore->flash_window = SSB_FLASH2;
725 - mcore->flash_window_size = SSB_FLASH2_SZ;
726 + mcore->pflash.present = true;
727 + mcore->pflash.window = SSB_FLASH2;
728 + mcore->pflash.window_size = SSB_FLASH2_SZ;
729 if ((ssb_read32(bus->chipco.dev, SSB_CHIPCO_FLASH_CFG)
730 & SSB_CHIPCO_CFG_DS16) == 0)
731 - mcore->flash_buswidth = 1;
732 + mcore->pflash.buswidth = 1;
734 - mcore->flash_buswidth = 2;
735 + mcore->pflash.buswidth = 2;
739 @@ -225,9 +228,9 @@ u32 ssb_cpu_clock(struct ssb_mipscore *m
740 if (bus->chipco.capabilities & SSB_CHIPCO_CAP_PMU)
741 return ssb_pmu_get_cpu_clock(&bus->chipco);
743 - if (bus->extif.dev) {
744 + if (ssb_extif_available(&bus->extif)) {
745 ssb_extif_get_clockcontrol(&bus->extif, &pll_type, &n, &m);
746 - } else if (bus->chipco.dev) {
747 + } else if (ssb_chipco_available(&bus->chipco)) {
748 ssb_chipco_get_clockcpu(&bus->chipco, &pll_type, &n, &m);
751 @@ -263,9 +266,9 @@ void ssb_mipscore_init(struct ssb_mipsco
753 ns = 1000000000 / hz;
755 - if (bus->extif.dev)
756 + if (ssb_extif_available(&bus->extif))
757 ssb_extif_timing_init(&bus->extif, ns);
758 - else if (bus->chipco.dev)
759 + else if (ssb_chipco_available(&bus->chipco))
760 ssb_chipco_timing_init(&bus->chipco, ns);
762 /* Assign IRQs to all cores on the bus, start with irq line 2, because serial usually takes 1 */
763 --- a/drivers/ssb/embedded.c
764 +++ b/drivers/ssb/embedded.c
767 * Copyright 2005-2008, Broadcom Corporation
768 * Copyright 2006-2008, Michael Buesch <m@bues.ch>
769 + * Copyright 2012, Hauke Mehrtens <hauke@hauke-m.de>
771 * Licensed under the GNU/GPL. See COPYING for details.
774 #include <linux/export.h>
775 +#include <linux/platform_device.h>
776 #include <linux/ssb/ssb.h>
777 #include <linux/ssb/ssb_embedded.h>
778 #include <linux/ssb/ssb_driver_pci.h>
779 @@ -32,6 +34,39 @@ int ssb_watchdog_timer_set(struct ssb_bu
781 EXPORT_SYMBOL(ssb_watchdog_timer_set);
783 +int ssb_watchdog_register(struct ssb_bus *bus)
785 + struct bcm47xx_wdt wdt = {};
786 + struct platform_device *pdev;
788 + if (ssb_chipco_available(&bus->chipco)) {
789 + wdt.driver_data = &bus->chipco;
790 + wdt.timer_set = ssb_chipco_watchdog_timer_set_wdt;
791 + wdt.timer_set_ms = ssb_chipco_watchdog_timer_set_ms;
792 + wdt.max_timer_ms = bus->chipco.max_timer_ms;
793 + } else if (ssb_extif_available(&bus->extif)) {
794 + wdt.driver_data = &bus->extif;
795 + wdt.timer_set = ssb_extif_watchdog_timer_set_wdt;
796 + wdt.timer_set_ms = ssb_extif_watchdog_timer_set_ms;
797 + wdt.max_timer_ms = SSB_EXTIF_WATCHDOG_MAX_TIMER_MS;
802 + pdev = platform_device_register_data(NULL, "bcm47xx-wdt",
803 + bus->busnumber, &wdt,
805 + if (IS_ERR(pdev)) {
806 + ssb_dprintk(KERN_INFO PFX
807 + "can not register watchdog device, err: %li\n",
809 + return PTR_ERR(pdev);
812 + bus->watchdog = pdev;
816 u32 ssb_gpio_in(struct ssb_bus *bus, u32 mask)
819 --- a/drivers/ssb/main.c
820 +++ b/drivers/ssb/main.c
822 #include <linux/delay.h>
823 #include <linux/io.h>
824 #include <linux/module.h>
825 +#include <linux/platform_device.h>
826 #include <linux/ssb/ssb.h>
827 #include <linux/ssb/ssb_regs.h>
828 #include <linux/ssb/ssb_driver_gige.h>
829 @@ -433,6 +434,11 @@ static void ssb_devices_unregister(struc
831 device_unregister(sdev->dev);
834 +#ifdef CONFIG_SSB_EMBEDDED
835 + if (bus->bustype == SSB_BUSTYPE_SSB)
836 + platform_device_unregister(bus->watchdog);
840 void ssb_bus_unregister(struct ssb_bus *bus)
841 @@ -561,6 +567,8 @@ static int __devinit ssb_attach_queued_b
844 ssb_pcicore_init(&bus->pcicore);
845 + if (bus->bustype == SSB_BUSTYPE_SSB)
846 + ssb_watchdog_register(bus);
847 ssb_bus_may_powerdown(bus);
849 err = ssb_devices_register(bus);
850 @@ -796,7 +804,14 @@ static int __devinit ssb_bus_register(st
852 goto err_pcmcia_exit;
853 ssb_chipcommon_init(&bus->chipco);
854 + ssb_extif_init(&bus->extif);
855 ssb_mipscore_init(&bus->mipscore);
856 + err = ssb_gpio_init(bus);
857 + if (err == -ENOTSUPP)
858 + ssb_dprintk(KERN_DEBUG PFX "GPIO driver not activated\n");
860 + ssb_dprintk(KERN_ERR PFX
861 + "Error registering GPIO driver: %i\n", err);
862 err = ssb_fetch_invariants(bus, get_invariants);
864 ssb_bus_may_powerdown(bus);
865 @@ -1118,8 +1133,7 @@ static u32 ssb_tmslow_reject_bitmask(str
866 case SSB_IDLOW_SSBREV_27: /* same here */
867 return SSB_TMSLOW_REJECT; /* this is a guess */
869 - printk(KERN_INFO "ssb: Backplane Revision 0x%.8X\n", rev);
871 + WARN(1, KERN_INFO "ssb: Backplane Revision 0x%.8X\n", rev);
873 return (SSB_TMSLOW_REJECT | SSB_TMSLOW_REJECT_23);
875 --- a/drivers/ssb/ssb_private.h
876 +++ b/drivers/ssb/ssb_private.h
879 #include <linux/ssb/ssb.h>
880 #include <linux/types.h>
881 +#include <linux/bcm47xx_wdt.h>
885 @@ -210,5 +211,63 @@ static inline void b43_pci_ssb_bridge_ex
886 /* driver_chipcommon_pmu.c */
887 extern u32 ssb_pmu_get_cpu_clock(struct ssb_chipcommon *cc);
888 extern u32 ssb_pmu_get_controlclock(struct ssb_chipcommon *cc);
889 +extern u32 ssb_pmu_get_alp_clock(struct ssb_chipcommon *cc);
891 +extern u32 ssb_chipco_watchdog_timer_set_wdt(struct bcm47xx_wdt *wdt,
893 +extern u32 ssb_chipco_watchdog_timer_set_ms(struct bcm47xx_wdt *wdt, u32 ms);
895 +/* driver_chipcommon_sflash.c */
896 +#ifdef CONFIG_SSB_SFLASH
897 +int ssb_sflash_init(struct ssb_chipcommon *cc);
899 +static inline int ssb_sflash_init(struct ssb_chipcommon *cc)
901 + pr_err("Serial flash not supported\n");
904 +#endif /* CONFIG_SSB_SFLASH */
906 +#ifdef CONFIG_SSB_DRIVER_EXTIF
907 +extern u32 ssb_extif_watchdog_timer_set_wdt(struct bcm47xx_wdt *wdt, u32 ticks);
908 +extern u32 ssb_extif_watchdog_timer_set_ms(struct bcm47xx_wdt *wdt, u32 ms);
910 +static inline u32 ssb_extif_watchdog_timer_set_wdt(struct bcm47xx_wdt *wdt,
915 +static inline u32 ssb_extif_watchdog_timer_set_ms(struct bcm47xx_wdt *wdt,
922 +#ifdef CONFIG_SSB_EMBEDDED
923 +extern int ssb_watchdog_register(struct ssb_bus *bus);
924 +#else /* CONFIG_SSB_EMBEDDED */
925 +static inline int ssb_watchdog_register(struct ssb_bus *bus)
929 +#endif /* CONFIG_SSB_EMBEDDED */
931 +#ifdef CONFIG_SSB_DRIVER_EXTIF
932 +extern void ssb_extif_init(struct ssb_extif *extif);
934 +static inline void ssb_extif_init(struct ssb_extif *extif)
939 +#ifdef CONFIG_SSB_DRIVER_GPIO
940 +extern int ssb_gpio_init(struct ssb_bus *bus);
941 +#else /* CONFIG_SSB_DRIVER_GPIO */
942 +static inline int ssb_gpio_init(struct ssb_bus *bus)
946 +#endif /* CONFIG_SSB_DRIVER_GPIO */
948 #endif /* LINUX_SSB_PRIVATE_H_ */
949 --- a/include/linux/ssb/ssb.h
950 +++ b/include/linux/ssb/ssb.h
952 #include <linux/types.h>
953 #include <linux/spinlock.h>
954 #include <linux/pci.h>
955 +#include <linux/gpio.h>
956 #include <linux/mod_devicetable.h>
957 #include <linux/dma-mapping.h>
958 +#include <linux/platform_device.h>
960 #include <linux/ssb/ssb_regs.h>
962 @@ -432,7 +434,11 @@ struct ssb_bus {
963 #ifdef CONFIG_SSB_EMBEDDED
964 /* Lock for GPIO register access. */
965 spinlock_t gpio_lock;
966 + struct platform_device *watchdog;
967 #endif /* EMBEDDED */
968 +#ifdef CONFIG_SSB_DRIVER_GPIO
969 + struct gpio_chip gpio;
970 +#endif /* DRIVER_GPIO */
972 /* Internal-only stuff follows. Do not touch. */
973 struct list_head list;
974 --- a/include/linux/ssb/ssb_driver_chipcommon.h
975 +++ b/include/linux/ssb/ssb_driver_chipcommon.h
976 @@ -590,7 +590,10 @@ struct ssb_chipcommon {
978 /* Fast Powerup Delay constant */
979 u16 fast_pwrup_delay;
980 + spinlock_t gpio_lock;
981 struct ssb_chipcommon_pmu pmu;
986 static inline bool ssb_chipco_available(struct ssb_chipcommon *cc)
987 @@ -630,8 +633,7 @@ enum ssb_clkmode {
988 extern void ssb_chipco_set_clockmode(struct ssb_chipcommon *cc,
989 enum ssb_clkmode mode);
991 -extern void ssb_chipco_watchdog_timer_set(struct ssb_chipcommon *cc,
993 +extern u32 ssb_chipco_watchdog_timer_set(struct ssb_chipcommon *cc, u32 ticks);
995 void ssb_chipco_irq_mask(struct ssb_chipcommon *cc, u32 mask, u32 value);
997 @@ -644,6 +646,8 @@ u32 ssb_chipco_gpio_outen(struct ssb_chi
998 u32 ssb_chipco_gpio_control(struct ssb_chipcommon *cc, u32 mask, u32 value);
999 u32 ssb_chipco_gpio_intmask(struct ssb_chipcommon *cc, u32 mask, u32 value);
1000 u32 ssb_chipco_gpio_polarity(struct ssb_chipcommon *cc, u32 mask, u32 value);
1001 +u32 ssb_chipco_gpio_pullup(struct ssb_chipcommon *cc, u32 mask, u32 value);
1002 +u32 ssb_chipco_gpio_pulldown(struct ssb_chipcommon *cc, u32 mask, u32 value);
1004 #ifdef CONFIG_SSB_SERIAL
1005 extern int ssb_chipco_serial_init(struct ssb_chipcommon *cc,
1006 --- a/include/linux/ssb/ssb_driver_extif.h
1007 +++ b/include/linux/ssb/ssb_driver_extif.h
1008 @@ -152,12 +152,16 @@
1010 #define SSB_EXTIF_WATCHDOG_CLK 48000000 /* Hz */
1012 +#define SSB_EXTIF_WATCHDOG_MAX_TIMER ((1 << 28) - 1)
1013 +#define SSB_EXTIF_WATCHDOG_MAX_TIMER_MS (SSB_EXTIF_WATCHDOG_MAX_TIMER \
1014 + / (SSB_EXTIF_WATCHDOG_CLK / 1000))
1017 #ifdef CONFIG_SSB_DRIVER_EXTIF
1020 struct ssb_device *dev;
1021 + spinlock_t gpio_lock;
1024 static inline bool ssb_extif_available(struct ssb_extif *extif)
1025 @@ -171,8 +175,7 @@ extern void ssb_extif_get_clockcontrol(s
1026 extern void ssb_extif_timing_init(struct ssb_extif *extif,
1029 -extern void ssb_extif_watchdog_timer_set(struct ssb_extif *extif,
1031 +extern u32 ssb_extif_watchdog_timer_set(struct ssb_extif *extif, u32 ticks);
1033 /* Extif GPIO pin access */
1034 u32 ssb_extif_gpio_in(struct ssb_extif *extif, u32 mask);
1035 @@ -205,10 +208,52 @@ void ssb_extif_get_clockcontrol(struct s
1039 -void ssb_extif_watchdog_timer_set(struct ssb_extif *extif,
1041 +void ssb_extif_timing_init(struct ssb_extif *extif, unsigned long ns)
1046 +u32 ssb_extif_watchdog_timer_set(struct ssb_extif *extif, u32 ticks)
1051 +static inline u32 ssb_extif_gpio_in(struct ssb_extif *extif, u32 mask)
1056 +static inline u32 ssb_extif_gpio_out(struct ssb_extif *extif, u32 mask,
1062 +static inline u32 ssb_extif_gpio_outen(struct ssb_extif *extif, u32 mask,
1068 +static inline u32 ssb_extif_gpio_polarity(struct ssb_extif *extif, u32 mask,
1074 +static inline u32 ssb_extif_gpio_intmask(struct ssb_extif *extif, u32 mask,
1080 +#ifdef CONFIG_SSB_SERIAL
1081 +static inline int ssb_extif_serial_init(struct ssb_extif *extif,
1082 + struct ssb_serial_port *ports)
1086 +#endif /* CONFIG_SSB_SERIAL */
1088 #endif /* CONFIG_SSB_DRIVER_EXTIF */
1089 #endif /* LINUX_SSB_EXTIFCORE_H_ */
1090 --- a/include/linux/ssb/ssb_driver_mips.h
1091 +++ b/include/linux/ssb/ssb_driver_mips.h
1092 @@ -13,6 +13,12 @@ struct ssb_serial_port {
1093 unsigned int reg_shift;
1096 +struct ssb_pflash {
1103 struct ssb_mipscore {
1104 struct ssb_device *dev;
1105 @@ -20,9 +26,7 @@ struct ssb_mipscore {
1106 int nr_serial_ports;
1107 struct ssb_serial_port serial_ports[4];
1109 - u8 flash_buswidth;
1111 - u32 flash_window_size;
1112 + struct ssb_pflash pflash;
1115 extern void ssb_mipscore_init(struct ssb_mipscore *mcore);
1116 --- a/include/linux/ssb/ssb_regs.h
1117 +++ b/include/linux/ssb/ssb_regs.h
1119 #define SSB_SPROM8_HWIQ_IQSWP_IQCAL_SWP_SHIFT 4
1120 #define SSB_SPROM8_HWIQ_IQSWP_HW_IQCAL 0x0020
1121 #define SSB_SPROM8_HWIQ_IQSWP_HW_IQCAL_SHIFT 5
1122 -#define SSB_SPROM8_TEMPDELTA 0x00BA
1123 +#define SSB_SPROM8_TEMPDELTA 0x00BC
1124 #define SSB_SPROM8_TEMPDELTA_PHYCAL 0x00ff
1125 #define SSB_SPROM8_TEMPDELTA_PHYCAL_SHIFT 0
1126 #define SSB_SPROM8_TEMPDELTA_PERIOD 0x0f00
1128 +++ b/include/linux/bcm47xx_wdt.h
1130 +#ifndef LINUX_BCM47XX_WDT_H_
1131 +#define LINUX_BCM47XX_WDT_H_
1133 +#include <linux/types.h>
1136 +struct bcm47xx_wdt {
1137 + u32 (*timer_set)(struct bcm47xx_wdt *, u32);
1138 + u32 (*timer_set_ms)(struct bcm47xx_wdt *, u32);
1141 + void *driver_data;
1144 +static inline void *bcm47xx_wdt_get_drvdata(struct bcm47xx_wdt *wdt)
1146 + return wdt->driver_data;
1148 +#endif /* LINUX_BCM47XX_WDT_H_ */