target/linux/generic/patches-3.6/020-ssb_update.patch

   1 --- a/arch/mips/bcm47xx/nvram.c
   2 +++ b/arch/mips/bcm47xx/nvram.c
   3 @@ -43,8 +43,8 @@ static void early_nvram_init(void)
   4  #ifdef CONFIG_BCM47XX_SSB
   5         case BCM47XX_BUS_TYPE_SSB:
   6                 mcore_ssb = &bcm47xx_bus.ssb.mipscore;
   7 -               base = mcore_ssb->flash_window;
   8 -               lim = mcore_ssb->flash_window_size;
   9 +               base = mcore_ssb->pflash.window;
  10 +               lim = mcore_ssb->pflash.window_size;
  11                 break;
  12  #endif
  13  #ifdef CONFIG_BCM47XX_BCMA
  14 --- a/arch/mips/bcm47xx/wgt634u.c
  15 +++ b/arch/mips/bcm47xx/wgt634u.c
  16 @@ -156,10 +156,10 @@ static int __init wgt634u_init(void)
  17                                             SSB_CHIPCO_IRQ_GPIO);
  18                 }
  19
  20 -               wgt634u_flash_data.width = mcore->flash_buswidth;
  21 -               wgt634u_flash_resource.start = mcore->flash_window;
  22 -               wgt634u_flash_resource.end = mcore->flash_window
  23 -                                          + mcore->flash_window_size
  24 +               wgt634u_flash_data.width = mcore->pflash.buswidth;
  25 +               wgt634u_flash_resource.start = mcore->pflash.window;
  26 +               wgt634u_flash_resource.end = mcore->pflash.window
  27 +                                          + mcore->pflash.window_size
  28                                            - 1;
  29                 return platform_add_devices(wgt634u_devices,
  30                                             ARRAY_SIZE(wgt634u_devices));
  31 --- a/drivers/ssb/Kconfig
  32 +++ b/drivers/ssb/Kconfig
  33 @@ -136,10 +136,15 @@ config SSB_DRIVER_MIPS
  34
  35           If unsure, say N
  36
  37 +config SSB_SFLASH
  38 +       bool "SSB serial flash support"
  39 +       depends on SSB_DRIVER_MIPS && BROKEN
  40 +       default y
  41 +
  42  # Assumption: We are on embedded, if we compile the MIPS core.
  43  config SSB_EMBEDDED
  44         bool
  45 -       depends on SSB_DRIVER_MIPS
  46 +       depends on SSB_DRIVER_MIPS && SSB_PCICORE_HOSTMODE
  47         default y
  48
  49  config SSB_DRIVER_EXTIF
  50 @@ -160,4 +165,12 @@ config SSB_DRIVER_GIGE
  51
  52           If unsure, say N
  53
  54 +config SSB_DRIVER_GPIO
  55 +       bool "SSB GPIO driver"
  56 +       depends on SSB && GPIOLIB
  57 +       help
  58 +         Driver to provide access to the GPIO pins on the bus.
  59 +
  60 +         If unsure, say N
  61 +
  62  endmenu
  63 --- a/drivers/ssb/Makefile
  64 +++ b/drivers/ssb/Makefile
  65 @@ -11,10 +11,12 @@ ssb-$(CONFIG_SSB_SDIOHOST)          += sdio.o
  66  # built-in drivers
  67  ssb-y                                  += driver_chipcommon.o
  68  ssb-y                                  += driver_chipcommon_pmu.o
  69 +ssb-$(CONFIG_SSB_SFLASH)               += driver_chipcommon_sflash.o
  70  ssb-$(CONFIG_SSB_DRIVER_MIPS)          += driver_mipscore.o
  71  ssb-$(CONFIG_SSB_DRIVER_EXTIF)         += driver_extif.o
  72  ssb-$(CONFIG_SSB_DRIVER_PCICORE)       += driver_pcicore.o
  73  ssb-$(CONFIG_SSB_DRIVER_GIGE)          += driver_gige.o
  74 +ssb-$(CONFIG_SSB_DRIVER_GPIO)          += driver_gpio.o
  75
  76  # b43 pci-ssb-bridge driver
  77  # Not strictly a part of SSB, but kept here for convenience
  78 --- a/drivers/ssb/b43_pci_bridge.c
  79 +++ b/drivers/ssb/b43_pci_bridge.c
  80 @@ -37,6 +37,7 @@ static const struct pci_device_id b43_pc
  81         { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4329) },
  82         { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x432b) },
  83         { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x432c) },
  84 +       { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4350) },
  85         { 0, },
  86  };
  87  MODULE_DEVICE_TABLE(pci, b43_pci_bridge_tbl);
  88 --- a/drivers/ssb/driver_chipcommon.c
  89 +++ b/drivers/ssb/driver_chipcommon.c
  90 @@ -4,6 +4,7 @@
  91   *
  92   * Copyright 2005, Broadcom Corporation
  93   * Copyright 2006, 2007, Michael Buesch <m@bues.ch>
  94 + * Copyright 2012, Hauke Mehrtens <hauke@hauke-m.de>
  95   *
  96   * Licensed under the GNU/GPL. See COPYING for details.
  97   */
  98 @@ -12,6 +13,7 @@
  99  #include <linux/ssb/ssb_regs.h>
 100  #include <linux/export.h>
 101  #include <linux/pci.h>
 102 +#include <linux/bcm47xx_wdt.h>
 103
 104  #include "ssb_private.h"
 105
 106 @@ -280,13 +282,79 @@ static void calc_fast_powerup_delay(stru
 107         cc->fast_pwrup_delay = tmp;
 108  }
 109
 110 +static u32 ssb_chipco_alp_clock(struct ssb_chipcommon *cc)
 111 +{
 112 +       if (cc->capabilities & SSB_CHIPCO_CAP_PMU)
 113 +               return ssb_pmu_get_alp_clock(cc);
 114 +
 115 +       return 20000000;
 116 +}
 117 +
 118 +static u32 ssb_chipco_watchdog_get_max_timer(struct ssb_chipcommon *cc)
 119 +{
 120 +       u32 nb;
 121 +
 122 +       if (cc->capabilities & SSB_CHIPCO_CAP_PMU) {
 123 +               if (cc->dev->id.revision < 26)
 124 +                       nb = 16;
 125 +               else
 126 +                       nb = (cc->dev->id.revision >= 37) ? 32 : 24;
 127 +       } else {
 128 +               nb = 28;
 129 +       }
 130 +       if (nb == 32)
 131 +               return 0xffffffff;
 132 +       else
 133 +               return (1 << nb) - 1;
 134 +}
 135 +
 136 +u32 ssb_chipco_watchdog_timer_set_wdt(struct bcm47xx_wdt *wdt, u32 ticks)
 137 +{
 138 +       struct ssb_chipcommon *cc = bcm47xx_wdt_get_drvdata(wdt);
 139 +
 140 +       if (cc->dev->bus->bustype != SSB_BUSTYPE_SSB)
 141 +               return 0;
 142 +
 143 +       return ssb_chipco_watchdog_timer_set(cc, ticks);
 144 +}
 145 +
 146 +u32 ssb_chipco_watchdog_timer_set_ms(struct bcm47xx_wdt *wdt, u32 ms)
 147 +{
 148 +       struct ssb_chipcommon *cc = bcm47xx_wdt_get_drvdata(wdt);
 149 +       u32 ticks;
 150 +
 151 +       if (cc->dev->bus->bustype != SSB_BUSTYPE_SSB)
 152 +               return 0;
 153 +
 154 +       ticks = ssb_chipco_watchdog_timer_set(cc, cc->ticks_per_ms * ms);
 155 +       return ticks / cc->ticks_per_ms;
 156 +}
 157 +
 158 +static int ssb_chipco_watchdog_ticks_per_ms(struct ssb_chipcommon *cc)
 159 +{
 160 +       struct ssb_bus *bus = cc->dev->bus;
 161 +
 162 +       if (cc->capabilities & SSB_CHIPCO_CAP_PMU) {
 163 +                       /* based on 32KHz ILP clock */
 164 +                       return 32;
 165 +       } else {
 166 +               if (cc->dev->id.revision < 18)
 167 +                       return ssb_clockspeed(bus) / 1000;
 168 +               else
 169 +                       return ssb_chipco_alp_clock(cc) / 1000;
 170 +       }
 171 +}
 172 +
 173  void ssb_chipcommon_init(struct ssb_chipcommon *cc)
 174  {
 175         if (!cc->dev)
 176                 return; /* We don't have a ChipCommon */
 177 +
 178 +       spin_lock_init(&cc->gpio_lock);
 179 +
 180         if (cc->dev->id.revision >= 11)
 181                 cc->status = chipco_read32(cc, SSB_CHIPCO_CHIPSTAT);
 182 -       ssb_dprintk(KERN_INFO PFX "chipcommon status is 0x%x\n", cc->status);
 183 +       ssb_dbg("chipcommon status is 0x%x\n", cc->status);
 184
 185         if (cc->dev->id.revision >= 20) {
 186                 chipco_write32(cc, SSB_CHIPCO_GPIOPULLUP, 0);
 187 @@ -297,6 +365,11 @@ void ssb_chipcommon_init(struct ssb_chip
 188         chipco_powercontrol_init(cc);
 189         ssb_chipco_set_clockmode(cc, SSB_CLKMODE_FAST);
 190         calc_fast_powerup_delay(cc);
 191 +
 192 +       if (cc->dev->bus->bustype == SSB_BUSTYPE_SSB) {
 193 +               cc->ticks_per_ms = ssb_chipco_watchdog_ticks_per_ms(cc);
 194 +               cc->max_timer_ms = ssb_chipco_watchdog_get_max_timer(cc) / cc->ticks_per_ms;
 195 +       }
 196  }
 197
 198  void ssb_chipco_suspend(struct ssb_chipcommon *cc)
 199 @@ -395,10 +468,27 @@ void ssb_chipco_timing_init(struct ssb_c
 200  }
 201
 202  /* Set chip watchdog reset timer to fire in 'ticks' backplane cycles */
 203 -void ssb_chipco_watchdog_timer_set(struct ssb_chipcommon *cc, u32 ticks)
 204 +u32 ssb_chipco_watchdog_timer_set(struct ssb_chipcommon *cc, u32 ticks)
 205  {
 206 -       /* instant NMI */
 207 -       chipco_write32(cc, SSB_CHIPCO_WATCHDOG, ticks);
 208 +       u32 maxt;
 209 +       enum ssb_clkmode clkmode;
 210 +
 211 +       maxt = ssb_chipco_watchdog_get_max_timer(cc);
 212 +       if (cc->capabilities & SSB_CHIPCO_CAP_PMU) {
 213 +               if (ticks == 1)
 214 +                       ticks = 2;
 215 +               else if (ticks > maxt)
 216 +                       ticks = maxt;
 217 +               chipco_write32(cc, SSB_CHIPCO_PMU_WATCHDOG, ticks);
 218 +       } else {
 219 +               clkmode = ticks ? SSB_CLKMODE_FAST : SSB_CLKMODE_DYNAMIC;
 220 +               ssb_chipco_set_clockmode(cc, clkmode);
 221 +               if (ticks > maxt)
 222 +                       ticks = maxt;
 223 +               /* instant NMI */
 224 +               chipco_write32(cc, SSB_CHIPCO_WATCHDOG, ticks);
 225 +       }
 226 +       return ticks;
 227  }
 228
 229  void ssb_chipco_irq_mask(struct ssb_chipcommon *cc, u32 mask, u32 value)
 230 @@ -418,28 +508,93 @@ u32 ssb_chipco_gpio_in(struct ssb_chipco
 231
 232  u32 ssb_chipco_gpio_out(struct ssb_chipcommon *cc, u32 mask, u32 value)
 233  {
 234 -       return chipco_write32_masked(cc, SSB_CHIPCO_GPIOOUT, mask, value);
 235 +       unsigned long flags;
 236 +       u32 res = 0;
 237 +
 238 +       spin_lock_irqsave(&cc->gpio_lock, flags);
 239 +       res = chipco_write32_masked(cc, SSB_CHIPCO_GPIOOUT, mask, value);
 240 +       spin_unlock_irqrestore(&cc->gpio_lock, flags);
 241 +
 242 +       return res;
 243  }
 244
 245  u32 ssb_chipco_gpio_outen(struct ssb_chipcommon *cc, u32 mask, u32 value)
 246  {
 247 -       return chipco_write32_masked(cc, SSB_CHIPCO_GPIOOUTEN, mask, value);
 248 +       unsigned long flags;
 249 +       u32 res = 0;
 250 +
 251 +       spin_lock_irqsave(&cc->gpio_lock, flags);
 252 +       res = chipco_write32_masked(cc, SSB_CHIPCO_GPIOOUTEN, mask, value);
 253 +       spin_unlock_irqrestore(&cc->gpio_lock, flags);
 254 +
 255 +       return res;
 256  }
 257
 258  u32 ssb_chipco_gpio_control(struct ssb_chipcommon *cc, u32 mask, u32 value)
 259  {
 260 -       return chipco_write32_masked(cc, SSB_CHIPCO_GPIOCTL, mask, value);
 261 +       unsigned long flags;
 262 +       u32 res = 0;
 263 +
 264 +       spin_lock_irqsave(&cc->gpio_lock, flags);
 265 +       res = chipco_write32_masked(cc, SSB_CHIPCO_GPIOCTL, mask, value);
 266 +       spin_unlock_irqrestore(&cc->gpio_lock, flags);
 267 +
 268 +       return res;
 269  }
 270  EXPORT_SYMBOL(ssb_chipco_gpio_control);
 271
 272  u32 ssb_chipco_gpio_intmask(struct ssb_chipcommon *cc, u32 mask, u32 value)
 273  {
 274 -       return chipco_write32_masked(cc, SSB_CHIPCO_GPIOIRQ, mask, value);
 275 +       unsigned long flags;
 276 +       u32 res = 0;
 277 +
 278 +       spin_lock_irqsave(&cc->gpio_lock, flags);
 279 +       res = chipco_write32_masked(cc, SSB_CHIPCO_GPIOIRQ, mask, value);
 280 +       spin_unlock_irqrestore(&cc->gpio_lock, flags);
 281 +
 282 +       return res;
 283  }
 284
 285  u32 ssb_chipco_gpio_polarity(struct ssb_chipcommon *cc, u32 mask, u32 value)
 286  {
 287 -       return chipco_write32_masked(cc, SSB_CHIPCO_GPIOPOL, mask, value);
 288 +       unsigned long flags;
 289 +       u32 res = 0;
 290 +
 291 +       spin_lock_irqsave(&cc->gpio_lock, flags);
 292 +       res = chipco_write32_masked(cc, SSB_CHIPCO_GPIOPOL, mask, value);
 293 +       spin_unlock_irqrestore(&cc->gpio_lock, flags);
 294 +
 295 +       return res;
 296 +}
 297 +
 298 +u32 ssb_chipco_gpio_pullup(struct ssb_chipcommon *cc, u32 mask, u32 value)
 299 +{
 300 +       unsigned long flags;
 301 +       u32 res = 0;
 302 +
 303 +       if (cc->dev->id.revision < 20)
 304 +               return 0xffffffff;
 305 +
 306 +       spin_lock_irqsave(&cc->gpio_lock, flags);
 307 +       res = chipco_write32_masked(cc, SSB_CHIPCO_GPIOPULLUP, mask, value);
 308 +       spin_unlock_irqrestore(&cc->gpio_lock, flags);
 309 +
 310 +       return res;
 311 +}
 312 +
 313 +u32 ssb_chipco_gpio_pulldown(struct ssb_chipcommon *cc, u32 mask, u32 value)
 314 +{
 315 +       unsigned long flags;
 316 +       u32 res = 0;
 317 +
 318 +       if (cc->dev->id.revision < 20)
 319 +               return 0xffffffff;
 320 +
 321 +       spin_lock_irqsave(&cc->gpio_lock, flags);
 322 +       res = chipco_write32_masked(cc, SSB_CHIPCO_GPIOPULLDOWN, mask, value);
 323 +       spin_unlock_irqrestore(&cc->gpio_lock, flags);
 324 +
 325 +       return res;
 326  }
 327
 328  #ifdef CONFIG_SSB_SERIAL
 329 @@ -473,12 +628,7 @@ int ssb_chipco_serial_init(struct ssb_ch
 330                                        chipco_read32(cc, SSB_CHIPCO_CORECTL)
 331                                        | SSB_CHIPCO_CORECTL_UARTCLK0);
 332                 } else if ((ccrev >= 11) && (ccrev != 15)) {
 333 -                       /* Fixed ALP clock */
 334 -                       baud_base = 20000000;
 335 -                       if (cc->capabilities & SSB_CHIPCO_CAP_PMU) {
 336 -                               /* FIXME: baud_base is different for devices with a PMU */
 337 -                               SSB_WARN_ON(1);
 338 -                       }
 339 +                       baud_base = ssb_chipco_alp_clock(cc);
 340                         div = 1;
 341                         if (ccrev >= 21) {
 342                                 /* Turn off UART clock before switching clocksource. */
 343 --- a/drivers/ssb/driver_chipcommon_pmu.c
 344 +++ b/drivers/ssb/driver_chipcommon_pmu.c
 345 @@ -110,8 +110,8 @@ static void ssb_pmu0_pllinit_r0(struct s
 346                 return;
 347         }
 348
 349 -       ssb_printk(KERN_INFO PFX "Programming PLL to %u.%03u MHz\n",
 350 -                  (crystalfreq / 1000), (crystalfreq % 1000));
 351 +       ssb_info("Programming PLL to %u.%03u MHz\n",
 352 +                crystalfreq / 1000, crystalfreq % 1000);
 353
 354         /* First turn the PLL off. */
 355         switch (bus->chip_id) {
 356 @@ -138,7 +138,7 @@ static void ssb_pmu0_pllinit_r0(struct s
 357         }
 358         tmp = chipco_read32(cc, SSB_CHIPCO_CLKCTLST);
 359         if (tmp & SSB_CHIPCO_CLKCTLST_HAVEHT)
 360 -               ssb_printk(KERN_EMERG PFX "Failed to turn the PLL off!\n");
 361 +               ssb_emerg("Failed to turn the PLL off!\n");
 362
 363         /* Set PDIV in PLL control 0. */
 364         pllctl = ssb_chipco_pll_read(cc, SSB_PMU0_PLLCTL0);
 365 @@ -249,8 +249,8 @@ static void ssb_pmu1_pllinit_r0(struct s
 366                 return;
 367         }
 368
 369 -       ssb_printk(KERN_INFO PFX "Programming PLL to %u.%03u MHz\n",
 370 -                  (crystalfreq / 1000), (crystalfreq % 1000));
 371 +       ssb_info("Programming PLL to %u.%03u MHz\n",
 372 +                crystalfreq / 1000, crystalfreq % 1000);
 373
 374         /* First turn the PLL off. */
 375         switch (bus->chip_id) {
 376 @@ -275,7 +275,7 @@ static void ssb_pmu1_pllinit_r0(struct s
 377         }
 378         tmp = chipco_read32(cc, SSB_CHIPCO_CLKCTLST);
 379         if (tmp & SSB_CHIPCO_CLKCTLST_HAVEHT)
 380 -               ssb_printk(KERN_EMERG PFX "Failed to turn the PLL off!\n");
 381 +               ssb_emerg("Failed to turn the PLL off!\n");
 382
 383         /* Set p1div and p2div. */
 384         pllctl = ssb_chipco_pll_read(cc, SSB_PMU1_PLLCTL0);
 385 @@ -346,10 +346,11 @@ static void ssb_pmu_pll_init(struct ssb_
 386                         chipco_write32(cc, SSB_CHIPCO_PLLCTL_DATA, 0x380005C0);
 387                 }
 388                 break;
 389 +       case 43222:
 390 +               break;
 391         default:
 392 -               ssb_printk(KERN_ERR PFX
 393 -                          "ERROR: PLL init unknown for device %04X\n",
 394 -                          bus->chip_id);
 395 +               ssb_err("ERROR: PLL init unknown for device %04X\n",
 396 +                       bus->chip_id);
 397         }
 398  }
 399
 400 @@ -434,6 +435,7 @@ static void ssb_pmu_resources_init(struc
 401                  min_msk = 0xCBB;
 402                  break;
 403         case 0x4322:
 404 +       case 43222:
 405                 /* We keep the default settings:
 406                  * min_msk = 0xCBB
 407                  * max_msk = 0x7FFFF
 408 @@ -469,9 +471,8 @@ static void ssb_pmu_resources_init(struc
 409                 max_msk = 0xFFFFF;
 410                 break;
 411         default:
 412 -               ssb_printk(KERN_ERR PFX
 413 -                          "ERROR: PMU resource config unknown for device %04X\n",
 414 -                          bus->chip_id);
 415 +               ssb_err("ERROR: PMU resource config unknown for device %04X\n",
 416 +                       bus->chip_id);
 417         }
 418
 419         if (updown_tab) {
 420 @@ -523,8 +524,8 @@ void ssb_pmu_init(struct ssb_chipcommon
 421         pmucap = chipco_read32(cc, SSB_CHIPCO_PMU_CAP);
 422         cc->pmu.rev = (pmucap & SSB_CHIPCO_PMU_CAP_REVISION);
 423
 424 -       ssb_dprintk(KERN_DEBUG PFX "Found rev %u PMU (capabilities 0x%08X)\n",
 425 -                   cc->pmu.rev, pmucap);
 426 +       ssb_dbg("Found rev %u PMU (capabilities 0x%08X)\n",
 427 +               cc->pmu.rev, pmucap);
 428
 429         if (cc->pmu.rev == 1)
 430                 chipco_mask32(cc, SSB_CHIPCO_PMU_CTL,
 431 @@ -615,6 +616,32 @@ void ssb_pmu_set_ldo_paref(struct ssb_ch
 432  EXPORT_SYMBOL(ssb_pmu_set_ldo_voltage);
 433  EXPORT_SYMBOL(ssb_pmu_set_ldo_paref);
 434
 435 +static u32 ssb_pmu_get_alp_clock_clk0(struct ssb_chipcommon *cc)
 436 +{
 437 +       u32 crystalfreq;
 438 +       const struct pmu0_plltab_entry *e = NULL;
 439 +
 440 +       crystalfreq = chipco_read32(cc, SSB_CHIPCO_PMU_CTL) &
 441 +                     SSB_CHIPCO_PMU_CTL_XTALFREQ >> SSB_CHIPCO_PMU_CTL_XTALFREQ_SHIFT;
 442 +       e = pmu0_plltab_find_entry(crystalfreq);
 443 +       BUG_ON(!e);
 444 +       return e->freq * 1000;
 445 +}
 446 +
 447 +u32 ssb_pmu_get_alp_clock(struct ssb_chipcommon *cc)
 448 +{
 449 +       struct ssb_bus *bus = cc->dev->bus;
 450 +
 451 +       switch (bus->chip_id) {
 452 +       case 0x5354:
 453 +               ssb_pmu_get_alp_clock_clk0(cc);
 454 +       default:
 455 +               ssb_err("ERROR: PMU alp clock unknown for device %04X\n",
 456 +                       bus->chip_id);
 457 +               return 0;
 458 +       }
 459 +}
 460 +
 461  u32 ssb_pmu_get_cpu_clock(struct ssb_chipcommon *cc)
 462  {
 463         struct ssb_bus *bus = cc->dev->bus;
 464 @@ -624,9 +651,8 @@ u32 ssb_pmu_get_cpu_clock(struct ssb_chi
 465                 /* 5354 chip uses a non programmable PLL of frequency 240MHz */
 466                 return 240000000;
 467         default:
 468 -               ssb_printk(KERN_ERR PFX
 469 -                          "ERROR: PMU cpu clock unknown for device %04X\n",
 470 -                          bus->chip_id);
 471 +               ssb_err("ERROR: PMU cpu clock unknown for device %04X\n",
 472 +                       bus->chip_id);
 473                 return 0;
 474         }
 475  }
 476 @@ -639,9 +665,52 @@ u32 ssb_pmu_get_controlclock(struct ssb_
 477         case 0x5354:
 478                 return 120000000;
 479         default:
 480 -               ssb_printk(KERN_ERR PFX
 481 -                          "ERROR: PMU controlclock unknown for device %04X\n",
 482 -                          bus->chip_id);
 483 +               ssb_err("ERROR: PMU controlclock unknown for device %04X\n",
 484 +                       bus->chip_id);
 485                 return 0;
 486         }
 487  }
 488 +
 489 +void ssb_pmu_spuravoid_pllupdate(struct ssb_chipcommon *cc, int spuravoid)
 490 +{
 491 +       u32 pmu_ctl = 0;
 492 +
 493 +       switch (cc->dev->bus->chip_id) {
 494 +       case 0x4322:
 495 +               ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL0, 0x11100070);
 496 +               ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL1, 0x1014140a);
 497 +               ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL5, 0x88888854);
 498 +               if (spuravoid == 1)
 499 +                       ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL2, 0x05201828);
 500 +               else
 501 +                       ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL2, 0x05001828);
 502 +               pmu_ctl = SSB_CHIPCO_PMU_CTL_PLL_UPD;
 503 +               break;
 504 +       case 43222:
 505 +               if (spuravoid == 1) {
 506 +                       ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL0, 0x11500008);
 507 +                       ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL1, 0x0C000C06);
 508 +                       ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL2, 0x0F600a08);
 509 +                       ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL3, 0x00000000);
 510 +                       ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL4, 0x2001E920);
 511 +                       ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL5, 0x88888815);
 512 +               } else {
 513 +                       ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL0, 0x11100008);
 514 +                       ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL1, 0x0c000c06);
 515 +                       ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL2, 0x03000a08);
 516 +                       ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL3, 0x00000000);
 517 +                       ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL4, 0x200005c0);
 518 +                       ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL5, 0x88888855);
 519 +               }
 520 +               pmu_ctl = SSB_CHIPCO_PMU_CTL_PLL_UPD;
 521 +               break;
 522 +       default:
 523 +               ssb_printk(KERN_ERR PFX
 524 +                          "Unknown spuravoidance settings for chip 0x%04X, not changing PLL\n",
 525 +                          cc->dev->bus->chip_id);
 526 +               return;
 527 +       }
 528 +
 529 +       chipco_set32(cc, SSB_CHIPCO_PMU_CTL, pmu_ctl);
 530 +}
 531 +EXPORT_SYMBOL_GPL(ssb_pmu_spuravoid_pllupdate);
 532 --- /dev/null
 533 +++ b/drivers/ssb/driver_chipcommon_sflash.c
 534 @@ -0,0 +1,166 @@
 535 +/*
 536 + * Sonics Silicon Backplane
 537 + * ChipCommon serial flash interface
 538 + *
 539 + * Licensed under the GNU/GPL. See COPYING for details.
 540 + */
 541 +
 542 +#include <linux/ssb/ssb.h>
 543 +
 544 +#include "ssb_private.h"
 545 +
 546 +static struct resource ssb_sflash_resource = {
 547 +       .name   = "ssb_sflash",
 548 +       .start  = SSB_FLASH2,
 549 +       .end    = 0,
 550 +       .flags  = IORESOURCE_MEM | IORESOURCE_READONLY,
 551 +};
 552 +
 553 +struct platform_device ssb_sflash_dev = {
 554 +       .name           = "ssb_sflash",
 555 +       .resource       = &ssb_sflash_resource,
 556 +       .num_resources  = 1,
 557 +};
 558 +
 559 +struct ssb_sflash_tbl_e {
 560 +       char *name;
 561 +       u32 id;
 562 +       u32 blocksize;
 563 +       u16 numblocks;
 564 +};
 565 +
 566 +static const struct ssb_sflash_tbl_e ssb_sflash_st_tbl[] = {
 567 +       { "M25P20", 0x11, 0x10000, 4, },
 568 +       { "M25P40", 0x12, 0x10000, 8, },
 569 +
 570 +       { "M25P16", 0x14, 0x10000, 32, },
 571 +       { "M25P32", 0x15, 0x10000, 64, },
 572 +       { "M25P64", 0x16, 0x10000, 128, },
 573 +       { "M25FL128", 0x17, 0x10000, 256, },
 574 +       { 0 },
 575 +};
 576 +
 577 +static const struct ssb_sflash_tbl_e ssb_sflash_sst_tbl[] = {
 578 +       { "SST25WF512", 1, 0x1000, 16, },
 579 +       { "SST25VF512", 0x48, 0x1000, 16, },
 580 +       { "SST25WF010", 2, 0x1000, 32, },
 581 +       { "SST25VF010", 0x49, 0x1000, 32, },
 582 +       { "SST25WF020", 3, 0x1000, 64, },
 583 +       { "SST25VF020", 0x43, 0x1000, 64, },
 584 +       { "SST25WF040", 4, 0x1000, 128, },
 585 +       { "SST25VF040", 0x44, 0x1000, 128, },
 586 +       { "SST25VF040B", 0x8d, 0x1000, 128, },
 587 +       { "SST25WF080", 5, 0x1000, 256, },
 588 +       { "SST25VF080B", 0x8e, 0x1000, 256, },
 589 +       { "SST25VF016", 0x41, 0x1000, 512, },
 590 +       { "SST25VF032", 0x4a, 0x1000, 1024, },
 591 +       { "SST25VF064", 0x4b, 0x1000, 2048, },
 592 +       { 0 },
 593 +};
 594 +
 595 +static const struct ssb_sflash_tbl_e ssb_sflash_at_tbl[] = {
 596 +       { "AT45DB011", 0xc, 256, 512, },
 597 +       { "AT45DB021", 0x14, 256, 1024, },
 598 +       { "AT45DB041", 0x1c, 256, 2048, },
 599 +       { "AT45DB081", 0x24, 256, 4096, },
 600 +       { "AT45DB161", 0x2c, 512, 4096, },
 601 +       { "AT45DB321", 0x34, 512, 8192, },
 602 +       { "AT45DB642", 0x3c, 1024, 8192, },
 603 +       { 0 },
 604 +};
 605 +
 606 +static void ssb_sflash_cmd(struct ssb_chipcommon *cc, u32 opcode)
 607 +{
 608 +       int i;
 609 +       chipco_write32(cc, SSB_CHIPCO_FLASHCTL,
 610 +                      SSB_CHIPCO_FLASHCTL_START | opcode);
 611 +       for (i = 0; i < 1000; i++) {
 612 +               if (!(chipco_read32(cc, SSB_CHIPCO_FLASHCTL) &
 613 +                     SSB_CHIPCO_FLASHCTL_BUSY))
 614 +                       return;
 615 +               cpu_relax();
 616 +       }
 617 +       pr_err("SFLASH control command failed (timeout)!\n");
 618 +}
 619 +
 620 +/* Initialize serial flash access */
 621 +int ssb_sflash_init(struct ssb_chipcommon *cc)
 622 +{
 623 +       struct ssb_sflash *sflash = &cc->dev->bus->mipscore.sflash;
 624 +       const struct ssb_sflash_tbl_e *e;
 625 +       u32 id, id2;
 626 +
 627 +       switch (cc->capabilities & SSB_CHIPCO_CAP_FLASHT) {
 628 +       case SSB_CHIPCO_FLASHT_STSER:
 629 +               ssb_sflash_cmd(cc, SSB_CHIPCO_FLASHCTL_ST_DP);
 630 +
 631 +               chipco_write32(cc, SSB_CHIPCO_FLASHADDR, 0);
 632 +               ssb_sflash_cmd(cc, SSB_CHIPCO_FLASHCTL_ST_RES);
 633 +               id = chipco_read32(cc, SSB_CHIPCO_FLASHDATA);
 634 +
 635 +               chipco_write32(cc, SSB_CHIPCO_FLASHADDR, 1);
 636 +               ssb_sflash_cmd(cc, SSB_CHIPCO_FLASHCTL_ST_RES);
 637 +               id2 = chipco_read32(cc, SSB_CHIPCO_FLASHDATA);
 638 +
 639 +               switch (id) {
 640 +               case 0xbf:
 641 +                       for (e = ssb_sflash_sst_tbl; e->name; e++) {
 642 +                               if (e->id == id2)
 643 +                                       break;
 644 +                       }
 645 +                       break;
 646 +               case 0x13:
 647 +                       return -ENOTSUPP;
 648 +               default:
 649 +                       for (e = ssb_sflash_st_tbl; e->name; e++) {
 650 +                               if (e->id == id)
 651 +                                       break;
 652 +                       }
 653 +                       break;
 654 +               }
 655 +               if (!e->name) {
 656 +                       pr_err("Unsupported ST serial flash (id: 0x%X, id2: 0x%X)\n",
 657 +                              id, id2);
 658 +                       return -ENOTSUPP;
 659 +               }
 660 +
 661 +               break;
 662 +       case SSB_CHIPCO_FLASHT_ATSER:
 663 +               ssb_sflash_cmd(cc, SSB_CHIPCO_FLASHCTL_AT_STATUS);
 664 +               id = chipco_read32(cc, SSB_CHIPCO_FLASHDATA) & 0x3c;
 665 +
 666 +               for (e = ssb_sflash_at_tbl; e->name; e++) {
 667 +                       if (e->id == id)
 668 +                               break;
 669 +               }
 670 +               if (!e->name) {
 671 +                       pr_err("Unsupported Atmel serial flash (id: 0x%X)\n",
 672 +                              id);
 673 +                       return -ENOTSUPP;
 674 +               }
 675 +
 676 +               break;
 677 +       default:
 678 +               pr_err("Unsupported flash type\n");
 679 +               return -ENOTSUPP;
 680 +       }
 681 +
 682 +       sflash->window = SSB_FLASH2;
 683 +       sflash->blocksize = e->blocksize;
 684 +       sflash->numblocks = e->numblocks;
 685 +       sflash->size = sflash->blocksize * sflash->numblocks;
 686 +       sflash->present = true;
 687 +
 688 +       pr_info("Found %s serial flash (blocksize: 0x%X, blocks: %d)\n",
 689 +               e->name, e->blocksize, e->numblocks);
 690 +
 691 +       /* Prepare platform device, but don't register it yet. It's too early,
 692 +        * malloc (required by device_private_init) is not available yet. */
 693 +       ssb_sflash_dev.resource[0].end = ssb_sflash_dev.resource[0].start +
 694 +                                        sflash->size;
 695 +       ssb_sflash_dev.dev.platform_data = sflash;
 696 +
 697 +       pr_err("Serial flash support is not implemented yet!\n");
 698 +
 699 +       return -ENOTSUPP;
 700 +}
 701 --- a/drivers/ssb/driver_extif.c
 702 +++ b/drivers/ssb/driver_extif.c
 703 @@ -112,10 +112,37 @@ void ssb_extif_get_clockcontrol(struct s
 704         *m = extif_read32(extif, SSB_EXTIF_CLOCK_SB);
 705  }
 706
 707 -void ssb_extif_watchdog_timer_set(struct ssb_extif *extif,
 708 -                                 u32 ticks)
 709 +u32 ssb_extif_watchdog_timer_set_wdt(struct bcm47xx_wdt *wdt, u32 ticks)
 710  {
 711 +       struct ssb_extif *extif = bcm47xx_wdt_get_drvdata(wdt);
 712 +
 713 +       return ssb_extif_watchdog_timer_set(extif, ticks);
 714 +}
 715 +
 716 +u32 ssb_extif_watchdog_timer_set_ms(struct bcm47xx_wdt *wdt, u32 ms)
 717 +{
 718 +       struct ssb_extif *extif = bcm47xx_wdt_get_drvdata(wdt);
 719 +       u32 ticks = (SSB_EXTIF_WATCHDOG_CLK / 1000) * ms;
 720 +
 721 +       ticks = ssb_extif_watchdog_timer_set(extif, ticks);
 722 +
 723 +       return (ticks * 1000) / SSB_EXTIF_WATCHDOG_CLK;
 724 +}
 725 +
 726 +u32 ssb_extif_watchdog_timer_set(struct ssb_extif *extif, u32 ticks)
 727 +{
 728 +       if (ticks > SSB_EXTIF_WATCHDOG_MAX_TIMER)
 729 +               ticks = SSB_EXTIF_WATCHDOG_MAX_TIMER;
 730         extif_write32(extif, SSB_EXTIF_WATCHDOG, ticks);
 731 +
 732 +       return ticks;
 733 +}
 734 +
 735 +void ssb_extif_init(struct ssb_extif *extif)
 736 +{
 737 +       if (!extif->dev)
 738 +               return; /* We don't have a Extif core */
 739 +       spin_lock_init(&extif->gpio_lock);
 740  }
 741
 742  u32 ssb_extif_gpio_in(struct ssb_extif *extif, u32 mask)
 743 @@ -125,22 +152,50 @@ u32 ssb_extif_gpio_in(struct ssb_extif *
 744
 745  u32 ssb_extif_gpio_out(struct ssb_extif *extif, u32 mask, u32 value)
 746  {
 747 -       return extif_write32_masked(extif, SSB_EXTIF_GPIO_OUT(0),
 748 +       unsigned long flags;
 749 +       u32 res = 0;
 750 +
 751 +       spin_lock_irqsave(&extif->gpio_lock, flags);
 752 +       res = extif_write32_masked(extif, SSB_EXTIF_GPIO_OUT(0),
 753                                    mask, value);
 754 +       spin_unlock_irqrestore(&extif->gpio_lock, flags);
 755 +
 756 +       return res;
 757  }
 758
 759  u32 ssb_extif_gpio_outen(struct ssb_extif *extif, u32 mask, u32 value)
 760  {
 761 -       return extif_write32_masked(extif, SSB_EXTIF_GPIO_OUTEN(0),
 762 +       unsigned long flags;
 763 +       u32 res = 0;
 764 +
 765 +       spin_lock_irqsave(&extif->gpio_lock, flags);
 766 +       res = extif_write32_masked(extif, SSB_EXTIF_GPIO_OUTEN(0),
 767                                    mask, value);
 768 +       spin_unlock_irqrestore(&extif->gpio_lock, flags);
 769 +
 770 +       return res;
 771  }
 772
 773  u32 ssb_extif_gpio_polarity(struct ssb_extif *extif, u32 mask, u32 value)
 774  {
 775 -       return extif_write32_masked(extif, SSB_EXTIF_GPIO_INTPOL, mask, value);
 776 +       unsigned long flags;
 777 +       u32 res = 0;
 778 +
 779 +       spin_lock_irqsave(&extif->gpio_lock, flags);
 780 +       res = extif_write32_masked(extif, SSB_EXTIF_GPIO_INTPOL, mask, value);
 781 +       spin_unlock_irqrestore(&extif->gpio_lock, flags);
 782 +
 783 +       return res;
 784  }
 785
 786  u32 ssb_extif_gpio_intmask(struct ssb_extif *extif, u32 mask, u32 value)
 787  {
 788 -       return extif_write32_masked(extif, SSB_EXTIF_GPIO_INTMASK, mask, value);
 789 +       unsigned long flags;
 790 +       u32 res = 0;
 791 +
 792 +       spin_lock_irqsave(&extif->gpio_lock, flags);
 793 +       res = extif_write32_masked(extif, SSB_EXTIF_GPIO_INTMASK, mask, value);
 794 +       spin_unlock_irqrestore(&extif->gpio_lock, flags);
 795 +
 796 +       return res;
 797  }
 798 --- /dev/null
 799 +++ b/drivers/ssb/driver_gpio.c
 800 @@ -0,0 +1,210 @@
 801 +/*
 802 + * Sonics Silicon Backplane
 803 + * GPIO driver
 804 + *
 805 + * Copyright 2011, Broadcom Corporation
 806 + * Copyright 2012, Hauke Mehrtens <hauke@hauke-m.de>
 807 + *
 808 + * Licensed under the GNU/GPL. See COPYING for details.
 809 + */
 810 +
 811 +#include <linux/gpio.h>
 812 +#include <linux/export.h>
 813 +#include <linux/ssb/ssb.h>
 814 +
 815 +#include "ssb_private.h"
 816 +
 817 +static struct ssb_bus *ssb_gpio_get_bus(struct gpio_chip *chip)
 818 +{
 819 +       return container_of(chip, struct ssb_bus, gpio);
 820 +}
 821 +
 822 +static int ssb_gpio_chipco_get_value(struct gpio_chip *chip, unsigned gpio)
 823 +{
 824 +       struct ssb_bus *bus = ssb_gpio_get_bus(chip);
 825 +
 826 +       return !!ssb_chipco_gpio_in(&bus->chipco, 1 << gpio);
 827 +}
 828 +
 829 +static void ssb_gpio_chipco_set_value(struct gpio_chip *chip, unsigned gpio,
 830 +                                     int value)
 831 +{
 832 +       struct ssb_bus *bus = ssb_gpio_get_bus(chip);
 833 +
 834 +       ssb_chipco_gpio_out(&bus->chipco, 1 << gpio, value ? 1 << gpio : 0);
 835 +}
 836 +
 837 +static int ssb_gpio_chipco_direction_input(struct gpio_chip *chip,
 838 +                                          unsigned gpio)
 839 +{
 840 +       struct ssb_bus *bus = ssb_gpio_get_bus(chip);
 841 +
 842 +       ssb_chipco_gpio_outen(&bus->chipco, 1 << gpio, 0);
 843 +       return 0;
 844 +}
 845 +
 846 +static int ssb_gpio_chipco_direction_output(struct gpio_chip *chip,
 847 +                                           unsigned gpio, int value)
 848 +{
 849 +       struct ssb_bus *bus = ssb_gpio_get_bus(chip);
 850 +
 851 +       ssb_chipco_gpio_outen(&bus->chipco, 1 << gpio, 1 << gpio);
 852 +       ssb_chipco_gpio_out(&bus->chipco, 1 << gpio, value ? 1 << gpio : 0);
 853 +       return 0;
 854 +}
 855 +
 856 +static int ssb_gpio_chipco_request(struct gpio_chip *chip, unsigned gpio)
 857 +{
 858 +       struct ssb_bus *bus = ssb_gpio_get_bus(chip);
 859 +
 860 +       ssb_chipco_gpio_control(&bus->chipco, 1 << gpio, 0);
 861 +       /* clear pulldown */
 862 +       ssb_chipco_gpio_pulldown(&bus->chipco, 1 << gpio, 0);
 863 +       /* Set pullup */
 864 +       ssb_chipco_gpio_pullup(&bus->chipco, 1 << gpio, 1 << gpio);
 865 +
 866 +       return 0;
 867 +}
 868 +
 869 +static void ssb_gpio_chipco_free(struct gpio_chip *chip, unsigned gpio)
 870 +{
 871 +       struct ssb_bus *bus = ssb_gpio_get_bus(chip);
 872 +
 873 +       /* clear pullup */
 874 +       ssb_chipco_gpio_pullup(&bus->chipco, 1 << gpio, 0);
 875 +}
 876 +
 877 +static int ssb_gpio_chipco_to_irq(struct gpio_chip *chip, unsigned gpio)
 878 +{
 879 +       struct ssb_bus *bus = ssb_gpio_get_bus(chip);
 880 +
 881 +       if (bus->bustype == SSB_BUSTYPE_SSB)
 882 +               return ssb_mips_irq(bus->chipco.dev) + 2;
 883 +       else
 884 +               return -EINVAL;
 885 +}
 886 +
 887 +static int ssb_gpio_chipco_init(struct ssb_bus *bus)
 888 +{
 889 +       struct gpio_chip *chip = &bus->gpio;
 890 +
 891 +       chip->label             = "ssb_chipco_gpio";
 892 +       chip->owner             = THIS_MODULE;
 893 +       chip->request           = ssb_gpio_chipco_request;
 894 +       chip->free              = ssb_gpio_chipco_free;
 895 +       chip->get               = ssb_gpio_chipco_get_value;
 896 +       chip->set               = ssb_gpio_chipco_set_value;
 897 +       chip->direction_input   = ssb_gpio_chipco_direction_input;
 898 +       chip->direction_output  = ssb_gpio_chipco_direction_output;
 899 +       chip->to_irq            = ssb_gpio_chipco_to_irq;
 900 +       chip->ngpio             = 16;
 901 +       /* There is just one SoC in one device and its GPIO addresses should be
 902 +        * deterministic to address them more easily. The other buses could get
 903 +        * a random base number. */
 904 +       if (bus->bustype == SSB_BUSTYPE_SSB)
 905 +               chip->base              = 0;
 906 +       else
 907 +               chip->base              = -1;
 908 +
 909 +       return gpiochip_add(chip);
 910 +}
 911 +
 912 +#ifdef CONFIG_SSB_DRIVER_EXTIF
 913 +
 914 +static int ssb_gpio_extif_get_value(struct gpio_chip *chip, unsigned gpio)
 915 +{
 916 +       struct ssb_bus *bus = ssb_gpio_get_bus(chip);
 917 +
 918 +       return !!ssb_extif_gpio_in(&bus->extif, 1 << gpio);
 919 +}
 920 +
 921 +static void ssb_gpio_extif_set_value(struct gpio_chip *chip, unsigned gpio,
 922 +                                    int value)
 923 +{
 924 +       struct ssb_bus *bus = ssb_gpio_get_bus(chip);
 925 +
 926 +       ssb_extif_gpio_out(&bus->extif, 1 << gpio, value ? 1 << gpio : 0);
 927 +}
 928 +
 929 +static int ssb_gpio_extif_direction_input(struct gpio_chip *chip,
 930 +                                         unsigned gpio)
 931 +{
 932 +       struct ssb_bus *bus = ssb_gpio_get_bus(chip);
 933 +
 934 +       ssb_extif_gpio_outen(&bus->extif, 1 << gpio, 0);
 935 +       return 0;
 936 +}
 937 +
 938 +static int ssb_gpio_extif_direction_output(struct gpio_chip *chip,
 939 +                                          unsigned gpio, int value)
 940 +{
 941 +       struct ssb_bus *bus = ssb_gpio_get_bus(chip);
 942 +
 943 +       ssb_extif_gpio_outen(&bus->extif, 1 << gpio, 1 << gpio);
 944 +       ssb_extif_gpio_out(&bus->extif, 1 << gpio, value ? 1 << gpio : 0);
 945 +       return 0;
 946 +}
 947 +
 948 +static int ssb_gpio_extif_to_irq(struct gpio_chip *chip, unsigned gpio)
 949 +{
 950 +       struct ssb_bus *bus = ssb_gpio_get_bus(chip);
 951 +
 952 +       if (bus->bustype == SSB_BUSTYPE_SSB)
 953 +               return ssb_mips_irq(bus->extif.dev) + 2;
 954 +       else
 955 +               return -EINVAL;
 956 +}
 957 +
 958 +static int ssb_gpio_extif_init(struct ssb_bus *bus)
 959 +{
 960 +       struct gpio_chip *chip = &bus->gpio;
 961 +
 962 +       chip->label             = "ssb_extif_gpio";
 963 +       chip->owner             = THIS_MODULE;
 964 +       chip->get               = ssb_gpio_extif_get_value;
 965 +       chip->set               = ssb_gpio_extif_set_value;
 966 +       chip->direction_input   = ssb_gpio_extif_direction_input;
 967 +       chip->direction_output  = ssb_gpio_extif_direction_output;
 968 +       chip->to_irq            = ssb_gpio_extif_to_irq;
 969 +       chip->ngpio             = 5;
 970 +       /* There is just one SoC in one device and its GPIO addresses should be
 971 +        * deterministic to address them more easily. The other buses could get
 972 +        * a random base number. */
 973 +       if (bus->bustype == SSB_BUSTYPE_SSB)
 974 +               chip->base              = 0;
 975 +       else
 976 +               chip->base              = -1;
 977 +
 978 +       return gpiochip_add(chip);
 979 +}
 980 +
 981 +#else
 982 +static int ssb_gpio_extif_init(struct ssb_bus *bus)
 983 +{
 984 +       return -ENOTSUPP;
 985 +}
 986 +#endif
 987 +
 988 +int ssb_gpio_init(struct ssb_bus *bus)
 989 +{
 990 +       if (ssb_chipco_available(&bus->chipco))
 991 +               return ssb_gpio_chipco_init(bus);
 992 +       else if (ssb_extif_available(&bus->extif))
 993 +               return ssb_gpio_extif_init(bus);
 994 +       else
 995 +               SSB_WARN_ON(1);
 996 +
 997 +       return -1;
 998 +}
 999 +
1000 +int ssb_gpio_unregister(struct ssb_bus *bus)
1001 +{
1002 +       if (ssb_chipco_available(&bus->chipco) ||
1003 +           ssb_extif_available(&bus->extif)) {
1004 +               return gpiochip_remove(&bus->gpio);
1005 +       } else {
1006 +               SSB_WARN_ON(1);
1007 +       }
1008 +
1009 +       return -1;
1010 +}
1011 --- a/drivers/ssb/driver_mipscore.c
1012 +++ b/drivers/ssb/driver_mipscore.c
1013 @@ -10,6 +10,7 @@
1014
1015  #include <linux/ssb/ssb.h>
1016
1017 +#include <linux/mtd/physmap.h>
1018  #include <linux/serial.h>
1019  #include <linux/serial_core.h>
1020  #include <linux/serial_reg.h>
1021 @@ -17,6 +18,25 @@
1022
1023  #include "ssb_private.h"
1024
1025 +static const char * const part_probes[] = { "bcm47xxpart", NULL };
1026 +
1027 +static struct physmap_flash_data ssb_pflash_data = {
1028 +       .part_probe_types       = part_probes,
1029 +};
1030 +
1031 +static struct resource ssb_pflash_resource = {
1032 +       .name   = "ssb_pflash",
1033 +       .flags  = IORESOURCE_MEM,
1034 +};
1035 +
1036 +struct platform_device ssb_pflash_dev = {
1037 +       .name           = "physmap-flash",
1038 +       .dev            = {
1039 +               .platform_data  = &ssb_pflash_data,
1040 +       },
1041 +       .resource       = &ssb_pflash_resource,
1042 +       .num_resources  = 1,
1043 +};
1044
1045  static inline u32 mips_read32(struct ssb_mipscore *mcore,
1046                               u16 offset)
1047 @@ -147,21 +167,22 @@ static void set_irq(struct ssb_device *d
1048                 irqflag |= (ipsflag & ~ipsflag_irq_mask[irq]);
1049                 ssb_write32(mdev, SSB_IPSFLAG, irqflag);
1050         }
1051 -       ssb_dprintk(KERN_INFO PFX
1052 -                   "set_irq: core 0x%04x, irq %d => %d\n",
1053 -                   dev->id.coreid, oldirq+2, irq+2);
1054 +       ssb_dbg("set_irq: core 0x%04x, irq %d => %d\n",
1055 +               dev->id.coreid, oldirq+2, irq+2);
1056  }
1057
1058  static void print_irq(struct ssb_device *dev, unsigned int irq)
1059  {
1060 -       int i;
1061         static const char *irq_name[] = {"2(S)", "3", "4", "5", "6", "D", "I"};
1062 -       ssb_dprintk(KERN_INFO PFX
1063 -               "core 0x%04x, irq :", dev->id.coreid);
1064 -       for (i = 0; i <= 6; i++) {
1065 -               ssb_dprintk(" %s%s", irq_name[i], i==irq?"*":" ");
1066 -       }
1067 -       ssb_dprintk("\n");
1068 +       ssb_dbg("core 0x%04x, irq : %s%s %s%s %s%s %s%s %s%s %s%s %s%s\n",
1069 +               dev->id.coreid,
1070 +               irq_name[0], irq == 0 ? "*" : " ",
1071 +               irq_name[1], irq == 1 ? "*" : " ",
1072 +               irq_name[2], irq == 2 ? "*" : " ",
1073 +               irq_name[3], irq == 3 ? "*" : " ",
1074 +               irq_name[4], irq == 4 ? "*" : " ",
1075 +               irq_name[5], irq == 5 ? "*" : " ",
1076 +               irq_name[6], irq == 6 ? "*" : " ");
1077  }
1078
1079  static void dump_irq(struct ssb_bus *bus)
1080 @@ -178,9 +199,9 @@ static void ssb_mips_serial_init(struct
1081  {
1082         struct ssb_bus *bus = mcore->dev->bus;
1083
1084 -       if (bus->extif.dev)
1085 +       if (ssb_extif_available(&bus->extif))
1086                 mcore->nr_serial_ports = ssb_extif_serial_init(&bus->extif, mcore->serial_ports);
1087 -       else if (bus->chipco.dev)
1088 +       else if (ssb_chipco_available(&bus->chipco))
1089                 mcore->nr_serial_ports = ssb_chipco_serial_init(&bus->chipco, mcore->serial_ports);
1090         else
1091                 mcore->nr_serial_ports = 0;
1092 @@ -189,17 +210,42 @@ static void ssb_mips_serial_init(struct
1093  static void ssb_mips_flash_detect(struct ssb_mipscore *mcore)
1094  {
1095         struct ssb_bus *bus = mcore->dev->bus;
1096 +       struct ssb_pflash *pflash = &mcore->pflash;
1097
1098 -       mcore->flash_buswidth = 2;
1099 -       if (bus->chipco.dev) {
1100 -               mcore->flash_window = 0x1c000000;
1101 -               mcore->flash_window_size = 0x02000000;
1102 +       /* When there is no chipcommon on the bus there is 4MB flash */
1103 +       if (!ssb_chipco_available(&bus->chipco)) {
1104 +               pflash->present = true;
1105 +               pflash->buswidth = 2;
1106 +               pflash->window = SSB_FLASH1;
1107 +               pflash->window_size = SSB_FLASH1_SZ;
1108 +               goto ssb_pflash;
1109 +       }
1110 +
1111 +       /* There is ChipCommon, so use it to read info about flash */
1112 +       switch (bus->chipco.capabilities & SSB_CHIPCO_CAP_FLASHT) {
1113 +       case SSB_CHIPCO_FLASHT_STSER:
1114 +       case SSB_CHIPCO_FLASHT_ATSER:
1115 +               pr_debug("Found serial flash\n");
1116 +               ssb_sflash_init(&bus->chipco);
1117 +               break;
1118 +       case SSB_CHIPCO_FLASHT_PARA:
1119 +               pr_debug("Found parallel flash\n");
1120 +               pflash->present = true;
1121 +               pflash->window = SSB_FLASH2;
1122 +               pflash->window_size = SSB_FLASH2_SZ;
1123                 if ((ssb_read32(bus->chipco.dev, SSB_CHIPCO_FLASH_CFG)
1124                                & SSB_CHIPCO_CFG_DS16) == 0)
1125 -                       mcore->flash_buswidth = 1;
1126 -       } else {
1127 -               mcore->flash_window = 0x1fc00000;
1128 -               mcore->flash_window_size = 0x00400000;
1129 +                       pflash->buswidth = 1;
1130 +               else
1131 +                       pflash->buswidth = 2;
1132 +               break;
1133 +       }
1134 +
1135 +ssb_pflash:
1136 +       if (pflash->present) {
1137 +               ssb_pflash_data.width = pflash->buswidth;
1138 +               ssb_pflash_resource.start = pflash->window;
1139 +               ssb_pflash_resource.end = pflash->window + pflash->window_size;
1140         }
1141  }
1142
1143 @@ -211,9 +257,9 @@ u32 ssb_cpu_clock(struct ssb_mipscore *m
1144         if (bus->chipco.capabilities & SSB_CHIPCO_CAP_PMU)
1145                 return ssb_pmu_get_cpu_clock(&bus->chipco);
1146
1147 -       if (bus->extif.dev) {
1148 +       if (ssb_extif_available(&bus->extif)) {
1149                 ssb_extif_get_clockcontrol(&bus->extif, &pll_type, &n, &m);
1150 -       } else if (bus->chipco.dev) {
1151 +       } else if (ssb_chipco_available(&bus->chipco)) {
1152                 ssb_chipco_get_clockcpu(&bus->chipco, &pll_type, &n, &m);
1153         } else
1154                 return 0;
1155 @@ -241,7 +287,7 @@ void ssb_mipscore_init(struct ssb_mipsco
1156         if (!mcore->dev)
1157                 return; /* We don't have a MIPS core */
1158
1159 -       ssb_dprintk(KERN_INFO PFX "Initializing MIPS core...\n");
1160 +       ssb_dbg("Initializing MIPS core...\n");
1161
1162         bus = mcore->dev->bus;
1163         hz = ssb_clockspeed(bus);
1164 @@ -249,9 +295,9 @@ void ssb_mipscore_init(struct ssb_mipsco
1165                 hz = 100000000;
1166         ns = 1000000000 / hz;
1167
1168 -       if (bus->extif.dev)
1169 +       if (ssb_extif_available(&bus->extif))
1170                 ssb_extif_timing_init(&bus->extif, ns);
1171 -       else if (bus->chipco.dev)
1172 +       else if (ssb_chipco_available(&bus->chipco))
1173                 ssb_chipco_timing_init(&bus->chipco, ns);
1174
1175         /* Assign IRQs to all cores on the bus, start with irq line 2, because serial usually takes 1 */
1176 @@ -289,7 +335,7 @@ void ssb_mipscore_init(struct ssb_mipsco
1177                         break;
1178                 }
1179         }
1180 -       ssb_dprintk(KERN_INFO PFX "after irq reconfiguration\n");
1181 +       ssb_dbg("after irq reconfiguration\n");
1182         dump_irq(bus);
1183
1184         ssb_mips_serial_init(mcore);
1185 --- a/drivers/ssb/driver_pcicore.c
1186 +++ b/drivers/ssb/driver_pcicore.c
1187 @@ -263,8 +263,7 @@ int ssb_pcicore_plat_dev_init(struct pci
1188                 return -ENODEV;
1189         }
1190
1191 -       ssb_printk(KERN_INFO "PCI: Fixing up device %s\n",
1192 -                  pci_name(d));
1193 +       ssb_info("PCI: Fixing up device %s\n", pci_name(d));
1194
1195         /* Fix up interrupt lines */
1196         d->irq = ssb_mips_irq(extpci_core->dev) + 2;
1197 @@ -285,12 +284,12 @@ static void ssb_pcicore_fixup_pcibridge(
1198         if (dev->bus->number != 0 || PCI_SLOT(dev->devfn) != 0)
1199                 return;
1200
1201 -       ssb_printk(KERN_INFO "PCI: Fixing up bridge %s\n", pci_name(dev));
1202 +       ssb_info("PCI: Fixing up bridge %s\n", pci_name(dev));
1203
1204         /* Enable PCI bridge bus mastering and memory space */
1205         pci_set_master(dev);
1206         if (pcibios_enable_device(dev, ~0) < 0) {
1207 -               ssb_printk(KERN_ERR "PCI: SSB bridge enable failed\n");
1208 +               ssb_err("PCI: SSB bridge enable failed\n");
1209                 return;
1210         }
1211
1212 @@ -299,8 +298,8 @@ static void ssb_pcicore_fixup_pcibridge(
1213
1214         /* Make sure our latency is high enough to handle the devices behind us */
1215         lat = 168;
1216 -       ssb_printk(KERN_INFO "PCI: Fixing latency timer of device %s to %u\n",
1217 -                  pci_name(dev), lat);
1218 +       ssb_info("PCI: Fixing latency timer of device %s to %u\n",
1219 +                pci_name(dev), lat);
1220         pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat);
1221  }
1222  DECLARE_PCI_FIXUP_EARLY(PCI_ANY_ID, PCI_ANY_ID, ssb_pcicore_fixup_pcibridge);
1223 @@ -323,7 +322,7 @@ static void __devinit ssb_pcicore_init_h
1224                 return;
1225         extpci_core = pc;
1226
1227 -       ssb_dprintk(KERN_INFO PFX "PCIcore in host mode found\n");
1228 +       ssb_dbg("PCIcore in host mode found\n");
1229         /* Reset devices on the external PCI bus */
1230         val = SSB_PCICORE_CTL_RST_OE;
1231         val |= SSB_PCICORE_CTL_CLK_OE;
1232 @@ -338,7 +337,7 @@ static void __devinit ssb_pcicore_init_h
1233         udelay(1); /* Assertion time demanded by the PCI standard */
1234
1235         if (pc->dev->bus->has_cardbus_slot) {
1236 -               ssb_dprintk(KERN_INFO PFX "CardBus slot detected\n");
1237 +               ssb_dbg("CardBus slot detected\n");
1238                 pc->cardbusmode = 1;
1239                 /* GPIO 1 resets the bridge */
1240                 ssb_gpio_out(pc->dev->bus, 1, 1);
1241 --- a/drivers/ssb/embedded.c
1242 +++ b/drivers/ssb/embedded.c
1243 @@ -4,11 +4,13 @@
1244   *
1245   * Copyright 2005-2008, Broadcom Corporation
1246   * Copyright 2006-2008, Michael Buesch <m@bues.ch>
1247 + * Copyright 2012, Hauke Mehrtens <hauke@hauke-m.de>
1248   *
1249   * Licensed under the GNU/GPL. See COPYING for details.
1250   */
1251
1252  #include <linux/export.h>
1253 +#include <linux/platform_device.h>
1254  #include <linux/ssb/ssb.h>
1255  #include <linux/ssb/ssb_embedded.h>
1256  #include <linux/ssb/ssb_driver_pci.h>
1257 @@ -32,6 +34,38 @@ int ssb_watchdog_timer_set(struct ssb_bu
1258  }
1259  EXPORT_SYMBOL(ssb_watchdog_timer_set);
1260
1261 +int ssb_watchdog_register(struct ssb_bus *bus)
1262 +{
1263 +       struct bcm47xx_wdt wdt = {};
1264 +       struct platform_device *pdev;
1265 +
1266 +       if (ssb_chipco_available(&bus->chipco)) {
1267 +               wdt.driver_data = &bus->chipco;
1268 +               wdt.timer_set = ssb_chipco_watchdog_timer_set_wdt;
1269 +               wdt.timer_set_ms = ssb_chipco_watchdog_timer_set_ms;
1270 +               wdt.max_timer_ms = bus->chipco.max_timer_ms;
1271 +       } else if (ssb_extif_available(&bus->extif)) {
1272 +               wdt.driver_data = &bus->extif;
1273 +               wdt.timer_set = ssb_extif_watchdog_timer_set_wdt;
1274 +               wdt.timer_set_ms = ssb_extif_watchdog_timer_set_ms;
1275 +               wdt.max_timer_ms = SSB_EXTIF_WATCHDOG_MAX_TIMER_MS;
1276 +       } else {
1277 +               return -ENODEV;
1278 +       }
1279 +
1280 +       pdev = platform_device_register_data(NULL, "bcm47xx-wdt",
1281 +                                            bus->busnumber, &wdt,
1282 +                                            sizeof(wdt));
1283 +       if (IS_ERR(pdev)) {
1284 +               ssb_dbg("can not register watchdog device, err: %li\n",
1285 +                       PTR_ERR(pdev));
1286 +               return PTR_ERR(pdev);
1287 +       }
1288 +
1289 +       bus->watchdog = pdev;
1290 +       return 0;
1291 +}
1292 +
1293  u32 ssb_gpio_in(struct ssb_bus *bus, u32 mask)
1294  {
1295         unsigned long flags;
1296 --- a/drivers/ssb/main.c
1297 +++ b/drivers/ssb/main.c
1298 @@ -13,6 +13,7 @@
1299  #include <linux/delay.h>
1300  #include <linux/io.h>
1301  #include <linux/module.h>
1302 +#include <linux/platform_device.h>
1303  #include <linux/ssb/ssb.h>
1304  #include <linux/ssb/ssb_regs.h>
1305  #include <linux/ssb/ssb_driver_gige.h>
1306 @@ -274,8 +275,8 @@ int ssb_devices_thaw(struct ssb_freeze_c
1307
1308                 err = sdrv->probe(sdev, &sdev->id);
1309                 if (err) {
1310 -                       ssb_printk(KERN_ERR PFX "Failed to thaw device %s\n",
1311 -                                  dev_name(sdev->dev));
1312 +                       ssb_err("Failed to thaw device %s\n",
1313 +                               dev_name(sdev->dev));
1314                         result = err;
1315                 }
1316                 ssb_device_put(sdev);
1317 @@ -433,10 +434,23 @@ static void ssb_devices_unregister(struc
1318                 if (sdev->dev)
1319                         device_unregister(sdev->dev);
1320         }
1321 +
1322 +#ifdef CONFIG_SSB_EMBEDDED
1323 +       if (bus->bustype == SSB_BUSTYPE_SSB)
1324 +               platform_device_unregister(bus->watchdog);
1325 +#endif
1326  }
1327
1328  void ssb_bus_unregister(struct ssb_bus *bus)
1329  {
1330 +       int err;
1331 +
1332 +       err = ssb_gpio_unregister(bus);
1333 +       if (err == -EBUSY)
1334 +               ssb_dbg("Some GPIOs are still in use\n");
1335 +       else if (err)
1336 +               ssb_dbg("Can not unregister GPIO driver: %i\n", err);
1337 +
1338         ssb_buses_lock();
1339         ssb_devices_unregister(bus);
1340         list_del(&bus->list);
1341 @@ -482,8 +496,7 @@ static int ssb_devices_register(struct s
1342
1343                 devwrap = kzalloc(sizeof(*devwrap), GFP_KERNEL);
1344                 if (!devwrap) {
1345 -                       ssb_printk(KERN_ERR PFX
1346 -                                  "Could not allocate device\n");
1347 +                       ssb_err("Could not allocate device\n");
1348                         err = -ENOMEM;
1349                         goto error;
1350                 }
1351 @@ -522,9 +535,7 @@ static int ssb_devices_register(struct s
1352                 sdev->dev = dev;
1353                 err = device_register(dev);
1354                 if (err) {
1355 -                       ssb_printk(KERN_ERR PFX
1356 -                                  "Could not register %s\n",
1357 -                                  dev_name(dev));
1358 +                       ssb_err("Could not register %s\n", dev_name(dev));
1359                         /* Set dev to NULL to not unregister
1360                          * dev on error unwinding. */
1361                         sdev->dev = NULL;
1362 @@ -534,6 +545,22 @@ static int ssb_devices_register(struct s
1363                 dev_idx++;
1364         }
1365
1366 +#ifdef CONFIG_SSB_DRIVER_MIPS
1367 +       if (bus->mipscore.pflash.present) {
1368 +               err = platform_device_register(&ssb_pflash_dev);
1369 +               if (err)
1370 +                       pr_err("Error registering parallel flash\n");
1371 +       }
1372 +#endif
1373 +
1374 +#ifdef CONFIG_SSB_SFLASH
1375 +       if (bus->mipscore.sflash.present) {
1376 +               err = platform_device_register(&ssb_sflash_dev);
1377 +               if (err)
1378 +                       pr_err("Error registering serial flash\n");
1379 +       }
1380 +#endif
1381 +
1382         return 0;
1383  error:
1384         /* Unwind the already registered devices. */
1385 @@ -561,6 +588,8 @@ static int __devinit ssb_attach_queued_b
1386                 if (err)
1387                         goto error;
1388                 ssb_pcicore_init(&bus->pcicore);
1389 +               if (bus->bustype == SSB_BUSTYPE_SSB)
1390 +                       ssb_watchdog_register(bus);
1391                 ssb_bus_may_powerdown(bus);
1392
1393                 err = ssb_devices_register(bus);
1394 @@ -796,7 +825,13 @@ static int __devinit ssb_bus_register(st
1395         if (err)
1396                 goto err_pcmcia_exit;
1397         ssb_chipcommon_init(&bus->chipco);
1398 +       ssb_extif_init(&bus->extif);
1399         ssb_mipscore_init(&bus->mipscore);
1400 +       err = ssb_gpio_init(bus);
1401 +       if (err == -ENOTSUPP)
1402 +               ssb_dbg("GPIO driver not activated\n");
1403 +       else if (err)
1404 +               ssb_dbg("Error registering GPIO driver: %i\n", err);
1405         err = ssb_fetch_invariants(bus, get_invariants);
1406         if (err) {
1407                 ssb_bus_may_powerdown(bus);
1408 @@ -847,11 +882,11 @@ int __devinit ssb_bus_pcibus_register(st
1409
1410         err = ssb_bus_register(bus, ssb_pci_get_invariants, 0);
1411         if (!err) {
1412 -               ssb_printk(KERN_INFO PFX "Sonics Silicon Backplane found on "
1413 -                          "PCI device %s\n", dev_name(&host_pci->dev));
1414 +               ssb_info("Sonics Silicon Backplane found on PCI device %s\n",
1415 +                        dev_name(&host_pci->dev));
1416         } else {
1417 -               ssb_printk(KERN_ERR PFX "Failed to register PCI version"
1418 -                          " of SSB with error %d\n", err);
1419 +               ssb_err("Failed to register PCI version of SSB with error %d\n",
1420 +                       err);
1421         }
1422
1423         return err;
1424 @@ -872,8 +907,8 @@ int __devinit ssb_bus_pcmciabus_register
1425
1426         err = ssb_bus_register(bus, ssb_pcmcia_get_invariants, baseaddr);
1427         if (!err) {
1428 -               ssb_printk(KERN_INFO PFX "Sonics Silicon Backplane found on "
1429 -                          "PCMCIA device %s\n", pcmcia_dev->devname);
1430 +               ssb_info("Sonics Silicon Backplane found on PCMCIA device %s\n",
1431 +                        pcmcia_dev->devname);
1432         }
1433
1434         return err;
1435 @@ -895,8 +930,8 @@ int __devinit ssb_bus_sdiobus_register(s
1436
1437         err = ssb_bus_register(bus, ssb_sdio_get_invariants, ~0);
1438         if (!err) {
1439 -               ssb_printk(KERN_INFO PFX "Sonics Silicon Backplane found on "
1440 -                          "SDIO device %s\n", sdio_func_id(func));
1441 +               ssb_info("Sonics Silicon Backplane found on SDIO device %s\n",
1442 +                        sdio_func_id(func));
1443         }
1444
1445         return err;
1446 @@ -915,8 +950,8 @@ int __devinit ssb_bus_ssbbus_register(st
1447
1448         err = ssb_bus_register(bus, get_invariants, baseaddr);
1449         if (!err) {
1450 -               ssb_printk(KERN_INFO PFX "Sonics Silicon Backplane found at "
1451 -                          "address 0x%08lX\n", baseaddr);
1452 +               ssb_info("Sonics Silicon Backplane found at address 0x%08lX\n",
1453 +                        baseaddr);
1454         }
1455
1456         return err;
1457 @@ -1118,8 +1153,7 @@ static u32 ssb_tmslow_reject_bitmask(str
1458         case SSB_IDLOW_SSBREV_27:     /* same here */
1459                 return SSB_TMSLOW_REJECT;       /* this is a guess */
1460         default:
1461 -               printk(KERN_INFO "ssb: Backplane Revision 0x%.8X\n", rev);
1462 -               WARN_ON(1);
1463 +               WARN(1, KERN_INFO "ssb: Backplane Revision 0x%.8X\n", rev);
1464         }
1465         return (SSB_TMSLOW_REJECT | SSB_TMSLOW_REJECT_23);
1466  }
1467 @@ -1311,7 +1345,7 @@ out:
1468  #endif
1469         return err;
1470  error:
1471 -       ssb_printk(KERN_ERR PFX "Bus powerdown failed\n");
1472 +       ssb_err("Bus powerdown failed\n");
1473         goto out;
1474  }
1475  EXPORT_SYMBOL(ssb_bus_may_powerdown);
1476 @@ -1334,7 +1368,7 @@ int ssb_bus_powerup(struct ssb_bus *bus,
1477
1478         return 0;
1479  error:
1480 -       ssb_printk(KERN_ERR PFX "Bus powerup failed\n");
1481 +       ssb_err("Bus powerup failed\n");
1482         return err;
1483  }
1484  EXPORT_SYMBOL(ssb_bus_powerup);
1485 @@ -1442,15 +1476,13 @@ static int __init ssb_modinit(void)
1486
1487         err = b43_pci_ssb_bridge_init();
1488         if (err) {
1489 -               ssb_printk(KERN_ERR "Broadcom 43xx PCI-SSB-bridge "
1490 -                          "initialization failed\n");
1491 +               ssb_err("Broadcom 43xx PCI-SSB-bridge initialization failed\n");
1492                 /* don't fail SSB init because of this */
1493                 err = 0;
1494         }
1495         err = ssb_gige_init();
1496         if (err) {
1497 -               ssb_printk(KERN_ERR "SSB Broadcom Gigabit Ethernet "
1498 -                          "driver initialization failed\n");
1499 +               ssb_err("SSB Broadcom Gigabit Ethernet driver initialization failed\n");
1500                 /* don't fail SSB init because of this */
1501                 err = 0;
1502         }
1503 --- a/drivers/ssb/pci.c
1504 +++ b/drivers/ssb/pci.c
1505 @@ -56,7 +56,7 @@ int ssb_pci_switch_coreidx(struct ssb_bu
1506         }
1507         return 0;
1508  error:
1509 -       ssb_printk(KERN_ERR PFX "Failed to switch to core %u\n", coreidx);
1510 +       ssb_err("Failed to switch to core %u\n", coreidx);
1511         return -ENODEV;
1512  }
1513
1514 @@ -67,10 +67,9 @@ int ssb_pci_switch_core(struct ssb_bus *
1515         unsigned long flags;
1516
1517  #if SSB_VERBOSE_PCICORESWITCH_DEBUG
1518 -       ssb_printk(KERN_INFO PFX
1519 -                  "Switching to %s core, index %d\n",
1520 -                  ssb_core_name(dev->id.coreid),
1521 -                  dev->core_index);
1522 +       ssb_info("Switching to %s core, index %d\n",
1523 +                ssb_core_name(dev->id.coreid),
1524 +                dev->core_index);
1525  #endif
1526
1527         spin_lock_irqsave(&bus->bar_lock, flags);
1528 @@ -231,6 +230,15 @@ static inline u8 ssb_crc8(u8 crc, u8 dat
1529         return t[crc ^ data];
1530  }
1531
1532 +static void sprom_get_mac(char *mac, const u16 *in)
1533 +{
1534 +       int i;
1535 +       for (i = 0; i < 3; i++) {
1536 +               *mac++ = in[i] >> 8;
1537 +               *mac++ = in[i];
1538 +       }
1539 +}
1540 +
1541  static u8 ssb_sprom_crc(const u16 *sprom, u16 size)
1542  {
1543         int word;
1544 @@ -278,7 +286,7 @@ static int sprom_do_write(struct ssb_bus
1545         u32 spromctl;
1546         u16 size = bus->sprom_size;
1547
1548 -       ssb_printk(KERN_NOTICE PFX "Writing SPROM. Do NOT turn off the power! Please stand by...\n");
1549 +       ssb_notice("Writing SPROM. Do NOT turn off the power! Please stand by...\n");
1550         err = pci_read_config_dword(pdev, SSB_SPROMCTL, &spromctl);
1551         if (err)
1552                 goto err_ctlreg;
1553 @@ -286,17 +294,17 @@ static int sprom_do_write(struct ssb_bus
1554         err = pci_write_config_dword(pdev, SSB_SPROMCTL, spromctl);
1555         if (err)
1556                 goto err_ctlreg;
1557 -       ssb_printk(KERN_NOTICE PFX "[ 0%%");
1558 +       ssb_notice("[ 0%%");
1559         msleep(500);
1560         for (i = 0; i < size; i++) {
1561                 if (i == size / 4)
1562 -                       ssb_printk("25%%");
1563 +                       ssb_cont("25%%");
1564                 else if (i == size / 2)
1565 -                       ssb_printk("50%%");
1566 +                       ssb_cont("50%%");
1567                 else if (i == (size * 3) / 4)
1568 -                       ssb_printk("75%%");
1569 +                       ssb_cont("75%%");
1570                 else if (i % 2)
1571 -                       ssb_printk(".");
1572 +                       ssb_cont(".");
1573                 writew(sprom[i], bus->mmio + bus->sprom_offset + (i * 2));
1574                 mmiowb();
1575                 msleep(20);
1576 @@ -309,12 +317,12 @@ static int sprom_do_write(struct ssb_bus
1577         if (err)
1578                 goto err_ctlreg;
1579         msleep(500);
1580 -       ssb_printk("100%% ]\n");
1581 -       ssb_printk(KERN_NOTICE PFX "SPROM written.\n");
1582 +       ssb_cont("100%% ]\n");
1583 +       ssb_notice("SPROM written\n");
1584
1585         return 0;
1586  err_ctlreg:
1587 -       ssb_printk(KERN_ERR PFX "Could not access SPROM control register.\n");
1588 +       ssb_err("Could not access SPROM control register.\n");
1589         return err;
1590  }
1591
1592 @@ -339,10 +347,23 @@ static s8 r123_extract_antgain(u8 sprom_
1593         return (s8)gain;
1594  }
1595
1596 +static void sprom_extract_r23(struct ssb_sprom *out, const u16 *in)
1597 +{
1598 +       SPEX(boardflags_hi, SSB_SPROM2_BFLHI, 0xFFFF, 0);
1599 +       SPEX(opo, SSB_SPROM2_OPO, SSB_SPROM2_OPO_VALUE, 0);
1600 +       SPEX(pa1lob0, SSB_SPROM2_PA1LOB0, 0xFFFF, 0);
1601 +       SPEX(pa1lob1, SSB_SPROM2_PA1LOB1, 0xFFFF, 0);
1602 +       SPEX(pa1lob2, SSB_SPROM2_PA1LOB2, 0xFFFF, 0);
1603 +       SPEX(pa1hib0, SSB_SPROM2_PA1HIB0, 0xFFFF, 0);
1604 +       SPEX(pa1hib1, SSB_SPROM2_PA1HIB1, 0xFFFF, 0);
1605 +       SPEX(pa1hib2, SSB_SPROM2_PA1HIB2, 0xFFFF, 0);
1606 +       SPEX(maxpwr_ah, SSB_SPROM2_MAXP_A, SSB_SPROM2_MAXP_A_HI, 0);
1607 +       SPEX(maxpwr_al, SSB_SPROM2_MAXP_A, SSB_SPROM2_MAXP_A_LO,
1608 +            SSB_SPROM2_MAXP_A_LO_SHIFT);
1609 +}
1610 +
1611  static void sprom_extract_r123(struct ssb_sprom *out, const u16 *in)
1612  {
1613 -       int i;
1614 -       u16 v;
1615         u16 loc[3];
1616
1617         if (out->revision == 3)                 /* rev 3 moved MAC */
1618 @@ -352,19 +373,10 @@ static void sprom_extract_r123(struct ss
1619                 loc[1] = SSB_SPROM1_ET0MAC;
1620                 loc[2] = SSB_SPROM1_ET1MAC;
1621         }
1622 -       for (i = 0; i < 3; i++) {
1623 -               v = in[SPOFF(loc[0]) + i];
1624 -               *(((__be16 *)out->il0mac) + i) = cpu_to_be16(v);
1625 -       }
1626 +       sprom_get_mac(out->il0mac, &in[SPOFF(loc[0])]);
1627         if (out->revision < 3) {        /* only rev 1-2 have et0, et1 */
1628 -               for (i = 0; i < 3; i++) {
1629 -                       v = in[SPOFF(loc[1]) + i];
1630 -                       *(((__be16 *)out->et0mac) + i) = cpu_to_be16(v);
1631 -               }
1632 -               for (i = 0; i < 3; i++) {
1633 -                       v = in[SPOFF(loc[2]) + i];
1634 -                       *(((__be16 *)out->et1mac) + i) = cpu_to_be16(v);
1635 -               }
1636 +               sprom_get_mac(out->et0mac, &in[SPOFF(loc[1])]);
1637 +               sprom_get_mac(out->et1mac, &in[SPOFF(loc[2])]);
1638         }
1639         SPEX(et0phyaddr, SSB_SPROM1_ETHPHY, SSB_SPROM1_ETHPHY_ET0A, 0);
1640         SPEX(et1phyaddr, SSB_SPROM1_ETHPHY, SSB_SPROM1_ETHPHY_ET1A,
1641 @@ -372,6 +384,7 @@ static void sprom_extract_r123(struct ss
1642         SPEX(et0mdcport, SSB_SPROM1_ETHPHY, SSB_SPROM1_ETHPHY_ET0M, 14);
1643         SPEX(et1mdcport, SSB_SPROM1_ETHPHY, SSB_SPROM1_ETHPHY_ET1M, 15);
1644         SPEX(board_rev, SSB_SPROM1_BINF, SSB_SPROM1_BINF_BREV, 0);
1645 +       SPEX(board_type, SSB_SPROM1_SPID, 0xFFFF, 0);
1646         if (out->revision == 1)
1647                 SPEX(country_code, SSB_SPROM1_BINF, SSB_SPROM1_BINF_CCODE,
1648                      SSB_SPROM1_BINF_CCODE_SHIFT);
1649 @@ -398,8 +411,7 @@ static void sprom_extract_r123(struct ss
1650              SSB_SPROM1_ITSSI_A_SHIFT);
1651         SPEX(itssi_bg, SSB_SPROM1_ITSSI, SSB_SPROM1_ITSSI_BG, 0);
1652         SPEX(boardflags_lo, SSB_SPROM1_BFLLO, 0xFFFF, 0);
1653 -       if (out->revision >= 2)
1654 -               SPEX(boardflags_hi, SSB_SPROM2_BFLHI, 0xFFFF, 0);
1655 +
1656         SPEX(alpha2[0], SSB_SPROM1_CCODE, 0xff00, 8);
1657         SPEX(alpha2[1], SSB_SPROM1_CCODE, 0x00ff, 0);
1658
1659 @@ -410,6 +422,8 @@ static void sprom_extract_r123(struct ss
1660         out->antenna_gain.a1 = r123_extract_antgain(out->revision, in,
1661                                                     SSB_SPROM1_AGAIN_A,
1662                                                     SSB_SPROM1_AGAIN_A_SHIFT);
1663 +       if (out->revision >= 2)
1664 +               sprom_extract_r23(out, in);
1665  }
1666
1667  /* Revs 4 5 and 8 have partially shared layout */
1668 @@ -454,23 +468,20 @@ static void sprom_extract_r458(struct ss
1669
1670  static void sprom_extract_r45(struct ssb_sprom *out, const u16 *in)
1671  {
1672 -       int i;
1673 -       u16 v;
1674         u16 il0mac_offset;
1675
1676         if (out->revision == 4)
1677                 il0mac_offset = SSB_SPROM4_IL0MAC;
1678         else
1679                 il0mac_offset = SSB_SPROM5_IL0MAC;
1680 -       /* extract the MAC address */
1681 -       for (i = 0; i < 3; i++) {
1682 -               v = in[SPOFF(il0mac_offset) + i];
1683 -               *(((__be16 *)out->il0mac) + i) = cpu_to_be16(v);
1684 -       }
1685 +
1686 +       sprom_get_mac(out->il0mac, &in[SPOFF(il0mac_offset)]);
1687 +
1688         SPEX(et0phyaddr, SSB_SPROM4_ETHPHY, SSB_SPROM4_ETHPHY_ET0A, 0);
1689         SPEX(et1phyaddr, SSB_SPROM4_ETHPHY, SSB_SPROM4_ETHPHY_ET1A,
1690              SSB_SPROM4_ETHPHY_ET1A_SHIFT);
1691         SPEX(board_rev, SSB_SPROM4_BOARDREV, 0xFFFF, 0);
1692 +       SPEX(board_type, SSB_SPROM1_SPID, 0xFFFF, 0);
1693         if (out->revision == 4) {
1694                 SPEX(alpha2[0], SSB_SPROM4_CCODE, 0xff00, 8);
1695                 SPEX(alpha2[1], SSB_SPROM4_CCODE, 0x00ff, 0);
1696 @@ -530,7 +541,7 @@ static void sprom_extract_r45(struct ssb
1697  static void sprom_extract_r8(struct ssb_sprom *out, const u16 *in)
1698  {
1699         int i;
1700 -       u16 v, o;
1701 +       u16 o;
1702         u16 pwr_info_offset[] = {
1703                 SSB_SROM8_PWR_INFO_CORE0, SSB_SROM8_PWR_INFO_CORE1,
1704                 SSB_SROM8_PWR_INFO_CORE2, SSB_SROM8_PWR_INFO_CORE3
1705 @@ -539,11 +550,10 @@ static void sprom_extract_r8(struct ssb_
1706                         ARRAY_SIZE(out->core_pwr_info));
1707
1708         /* extract the MAC address */
1709 -       for (i = 0; i < 3; i++) {
1710 -               v = in[SPOFF(SSB_SPROM8_IL0MAC) + i];
1711 -               *(((__be16 *)out->il0mac) + i) = cpu_to_be16(v);
1712 -       }
1713 +       sprom_get_mac(out->il0mac, &in[SPOFF(SSB_SPROM8_IL0MAC)]);
1714 +
1715         SPEX(board_rev, SSB_SPROM8_BOARDREV, 0xFFFF, 0);
1716 +       SPEX(board_type, SSB_SPROM1_SPID, 0xFFFF, 0);
1717         SPEX(alpha2[0], SSB_SPROM8_CCODE, 0xff00, 8);
1718         SPEX(alpha2[1], SSB_SPROM8_CCODE, 0x00ff, 0);
1719         SPEX(boardflags_lo, SSB_SPROM8_BFLLO, 0xFFFF, 0);
1720 @@ -743,7 +753,7 @@ static int sprom_extract(struct ssb_bus
1721         memset(out, 0, sizeof(*out));
1722
1723         out->revision = in[size - 1] & 0x00FF;
1724 -       ssb_dprintk(KERN_DEBUG PFX "SPROM revision %d detected.\n", out->revision);
1725 +       ssb_dbg("SPROM revision %d detected\n", out->revision);
1726         memset(out->et0mac, 0xFF, 6);           /* preset et0 and et1 mac */
1727         memset(out->et1mac, 0xFF, 6);
1728
1729 @@ -752,7 +762,7 @@ static int sprom_extract(struct ssb_bus
1730                  * number stored in the SPROM.
1731                  * Always extract r1. */
1732                 out->revision = 1;
1733 -               ssb_dprintk(KERN_DEBUG PFX "SPROM treated as revision %d\n", out->revision);
1734 +               ssb_dbg("SPROM treated as revision %d\n", out->revision);
1735         }
1736
1737         switch (out->revision) {
1738 @@ -769,9 +779,8 @@ static int sprom_extract(struct ssb_bus
1739                 sprom_extract_r8(out, in);
1740                 break;
1741         default:
1742 -               ssb_printk(KERN_WARNING PFX "Unsupported SPROM"
1743 -                          " revision %d detected. Will extract"
1744 -                          " v1\n", out->revision);
1745 +               ssb_warn("Unsupported SPROM revision %d detected. Will extract v1\n",
1746 +                        out->revision);
1747                 out->revision = 1;
1748                 sprom_extract_r123(out, in);
1749         }
1750 @@ -791,7 +800,7 @@ static int ssb_pci_sprom_get(struct ssb_
1751         u16 *buf;
1752
1753         if (!ssb_is_sprom_available(bus)) {
1754 -               ssb_printk(KERN_ERR PFX "No SPROM available!\n");
1755 +               ssb_err("No SPROM available!\n");
1756                 return -ENODEV;
1757         }
1758         if (bus->chipco.dev) {  /* can be unavailable! */
1759 @@ -810,7 +819,7 @@ static int ssb_pci_sprom_get(struct ssb_
1760         } else {
1761                 bus->sprom_offset = SSB_SPROM_BASE1;
1762         }
1763 -       ssb_dprintk(KERN_INFO PFX "SPROM offset is 0x%x\n", bus->sprom_offset);
1764 +       ssb_dbg("SPROM offset is 0x%x\n", bus->sprom_offset);
1765
1766         buf = kcalloc(SSB_SPROMSIZE_WORDS_R123, sizeof(u16), GFP_KERNEL);
1767         if (!buf)
1768 @@ -835,18 +844,15 @@ static int ssb_pci_sprom_get(struct ssb_
1769                          * available for this device in some other storage */
1770                         err = ssb_fill_sprom_with_fallback(bus, sprom);
1771                         if (err) {
1772 -                               ssb_printk(KERN_WARNING PFX "WARNING: Using"
1773 -                                          " fallback SPROM failed (err %d)\n",
1774 -                                          err);
1775 +                               ssb_warn("WARNING: Using fallback SPROM failed (err %d)\n",
1776 +                                        err);
1777                         } else {
1778 -                               ssb_dprintk(KERN_DEBUG PFX "Using SPROM"
1779 -                                           " revision %d provided by"
1780 -                                           " platform.\n", sprom->revision);
1781 +                               ssb_dbg("Using SPROM revision %d provided by platform\n",
1782 +                                       sprom->revision);
1783                                 err = 0;
1784                                 goto out_free;
1785                         }
1786 -                       ssb_printk(KERN_WARNING PFX "WARNING: Invalid"
1787 -                                  " SPROM CRC (corrupt SPROM)\n");
1788 +                       ssb_warn("WARNING: Invalid SPROM CRC (corrupt SPROM)\n");
1789                 }
1790         }
1791         err = sprom_extract(bus, sprom, buf, bus->sprom_size);
1792 --- a/drivers/ssb/pcihost_wrapper.c
1793 +++ b/drivers/ssb/pcihost_wrapper.c
1794 @@ -38,7 +38,7 @@ static int ssb_pcihost_resume(struct pci
1795         struct ssb_bus *ssb = pci_get_drvdata(dev);
1796         int err;
1797
1798 -       pci_set_power_state(dev, 0);
1799 +       pci_set_power_state(dev, PCI_D0);
1800         err = pci_enable_device(dev);
1801         if (err)
1802                 return err;
1803 --- a/drivers/ssb/pcmcia.c
1804 +++ b/drivers/ssb/pcmcia.c
1805 @@ -143,7 +143,7 @@ int ssb_pcmcia_switch_coreidx(struct ssb
1806
1807         return 0;
1808  error:
1809 -       ssb_printk(KERN_ERR PFX "Failed to switch to core %u\n", coreidx);
1810 +       ssb_err("Failed to switch to core %u\n", coreidx);
1811         return err;
1812  }
1813
1814 @@ -153,10 +153,9 @@ int ssb_pcmcia_switch_core(struct ssb_bu
1815         int err;
1816
1817  #if SSB_VERBOSE_PCMCIACORESWITCH_DEBUG
1818 -       ssb_printk(KERN_INFO PFX
1819 -                  "Switching to %s core, index %d\n",
1820 -                  ssb_core_name(dev->id.coreid),
1821 -                  dev->core_index);
1822 +       ssb_info("Switching to %s core, index %d\n",
1823 +                ssb_core_name(dev->id.coreid),
1824 +                dev->core_index);
1825  #endif
1826
1827         err = ssb_pcmcia_switch_coreidx(bus, dev->core_index);
1828 @@ -192,7 +191,7 @@ int ssb_pcmcia_switch_segment(struct ssb
1829
1830         return 0;
1831  error:
1832 -       ssb_printk(KERN_ERR PFX "Failed to switch pcmcia segment\n");
1833 +       ssb_err("Failed to switch pcmcia segment\n");
1834         return err;
1835  }
1836
1837 @@ -549,44 +548,39 @@ static int ssb_pcmcia_sprom_write_all(st
1838         bool failed = 0;
1839         size_t size = SSB_PCMCIA_SPROM_SIZE;
1840
1841 -       ssb_printk(KERN_NOTICE PFX
1842 -                  "Writing SPROM. Do NOT turn off the power! "
1843 -                  "Please stand by...\n");
1844 +       ssb_notice("Writing SPROM. Do NOT turn off the power! Please stand by...\n");
1845         err = ssb_pcmcia_sprom_command(bus, SSB_PCMCIA_SPROMCTL_WRITEEN);
1846         if (err) {
1847 -               ssb_printk(KERN_NOTICE PFX
1848 -                          "Could not enable SPROM write access.\n");
1849 +               ssb_notice("Could not enable SPROM write access\n");
1850                 return -EBUSY;
1851         }
1852 -       ssb_printk(KERN_NOTICE PFX "[ 0%%");
1853 +       ssb_notice("[ 0%%");
1854         msleep(500);
1855         for (i = 0; i < size; i++) {
1856                 if (i == size / 4)
1857 -                       ssb_printk("25%%");
1858 +                       ssb_cont("25%%");
1859                 else if (i == size / 2)
1860 -                       ssb_printk("50%%");
1861 +                       ssb_cont("50%%");
1862                 else if (i == (size * 3) / 4)
1863 -                       ssb_printk("75%%");
1864 +                       ssb_cont("75%%");
1865                 else if (i % 2)
1866 -                       ssb_printk(".");
1867 +                       ssb_cont(".");
1868                 err = ssb_pcmcia_sprom_write(bus, i, sprom[i]);
1869                 if (err) {
1870 -                       ssb_printk(KERN_NOTICE PFX
1871 -                                  "Failed to write to SPROM.\n");
1872 +                       ssb_notice("Failed to write to SPROM\n");
1873                         failed = 1;
1874                         break;
1875                 }
1876         }
1877         err = ssb_pcmcia_sprom_command(bus, SSB_PCMCIA_SPROMCTL_WRITEDIS);
1878         if (err) {
1879 -               ssb_printk(KERN_NOTICE PFX
1880 -                          "Could not disable SPROM write access.\n");
1881 +               ssb_notice("Could not disable SPROM write access\n");
1882                 failed = 1;
1883         }
1884         msleep(500);
1885         if (!failed) {
1886 -               ssb_printk("100%% ]\n");
1887 -               ssb_printk(KERN_NOTICE PFX "SPROM written.\n");
1888 +               ssb_cont("100%% ]\n");
1889 +               ssb_notice("SPROM written\n");
1890         }
1891
1892         return failed ? -EBUSY : 0;
1893 @@ -700,7 +694,7 @@ static int ssb_pcmcia_do_get_invariants(
1894         return -ENOSPC; /* continue with next entry */
1895
1896  error:
1897 -       ssb_printk(KERN_ERR PFX
1898 +       ssb_err(
1899                    "PCMCIA: Failed to fetch device invariants: %s\n",
1900                    error_description);
1901         return -ENODEV;
1902 @@ -722,7 +716,7 @@ int ssb_pcmcia_get_invariants(struct ssb
1903         res = pcmcia_loop_tuple(bus->host_pcmcia, CISTPL_FUNCE,
1904                                 ssb_pcmcia_get_mac, sprom);
1905         if (res != 0) {
1906 -               ssb_printk(KERN_ERR PFX
1907 +               ssb_err(
1908                         "PCMCIA: Failed to fetch MAC address\n");
1909                 return -ENODEV;
1910         }
1911 @@ -733,7 +727,7 @@ int ssb_pcmcia_get_invariants(struct ssb
1912         if ((res == 0) || (res == -ENOSPC))
1913                 return 0;
1914
1915 -       ssb_printk(KERN_ERR PFX
1916 +       ssb_err(
1917                         "PCMCIA: Failed to fetch device invariants\n");
1918         return -ENODEV;
1919  }
1920 @@ -843,6 +837,6 @@ int ssb_pcmcia_init(struct ssb_bus *bus)
1921
1922         return 0;
1923  error:
1924 -       ssb_printk(KERN_ERR PFX "Failed to initialize PCMCIA host device\n");
1925 +       ssb_err("Failed to initialize PCMCIA host device\n");
1926         return err;
1927  }
1928 --- a/drivers/ssb/scan.c
1929 +++ b/drivers/ssb/scan.c
1930 @@ -125,8 +125,7 @@ static u16 pcidev_to_chipid(struct pci_d
1931                 chipid_fallback = 0x4401;
1932                 break;
1933         default:
1934 -               ssb_printk(KERN_ERR PFX
1935 -                          "PCI-ID not in fallback list\n");
1936 +               ssb_err("PCI-ID not in fallback list\n");
1937         }
1938
1939         return chipid_fallback;
1940 @@ -152,8 +151,7 @@ static u8 chipid_to_nrcores(u16 chipid)
1941         case 0x4704:
1942                 return 9;
1943         default:
1944 -               ssb_printk(KERN_ERR PFX
1945 -                          "CHIPID not in nrcores fallback list\n");
1946 +               ssb_err("CHIPID not in nrcores fallback list\n");
1947         }
1948
1949         return 1;
1950 @@ -320,15 +318,13 @@ int ssb_bus_scan(struct ssb_bus *bus,
1951                         bus->chip_package = 0;
1952                 }
1953         }
1954 -       ssb_printk(KERN_INFO PFX "Found chip with id 0x%04X, rev 0x%02X and "
1955 -                  "package 0x%02X\n", bus->chip_id, bus->chip_rev,
1956 -                  bus->chip_package);
1957 +       ssb_info("Found chip with id 0x%04X, rev 0x%02X and package 0x%02X\n",
1958 +                bus->chip_id, bus->chip_rev, bus->chip_package);
1959         if (!bus->nr_devices)
1960                 bus->nr_devices = chipid_to_nrcores(bus->chip_id);
1961         if (bus->nr_devices > ARRAY_SIZE(bus->devices)) {
1962 -               ssb_printk(KERN_ERR PFX
1963 -                          "More than %d ssb cores found (%d)\n",
1964 -                          SSB_MAX_NR_CORES, bus->nr_devices);
1965 +               ssb_err("More than %d ssb cores found (%d)\n",
1966 +                       SSB_MAX_NR_CORES, bus->nr_devices);
1967                 goto err_unmap;
1968         }
1969         if (bus->bustype == SSB_BUSTYPE_SSB) {
1970 @@ -370,8 +366,7 @@ int ssb_bus_scan(struct ssb_bus *bus,
1971                         nr_80211_cores++;
1972                         if (nr_80211_cores > 1) {
1973                                 if (!we_support_multiple_80211_cores(bus)) {
1974 -                                       ssb_dprintk(KERN_INFO PFX "Ignoring additional "
1975 -                                                   "802.11 core\n");
1976 +                                       ssb_dbg("Ignoring additional 802.11 core\n");
1977                                         continue;
1978                                 }
1979                         }
1980 @@ -379,8 +374,7 @@ int ssb_bus_scan(struct ssb_bus *bus,
1981                 case SSB_DEV_EXTIF:
1982  #ifdef CONFIG_SSB_DRIVER_EXTIF
1983                         if (bus->extif.dev) {
1984 -                               ssb_printk(KERN_WARNING PFX
1985 -                                          "WARNING: Multiple EXTIFs found\n");
1986 +                               ssb_warn("WARNING: Multiple EXTIFs found\n");
1987                                 break;
1988                         }
1989                         bus->extif.dev = dev;
1990 @@ -388,8 +382,7 @@ int ssb_bus_scan(struct ssb_bus *bus,
1991                         break;
1992                 case SSB_DEV_CHIPCOMMON:
1993                         if (bus->chipco.dev) {
1994 -                               ssb_printk(KERN_WARNING PFX
1995 -                                          "WARNING: Multiple ChipCommon found\n");
1996 +                               ssb_warn("WARNING: Multiple ChipCommon found\n");
1997                                 break;
1998                         }
1999                         bus->chipco.dev = dev;
2000 @@ -398,8 +391,7 @@ int ssb_bus_scan(struct ssb_bus *bus,
2001                 case SSB_DEV_MIPS_3302:
2002  #ifdef CONFIG_SSB_DRIVER_MIPS
2003                         if (bus->mipscore.dev) {
2004 -                               ssb_printk(KERN_WARNING PFX
2005 -                                          "WARNING: Multiple MIPS cores found\n");
2006 +                               ssb_warn("WARNING: Multiple MIPS cores found\n");
2007                                 break;
2008                         }
2009                         bus->mipscore.dev = dev;
2010 @@ -420,8 +412,7 @@ int ssb_bus_scan(struct ssb_bus *bus,
2011                                 }
2012                         }
2013                         if (bus->pcicore.dev) {
2014 -                               ssb_printk(KERN_WARNING PFX
2015 -                                          "WARNING: Multiple PCI(E) cores found\n");
2016 +                               ssb_warn("WARNING: Multiple PCI(E) cores found\n");
2017                                 break;
2018                         }
2019                         bus->pcicore.dev = dev;
2020 --- a/drivers/ssb/sprom.c
2021 +++ b/drivers/ssb/sprom.c
2022 @@ -54,7 +54,7 @@ static int hex2sprom(u16 *sprom, const c
2023         while (cnt < sprom_size_words) {
2024                 memcpy(tmp, dump, 4);
2025                 dump += 4;
2026 -               err = strict_strtoul(tmp, 16, &parsed);
2027 +               err = kstrtoul(tmp, 16, &parsed);
2028                 if (err)
2029                         return err;
2030                 sprom[cnt++] = swab16((u16)parsed);
2031 @@ -127,13 +127,13 @@ ssize_t ssb_attr_sprom_store(struct ssb_
2032                 goto out_kfree;
2033         err = ssb_devices_freeze(bus, &freeze);
2034         if (err) {
2035 -               ssb_printk(KERN_ERR PFX "SPROM write: Could not freeze all devices\n");
2036 +               ssb_err("SPROM write: Could not freeze all devices\n");
2037                 goto out_unlock;
2038         }
2039         res = sprom_write(bus, sprom);
2040         err = ssb_devices_thaw(&freeze);
2041         if (err)
2042 -               ssb_printk(KERN_ERR PFX "SPROM write: Could not thaw all devices\n");
2043 +               ssb_err("SPROM write: Could not thaw all devices\n");
2044  out_unlock:
2045         mutex_unlock(&bus->sprom_mutex);
2046  out_kfree:
2047 --- a/drivers/ssb/ssb_private.h
2048 +++ b/drivers/ssb/ssb_private.h
2049 @@ -3,21 +3,33 @@
2050
2051  #include <linux/ssb/ssb.h>
2052  #include <linux/types.h>
2053 +#include <linux/bcm47xx_wdt.h>
2054
2055
2056  #define PFX    "ssb: "
2057
2058  #ifdef CONFIG_SSB_SILENT
2059 -# define ssb_printk(fmt, x...) do { /* nothing */ } while (0)
2060 +# define ssb_printk(fmt, ...)                                  \
2061 +       do { if (0) printk(fmt, ##__VA_ARGS__); } while (0)
2062  #else
2063 -# define ssb_printk            printk
2064 +# define ssb_printk(fmt, ...)                                  \
2065 +       printk(fmt, ##__VA_ARGS__)
2066  #endif /* CONFIG_SSB_SILENT */
2067
2068 +#define ssb_emerg(fmt, ...)    ssb_printk(KERN_EMERG PFX fmt, ##__VA_ARGS__)
2069 +#define ssb_err(fmt, ...)      ssb_printk(KERN_ERR PFX fmt, ##__VA_ARGS__)
2070 +#define ssb_warn(fmt, ...)     ssb_printk(KERN_WARNING PFX fmt, ##__VA_ARGS__)
2071 +#define ssb_notice(fmt, ...)   ssb_printk(KERN_NOTICE PFX fmt, ##__VA_ARGS__)
2072 +#define ssb_info(fmt, ...)     ssb_printk(KERN_INFO PFX fmt, ##__VA_ARGS__)
2073 +#define ssb_cont(fmt, ...)     ssb_printk(KERN_CONT fmt, ##__VA_ARGS__)
2074 +
2075  /* dprintk: Debugging printk; vanishes for non-debug compilation */
2076  #ifdef CONFIG_SSB_DEBUG
2077 -# define ssb_dprintk(fmt, x...)        ssb_printk(fmt , ##x)
2078 +# define ssb_dbg(fmt, ...)                                     \
2079 +       ssb_printk(KERN_DEBUG PFX fmt, ##__VA_ARGS__)
2080  #else
2081 -# define ssb_dprintk(fmt, x...)        do { /* nothing */ } while (0)
2082 +# define ssb_dbg(fmt, ...)                                     \
2083 +       do { if (0) printk(KERN_DEBUG PFX fmt, ##__VA_ARGS__); } while (0)
2084  #endif
2085
2086  #ifdef CONFIG_SSB_DEBUG
2087 @@ -210,5 +222,76 @@ static inline void b43_pci_ssb_bridge_ex
2088  /* driver_chipcommon_pmu.c */
2089  extern u32 ssb_pmu_get_cpu_clock(struct ssb_chipcommon *cc);
2090  extern u32 ssb_pmu_get_controlclock(struct ssb_chipcommon *cc);
2091 +extern u32 ssb_pmu_get_alp_clock(struct ssb_chipcommon *cc);
2092 +
2093 +extern u32 ssb_chipco_watchdog_timer_set_wdt(struct bcm47xx_wdt *wdt,
2094 +                                            u32 ticks);
2095 +extern u32 ssb_chipco_watchdog_timer_set_ms(struct bcm47xx_wdt *wdt, u32 ms);
2096 +
2097 +/* driver_chipcommon_sflash.c */
2098 +#ifdef CONFIG_SSB_SFLASH
2099 +int ssb_sflash_init(struct ssb_chipcommon *cc);
2100 +#else
2101 +static inline int ssb_sflash_init(struct ssb_chipcommon *cc)
2102 +{
2103 +       pr_err("Serial flash not supported\n");
2104 +       return 0;
2105 +}
2106 +#endif /* CONFIG_SSB_SFLASH */
2107 +
2108 +#ifdef CONFIG_SSB_DRIVER_MIPS
2109 +extern struct platform_device ssb_pflash_dev;
2110 +#endif
2111 +
2112 +#ifdef CONFIG_SSB_SFLASH
2113 +extern struct platform_device ssb_sflash_dev;
2114 +#endif
2115 +
2116 +#ifdef CONFIG_SSB_DRIVER_EXTIF
2117 +extern u32 ssb_extif_watchdog_timer_set_wdt(struct bcm47xx_wdt *wdt, u32 ticks);
2118 +extern u32 ssb_extif_watchdog_timer_set_ms(struct bcm47xx_wdt *wdt, u32 ms);
2119 +#else
2120 +static inline u32 ssb_extif_watchdog_timer_set_wdt(struct bcm47xx_wdt *wdt,
2121 +                                                  u32 ticks)
2122 +{
2123 +       return 0;
2124 +}
2125 +static inline u32 ssb_extif_watchdog_timer_set_ms(struct bcm47xx_wdt *wdt,
2126 +                                                 u32 ms)
2127 +{
2128 +       return 0;
2129 +}
2130 +#endif
2131 +
2132 +#ifdef CONFIG_SSB_EMBEDDED
2133 +extern int ssb_watchdog_register(struct ssb_bus *bus);
2134 +#else /* CONFIG_SSB_EMBEDDED */
2135 +static inline int ssb_watchdog_register(struct ssb_bus *bus)
2136 +{
2137 +       return 0;
2138 +}
2139 +#endif /* CONFIG_SSB_EMBEDDED */
2140 +
2141 +#ifdef CONFIG_SSB_DRIVER_EXTIF
2142 +extern void ssb_extif_init(struct ssb_extif *extif);
2143 +#else
2144 +static inline void ssb_extif_init(struct ssb_extif *extif)
2145 +{
2146 +}
2147 +#endif
2148 +
2149 +#ifdef CONFIG_SSB_DRIVER_GPIO
2150 +extern int ssb_gpio_init(struct ssb_bus *bus);
2151 +extern int ssb_gpio_unregister(struct ssb_bus *bus);
2152 +#else /* CONFIG_SSB_DRIVER_GPIO */
2153 +static inline int ssb_gpio_init(struct ssb_bus *bus)
2154 +{
2155 +       return -ENOTSUPP;
2156 +}
2157 +static inline int ssb_gpio_unregister(struct ssb_bus *bus)
2158 +{
2159 +       return 0;
2160 +}
2161 +#endif /* CONFIG_SSB_DRIVER_GPIO */
2162
2163  #endif /* LINUX_SSB_PRIVATE_H_ */
2164 --- a/include/linux/ssb/ssb.h
2165 +++ b/include/linux/ssb/ssb.h
2166 @@ -6,8 +6,10 @@
2167  #include <linux/types.h>
2168  #include <linux/spinlock.h>
2169  #include <linux/pci.h>
2170 +#include <linux/gpio.h>
2171  #include <linux/mod_devicetable.h>
2172  #include <linux/dma-mapping.h>
2173 +#include <linux/platform_device.h>
2174
2175  #include <linux/ssb/ssb_regs.h>
2176
2177 @@ -24,9 +26,9 @@ struct ssb_sprom_core_pwr_info {
2178
2179  struct ssb_sprom {
2180         u8 revision;
2181 -       u8 il0mac[6];           /* MAC address for 802.11b/g */
2182 -       u8 et0mac[6];           /* MAC address for Ethernet */
2183 -       u8 et1mac[6];           /* MAC address for 802.11a */
2184 +       u8 il0mac[6] __aligned(sizeof(u16));    /* MAC address for 802.11b/g */
2185 +       u8 et0mac[6] __aligned(sizeof(u16));    /* MAC address for Ethernet */
2186 +       u8 et1mac[6] __aligned(sizeof(u16));    /* MAC address for 802.11a */
2187         u8 et0phyaddr;          /* MII address for enet0 */
2188         u8 et1phyaddr;          /* MII address for enet1 */
2189         u8 et0mdcport;          /* MDIO for enet0 */
2190 @@ -338,13 +340,61 @@ enum ssb_bustype {
2191  #define SSB_BOARDVENDOR_DELL   0x1028  /* Dell */
2192  #define SSB_BOARDVENDOR_HP     0x0E11  /* HP */
2193  /* board_type */
2194 +#define SSB_BOARD_BCM94301CB   0x0406
2195 +#define SSB_BOARD_BCM94301MP   0x0407
2196 +#define SSB_BOARD_BU4309       0x040A
2197 +#define SSB_BOARD_BCM94309CB   0x040B
2198 +#define SSB_BOARD_BCM4309MP    0x040C
2199 +#define SSB_BOARD_BU4306       0x0416
2200  #define SSB_BOARD_BCM94306MP   0x0418
2201  #define SSB_BOARD_BCM4309G     0x0421
2202  #define SSB_BOARD_BCM4306CB    0x0417
2203 -#define SSB_BOARD_BCM4309MP    0x040C
2204 +#define SSB_BOARD_BCM94306PC   0x0425  /* pcmcia 3.3v 4306 card */
2205 +#define SSB_BOARD_BCM94306CBSG 0x042B  /* with SiGe PA */
2206 +#define SSB_BOARD_PCSG94306    0x042D  /* with SiGe PA */
2207 +#define SSB_BOARD_BU4704SD     0x042E  /* with sdram */
2208 +#define SSB_BOARD_BCM94704AGR  0x042F  /* dual 11a/11g Router */
2209 +#define SSB_BOARD_BCM94308MP   0x0430  /* 11a-only minipci */
2210 +#define SSB_BOARD_BU4318       0x0447
2211 +#define SSB_BOARD_CB4318       0x0448
2212 +#define SSB_BOARD_MPG4318      0x0449
2213  #define SSB_BOARD_MP4318       0x044A
2214 -#define SSB_BOARD_BU4306       0x0416
2215 -#define SSB_BOARD_BU4309       0x040A
2216 +#define SSB_BOARD_SD4318       0x044B
2217 +#define SSB_BOARD_BCM94306P    0x044C  /* with SiGe */
2218 +#define SSB_BOARD_BCM94303MP   0x044E
2219 +#define SSB_BOARD_BCM94306MPM  0x0450
2220 +#define SSB_BOARD_BCM94306MPL  0x0453
2221 +#define SSB_BOARD_PC4303       0x0454  /* pcmcia */
2222 +#define SSB_BOARD_BCM94306MPLNA        0x0457
2223 +#define SSB_BOARD_BCM94306MPH  0x045B
2224 +#define SSB_BOARD_BCM94306PCIV 0x045C
2225 +#define SSB_BOARD_BCM94318MPGH 0x0463
2226 +#define SSB_BOARD_BU4311       0x0464
2227 +#define SSB_BOARD_BCM94311MC   0x0465
2228 +#define SSB_BOARD_BCM94311MCAG 0x0466
2229 +/* 4321 boards */
2230 +#define SSB_BOARD_BU4321       0x046B
2231 +#define SSB_BOARD_BU4321E      0x047C
2232 +#define SSB_BOARD_MP4321       0x046C
2233 +#define SSB_BOARD_CB2_4321     0x046D
2234 +#define SSB_BOARD_CB2_4321_AG  0x0066
2235 +#define SSB_BOARD_MC4321       0x046E
2236 +/* 4325 boards */
2237 +#define SSB_BOARD_BCM94325DEVBU        0x0490
2238 +#define SSB_BOARD_BCM94325BGABU        0x0491
2239 +#define SSB_BOARD_BCM94325SDGWB        0x0492
2240 +#define SSB_BOARD_BCM94325SDGMDL       0x04AA
2241 +#define SSB_BOARD_BCM94325SDGMDL2      0x04C6
2242 +#define SSB_BOARD_BCM94325SDGMDL3      0x04C9
2243 +#define SSB_BOARD_BCM94325SDABGWBA     0x04E1
2244 +/* 4322 boards */
2245 +#define SSB_BOARD_BCM94322MC   0x04A4
2246 +#define SSB_BOARD_BCM94322USB  0x04A8  /* dualband */
2247 +#define SSB_BOARD_BCM94322HM   0x04B0
2248 +#define SSB_BOARD_BCM94322USB2D        0x04Bf  /* single band discrete front end */
2249 +/* 4312 boards */
2250 +#define SSB_BOARD_BU4312       0x048A
2251 +#define SSB_BOARD_BCM4312MCGSG 0x04B5
2252  /* chip_package */
2253  #define SSB_CHIPPACK_BCM4712S  1       /* Small 200pin 4712 */
2254  #define SSB_CHIPPACK_BCM4712M  2       /* Medium 225pin 4712 */
2255 @@ -432,7 +482,11 @@ struct ssb_bus {
2256  #ifdef CONFIG_SSB_EMBEDDED
2257         /* Lock for GPIO register access. */
2258         spinlock_t gpio_lock;
2259 +       struct platform_device *watchdog;
2260  #endif /* EMBEDDED */
2261 +#ifdef CONFIG_SSB_DRIVER_GPIO
2262 +       struct gpio_chip gpio;
2263 +#endif /* DRIVER_GPIO */
2264
2265         /* Internal-only stuff follows. Do not touch. */
2266         struct list_head list;
2267 --- a/include/linux/ssb/ssb_driver_chipcommon.h
2268 +++ b/include/linux/ssb/ssb_driver_chipcommon.h
2269 @@ -219,6 +219,7 @@
2270  #define SSB_CHIPCO_PMU_CTL                     0x0600 /* PMU control */
2271  #define  SSB_CHIPCO_PMU_CTL_ILP_DIV            0xFFFF0000 /* ILP div mask */
2272  #define  SSB_CHIPCO_PMU_CTL_ILP_DIV_SHIFT      16
2273 +#define  SSB_CHIPCO_PMU_CTL_PLL_UPD            0x00000400
2274  #define  SSB_CHIPCO_PMU_CTL_NOILPONW           0x00000200 /* No ILP on wait */
2275  #define  SSB_CHIPCO_PMU_CTL_HTREQEN            0x00000100 /* HT req enable */
2276  #define  SSB_CHIPCO_PMU_CTL_ALPREQEN           0x00000080 /* ALP req enable */
2277 @@ -504,7 +505,9 @@
2278  #define SSB_CHIPCO_FLASHCTL_ST_SE      0x02D8          /* Sector Erase */
2279  #define SSB_CHIPCO_FLASHCTL_ST_BE      0x00C7          /* Bulk Erase */
2280  #define SSB_CHIPCO_FLASHCTL_ST_DP      0x00B9          /* Deep Power-down */
2281 -#define SSB_CHIPCO_FLASHCTL_ST_RSIG    0x03AB          /* Read Electronic Signature */
2282 +#define SSB_CHIPCO_FLASHCTL_ST_RES     0x03AB          /* Read Electronic Signature */
2283 +#define SSB_CHIPCO_FLASHCTL_ST_CSA     0x1000          /* Keep chip select asserted */
2284 +#define SSB_CHIPCO_FLASHCTL_ST_SSE     0x0220          /* Sub-sector Erase */
2285
2286  /* Status register bits for ST flashes */
2287  #define SSB_CHIPCO_FLASHSTA_ST_WIP     0x01            /* Write In Progress */
2288 @@ -588,7 +591,10 @@ struct ssb_chipcommon {
2289         u32 status;
2290         /* Fast Powerup Delay constant */
2291         u16 fast_pwrup_delay;
2292 +       spinlock_t gpio_lock;
2293         struct ssb_chipcommon_pmu pmu;
2294 +       u32 ticks_per_ms;
2295 +       u32 max_timer_ms;
2296  };
2297
2298  static inline bool ssb_chipco_available(struct ssb_chipcommon *cc)
2299 @@ -628,8 +634,7 @@ enum ssb_clkmode {
2300  extern void ssb_chipco_set_clockmode(struct ssb_chipcommon *cc,
2301                                      enum ssb_clkmode mode);
2302
2303 -extern void ssb_chipco_watchdog_timer_set(struct ssb_chipcommon *cc,
2304 -                                         u32 ticks);
2305 +extern u32 ssb_chipco_watchdog_timer_set(struct ssb_chipcommon *cc, u32 ticks);
2306
2307  void ssb_chipco_irq_mask(struct ssb_chipcommon *cc, u32 mask, u32 value);
2308
2309 @@ -642,6 +647,8 @@ u32 ssb_chipco_gpio_outen(struct ssb_chi
2310  u32 ssb_chipco_gpio_control(struct ssb_chipcommon *cc, u32 mask, u32 value);
2311  u32 ssb_chipco_gpio_intmask(struct ssb_chipcommon *cc, u32 mask, u32 value);
2312  u32 ssb_chipco_gpio_polarity(struct ssb_chipcommon *cc, u32 mask, u32 value);
2313 +u32 ssb_chipco_gpio_pullup(struct ssb_chipcommon *cc, u32 mask, u32 value);
2314 +u32 ssb_chipco_gpio_pulldown(struct ssb_chipcommon *cc, u32 mask, u32 value);
2315
2316  #ifdef CONFIG_SSB_SERIAL
2317  extern int ssb_chipco_serial_init(struct ssb_chipcommon *cc,
2318 @@ -661,5 +668,6 @@ enum ssb_pmu_ldo_volt_id {
2319  void ssb_pmu_set_ldo_voltage(struct ssb_chipcommon *cc,
2320                              enum ssb_pmu_ldo_volt_id id, u32 voltage);
2321  void ssb_pmu_set_ldo_paref(struct ssb_chipcommon *cc, bool on);
2322 +void ssb_pmu_spuravoid_pllupdate(struct ssb_chipcommon *cc, int spuravoid);
2323
2324  #endif /* LINUX_SSB_CHIPCO_H_ */
2325 --- a/include/linux/ssb/ssb_driver_extif.h
2326 +++ b/include/linux/ssb/ssb_driver_extif.h
2327 @@ -152,12 +152,16 @@
2328  /* watchdog */
2329  #define SSB_EXTIF_WATCHDOG_CLK         48000000        /* Hz */
2330
2331 +#define SSB_EXTIF_WATCHDOG_MAX_TIMER   ((1 << 28) - 1)
2332 +#define SSB_EXTIF_WATCHDOG_MAX_TIMER_MS        (SSB_EXTIF_WATCHDOG_MAX_TIMER \
2333 +                                        / (SSB_EXTIF_WATCHDOG_CLK / 1000))
2334
2335
2336  #ifdef CONFIG_SSB_DRIVER_EXTIF
2337
2338  struct ssb_extif {
2339         struct ssb_device *dev;
2340 +       spinlock_t gpio_lock;
2341  };
2342
2343  static inline bool ssb_extif_available(struct ssb_extif *extif)
2344 @@ -171,8 +175,7 @@ extern void ssb_extif_get_clockcontrol(s
2345  extern void ssb_extif_timing_init(struct ssb_extif *extif,
2346                                   unsigned long ns);
2347
2348 -extern void ssb_extif_watchdog_timer_set(struct ssb_extif *extif,
2349 -                                        u32 ticks);
2350 +extern u32 ssb_extif_watchdog_timer_set(struct ssb_extif *extif, u32 ticks);
2351
2352  /* Extif GPIO pin access */
2353  u32 ssb_extif_gpio_in(struct ssb_extif *extif, u32 mask);
2354 @@ -205,10 +208,52 @@ void ssb_extif_get_clockcontrol(struct s
2355  }
2356
2357  static inline
2358 -void ssb_extif_watchdog_timer_set(struct ssb_extif *extif,
2359 -                                 u32 ticks)
2360 +void ssb_extif_timing_init(struct ssb_extif *extif, unsigned long ns)
2361  {
2362  }
2363
2364 +static inline
2365 +u32 ssb_extif_watchdog_timer_set(struct ssb_extif *extif, u32 ticks)
2366 +{
2367 +       return 0;
2368 +}
2369 +
2370 +static inline u32 ssb_extif_gpio_in(struct ssb_extif *extif, u32 mask)
2371 +{
2372 +       return 0;
2373 +}
2374 +
2375 +static inline u32 ssb_extif_gpio_out(struct ssb_extif *extif, u32 mask,
2376 +                                    u32 value)
2377 +{
2378 +       return 0;
2379 +}
2380 +
2381 +static inline u32 ssb_extif_gpio_outen(struct ssb_extif *extif, u32 mask,
2382 +                                      u32 value)
2383 +{
2384 +       return 0;
2385 +}
2386 +
2387 +static inline u32 ssb_extif_gpio_polarity(struct ssb_extif *extif, u32 mask,
2388 +                                         u32 value)
2389 +{
2390 +       return 0;
2391 +}
2392 +
2393 +static inline u32 ssb_extif_gpio_intmask(struct ssb_extif *extif, u32 mask,
2394 +                                        u32 value)
2395 +{
2396 +       return 0;
2397 +}
2398 +
2399 +#ifdef CONFIG_SSB_SERIAL
2400 +static inline int ssb_extif_serial_init(struct ssb_extif *extif,
2401 +                                       struct ssb_serial_port *ports)
2402 +{
2403 +       return 0;
2404 +}
2405 +#endif /* CONFIG_SSB_SERIAL */
2406 +
2407  #endif /* CONFIG_SSB_DRIVER_EXTIF */
2408  #endif /* LINUX_SSB_EXTIFCORE_H_ */
2409 --- a/include/linux/ssb/ssb_driver_gige.h
2410 +++ b/include/linux/ssb/ssb_driver_gige.h
2411 @@ -97,21 +97,16 @@ static inline bool ssb_gige_must_flush_p
2412         return 0;
2413  }
2414
2415 -#ifdef CONFIG_BCM47XX
2416 -#include <asm/mach-bcm47xx/nvram.h>
2417  /* Get the device MAC address */
2418 -static inline void ssb_gige_get_macaddr(struct pci_dev *pdev, u8 *macaddr)
2419 -{
2420 -       char buf[20];
2421 -       if (nvram_getenv("et0macaddr", buf, sizeof(buf)) < 0)
2422 -               return;
2423 -       nvram_parse_macaddr(buf, macaddr);
2424 -}
2425 -#else
2426 -static inline void ssb_gige_get_macaddr(struct pci_dev *pdev, u8 *macaddr)
2427 +static inline int ssb_gige_get_macaddr(struct pci_dev *pdev, u8 *macaddr)
2428  {
2429 +       struct ssb_gige *dev = pdev_to_ssb_gige(pdev);
2430 +       if (!dev)
2431 +               return -ENODEV;
2432 +
2433 +       memcpy(macaddr, dev->dev->bus->sprom.et0mac, 6);
2434 +       return 0;
2435  }
2436 -#endif
2437
2438  extern int ssb_gige_pcibios_plat_dev_init(struct ssb_device *sdev,
2439                                           struct pci_dev *pdev);
2440 @@ -175,6 +170,10 @@ static inline bool ssb_gige_must_flush_p
2441  {
2442         return 0;
2443  }
2444 +static inline int ssb_gige_get_macaddr(struct pci_dev *pdev, u8 *macaddr)
2445 +{
2446 +       return -ENODEV;
2447 +}
2448
2449  #endif /* CONFIG_SSB_DRIVER_GIGE */
2450  #endif /* LINUX_SSB_DRIVER_GIGE_H_ */
2451 --- a/include/linux/ssb/ssb_driver_mips.h
2452 +++ b/include/linux/ssb/ssb_driver_mips.h
2453 @@ -13,6 +13,24 @@ struct ssb_serial_port {
2454         unsigned int reg_shift;
2455  };
2456
2457 +struct ssb_pflash {
2458 +       bool present;
2459 +       u8 buswidth;
2460 +       u32 window;
2461 +       u32 window_size;
2462 +};
2463 +
2464 +#ifdef CONFIG_SSB_SFLASH
2465 +struct ssb_sflash {
2466 +       bool present;
2467 +       u32 window;
2468 +       u32 blocksize;
2469 +       u16 numblocks;
2470 +       u32 size;
2471 +
2472 +       void *priv;
2473 +};
2474 +#endif
2475
2476  struct ssb_mipscore {
2477         struct ssb_device *dev;
2478 @@ -20,9 +38,10 @@ struct ssb_mipscore {
2479         int nr_serial_ports;
2480         struct ssb_serial_port serial_ports[4];
2481
2482 -       u8 flash_buswidth;
2483 -       u32 flash_window;
2484 -       u32 flash_window_size;
2485 +       struct ssb_pflash pflash;
2486 +#ifdef CONFIG_SSB_SFLASH
2487 +       struct ssb_sflash sflash;
2488 +#endif
2489  };
2490
2491  extern void ssb_mipscore_init(struct ssb_mipscore *mcore);
2492 @@ -41,6 +60,11 @@ void ssb_mipscore_init(struct ssb_mipsco
2493  {
2494  }
2495
2496 +static inline unsigned int ssb_mips_irq(struct ssb_device *dev)
2497 +{
2498 +       return 0;
2499 +}
2500 +
2501  #endif /* CONFIG_SSB_DRIVER_MIPS */
2502
2503  #endif /* LINUX_SSB_MIPSCORE_H_ */
2504 --- a/include/linux/ssb/ssb_regs.h
2505 +++ b/include/linux/ssb/ssb_regs.h
2506 @@ -172,6 +172,7 @@
2507  #define SSB_SPROMSIZE_WORDS_R4         220
2508  #define SSB_SPROMSIZE_BYTES_R123       (SSB_SPROMSIZE_WORDS_R123 * sizeof(u16))
2509  #define SSB_SPROMSIZE_BYTES_R4         (SSB_SPROMSIZE_WORDS_R4 * sizeof(u16))
2510 +#define SSB_SPROMSIZE_WORDS_R10                230
2511  #define SSB_SPROM_BASE1                        0x1000
2512  #define SSB_SPROM_BASE31               0x0800
2513  #define SSB_SPROM_REVISION             0x007E
2514 @@ -289,11 +290,11 @@
2515  #define  SSB_SPROM4_ETHPHY_ET1A_SHIFT  5
2516  #define  SSB_SPROM4_ETHPHY_ET0M                (1<<14) /* MDIO for enet0 */
2517  #define  SSB_SPROM4_ETHPHY_ET1M                (1<<15) /* MDIO for enet1 */
2518 -#define SSB_SPROM4_ANTAVAIL            0x005D  /* Antenna available bitfields */
2519 -#define  SSB_SPROM4_ANTAVAIL_A         0x00FF  /* A-PHY bitfield */
2520 -#define  SSB_SPROM4_ANTAVAIL_A_SHIFT   0
2521 -#define  SSB_SPROM4_ANTAVAIL_BG                0xFF00  /* B-PHY and G-PHY bitfield */
2522 -#define  SSB_SPROM4_ANTAVAIL_BG_SHIFT  8
2523 +#define SSB_SPROM4_ANTAVAIL            0x005C  /* Antenna available bitfields */
2524 +#define  SSB_SPROM4_ANTAVAIL_BG                0x00FF  /* B-PHY and G-PHY bitfield */
2525 +#define  SSB_SPROM4_ANTAVAIL_BG_SHIFT  0
2526 +#define  SSB_SPROM4_ANTAVAIL_A         0xFF00  /* A-PHY bitfield */
2527 +#define  SSB_SPROM4_ANTAVAIL_A_SHIFT   8
2528  #define SSB_SPROM4_AGAIN01             0x005E  /* Antenna Gain (in dBm Q5.2) */
2529  #define  SSB_SPROM4_AGAIN0             0x00FF  /* Antenna 0 */
2530  #define  SSB_SPROM4_AGAIN0_SHIFT       0
2531 @@ -485,7 +486,7 @@
2532  #define  SSB_SPROM8_HWIQ_IQSWP_IQCAL_SWP_SHIFT 4
2533  #define  SSB_SPROM8_HWIQ_IQSWP_HW_IQCAL        0x0020
2534  #define  SSB_SPROM8_HWIQ_IQSWP_HW_IQCAL_SHIFT  5
2535 -#define SSB_SPROM8_TEMPDELTA           0x00BA
2536 +#define SSB_SPROM8_TEMPDELTA           0x00BC
2537  #define  SSB_SPROM8_TEMPDELTA_PHYCAL   0x00ff
2538  #define  SSB_SPROM8_TEMPDELTA_PHYCAL_SHIFT     0
2539  #define  SSB_SPROM8_TEMPDELTA_PERIOD   0x0f00
2540 --- /dev/null
2541 +++ b/include/linux/bcm47xx_wdt.h
2542 @@ -0,0 +1,19 @@
2543 +#ifndef LINUX_BCM47XX_WDT_H_
2544 +#define LINUX_BCM47XX_WDT_H_
2545 +
2546 +#include <linux/types.h>
2547 +
2548 +
2549 +struct bcm47xx_wdt {
2550 +       u32 (*timer_set)(struct bcm47xx_wdt *, u32);
2551 +       u32 (*timer_set_ms)(struct bcm47xx_wdt *, u32);
2552 +       u32 max_timer_ms;
2553 +
2554 +       void *driver_data;
2555 +};
2556 +
2557 +static inline void *bcm47xx_wdt_get_drvdata(struct bcm47xx_wdt *wdt)
2558 +{
2559 +       return wdt->driver_data;
2560 +}
2561 +#endif /* LINUX_BCM47XX_WDT_H_ */
2562 --- a/drivers/net/wireless/b43/phy_n.c
2563 +++ b/drivers/net/wireless/b43/phy_n.c
2564 @@ -4583,7 +4583,8 @@ static void b43_nphy_pmu_spur_avoid(stru
2565  #endif
2566  #ifdef CONFIG_B43_SSB
2567         case B43_BUS_SSB:
2568 -               /* FIXME */
2569 +               ssb_pmu_spuravoid_pllupdate(&dev->dev->sdev->bus->chipco,
2570 +                                           avoid);
2571                 break;
2572  #endif
2573         }