target/linux/generic/patches-2.6.34/975-ssb_update.patch

   1 --- a/drivers/net/b44.c
   2 +++ b/drivers/net/b44.c
   3 @@ -135,7 +135,6 @@ static void b44_init_rings(struct b44 *)
   4
   5  static void b44_init_hw(struct b44 *, int);
   6
   7 -static int dma_desc_align_mask;
   8  static int dma_desc_sync_size;
   9  static int instance;
  10
  11 @@ -150,9 +149,8 @@ static inline void b44_sync_dma_desc_for
  12                                                 unsigned long offset,
  13                                                 enum dma_data_direction dir)
  14  {
  15 -       ssb_dma_sync_single_range_for_device(sdev, dma_base,
  16 -                                            offset & dma_desc_align_mask,
  17 -                                            dma_desc_sync_size, dir);
  18 +       dma_sync_single_for_device(sdev->dma_dev, dma_base + offset,
  19 +                                  dma_desc_sync_size, dir);
  20  }
  21
  22  static inline void b44_sync_dma_desc_for_cpu(struct ssb_device *sdev,
  23 @@ -160,9 +158,8 @@ static inline void b44_sync_dma_desc_for
  24                                              unsigned long offset,
  25                                              enum dma_data_direction dir)
  26  {
  27 -       ssb_dma_sync_single_range_for_cpu(sdev, dma_base,
  28 -                                         offset & dma_desc_align_mask,
  29 -                                         dma_desc_sync_size, dir);
  30 +       dma_sync_single_for_cpu(sdev->dma_dev, dma_base + offset,
  31 +                               dma_desc_sync_size, dir);
  32  }
  33
  34  static inline unsigned long br32(const struct b44 *bp, unsigned long reg)
  35 @@ -608,10 +605,10 @@ static void b44_tx(struct b44 *bp)
  36
  37                 BUG_ON(skb == NULL);
  38
  39 -               ssb_dma_unmap_single(bp->sdev,
  40 -                                    rp->mapping,
  41 -                                    skb->len,
  42 -                                    DMA_TO_DEVICE);
  43 +               dma_unmap_single(bp->sdev->dma_dev,
  44 +                                rp->mapping,
  45 +                                skb->len,
  46 +                                DMA_TO_DEVICE);
  47                 rp->skb = NULL;
  48                 dev_kfree_skb_irq(skb);
  49         }
  50 @@ -648,29 +645,29 @@ static int b44_alloc_rx_skb(struct b44 *
  51         if (skb == NULL)
  52                 return -ENOMEM;
  53
  54 -       mapping = ssb_dma_map_single(bp->sdev, skb->data,
  55 -                                    RX_PKT_BUF_SZ,
  56 -                                    DMA_FROM_DEVICE);
  57 +       mapping = dma_map_single(bp->sdev->dma_dev, skb->data,
  58 +                                RX_PKT_BUF_SZ,
  59 +                                DMA_FROM_DEVICE);
  60
  61         /* Hardware bug work-around, the chip is unable to do PCI DMA
  62            to/from anything above 1GB :-( */
  63 -       if (ssb_dma_mapping_error(bp->sdev, mapping) ||
  64 +       if (dma_mapping_error(bp->sdev->dma_dev, mapping) ||
  65                 mapping + RX_PKT_BUF_SZ > DMA_BIT_MASK(30)) {
  66                 /* Sigh... */
  67 -               if (!ssb_dma_mapping_error(bp->sdev, mapping))
  68 -                       ssb_dma_unmap_single(bp->sdev, mapping,
  69 +               if (!dma_mapping_error(bp->sdev->dma_dev, mapping))
  70 +                       dma_unmap_single(bp->sdev->dma_dev, mapping,
  71                                              RX_PKT_BUF_SZ, DMA_FROM_DEVICE);
  72                 dev_kfree_skb_any(skb);
  73                 skb = __netdev_alloc_skb(bp->dev, RX_PKT_BUF_SZ, GFP_ATOMIC|GFP_DMA);
  74                 if (skb == NULL)
  75                         return -ENOMEM;
  76 -               mapping = ssb_dma_map_single(bp->sdev, skb->data,
  77 -                                            RX_PKT_BUF_SZ,
  78 -                                            DMA_FROM_DEVICE);
  79 -               if (ssb_dma_mapping_error(bp->sdev, mapping) ||
  80 -                       mapping + RX_PKT_BUF_SZ > DMA_BIT_MASK(30)) {
  81 -                       if (!ssb_dma_mapping_error(bp->sdev, mapping))
  82 -                               ssb_dma_unmap_single(bp->sdev, mapping, RX_PKT_BUF_SZ,DMA_FROM_DEVICE);
  83 +               mapping = dma_map_single(bp->sdev->dma_dev, skb->data,
  84 +                                        RX_PKT_BUF_SZ,
  85 +                                        DMA_FROM_DEVICE);
  86 +               if (dma_mapping_error(bp->sdev->dma_dev, mapping) ||
  87 +                   mapping + RX_PKT_BUF_SZ > DMA_BIT_MASK(30)) {
  88 +                       if (!dma_mapping_error(bp->sdev->dma_dev, mapping))
  89 +                               dma_unmap_single(bp->sdev->dma_dev, mapping, RX_PKT_BUF_SZ,DMA_FROM_DEVICE);
  90                         dev_kfree_skb_any(skb);
  91                         return -ENOMEM;
  92                 }
  93 @@ -745,9 +742,9 @@ static void b44_recycle_rx(struct b44 *b
  94                                              dest_idx * sizeof(*dest_desc),
  95                                              DMA_BIDIRECTIONAL);
  96
  97 -       ssb_dma_sync_single_for_device(bp->sdev, dest_map->mapping,
  98 -                                      RX_PKT_BUF_SZ,
  99 -                                      DMA_FROM_DEVICE);
 100 +       dma_sync_single_for_device(bp->sdev->dma_dev, dest_map->mapping,
 101 +                                  RX_PKT_BUF_SZ,
 102 +                                  DMA_FROM_DEVICE);
 103  }
 104
 105  static int b44_rx(struct b44 *bp, int budget)
 106 @@ -767,9 +764,9 @@ static int b44_rx(struct b44 *bp, int bu
 107                 struct rx_header *rh;
 108                 u16 len;
 109
 110 -               ssb_dma_sync_single_for_cpu(bp->sdev, map,
 111 -                                           RX_PKT_BUF_SZ,
 112 -                                           DMA_FROM_DEVICE);
 113 +               dma_sync_single_for_cpu(bp->sdev->dma_dev, map,
 114 +                                       RX_PKT_BUF_SZ,
 115 +                                       DMA_FROM_DEVICE);
 116                 rh = (struct rx_header *) skb->data;
 117                 len = le16_to_cpu(rh->len);
 118                 if ((len > (RX_PKT_BUF_SZ - RX_PKT_OFFSET)) ||
 119 @@ -801,8 +798,8 @@ static int b44_rx(struct b44 *bp, int bu
 120                         skb_size = b44_alloc_rx_skb(bp, cons, bp->rx_prod);
 121                         if (skb_size < 0)
 122                                 goto drop_it;
 123 -                       ssb_dma_unmap_single(bp->sdev, map,
 124 -                                            skb_size, DMA_FROM_DEVICE);
 125 +                       dma_unmap_single(bp->sdev->dma_dev, map,
 126 +                                        skb_size, DMA_FROM_DEVICE);
 127                         /* Leave out rx_header */
 128                         skb_put(skb, len + RX_PKT_OFFSET);
 129                         skb_pull(skb, RX_PKT_OFFSET);
 130 @@ -954,24 +951,24 @@ static netdev_tx_t b44_start_xmit(struct
 131                 goto err_out;
 132         }
 133
 134 -       mapping = ssb_dma_map_single(bp->sdev, skb->data, len, DMA_TO_DEVICE);
 135 -       if (ssb_dma_mapping_error(bp->sdev, mapping) || mapping + len > DMA_BIT_MASK(30)) {
 136 +       mapping = dma_map_single(bp->sdev->dma_dev, skb->data, len, DMA_TO_DEVICE);
 137 +       if (dma_mapping_error(bp->sdev->dma_dev, mapping) || mapping + len > DMA_BIT_MASK(30)) {
 138                 struct sk_buff *bounce_skb;
 139
 140                 /* Chip can't handle DMA to/from >1GB, use bounce buffer */
 141 -               if (!ssb_dma_mapping_error(bp->sdev, mapping))
 142 -                       ssb_dma_unmap_single(bp->sdev, mapping, len,
 143 +               if (!dma_mapping_error(bp->sdev->dma_dev, mapping))
 144 +                       dma_unmap_single(bp->sdev->dma_dev, mapping, len,
 145                                              DMA_TO_DEVICE);
 146
 147                 bounce_skb = __netdev_alloc_skb(dev, len, GFP_ATOMIC | GFP_DMA);
 148                 if (!bounce_skb)
 149                         goto err_out;
 150
 151 -               mapping = ssb_dma_map_single(bp->sdev, bounce_skb->data,
 152 -                                            len, DMA_TO_DEVICE);
 153 -               if (ssb_dma_mapping_error(bp->sdev, mapping) || mapping + len > DMA_BIT_MASK(30)) {
 154 -                       if (!ssb_dma_mapping_error(bp->sdev, mapping))
 155 -                               ssb_dma_unmap_single(bp->sdev, mapping,
 156 +               mapping = dma_map_single(bp->sdev->dma_dev, bounce_skb->data,
 157 +                                        len, DMA_TO_DEVICE);
 158 +               if (dma_mapping_error(bp->sdev->dma_dev, mapping) || mapping + len > DMA_BIT_MASK(30)) {
 159 +                       if (!dma_mapping_error(bp->sdev->dma_dev, mapping))
 160 +                               dma_unmap_single(bp->sdev->dma_dev, mapping,
 161                                                      len, DMA_TO_DEVICE);
 162                         dev_kfree_skb_any(bounce_skb);
 163                         goto err_out;
 164 @@ -1014,8 +1011,6 @@ static netdev_tx_t b44_start_xmit(struct
 165         if (TX_BUFFS_AVAIL(bp) < 1)
 166                 netif_stop_queue(dev);
 167
 168 -       dev->trans_start = jiffies;
 169 -
 170  out_unlock:
 171         spin_unlock_irqrestore(&bp->lock, flags);
 172
 173 @@ -1070,8 +1065,8 @@ static void b44_free_rings(struct b44 *b
 174
 175                 if (rp->skb == NULL)
 176                         continue;
 177 -               ssb_dma_unmap_single(bp->sdev, rp->mapping, RX_PKT_BUF_SZ,
 178 -                                    DMA_FROM_DEVICE);
 179 +               dma_unmap_single(bp->sdev->dma_dev, rp->mapping, RX_PKT_BUF_SZ,
 180 +                                DMA_FROM_DEVICE);
 181                 dev_kfree_skb_any(rp->skb);
 182                 rp->skb = NULL;
 183         }
 184 @@ -1082,8 +1077,8 @@ static void b44_free_rings(struct b44 *b
 185
 186                 if (rp->skb == NULL)
 187                         continue;
 188 -               ssb_dma_unmap_single(bp->sdev, rp->mapping, rp->skb->len,
 189 -                                    DMA_TO_DEVICE);
 190 +               dma_unmap_single(bp->sdev->dma_dev, rp->mapping, rp->skb->len,
 191 +                                DMA_TO_DEVICE);
 192                 dev_kfree_skb_any(rp->skb);
 193                 rp->skb = NULL;
 194         }
 195 @@ -1105,14 +1100,12 @@ static void b44_init_rings(struct b44 *b
 196         memset(bp->tx_ring, 0, B44_TX_RING_BYTES);
 197
 198         if (bp->flags & B44_FLAG_RX_RING_HACK)
 199 -               ssb_dma_sync_single_for_device(bp->sdev, bp->rx_ring_dma,
 200 -                                              DMA_TABLE_BYTES,
 201 -                                              DMA_BIDIRECTIONAL);
 202 +               dma_sync_single_for_device(bp->sdev->dma_dev, bp->rx_ring_dma,
 203 +                                          DMA_TABLE_BYTES, DMA_BIDIRECTIONAL);
 204
 205         if (bp->flags & B44_FLAG_TX_RING_HACK)
 206 -               ssb_dma_sync_single_for_device(bp->sdev, bp->tx_ring_dma,
 207 -                                              DMA_TABLE_BYTES,
 208 -                                              DMA_TO_DEVICE);
 209 +               dma_sync_single_for_device(bp->sdev->dma_dev, bp->tx_ring_dma,
 210 +                                          DMA_TABLE_BYTES, DMA_TO_DEVICE);
 211
 212         for (i = 0; i < bp->rx_pending; i++) {
 213                 if (b44_alloc_rx_skb(bp, -1, i) < 0)
 214 @@ -1132,27 +1125,23 @@ static void b44_free_consistent(struct b
 215         bp->tx_buffers = NULL;
 216         if (bp->rx_ring) {
 217                 if (bp->flags & B44_FLAG_RX_RING_HACK) {
 218 -                       ssb_dma_unmap_single(bp->sdev, bp->rx_ring_dma,
 219 -                                            DMA_TABLE_BYTES,
 220 -                                            DMA_BIDIRECTIONAL);
 221 +                       dma_unmap_single(bp->sdev->dma_dev, bp->rx_ring_dma,
 222 +                                        DMA_TABLE_BYTES, DMA_BIDIRECTIONAL);
 223                         kfree(bp->rx_ring);
 224                 } else
 225 -                       ssb_dma_free_consistent(bp->sdev, DMA_TABLE_BYTES,
 226 -                                               bp->rx_ring, bp->rx_ring_dma,
 227 -                                               GFP_KERNEL);
 228 +                       dma_free_coherent(bp->sdev->dma_dev, DMA_TABLE_BYTES,
 229 +                                         bp->rx_ring, bp->rx_ring_dma);
 230                 bp->rx_ring = NULL;
 231                 bp->flags &= ~B44_FLAG_RX_RING_HACK;
 232         }
 233         if (bp->tx_ring) {
 234                 if (bp->flags & B44_FLAG_TX_RING_HACK) {
 235 -                       ssb_dma_unmap_single(bp->sdev, bp->tx_ring_dma,
 236 -                                            DMA_TABLE_BYTES,
 237 -                                            DMA_TO_DEVICE);
 238 +                       dma_unmap_single(bp->sdev->dma_dev, bp->tx_ring_dma,
 239 +                                        DMA_TABLE_BYTES, DMA_TO_DEVICE);
 240                         kfree(bp->tx_ring);
 241                 } else
 242 -                       ssb_dma_free_consistent(bp->sdev, DMA_TABLE_BYTES,
 243 -                                               bp->tx_ring, bp->tx_ring_dma,
 244 -                                               GFP_KERNEL);
 245 +                       dma_free_coherent(bp->sdev->dma_dev, DMA_TABLE_BYTES,
 246 +                                         bp->tx_ring, bp->tx_ring_dma);
 247                 bp->tx_ring = NULL;
 248                 bp->flags &= ~B44_FLAG_TX_RING_HACK;
 249         }
 250 @@ -1177,7 +1166,8 @@ static int b44_alloc_consistent(struct b
 251                 goto out_err;
 252
 253         size = DMA_TABLE_BYTES;
 254 -       bp->rx_ring = ssb_dma_alloc_consistent(bp->sdev, size, &bp->rx_ring_dma, gfp);
 255 +       bp->rx_ring = dma_alloc_coherent(bp->sdev->dma_dev, size,
 256 +                                        &bp->rx_ring_dma, gfp);
 257         if (!bp->rx_ring) {
 258                 /* Allocation may have failed due to pci_alloc_consistent
 259                    insisting on use of GFP_DMA, which is more restrictive
 260 @@ -1189,11 +1179,11 @@ static int b44_alloc_consistent(struct b
 261                 if (!rx_ring)
 262                         goto out_err;
 263
 264 -               rx_ring_dma = ssb_dma_map_single(bp->sdev, rx_ring,
 265 -                                                DMA_TABLE_BYTES,
 266 -                                                DMA_BIDIRECTIONAL);
 267 +               rx_ring_dma = dma_map_single(bp->sdev->dma_dev, rx_ring,
 268 +                                            DMA_TABLE_BYTES,
 269 +                                            DMA_BIDIRECTIONAL);
 270
 271 -               if (ssb_dma_mapping_error(bp->sdev, rx_ring_dma) ||
 272 +               if (dma_mapping_error(bp->sdev->dma_dev, rx_ring_dma) ||
 273                         rx_ring_dma + size > DMA_BIT_MASK(30)) {
 274                         kfree(rx_ring);
 275                         goto out_err;
 276 @@ -1204,7 +1194,8 @@ static int b44_alloc_consistent(struct b
 277                 bp->flags |= B44_FLAG_RX_RING_HACK;
 278         }
 279
 280 -       bp->tx_ring = ssb_dma_alloc_consistent(bp->sdev, size, &bp->tx_ring_dma, gfp);
 281 +       bp->tx_ring = dma_alloc_coherent(bp->sdev->dma_dev, size,
 282 +                                        &bp->tx_ring_dma, gfp);
 283         if (!bp->tx_ring) {
 284                 /* Allocation may have failed due to ssb_dma_alloc_consistent
 285                    insisting on use of GFP_DMA, which is more restrictive
 286 @@ -1216,11 +1207,11 @@ static int b44_alloc_consistent(struct b
 287                 if (!tx_ring)
 288                         goto out_err;
 289
 290 -               tx_ring_dma = ssb_dma_map_single(bp->sdev, tx_ring,
 291 -                                           DMA_TABLE_BYTES,
 292 -                                           DMA_TO_DEVICE);
 293 +               tx_ring_dma = dma_map_single(bp->sdev->dma_dev, tx_ring,
 294 +                                            DMA_TABLE_BYTES,
 295 +                                            DMA_TO_DEVICE);
 296
 297 -               if (ssb_dma_mapping_error(bp->sdev, tx_ring_dma) ||
 298 +               if (dma_mapping_error(bp->sdev->dma_dev, tx_ring_dma) ||
 299                         tx_ring_dma + size > DMA_BIT_MASK(30)) {
 300                         kfree(tx_ring);
 301                         goto out_err;
 302 @@ -2176,12 +2167,14 @@ static int __devinit b44_init_one(struct
 303                         "Failed to powerup the bus\n");
 304                 goto err_out_free_dev;
 305         }
 306 -       err = ssb_dma_set_mask(sdev, DMA_BIT_MASK(30));
 307 -       if (err) {
 308 +
 309 +       if (dma_set_mask(sdev->dma_dev, DMA_BIT_MASK(30)) ||
 310 +           dma_set_coherent_mask(sdev->dma_dev, DMA_BIT_MASK(30))) {
 311                 dev_err(sdev->dev,
 312                         "Required 30BIT DMA mask unsupported by the system\n");
 313                 goto err_out_powerdown;
 314         }
 315 +
 316         err = b44_get_invariants(bp);
 317         if (err) {
 318                 dev_err(sdev->dev,
 319 @@ -2346,7 +2339,6 @@ static int __init b44_init(void)
 320         int err;
 321
 322         /* Setup paramaters for syncing RX/TX DMA descriptors */
 323 -       dma_desc_align_mask = ~(dma_desc_align_size - 1);
 324         dma_desc_sync_size = max_t(unsigned int, dma_desc_align_size, sizeof(struct dma_desc));
 325
 326         err = b44_pci_init();
 327 --- a/drivers/ssb/b43_pci_bridge.c
 328 +++ b/drivers/ssb/b43_pci_bridge.c
 329 @@ -24,6 +24,7 @@ static const struct pci_device_id b43_pc
 330         { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4312) },
 331         { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4315) },
 332         { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4318) },
 333 +       { PCI_DEVICE(PCI_VENDOR_ID_BCM_GVC,  0x4318) },
 334         { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4319) },
 335         { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4320) },
 336         { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4321) },
 337 --- a/drivers/ssb/driver_chipcommon.c
 338 +++ b/drivers/ssb/driver_chipcommon.c
 339 @@ -209,6 +209,24 @@ static void chipco_powercontrol_init(str
 340         }
 341  }
 342
 343 +/* http://bcm-v4.sipsolutions.net/802.11/PmuFastPwrupDelay */
 344 +static u16 pmu_fast_powerup_delay(struct ssb_chipcommon *cc)
 345 +{
 346 +       struct ssb_bus *bus = cc->dev->bus;
 347 +
 348 +       switch (bus->chip_id) {
 349 +       case 0x4312:
 350 +       case 0x4322:
 351 +       case 0x4328:
 352 +               return 7000;
 353 +       case 0x4325:
 354 +               /* TODO: */
 355 +       default:
 356 +               return 15000;
 357 +       }
 358 +}
 359 +
 360 +/* http://bcm-v4.sipsolutions.net/802.11/ClkctlFastPwrupDelay */
 361  static void calc_fast_powerup_delay(struct ssb_chipcommon *cc)
 362  {
 363         struct ssb_bus *bus = cc->dev->bus;
 364 @@ -218,6 +236,12 @@ static void calc_fast_powerup_delay(stru
 365
 366         if (bus->bustype != SSB_BUSTYPE_PCI)
 367                 return;
 368 +
 369 +       if (cc->capabilities & SSB_CHIPCO_CAP_PMU) {
 370 +               cc->fast_pwrup_delay = pmu_fast_powerup_delay(cc);
 371 +               return;
 372 +       }
 373 +
 374         if (!(cc->capabilities & SSB_CHIPCO_CAP_PCTL))
 375                 return;
 376
 377 @@ -373,6 +397,7 @@ u32 ssb_chipco_gpio_control(struct ssb_c
 378  {
 379         return chipco_write32_masked(cc, SSB_CHIPCO_GPIOCTL, mask, value);
 380  }
 381 +EXPORT_SYMBOL(ssb_chipco_gpio_control);
 382
 383  u32 ssb_chipco_gpio_intmask(struct ssb_chipcommon *cc, u32 mask, u32 value)
 384  {
 385 --- a/drivers/ssb/driver_chipcommon_pmu.c
 386 +++ b/drivers/ssb/driver_chipcommon_pmu.c
 387 @@ -502,9 +502,9 @@ static void ssb_pmu_resources_init(struc
 388                 chipco_write32(cc, SSB_CHIPCO_PMU_MAXRES_MSK, max_msk);
 389  }
 390
 391 +/* http://bcm-v4.sipsolutions.net/802.11/SSB/PmuInit */
 392  void ssb_pmu_init(struct ssb_chipcommon *cc)
 393  {
 394 -       struct ssb_bus *bus = cc->dev->bus;
 395         u32 pmucap;
 396
 397         if (!(cc->capabilities & SSB_CHIPCO_CAP_PMU))
 398 @@ -516,15 +516,12 @@ void ssb_pmu_init(struct ssb_chipcommon
 399         ssb_dprintk(KERN_DEBUG PFX "Found rev %u PMU (capabilities 0x%08X)\n",
 400                     cc->pmu.rev, pmucap);
 401
 402 -       if (cc->pmu.rev >= 1) {
 403 -               if ((bus->chip_id == 0x4325) && (bus->chip_rev < 2)) {
 404 -                       chipco_mask32(cc, SSB_CHIPCO_PMU_CTL,
 405 -                                     ~SSB_CHIPCO_PMU_CTL_NOILPONW);
 406 -               } else {
 407 -                       chipco_set32(cc, SSB_CHIPCO_PMU_CTL,
 408 -                                    SSB_CHIPCO_PMU_CTL_NOILPONW);
 409 -               }
 410 -       }
 411 +       if (cc->pmu.rev == 1)
 412 +               chipco_mask32(cc, SSB_CHIPCO_PMU_CTL,
 413 +                             ~SSB_CHIPCO_PMU_CTL_NOILPONW);
 414 +       else
 415 +               chipco_set32(cc, SSB_CHIPCO_PMU_CTL,
 416 +                            SSB_CHIPCO_PMU_CTL_NOILPONW);
 417         ssb_pmu_pll_init(cc);
 418         ssb_pmu_resources_init(cc);
 419  }
 420 --- a/drivers/ssb/main.c
 421 +++ b/drivers/ssb/main.c
 422 @@ -385,6 +385,35 @@ static int ssb_device_uevent(struct devi
 423                              ssb_dev->id.revision);
 424  }
 425
 426 +#define ssb_config_attr(attrib, field, format_string) \
 427 +static ssize_t \
 428 +attrib##_show(struct device *dev, struct device_attribute *attr, char *buf) \
 429 +{ \
 430 +       return sprintf(buf, format_string, dev_to_ssb_dev(dev)->field); \
 431 +}
 432 +
 433 +ssb_config_attr(core_num, core_index, "%u\n")
 434 +ssb_config_attr(coreid, id.coreid, "0x%04x\n")
 435 +ssb_config_attr(vendor, id.vendor, "0x%04x\n")
 436 +ssb_config_attr(revision, id.revision, "%u\n")
 437 +ssb_config_attr(irq, irq, "%u\n")
 438 +static ssize_t
 439 +name_show(struct device *dev, struct device_attribute *attr, char *buf)
 440 +{
 441 +       return sprintf(buf, "%s\n",
 442 +                      ssb_core_name(dev_to_ssb_dev(dev)->id.coreid));
 443 +}
 444 +
 445 +static struct device_attribute ssb_device_attrs[] = {
 446 +       __ATTR_RO(name),
 447 +       __ATTR_RO(core_num),
 448 +       __ATTR_RO(coreid),
 449 +       __ATTR_RO(vendor),
 450 +       __ATTR_RO(revision),
 451 +       __ATTR_RO(irq),
 452 +       __ATTR_NULL,
 453 +};
 454 +
 455  static struct bus_type ssb_bustype = {
 456         .name           = "ssb",
 457         .match          = ssb_bus_match,
 458 @@ -394,6 +423,7 @@ static struct bus_type ssb_bustype = {
 459         .suspend        = ssb_device_suspend,
 460         .resume         = ssb_device_resume,
 461         .uevent         = ssb_device_uevent,
 462 +       .dev_attrs      = ssb_device_attrs,
 463  };
 464
 465  static void ssb_buses_lock(void)
 466 @@ -486,6 +516,7 @@ static int ssb_devices_register(struct s
 467  #ifdef CONFIG_SSB_PCIHOST
 468                         sdev->irq = bus->host_pci->irq;
 469                         dev->parent = &bus->host_pci->dev;
 470 +                       sdev->dma_dev = dev->parent;
 471  #endif
 472                         break;
 473                 case SSB_BUSTYPE_PCMCIA:
 474 @@ -501,6 +532,7 @@ static int ssb_devices_register(struct s
 475                         break;
 476                 case SSB_BUSTYPE_SSB:
 477                         dev->dma_mask = &dev->coherent_dma_mask;
 478 +                       sdev->dma_dev = dev;
 479                         break;
 480                 }
 481
 482 @@ -834,6 +866,9 @@ int ssb_bus_pcibus_register(struct ssb_b
 483         if (!err) {
 484                 ssb_printk(KERN_INFO PFX "Sonics Silicon Backplane found on "
 485                            "PCI device %s\n", dev_name(&host_pci->dev));
 486 +       } else {
 487 +               ssb_printk(KERN_ERR PFX "Failed to register PCI version"
 488 +                          " of SSB with error %d\n", err);
 489         }
 490
 491         return err;
 492 @@ -1159,10 +1194,10 @@ void ssb_device_enable(struct ssb_device
 493  }
 494  EXPORT_SYMBOL(ssb_device_enable);
 495
 496 -/* Wait for a bit in a register to get set or unset.
 497 +/* Wait for bitmask in a register to get set or cleared.
 498   * timeout is in units of ten-microseconds */
 499 -static int ssb_wait_bit(struct ssb_device *dev, u16 reg, u32 bitmask,
 500 -                       int timeout, int set)
 501 +static int ssb_wait_bits(struct ssb_device *dev, u16 reg, u32 bitmask,
 502 +                        int timeout, int set)
 503  {
 504         int i;
 505         u32 val;
 506 @@ -1170,7 +1205,7 @@ static int ssb_wait_bit(struct ssb_devic
 507         for (i = 0; i < timeout; i++) {
 508                 val = ssb_read32(dev, reg);
 509                 if (set) {
 510 -                       if (val & bitmask)
 511 +                       if ((val & bitmask) == bitmask)
 512                                 return 0;
 513                 } else {
 514                         if (!(val & bitmask))
 515 @@ -1187,20 +1222,38 @@ static int ssb_wait_bit(struct ssb_devic
 516
 517  void ssb_device_disable(struct ssb_device *dev, u32 core_specific_flags)
 518  {
 519 -       u32 reject;
 520 +       u32 reject, val;
 521
 522         if (ssb_read32(dev, SSB_TMSLOW) & SSB_TMSLOW_RESET)
 523                 return;
 524
 525         reject = ssb_tmslow_reject_bitmask(dev);
 526 -       ssb_write32(dev, SSB_TMSLOW, reject | SSB_TMSLOW_CLOCK);
 527 -       ssb_wait_bit(dev, SSB_TMSLOW, reject, 1000, 1);
 528 -       ssb_wait_bit(dev, SSB_TMSHIGH, SSB_TMSHIGH_BUSY, 1000, 0);
 529 -       ssb_write32(dev, SSB_TMSLOW,
 530 -                   SSB_TMSLOW_FGC | SSB_TMSLOW_CLOCK |
 531 -                   reject | SSB_TMSLOW_RESET |
 532 -                   core_specific_flags);
 533 -       ssb_flush_tmslow(dev);
 534 +
 535 +       if (ssb_read32(dev, SSB_TMSLOW) & SSB_TMSLOW_CLOCK) {
 536 +               ssb_write32(dev, SSB_TMSLOW, reject | SSB_TMSLOW_CLOCK);
 537 +               ssb_wait_bits(dev, SSB_TMSLOW, reject, 1000, 1);
 538 +               ssb_wait_bits(dev, SSB_TMSHIGH, SSB_TMSHIGH_BUSY, 1000, 0);
 539 +
 540 +               if (ssb_read32(dev, SSB_IDLOW) & SSB_IDLOW_INITIATOR) {
 541 +                       val = ssb_read32(dev, SSB_IMSTATE);
 542 +                       val |= SSB_IMSTATE_REJECT;
 543 +                       ssb_write32(dev, SSB_IMSTATE, val);
 544 +                       ssb_wait_bits(dev, SSB_IMSTATE, SSB_IMSTATE_BUSY, 1000,
 545 +                                     0);
 546 +               }
 547 +
 548 +               ssb_write32(dev, SSB_TMSLOW,
 549 +                       SSB_TMSLOW_FGC | SSB_TMSLOW_CLOCK |
 550 +                       reject | SSB_TMSLOW_RESET |
 551 +                       core_specific_flags);
 552 +               ssb_flush_tmslow(dev);
 553 +
 554 +               if (ssb_read32(dev, SSB_IDLOW) & SSB_IDLOW_INITIATOR) {
 555 +                       val = ssb_read32(dev, SSB_IMSTATE);
 556 +                       val &= ~SSB_IMSTATE_REJECT;
 557 +                       ssb_write32(dev, SSB_IMSTATE, val);
 558 +               }
 559 +       }
 560
 561         ssb_write32(dev, SSB_TMSLOW,
 562                     reject | SSB_TMSLOW_RESET |
 563 @@ -1223,80 +1276,6 @@ u32 ssb_dma_translation(struct ssb_devic
 564  }
 565  EXPORT_SYMBOL(ssb_dma_translation);
 566
 567 -int ssb_dma_set_mask(struct ssb_device *dev, u64 mask)
 568 -{
 569 -#ifdef CONFIG_SSB_PCIHOST
 570 -       int err;
 571 -#endif
 572 -
 573 -       switch (dev->bus->bustype) {
 574 -       case SSB_BUSTYPE_PCI:
 575 -#ifdef CONFIG_SSB_PCIHOST
 576 -               err = pci_set_dma_mask(dev->bus->host_pci, mask);
 577 -               if (err)
 578 -                       return err;
 579 -               err = pci_set_consistent_dma_mask(dev->bus->host_pci, mask);
 580 -               return err;
 581 -#endif
 582 -       case SSB_BUSTYPE_SSB:
 583 -               return dma_set_mask(dev->dev, mask);
 584 -       default:
 585 -               __ssb_dma_not_implemented(dev);
 586 -       }
 587 -       return -ENOSYS;
 588 -}
 589 -EXPORT_SYMBOL(ssb_dma_set_mask);
 590 -
 591 -void * ssb_dma_alloc_consistent(struct ssb_device *dev, size_t size,
 592 -                               dma_addr_t *dma_handle, gfp_t gfp_flags)
 593 -{
 594 -       switch (dev->bus->bustype) {
 595 -       case SSB_BUSTYPE_PCI:
 596 -#ifdef CONFIG_SSB_PCIHOST
 597 -               if (gfp_flags & GFP_DMA) {
 598 -                       /* Workaround: The PCI API does not support passing
 599 -                        * a GFP flag. */
 600 -                       return dma_alloc_coherent(&dev->bus->host_pci->dev,
 601 -                                                 size, dma_handle, gfp_flags);
 602 -               }
 603 -               return pci_alloc_consistent(dev->bus->host_pci, size, dma_handle);
 604 -#endif
 605 -       case SSB_BUSTYPE_SSB:
 606 -               return dma_alloc_coherent(dev->dev, size, dma_handle, gfp_flags);
 607 -       default:
 608 -               __ssb_dma_not_implemented(dev);
 609 -       }
 610 -       return NULL;
 611 -}
 612 -EXPORT_SYMBOL(ssb_dma_alloc_consistent);
 613 -
 614 -void ssb_dma_free_consistent(struct ssb_device *dev, size_t size,
 615 -                            void *vaddr, dma_addr_t dma_handle,
 616 -                            gfp_t gfp_flags)
 617 -{
 618 -       switch (dev->bus->bustype) {
 619 -       case SSB_BUSTYPE_PCI:
 620 -#ifdef CONFIG_SSB_PCIHOST
 621 -               if (gfp_flags & GFP_DMA) {
 622 -                       /* Workaround: The PCI API does not support passing
 623 -                        * a GFP flag. */
 624 -                       dma_free_coherent(&dev->bus->host_pci->dev,
 625 -                                         size, vaddr, dma_handle);
 626 -                       return;
 627 -               }
 628 -               pci_free_consistent(dev->bus->host_pci, size,
 629 -                                   vaddr, dma_handle);
 630 -               return;
 631 -#endif
 632 -       case SSB_BUSTYPE_SSB:
 633 -               dma_free_coherent(dev->dev, size, vaddr, dma_handle);
 634 -               return;
 635 -       default:
 636 -               __ssb_dma_not_implemented(dev);
 637 -       }
 638 -}
 639 -EXPORT_SYMBOL(ssb_dma_free_consistent);
 640 -
 641  int ssb_bus_may_powerdown(struct ssb_bus *bus)
 642  {
 643         struct ssb_chipcommon *cc;
 644 --- a/drivers/ssb/pci.c
 645 +++ b/drivers/ssb/pci.c
 646 @@ -168,7 +168,7 @@ err_pci:
 647  }
 648
 649  /* Get the word-offset for a SSB_SPROM_XXX define. */
 650 -#define SPOFF(offset)  (((offset) - SSB_SPROM_BASE1) / sizeof(u16))
 651 +#define SPOFF(offset)  ((offset) / sizeof(u16))
 652  /* Helper to extract some _offset, which is one of the SSB_SPROM_XXX defines. */
 653  #define SPEX16(_outvar, _offset, _mask, _shift)        \
 654         out->_outvar = ((in[SPOFF(_offset)] & (_mask)) >> (_shift))
 655 @@ -406,6 +406,46 @@ static void sprom_extract_r123(struct ss
 656         out->antenna_gain.ghz5.a3 = gain;
 657  }
 658
 659 +/* Revs 4 5 and 8 have partially shared layout */
 660 +static void sprom_extract_r458(struct ssb_sprom *out, const u16 *in)
 661 +{
 662 +       SPEX(txpid2g[0], SSB_SPROM4_TXPID2G01,
 663 +            SSB_SPROM4_TXPID2G0, SSB_SPROM4_TXPID2G0_SHIFT);
 664 +       SPEX(txpid2g[1], SSB_SPROM4_TXPID2G01,
 665 +            SSB_SPROM4_TXPID2G1, SSB_SPROM4_TXPID2G1_SHIFT);
 666 +       SPEX(txpid2g[2], SSB_SPROM4_TXPID2G23,
 667 +            SSB_SPROM4_TXPID2G2, SSB_SPROM4_TXPID2G2_SHIFT);
 668 +       SPEX(txpid2g[3], SSB_SPROM4_TXPID2G23,
 669 +            SSB_SPROM4_TXPID2G3, SSB_SPROM4_TXPID2G3_SHIFT);
 670 +
 671 +       SPEX(txpid5gl[0], SSB_SPROM4_TXPID5GL01,
 672 +            SSB_SPROM4_TXPID5GL0, SSB_SPROM4_TXPID5GL0_SHIFT);
 673 +       SPEX(txpid5gl[1], SSB_SPROM4_TXPID5GL01,
 674 +            SSB_SPROM4_TXPID5GL1, SSB_SPROM4_TXPID5GL1_SHIFT);
 675 +       SPEX(txpid5gl[2], SSB_SPROM4_TXPID5GL23,
 676 +            SSB_SPROM4_TXPID5GL2, SSB_SPROM4_TXPID5GL2_SHIFT);
 677 +       SPEX(txpid5gl[3], SSB_SPROM4_TXPID5GL23,
 678 +            SSB_SPROM4_TXPID5GL3, SSB_SPROM4_TXPID5GL3_SHIFT);
 679 +
 680 +       SPEX(txpid5g[0], SSB_SPROM4_TXPID5G01,
 681 +            SSB_SPROM4_TXPID5G0, SSB_SPROM4_TXPID5G0_SHIFT);
 682 +       SPEX(txpid5g[1], SSB_SPROM4_TXPID5G01,
 683 +            SSB_SPROM4_TXPID5G1, SSB_SPROM4_TXPID5G1_SHIFT);
 684 +       SPEX(txpid5g[2], SSB_SPROM4_TXPID5G23,
 685 +            SSB_SPROM4_TXPID5G2, SSB_SPROM4_TXPID5G2_SHIFT);
 686 +       SPEX(txpid5g[3], SSB_SPROM4_TXPID5G23,
 687 +            SSB_SPROM4_TXPID5G3, SSB_SPROM4_TXPID5G3_SHIFT);
 688 +
 689 +       SPEX(txpid5gh[0], SSB_SPROM4_TXPID5GH01,
 690 +            SSB_SPROM4_TXPID5GH0, SSB_SPROM4_TXPID5GH0_SHIFT);
 691 +       SPEX(txpid5gh[1], SSB_SPROM4_TXPID5GH01,
 692 +            SSB_SPROM4_TXPID5GH1, SSB_SPROM4_TXPID5GH1_SHIFT);
 693 +       SPEX(txpid5gh[2], SSB_SPROM4_TXPID5GH23,
 694 +            SSB_SPROM4_TXPID5GH2, SSB_SPROM4_TXPID5GH2_SHIFT);
 695 +       SPEX(txpid5gh[3], SSB_SPROM4_TXPID5GH23,
 696 +            SSB_SPROM4_TXPID5GH3, SSB_SPROM4_TXPID5GH3_SHIFT);
 697 +}
 698 +
 699  static void sprom_extract_r45(struct ssb_sprom *out, const u16 *in)
 700  {
 701         int i;
 702 @@ -428,10 +468,14 @@ static void sprom_extract_r45(struct ssb
 703                 SPEX(country_code, SSB_SPROM4_CCODE, 0xFFFF, 0);
 704                 SPEX(boardflags_lo, SSB_SPROM4_BFLLO, 0xFFFF, 0);
 705                 SPEX(boardflags_hi, SSB_SPROM4_BFLHI, 0xFFFF, 0);
 706 +               SPEX(boardflags2_lo, SSB_SPROM4_BFL2LO, 0xFFFF, 0);
 707 +               SPEX(boardflags2_hi, SSB_SPROM4_BFL2HI, 0xFFFF, 0);
 708         } else {
 709                 SPEX(country_code, SSB_SPROM5_CCODE, 0xFFFF, 0);
 710                 SPEX(boardflags_lo, SSB_SPROM5_BFLLO, 0xFFFF, 0);
 711                 SPEX(boardflags_hi, SSB_SPROM5_BFLHI, 0xFFFF, 0);
 712 +               SPEX(boardflags2_lo, SSB_SPROM5_BFL2LO, 0xFFFF, 0);
 713 +               SPEX(boardflags2_hi, SSB_SPROM5_BFL2HI, 0xFFFF, 0);
 714         }
 715         SPEX(ant_available_a, SSB_SPROM4_ANTAVAIL, SSB_SPROM4_ANTAVAIL_A,
 716              SSB_SPROM4_ANTAVAIL_A_SHIFT);
 717 @@ -471,6 +515,8 @@ static void sprom_extract_r45(struct ssb
 718         memcpy(&out->antenna_gain.ghz5, &out->antenna_gain.ghz24,
 719                sizeof(out->antenna_gain.ghz5));
 720
 721 +       sprom_extract_r458(out, in);
 722 +
 723         /* TODO - get remaining rev 4 stuff needed */
 724  }
 725
 726 @@ -561,6 +607,8 @@ static void sprom_extract_r8(struct ssb_
 727         memcpy(&out->antenna_gain.ghz5, &out->antenna_gain.ghz24,
 728                sizeof(out->antenna_gain.ghz5));
 729
 730 +       sprom_extract_r458(out, in);
 731 +
 732         /* TODO - get remaining rev 8 stuff needed */
 733  }
 734
 735 @@ -573,37 +621,34 @@ static int sprom_extract(struct ssb_bus
 736         ssb_dprintk(KERN_DEBUG PFX "SPROM revision %d detected.\n", out->revision);
 737         memset(out->et0mac, 0xFF, 6);           /* preset et0 and et1 mac */
 738         memset(out->et1mac, 0xFF, 6);
 739 +
 740         if ((bus->chip_id & 0xFF00) == 0x4400) {
 741                 /* Workaround: The BCM44XX chip has a stupid revision
 742                  * number stored in the SPROM.
 743                  * Always extract r1. */
 744                 out->revision = 1;
 745 +               ssb_dprintk(KERN_DEBUG PFX "SPROM treated as revision %d\n", out->revision);
 746 +       }
 747 +
 748 +       switch (out->revision) {
 749 +       case 1:
 750 +       case 2:
 751 +       case 3:
 752                 sprom_extract_r123(out, in);
 753 -       } else if (bus->chip_id == 0x4321) {
 754 -               /* the BCM4328 has a chipid == 0x4321 and a rev 4 SPROM */
 755 -               out->revision = 4;
 756 +               break;
 757 +       case 4:
 758 +       case 5:
 759                 sprom_extract_r45(out, in);
 760 -       } else {
 761 -               switch (out->revision) {
 762 -               case 1:
 763 -               case 2:
 764 -               case 3:
 765 -                       sprom_extract_r123(out, in);
 766 -                       break;
 767 -               case 4:
 768 -               case 5:
 769 -                       sprom_extract_r45(out, in);
 770 -                       break;
 771 -               case 8:
 772 -                       sprom_extract_r8(out, in);
 773 -                       break;
 774 -               default:
 775 -                       ssb_printk(KERN_WARNING PFX "Unsupported SPROM"
 776 -                                  "  revision %d detected. Will extract"
 777 -                                  " v1\n", out->revision);
 778 -                       out->revision = 1;
 779 -                       sprom_extract_r123(out, in);
 780 -               }
 781 +               break;
 782 +       case 8:
 783 +               sprom_extract_r8(out, in);
 784 +               break;
 785 +       default:
 786 +               ssb_printk(KERN_WARNING PFX "Unsupported SPROM"
 787 +                          " revision %d detected. Will extract"
 788 +                          " v1\n", out->revision);
 789 +               out->revision = 1;
 790 +               sprom_extract_r123(out, in);
 791         }
 792
 793         if (out->boardflags_lo == 0xFFFF)
 794 @@ -618,7 +663,7 @@ static int ssb_pci_sprom_get(struct ssb_
 795                              struct ssb_sprom *sprom)
 796  {
 797         const struct ssb_sprom *fallback;
 798 -       int err = -ENOMEM;
 799 +       int err;
 800         u16 *buf;
 801
 802         if (!ssb_is_sprom_available(bus)) {
 803 @@ -645,7 +690,7 @@ static int ssb_pci_sprom_get(struct ssb_
 804
 805         buf = kcalloc(SSB_SPROMSIZE_WORDS_R123, sizeof(u16), GFP_KERNEL);
 806         if (!buf)
 807 -               goto out;
 808 +               return -ENOMEM;
 809         bus->sprom_size = SSB_SPROMSIZE_WORDS_R123;
 810         sprom_do_read(bus, buf);
 811         err = sprom_check_crc(buf, bus->sprom_size);
 812 @@ -655,7 +700,7 @@ static int ssb_pci_sprom_get(struct ssb_
 813                 buf = kcalloc(SSB_SPROMSIZE_WORDS_R4, sizeof(u16),
 814                               GFP_KERNEL);
 815                 if (!buf)
 816 -                       goto out;
 817 +                       return -ENOMEM;
 818                 bus->sprom_size = SSB_SPROMSIZE_WORDS_R4;
 819                 sprom_do_read(bus, buf);
 820                 err = sprom_check_crc(buf, bus->sprom_size);
 821 @@ -677,7 +722,6 @@ static int ssb_pci_sprom_get(struct ssb_
 822
 823  out_free:
 824         kfree(buf);
 825 -out:
 826         return err;
 827  }
 828
 829 --- a/drivers/ssb/pcihost_wrapper.c
 830 +++ b/drivers/ssb/pcihost_wrapper.c
 831 @@ -59,6 +59,7 @@ static int ssb_pcihost_probe(struct pci_
 832         struct ssb_bus *ssb;
 833         int err = -ENOMEM;
 834         const char *name;
 835 +       u32 val;
 836
 837         ssb = kzalloc(sizeof(*ssb), GFP_KERNEL);
 838         if (!ssb)
 839 @@ -74,6 +75,12 @@ static int ssb_pcihost_probe(struct pci_
 840                 goto err_pci_disable;
 841         pci_set_master(dev);
 842
 843 +       /* Disable the RETRY_TIMEOUT register (0x41) to keep
 844 +        * PCI Tx retries from interfering with C3 CPU state */
 845 +       pci_read_config_dword(dev, 0x40, &val);
 846 +       if ((val & 0x0000ff00) != 0)
 847 +               pci_write_config_dword(dev, 0x40, val & 0xffff00ff);
 848 +
 849         err = ssb_bus_pcibus_register(ssb, dev);
 850         if (err)
 851                 goto err_pci_release_regions;
 852 --- a/drivers/ssb/pcmcia.c
 853 +++ b/drivers/ssb/pcmcia.c
 854 @@ -745,7 +745,7 @@ int ssb_pcmcia_get_invariants(struct ssb
 855
 856         /* Fetch the vendor specific tuples. */
 857         res = pcmcia_loop_tuple(bus->host_pcmcia, SSB_PCMCIA_CIS,
 858 -                               ssb_pcmcia_do_get_invariants, sprom);
 859 +                               ssb_pcmcia_do_get_invariants, iv);
 860         if ((res == 0) || (res == -ENOSPC))
 861                 return 0;
 862
 863 --- a/drivers/ssb/scan.c
 864 +++ b/drivers/ssb/scan.c
 865 @@ -407,10 +407,10 @@ int ssb_bus_scan(struct ssb_bus *bus,
 866                                 /* Ignore PCI cores on PCI-E cards.
 867                                  * Ignore PCI-E cores on PCI cards. */
 868                                 if (dev->id.coreid == SSB_DEV_PCI) {
 869 -                                       if (bus->host_pci->is_pcie)
 870 +                                       if (pci_is_pcie(bus->host_pci))
 871                                                 continue;
 872                                 } else {
 873 -                                       if (!bus->host_pci->is_pcie)
 874 +                                       if (!pci_is_pcie(bus->host_pci))
 875                                                 continue;
 876                                 }
 877                         }
 878 @@ -422,6 +422,16 @@ int ssb_bus_scan(struct ssb_bus *bus,
 879                         bus->pcicore.dev = dev;
 880  #endif /* CONFIG_SSB_DRIVER_PCICORE */
 881                         break;
 882 +               case SSB_DEV_ETHERNET:
 883 +                       if (bus->bustype == SSB_BUSTYPE_PCI) {
 884 +                               if (bus->host_pci->vendor == PCI_VENDOR_ID_BROADCOM &&
 885 +                                   (bus->host_pci->device & 0xFF00) == 0x4300) {
 886 +                                       /* This is a dangling ethernet core on a
 887 +                                        * wireless device. Ignore it. */
 888 +                                       continue;
 889 +                               }
 890 +                       }
 891 +                       break;
 892                 default:
 893                         break;
 894                 }
 895 --- a/include/linux/pci_ids.h
 896 +++ b/include/linux/pci_ids.h
 897 @@ -2038,6 +2038,7 @@
 898  #define PCI_DEVICE_ID_AFAVLAB_P030     0x2182
 899  #define PCI_SUBDEVICE_ID_AFAVLAB_P061          0x2150
 900
 901 +#define PCI_VENDOR_ID_BCM_GVC          0x14a4
 902  #define PCI_VENDOR_ID_BROADCOM         0x14e4
 903  #define PCI_DEVICE_ID_TIGON3_5752      0x1600
 904  #define PCI_DEVICE_ID_TIGON3_5752M     0x1601
 905 --- a/include/linux/ssb/ssb.h
 906 +++ b/include/linux/ssb/ssb.h
 907 @@ -55,6 +55,10 @@ struct ssb_sprom {
 908         u8 tri5gl;              /* 5.2GHz TX isolation */
 909         u8 tri5g;               /* 5.3GHz TX isolation */
 910         u8 tri5gh;              /* 5.8GHz TX isolation */
 911 +       u8 txpid2g[4];          /* 2GHz TX power index */
 912 +       u8 txpid5gl[4];         /* 4.9 - 5.1GHz TX power index */
 913 +       u8 txpid5g[4];          /* 5.1 - 5.5GHz TX power index */
 914 +       u8 txpid5gh[4];         /* 5.5 - ...GHz TX power index */
 915         u8 rxpo2g;              /* 2GHz RX power offset */
 916         u8 rxpo5g;              /* 5GHz RX power offset */
 917         u8 rssisav2g;           /* 2GHz RSSI params */
 918 @@ -167,7 +171,7 @@ struct ssb_device {
 919          * is an optimization. */
 920         const struct ssb_bus_ops *ops;
 921
 922 -       struct device *dev;
 923 +       struct device *dev, *dma_dev;
 924
 925         struct ssb_bus *bus;
 926         struct ssb_device_id id;
 927 @@ -470,14 +474,6 @@ extern u32 ssb_dma_translation(struct ss
 928  #define SSB_DMA_TRANSLATION_MASK       0xC0000000
 929  #define SSB_DMA_TRANSLATION_SHIFT      30
 930
 931 -extern int ssb_dma_set_mask(struct ssb_device *dev, u64 mask);
 932 -
 933 -extern void * ssb_dma_alloc_consistent(struct ssb_device *dev, size_t size,
 934 -                                      dma_addr_t *dma_handle, gfp_t gfp_flags);
 935 -extern void ssb_dma_free_consistent(struct ssb_device *dev, size_t size,
 936 -                                   void *vaddr, dma_addr_t dma_handle,
 937 -                                   gfp_t gfp_flags);
 938 -
 939  static inline void __cold __ssb_dma_not_implemented(struct ssb_device *dev)
 940  {
 941  #ifdef CONFIG_SSB_DEBUG
 942 @@ -486,155 +482,6 @@ static inline void __cold __ssb_dma_not_
 943  #endif /* DEBUG */
 944  }
 945
 946 -static inline int ssb_dma_mapping_error(struct ssb_device *dev, dma_addr_t addr)
 947 -{
 948 -       switch (dev->bus->bustype) {
 949 -       case SSB_BUSTYPE_PCI:
 950 -#ifdef CONFIG_SSB_PCIHOST
 951 -               return pci_dma_mapping_error(dev->bus->host_pci, addr);
 952 -#endif
 953 -               break;
 954 -       case SSB_BUSTYPE_SSB:
 955 -               return dma_mapping_error(dev->dev, addr);
 956 -       default:
 957 -               break;
 958 -       }
 959 -       __ssb_dma_not_implemented(dev);
 960 -       return -ENOSYS;
 961 -}
 962 -
 963 -static inline dma_addr_t ssb_dma_map_single(struct ssb_device *dev, void *p,
 964 -                                           size_t size, enum dma_data_direction dir)
 965 -{
 966 -       switch (dev->bus->bustype) {
 967 -       case SSB_BUSTYPE_PCI:
 968 -#ifdef CONFIG_SSB_PCIHOST
 969 -               return pci_map_single(dev->bus->host_pci, p, size, dir);
 970 -#endif
 971 -               break;
 972 -       case SSB_BUSTYPE_SSB:
 973 -               return dma_map_single(dev->dev, p, size, dir);
 974 -       default:
 975 -               break;
 976 -       }
 977 -       __ssb_dma_not_implemented(dev);
 978 -       return 0;
 979 -}
 980 -
 981 -static inline void ssb_dma_unmap_single(struct ssb_device *dev, dma_addr_t dma_addr,
 982 -                                       size_t size, enum dma_data_direction dir)
 983 -{
 984 -       switch (dev->bus->bustype) {
 985 -       case SSB_BUSTYPE_PCI:
 986 -#ifdef CONFIG_SSB_PCIHOST
 987 -               pci_unmap_single(dev->bus->host_pci, dma_addr, size, dir);
 988 -               return;
 989 -#endif
 990 -               break;
 991 -       case SSB_BUSTYPE_SSB:
 992 -               dma_unmap_single(dev->dev, dma_addr, size, dir);
 993 -               return;
 994 -       default:
 995 -               break;
 996 -       }
 997 -       __ssb_dma_not_implemented(dev);
 998 -}
 999 -
1000 -static inline void ssb_dma_sync_single_for_cpu(struct ssb_device *dev,
1001 -                                              dma_addr_t dma_addr,
1002 -                                              size_t size,
1003 -                                              enum dma_data_direction dir)
1004 -{
1005 -       switch (dev->bus->bustype) {
1006 -       case SSB_BUSTYPE_PCI:
1007 -#ifdef CONFIG_SSB_PCIHOST
1008 -               pci_dma_sync_single_for_cpu(dev->bus->host_pci, dma_addr,
1009 -                                           size, dir);
1010 -               return;
1011 -#endif
1012 -               break;
1013 -       case SSB_BUSTYPE_SSB:
1014 -               dma_sync_single_for_cpu(dev->dev, dma_addr, size, dir);
1015 -               return;
1016 -       default:
1017 -               break;
1018 -       }
1019 -       __ssb_dma_not_implemented(dev);
1020 -}
1021 -
1022 -static inline void ssb_dma_sync_single_for_device(struct ssb_device *dev,
1023 -                                                 dma_addr_t dma_addr,
1024 -                                                 size_t size,
1025 -                                                 enum dma_data_direction dir)
1026 -{
1027 -       switch (dev->bus->bustype) {
1028 -       case SSB_BUSTYPE_PCI:
1029 -#ifdef CONFIG_SSB_PCIHOST
1030 -               pci_dma_sync_single_for_device(dev->bus->host_pci, dma_addr,
1031 -                                              size, dir);
1032 -               return;
1033 -#endif
1034 -               break;
1035 -       case SSB_BUSTYPE_SSB:
1036 -               dma_sync_single_for_device(dev->dev, dma_addr, size, dir);
1037 -               return;
1038 -       default:
1039 -               break;
1040 -       }
1041 -       __ssb_dma_not_implemented(dev);
1042 -}
1043 -
1044 -static inline void ssb_dma_sync_single_range_for_cpu(struct ssb_device *dev,
1045 -                                                    dma_addr_t dma_addr,
1046 -                                                    unsigned long offset,
1047 -                                                    size_t size,
1048 -                                                    enum dma_data_direction dir)
1049 -{
1050 -       switch (dev->bus->bustype) {
1051 -       case SSB_BUSTYPE_PCI:
1052 -#ifdef CONFIG_SSB_PCIHOST
1053 -               /* Just sync everything. That's all the PCI API can do. */
1054 -               pci_dma_sync_single_for_cpu(dev->bus->host_pci, dma_addr,
1055 -                                           offset + size, dir);
1056 -               return;
1057 -#endif
1058 -               break;
1059 -       case SSB_BUSTYPE_SSB:
1060 -               dma_sync_single_range_for_cpu(dev->dev, dma_addr, offset,
1061 -                                             size, dir);
1062 -               return;
1063 -       default:
1064 -               break;
1065 -       }
1066 -       __ssb_dma_not_implemented(dev);
1067 -}
1068 -
1069 -static inline void ssb_dma_sync_single_range_for_device(struct ssb_device *dev,
1070 -                                                       dma_addr_t dma_addr,
1071 -                                                       unsigned long offset,
1072 -                                                       size_t size,
1073 -                                                       enum dma_data_direction dir)
1074 -{
1075 -       switch (dev->bus->bustype) {
1076 -       case SSB_BUSTYPE_PCI:
1077 -#ifdef CONFIG_SSB_PCIHOST
1078 -               /* Just sync everything. That's all the PCI API can do. */
1079 -               pci_dma_sync_single_for_device(dev->bus->host_pci, dma_addr,
1080 -                                              offset + size, dir);
1081 -               return;
1082 -#endif
1083 -               break;
1084 -       case SSB_BUSTYPE_SSB:
1085 -               dma_sync_single_range_for_device(dev->dev, dma_addr, offset,
1086 -                                                size, dir);
1087 -               return;
1088 -       default:
1089 -               break;
1090 -       }
1091 -       __ssb_dma_not_implemented(dev);
1092 -}
1093 -
1094 -
1095  #ifdef CONFIG_SSB_PCIHOST
1096  /* PCI-host wrapper driver */
1097  extern int ssb_pcihost_register(struct pci_driver *driver);
1098 --- a/include/linux/ssb/ssb_regs.h
1099 +++ b/include/linux/ssb/ssb_regs.h
1100 @@ -85,6 +85,8 @@
1101  #define  SSB_IMSTATE_AP_RSV    0x00000030 /* Reserved */
1102  #define  SSB_IMSTATE_IBE       0x00020000 /* In Band Error */
1103  #define  SSB_IMSTATE_TO                0x00040000 /* Timeout */
1104 +#define  SSB_IMSTATE_BUSY      0x01800000 /* Busy (Backplane rev >= 2.3 only) */
1105 +#define  SSB_IMSTATE_REJECT    0x02000000 /* Reject (Backplane rev >= 2.3 only) */
1106  #define SSB_INTVEC             0x0F94     /* SB Interrupt Mask */
1107  #define  SSB_INTVEC_PCI                0x00000001 /* Enable interrupts for PCI */
1108  #define  SSB_INTVEC_ENET0      0x00000002 /* Enable interrupts for enet 0 */
1109 @@ -172,25 +174,25 @@
1110  #define SSB_SPROMSIZE_BYTES_R4         (SSB_SPROMSIZE_WORDS_R4 * sizeof(u16))
1111  #define SSB_SPROM_BASE1                        0x1000
1112  #define SSB_SPROM_BASE31               0x0800
1113 -#define SSB_SPROM_REVISION             0x107E
1114 +#define SSB_SPROM_REVISION             0x007E
1115  #define  SSB_SPROM_REVISION_REV                0x00FF  /* SPROM Revision number */
1116  #define  SSB_SPROM_REVISION_CRC                0xFF00  /* SPROM CRC8 value */
1117  #define  SSB_SPROM_REVISION_CRC_SHIFT  8
1118
1119  /* SPROM Revision 1 */
1120 -#define SSB_SPROM1_SPID                        0x1004  /* Subsystem Product ID for PCI */
1121 -#define SSB_SPROM1_SVID                        0x1006  /* Subsystem Vendor ID for PCI */
1122 -#define SSB_SPROM1_PID                 0x1008  /* Product ID for PCI */
1123 -#define SSB_SPROM1_IL0MAC              0x1048  /* 6 bytes MAC address for 802.11b/g */
1124 -#define SSB_SPROM1_ET0MAC              0x104E  /* 6 bytes MAC address for Ethernet */
1125 -#define SSB_SPROM1_ET1MAC              0x1054  /* 6 bytes MAC address for 802.11a */
1126 -#define SSB_SPROM1_ETHPHY              0x105A  /* Ethernet PHY settings */
1127 +#define SSB_SPROM1_SPID                        0x0004  /* Subsystem Product ID for PCI */
1128 +#define SSB_SPROM1_SVID                        0x0006  /* Subsystem Vendor ID for PCI */
1129 +#define SSB_SPROM1_PID                 0x0008  /* Product ID for PCI */
1130 +#define SSB_SPROM1_IL0MAC              0x0048  /* 6 bytes MAC address for 802.11b/g */
1131 +#define SSB_SPROM1_ET0MAC              0x004E  /* 6 bytes MAC address for Ethernet */
1132 +#define SSB_SPROM1_ET1MAC              0x0054  /* 6 bytes MAC address for 802.11a */
1133 +#define SSB_SPROM1_ETHPHY              0x005A  /* Ethernet PHY settings */
1134  #define  SSB_SPROM1_ETHPHY_ET0A                0x001F  /* MII Address for enet0 */
1135  #define  SSB_SPROM1_ETHPHY_ET1A                0x03E0  /* MII Address for enet1 */
1136  #define  SSB_SPROM1_ETHPHY_ET1A_SHIFT  5
1137  #define  SSB_SPROM1_ETHPHY_ET0M                (1<<14) /* MDIO for enet0 */
1138  #define  SSB_SPROM1_ETHPHY_ET1M                (1<<15) /* MDIO for enet1 */
1139 -#define SSB_SPROM1_BINF                        0x105C  /* Board info */
1140 +#define SSB_SPROM1_BINF                        0x005C  /* Board info */
1141  #define  SSB_SPROM1_BINF_BREV          0x00FF  /* Board Revision */
1142  #define  SSB_SPROM1_BINF_CCODE         0x0F00  /* Country Code */
1143  #define  SSB_SPROM1_BINF_CCODE_SHIFT   8
1144 @@ -198,63 +200,63 @@
1145  #define  SSB_SPROM1_BINF_ANTBG_SHIFT   12
1146  #define  SSB_SPROM1_BINF_ANTA          0xC000  /* Available A-PHY antennas */
1147  #define  SSB_SPROM1_BINF_ANTA_SHIFT    14
1148 -#define SSB_SPROM1_PA0B0               0x105E
1149 -#define SSB_SPROM1_PA0B1               0x1060
1150 -#define SSB_SPROM1_PA0B2               0x1062
1151 -#define SSB_SPROM1_GPIOA               0x1064  /* General Purpose IO pins 0 and 1 */
1152 +#define SSB_SPROM1_PA0B0               0x005E
1153 +#define SSB_SPROM1_PA0B1               0x0060
1154 +#define SSB_SPROM1_PA0B2               0x0062
1155 +#define SSB_SPROM1_GPIOA               0x0064  /* General Purpose IO pins 0 and 1 */
1156  #define  SSB_SPROM1_GPIOA_P0           0x00FF  /* Pin 0 */
1157  #define  SSB_SPROM1_GPIOA_P1           0xFF00  /* Pin 1 */
1158  #define  SSB_SPROM1_GPIOA_P1_SHIFT     8
1159 -#define SSB_SPROM1_GPIOB               0x1066  /* General Purpuse IO pins 2 and 3 */
1160 +#define SSB_SPROM1_GPIOB               0x0066  /* General Purpuse IO pins 2 and 3 */
1161  #define  SSB_SPROM1_GPIOB_P2           0x00FF  /* Pin 2 */
1162  #define  SSB_SPROM1_GPIOB_P3           0xFF00  /* Pin 3 */
1163  #define  SSB_SPROM1_GPIOB_P3_SHIFT     8
1164 -#define SSB_SPROM1_MAXPWR              0x1068  /* Power Amplifier Max Power */
1165 +#define SSB_SPROM1_MAXPWR              0x0068  /* Power Amplifier Max Power */
1166  #define  SSB_SPROM1_MAXPWR_BG          0x00FF  /* B-PHY and G-PHY (in dBm Q5.2) */
1167  #define  SSB_SPROM1_MAXPWR_A           0xFF00  /* A-PHY (in dBm Q5.2) */
1168  #define  SSB_SPROM1_MAXPWR_A_SHIFT     8
1169 -#define SSB_SPROM1_PA1B0               0x106A
1170 -#define SSB_SPROM1_PA1B1               0x106C
1171 -#define SSB_SPROM1_PA1B2               0x106E
1172 -#define SSB_SPROM1_ITSSI               0x1070  /* Idle TSSI Target */
1173 +#define SSB_SPROM1_PA1B0               0x006A
1174 +#define SSB_SPROM1_PA1B1               0x006C
1175 +#define SSB_SPROM1_PA1B2               0x006E
1176 +#define SSB_SPROM1_ITSSI               0x0070  /* Idle TSSI Target */
1177  #define  SSB_SPROM1_ITSSI_BG           0x00FF  /* B-PHY and G-PHY*/
1178  #define  SSB_SPROM1_ITSSI_A            0xFF00  /* A-PHY */
1179  #define  SSB_SPROM1_ITSSI_A_SHIFT      8
1180 -#define SSB_SPROM1_BFLLO               0x1072  /* Boardflags (low 16 bits) */
1181 -#define SSB_SPROM1_AGAIN               0x1074  /* Antenna Gain (in dBm Q5.2) */
1182 +#define SSB_SPROM1_BFLLO               0x0072  /* Boardflags (low 16 bits) */
1183 +#define SSB_SPROM1_AGAIN               0x0074  /* Antenna Gain (in dBm Q5.2) */
1184  #define  SSB_SPROM1_AGAIN_BG           0x00FF  /* B-PHY and G-PHY */
1185  #define  SSB_SPROM1_AGAIN_BG_SHIFT     0
1186  #define  SSB_SPROM1_AGAIN_A            0xFF00  /* A-PHY */
1187  #define  SSB_SPROM1_AGAIN_A_SHIFT      8
1188
1189  /* SPROM Revision 2 (inherits from rev 1) */
1190 -#define SSB_SPROM2_BFLHI               0x1038  /* Boardflags (high 16 bits) */
1191 -#define SSB_SPROM2_MAXP_A              0x103A  /* A-PHY Max Power */
1192 +#define SSB_SPROM2_BFLHI               0x0038  /* Boardflags (high 16 bits) */
1193 +#define SSB_SPROM2_MAXP_A              0x003A  /* A-PHY Max Power */
1194  #define  SSB_SPROM2_MAXP_A_HI          0x00FF  /* Max Power High */
1195  #define  SSB_SPROM2_MAXP_A_LO          0xFF00  /* Max Power Low */
1196  #define  SSB_SPROM2_MAXP_A_LO_SHIFT    8
1197 -#define SSB_SPROM2_PA1LOB0             0x103C  /* A-PHY PowerAmplifier Low Settings */
1198 -#define SSB_SPROM2_PA1LOB1             0x103E  /* A-PHY PowerAmplifier Low Settings */
1199 -#define SSB_SPROM2_PA1LOB2             0x1040  /* A-PHY PowerAmplifier Low Settings */
1200 -#define SSB_SPROM2_PA1HIB0             0x1042  /* A-PHY PowerAmplifier High Settings */
1201 -#define SSB_SPROM2_PA1HIB1             0x1044  /* A-PHY PowerAmplifier High Settings */
1202 -#define SSB_SPROM2_PA1HIB2             0x1046  /* A-PHY PowerAmplifier High Settings */
1203 -#define SSB_SPROM2_OPO                 0x1078  /* OFDM Power Offset from CCK Level */
1204 +#define SSB_SPROM2_PA1LOB0             0x003C  /* A-PHY PowerAmplifier Low Settings */
1205 +#define SSB_SPROM2_PA1LOB1             0x003E  /* A-PHY PowerAmplifier Low Settings */
1206 +#define SSB_SPROM2_PA1LOB2             0x0040  /* A-PHY PowerAmplifier Low Settings */
1207 +#define SSB_SPROM2_PA1HIB0             0x0042  /* A-PHY PowerAmplifier High Settings */
1208 +#define SSB_SPROM2_PA1HIB1             0x0044  /* A-PHY PowerAmplifier High Settings */
1209 +#define SSB_SPROM2_PA1HIB2             0x0046  /* A-PHY PowerAmplifier High Settings */
1210 +#define SSB_SPROM2_OPO                 0x0078  /* OFDM Power Offset from CCK Level */
1211  #define  SSB_SPROM2_OPO_VALUE          0x00FF
1212  #define  SSB_SPROM2_OPO_UNUSED         0xFF00
1213 -#define SSB_SPROM2_CCODE               0x107C  /* Two char Country Code */
1214 +#define SSB_SPROM2_CCODE               0x007C  /* Two char Country Code */
1215
1216  /* SPROM Revision 3 (inherits most data from rev 2) */
1217 -#define SSB_SPROM3_IL0MAC              0x104A  /* 6 bytes MAC address for 802.11b/g */
1218 -#define SSB_SPROM3_OFDMAPO             0x102C  /* A-PHY OFDM Mid Power Offset (4 bytes, BigEndian) */
1219 -#define SSB_SPROM3_OFDMALPO            0x1030  /* A-PHY OFDM Low Power Offset (4 bytes, BigEndian) */
1220 -#define SSB_SPROM3_OFDMAHPO            0x1034  /* A-PHY OFDM High Power Offset (4 bytes, BigEndian) */
1221 -#define SSB_SPROM3_GPIOLDC             0x1042  /* GPIO LED Powersave Duty Cycle (4 bytes, BigEndian) */
1222 +#define SSB_SPROM3_OFDMAPO             0x002C  /* A-PHY OFDM Mid Power Offset (4 bytes, BigEndian) */
1223 +#define SSB_SPROM3_OFDMALPO            0x0030  /* A-PHY OFDM Low Power Offset (4 bytes, BigEndian) */
1224 +#define SSB_SPROM3_OFDMAHPO            0x0034  /* A-PHY OFDM High Power Offset (4 bytes, BigEndian) */
1225 +#define SSB_SPROM3_GPIOLDC             0x0042  /* GPIO LED Powersave Duty Cycle (4 bytes, BigEndian) */
1226  #define  SSB_SPROM3_GPIOLDC_OFF                0x0000FF00      /* Off Count */
1227  #define  SSB_SPROM3_GPIOLDC_OFF_SHIFT  8
1228  #define  SSB_SPROM3_GPIOLDC_ON         0x00FF0000      /* On Count */
1229  #define  SSB_SPROM3_GPIOLDC_ON_SHIFT   16
1230 -#define SSB_SPROM3_CCKPO               0x1078  /* CCK Power Offset */
1231 +#define SSB_SPROM3_IL0MAC              0x004A  /* 6 bytes MAC address for 802.11b/g */
1232 +#define SSB_SPROM3_CCKPO               0x0078  /* CCK Power Offset */
1233  #define  SSB_SPROM3_CCKPO_1M           0x000F  /* 1M Rate PO */
1234  #define  SSB_SPROM3_CCKPO_2M           0x00F0  /* 2M Rate PO */
1235  #define  SSB_SPROM3_CCKPO_2M_SHIFT     4
1236 @@ -265,100 +267,144 @@
1237  #define  SSB_SPROM3_OFDMGPO            0x107A  /* G-PHY OFDM Power Offset (4 bytes, BigEndian) */
1238
1239  /* SPROM Revision 4 */
1240 -#define SSB_SPROM4_IL0MAC              0x104C  /* 6 byte MAC address for a/b/g/n */
1241 -#define SSB_SPROM4_ETHPHY              0x105A  /* Ethernet PHY settings ?? */
1242 +#define SSB_SPROM4_BFLLO               0x0044  /* Boardflags (low 16 bits) */
1243 +#define SSB_SPROM4_BFLHI               0x0046  /* Board Flags Hi */
1244 +#define SSB_SPROM4_BFL2LO              0x0048  /* Board flags 2 (low 16 bits) */
1245 +#define SSB_SPROM4_BFL2HI              0x004A  /* Board flags 2 Hi */
1246 +#define SSB_SPROM4_IL0MAC              0x004C  /* 6 byte MAC address for a/b/g/n */
1247 +#define SSB_SPROM4_CCODE               0x0052  /* Country Code (2 bytes) */
1248 +#define SSB_SPROM4_GPIOA               0x0056  /* Gen. Purpose IO # 0 and 1 */
1249 +#define  SSB_SPROM4_GPIOA_P0           0x00FF  /* Pin 0 */
1250 +#define  SSB_SPROM4_GPIOA_P1           0xFF00  /* Pin 1 */
1251 +#define  SSB_SPROM4_GPIOA_P1_SHIFT     8
1252 +#define SSB_SPROM4_GPIOB               0x0058  /* Gen. Purpose IO # 2 and 3 */
1253 +#define  SSB_SPROM4_GPIOB_P2           0x00FF  /* Pin 2 */
1254 +#define  SSB_SPROM4_GPIOB_P3           0xFF00  /* Pin 3 */
1255 +#define  SSB_SPROM4_GPIOB_P3_SHIFT     8
1256 +#define SSB_SPROM4_ETHPHY              0x005A  /* Ethernet PHY settings ?? */
1257  #define  SSB_SPROM4_ETHPHY_ET0A                0x001F  /* MII Address for enet0 */
1258  #define  SSB_SPROM4_ETHPHY_ET1A                0x03E0  /* MII Address for enet1 */
1259  #define  SSB_SPROM4_ETHPHY_ET1A_SHIFT  5
1260  #define  SSB_SPROM4_ETHPHY_ET0M                (1<<14) /* MDIO for enet0 */
1261  #define  SSB_SPROM4_ETHPHY_ET1M                (1<<15) /* MDIO for enet1 */
1262 -#define SSB_SPROM4_CCODE               0x1052  /* Country Code (2 bytes) */
1263 -#define SSB_SPROM4_ANTAVAIL            0x105D  /* Antenna available bitfields */
1264 -#define SSB_SPROM4_ANTAVAIL_A          0x00FF  /* A-PHY bitfield */
1265 -#define SSB_SPROM4_ANTAVAIL_A_SHIFT    0
1266 -#define SSB_SPROM4_ANTAVAIL_BG         0xFF00  /* B-PHY and G-PHY bitfield */
1267 -#define SSB_SPROM4_ANTAVAIL_BG_SHIFT   8
1268 -#define SSB_SPROM4_BFLLO               0x1044  /* Boardflags (low 16 bits) */
1269 -#define SSB_SPROM4_AGAIN01             0x105E  /* Antenna Gain (in dBm Q5.2) */
1270 +#define SSB_SPROM4_ANTAVAIL            0x005D  /* Antenna available bitfields */
1271 +#define  SSB_SPROM4_ANTAVAIL_A         0x00FF  /* A-PHY bitfield */
1272 +#define  SSB_SPROM4_ANTAVAIL_A_SHIFT   0
1273 +#define  SSB_SPROM4_ANTAVAIL_BG                0xFF00  /* B-PHY and G-PHY bitfield */
1274 +#define  SSB_SPROM4_ANTAVAIL_BG_SHIFT  8
1275 +#define SSB_SPROM4_AGAIN01             0x005E  /* Antenna Gain (in dBm Q5.2) */
1276  #define  SSB_SPROM4_AGAIN0             0x00FF  /* Antenna 0 */
1277  #define  SSB_SPROM4_AGAIN0_SHIFT       0
1278  #define  SSB_SPROM4_AGAIN1             0xFF00  /* Antenna 1 */
1279  #define  SSB_SPROM4_AGAIN1_SHIFT       8
1280 -#define SSB_SPROM4_AGAIN23             0x1060
1281 +#define SSB_SPROM4_AGAIN23             0x0060
1282  #define  SSB_SPROM4_AGAIN2             0x00FF  /* Antenna 2 */
1283  #define  SSB_SPROM4_AGAIN2_SHIFT       0
1284  #define  SSB_SPROM4_AGAIN3             0xFF00  /* Antenna 3 */
1285  #define  SSB_SPROM4_AGAIN3_SHIFT       8
1286 -#define SSB_SPROM4_BFLHI               0x1046  /* Board Flags Hi */
1287 -#define SSB_SPROM4_MAXP_BG             0x1080  /* Max Power BG in path 1 */
1288 +#define SSB_SPROM4_TXPID2G01           0x0062  /* TX Power Index 2GHz */
1289 +#define  SSB_SPROM4_TXPID2G0           0x00FF
1290 +#define  SSB_SPROM4_TXPID2G0_SHIFT     0
1291 +#define  SSB_SPROM4_TXPID2G1           0xFF00
1292 +#define  SSB_SPROM4_TXPID2G1_SHIFT     8
1293 +#define SSB_SPROM4_TXPID2G23           0x0064  /* TX Power Index 2GHz */
1294 +#define  SSB_SPROM4_TXPID2G2           0x00FF
1295 +#define  SSB_SPROM4_TXPID2G2_SHIFT     0
1296 +#define  SSB_SPROM4_TXPID2G3           0xFF00
1297 +#define  SSB_SPROM4_TXPID2G3_SHIFT     8
1298 +#define SSB_SPROM4_TXPID5G01           0x0066  /* TX Power Index 5GHz middle subband */
1299 +#define  SSB_SPROM4_TXPID5G0           0x00FF
1300 +#define  SSB_SPROM4_TXPID5G0_SHIFT     0
1301 +#define  SSB_SPROM4_TXPID5G1           0xFF00
1302 +#define  SSB_SPROM4_TXPID5G1_SHIFT     8
1303 +#define SSB_SPROM4_TXPID5G23           0x0068  /* TX Power Index 5GHz middle subband */
1304 +#define  SSB_SPROM4_TXPID5G2           0x00FF
1305 +#define  SSB_SPROM4_TXPID5G2_SHIFT     0
1306 +#define  SSB_SPROM4_TXPID5G3           0xFF00
1307 +#define  SSB_SPROM4_TXPID5G3_SHIFT     8
1308 +#define SSB_SPROM4_TXPID5GL01          0x006A  /* TX Power Index 5GHz low subband */
1309 +#define  SSB_SPROM4_TXPID5GL0          0x00FF
1310 +#define  SSB_SPROM4_TXPID5GL0_SHIFT    0
1311 +#define  SSB_SPROM4_TXPID5GL1          0xFF00
1312 +#define  SSB_SPROM4_TXPID5GL1_SHIFT    8
1313 +#define SSB_SPROM4_TXPID5GL23          0x006C  /* TX Power Index 5GHz low subband */
1314 +#define  SSB_SPROM4_TXPID5GL2          0x00FF
1315 +#define  SSB_SPROM4_TXPID5GL2_SHIFT    0
1316 +#define  SSB_SPROM4_TXPID5GL3          0xFF00
1317 +#define  SSB_SPROM4_TXPID5GL3_SHIFT    8
1318 +#define SSB_SPROM4_TXPID5GH01          0x006E  /* TX Power Index 5GHz high subband */
1319 +#define  SSB_SPROM4_TXPID5GH0          0x00FF
1320 +#define  SSB_SPROM4_TXPID5GH0_SHIFT    0
1321 +#define  SSB_SPROM4_TXPID5GH1          0xFF00
1322 +#define  SSB_SPROM4_TXPID5GH1_SHIFT    8
1323 +#define SSB_SPROM4_TXPID5GH23          0x0070  /* TX Power Index 5GHz high subband */
1324 +#define  SSB_SPROM4_TXPID5GH2          0x00FF
1325 +#define  SSB_SPROM4_TXPID5GH2_SHIFT    0
1326 +#define  SSB_SPROM4_TXPID5GH3          0xFF00
1327 +#define  SSB_SPROM4_TXPID5GH3_SHIFT    8
1328 +#define SSB_SPROM4_MAXP_BG             0x0080  /* Max Power BG in path 1 */
1329  #define  SSB_SPROM4_MAXP_BG_MASK       0x00FF  /* Mask for Max Power BG */
1330  #define  SSB_SPROM4_ITSSI_BG           0xFF00  /* Mask for path 1 itssi_bg */
1331  #define  SSB_SPROM4_ITSSI_BG_SHIFT     8
1332 -#define SSB_SPROM4_MAXP_A              0x108A  /* Max Power A in path 1 */
1333 +#define SSB_SPROM4_MAXP_A              0x008A  /* Max Power A in path 1 */
1334  #define  SSB_SPROM4_MAXP_A_MASK                0x00FF  /* Mask for Max Power A */
1335  #define  SSB_SPROM4_ITSSI_A            0xFF00  /* Mask for path 1 itssi_a */
1336  #define  SSB_SPROM4_ITSSI_A_SHIFT      8
1337 -#define SSB_SPROM4_GPIOA               0x1056  /* Gen. Purpose IO # 0 and 1 */
1338 -#define  SSB_SPROM4_GPIOA_P0           0x00FF  /* Pin 0 */
1339 -#define  SSB_SPROM4_GPIOA_P1           0xFF00  /* Pin 1 */
1340 -#define  SSB_SPROM4_GPIOA_P1_SHIFT     8
1341 -#define SSB_SPROM4_GPIOB               0x1058  /* Gen. Purpose IO # 2 and 3 */
1342 -#define  SSB_SPROM4_GPIOB_P2           0x00FF  /* Pin 2 */
1343 -#define  SSB_SPROM4_GPIOB_P3           0xFF00  /* Pin 3 */
1344 -#define  SSB_SPROM4_GPIOB_P3_SHIFT     8
1345 -#define SSB_SPROM4_PA0B0               0x1082  /* The paXbY locations are */
1346 -#define SSB_SPROM4_PA0B1               0x1084  /*   only guesses */
1347 -#define SSB_SPROM4_PA0B2               0x1086
1348 -#define SSB_SPROM4_PA1B0               0x108E
1349 -#define SSB_SPROM4_PA1B1               0x1090
1350 -#define SSB_SPROM4_PA1B2               0x1092
1351 +#define SSB_SPROM4_PA0B0               0x0082  /* The paXbY locations are */
1352 +#define SSB_SPROM4_PA0B1               0x0084  /*   only guesses */
1353 +#define SSB_SPROM4_PA0B2               0x0086
1354 +#define SSB_SPROM4_PA1B0               0x008E
1355 +#define SSB_SPROM4_PA1B1               0x0090
1356 +#define SSB_SPROM4_PA1B2               0x0092
1357
1358  /* SPROM Revision 5 (inherits most data from rev 4) */
1359 -#define SSB_SPROM5_BFLLO               0x104A  /* Boardflags (low 16 bits) */
1360 -#define SSB_SPROM5_BFLHI               0x104C  /* Board Flags Hi */
1361 -#define SSB_SPROM5_IL0MAC              0x1052  /* 6 byte MAC address for a/b/g/n */
1362 -#define SSB_SPROM5_CCODE               0x1044  /* Country Code (2 bytes) */
1363 -#define SSB_SPROM5_GPIOA               0x1076  /* Gen. Purpose IO # 0 and 1 */
1364 +#define SSB_SPROM5_CCODE               0x0044  /* Country Code (2 bytes) */
1365 +#define SSB_SPROM5_BFLLO               0x004A  /* Boardflags (low 16 bits) */
1366 +#define SSB_SPROM5_BFLHI               0x004C  /* Board Flags Hi */
1367 +#define SSB_SPROM5_BFL2LO              0x004E  /* Board flags 2 (low 16 bits) */
1368 +#define SSB_SPROM5_BFL2HI              0x0050  /* Board flags 2 Hi */
1369 +#define SSB_SPROM5_IL0MAC              0x0052  /* 6 byte MAC address for a/b/g/n */
1370 +#define SSB_SPROM5_GPIOA               0x0076  /* Gen. Purpose IO # 0 and 1 */
1371  #define  SSB_SPROM5_GPIOA_P0           0x00FF  /* Pin 0 */
1372  #define  SSB_SPROM5_GPIOA_P1           0xFF00  /* Pin 1 */
1373  #define  SSB_SPROM5_GPIOA_P1_SHIFT     8
1374 -#define SSB_SPROM5_GPIOB               0x1078  /* Gen. Purpose IO # 2 and 3 */
1375 +#define SSB_SPROM5_GPIOB               0x0078  /* Gen. Purpose IO # 2 and 3 */
1376  #define  SSB_SPROM5_GPIOB_P2           0x00FF  /* Pin 2 */
1377  #define  SSB_SPROM5_GPIOB_P3           0xFF00  /* Pin 3 */
1378  #define  SSB_SPROM5_GPIOB_P3_SHIFT     8
1379
1380  /* SPROM Revision 8 */
1381 -#define SSB_SPROM8_BOARDREV            0x1082  /* Board revision */
1382 -#define SSB_SPROM8_BFLLO               0x1084  /* Board flags (bits 0-15) */
1383 -#define SSB_SPROM8_BFLHI               0x1086  /* Board flags (bits 16-31) */
1384 -#define SSB_SPROM8_BFL2LO              0x1088  /* Board flags (bits 32-47) */
1385 -#define SSB_SPROM8_BFL2HI              0x108A  /* Board flags (bits 48-63) */
1386 -#define SSB_SPROM8_IL0MAC              0x108C  /* 6 byte MAC address */
1387 -#define SSB_SPROM8_CCODE               0x1092  /* 2 byte country code */
1388 -#define SSB_SPROM8_ANTAVAIL            0x109C  /* Antenna available bitfields*/
1389 -#define SSB_SPROM8_ANTAVAIL_A          0xFF00  /* A-PHY bitfield */
1390 -#define SSB_SPROM8_ANTAVAIL_A_SHIFT    8
1391 -#define SSB_SPROM8_ANTAVAIL_BG         0x00FF  /* B-PHY and G-PHY bitfield */
1392 -#define SSB_SPROM8_ANTAVAIL_BG_SHIFT   0
1393 -#define SSB_SPROM8_AGAIN01             0x109E  /* Antenna Gain (in dBm Q5.2) */
1394 +#define SSB_SPROM8_BOARDREV            0x0082  /* Board revision */
1395 +#define SSB_SPROM8_BFLLO               0x0084  /* Board flags (bits 0-15) */
1396 +#define SSB_SPROM8_BFLHI               0x0086  /* Board flags (bits 16-31) */
1397 +#define SSB_SPROM8_BFL2LO              0x0088  /* Board flags (bits 32-47) */
1398 +#define SSB_SPROM8_BFL2HI              0x008A  /* Board flags (bits 48-63) */
1399 +#define SSB_SPROM8_IL0MAC              0x008C  /* 6 byte MAC address */
1400 +#define SSB_SPROM8_CCODE               0x0092  /* 2 byte country code */
1401 +#define SSB_SPROM8_GPIOA               0x0096  /*Gen. Purpose IO # 0 and 1 */
1402 +#define  SSB_SPROM8_GPIOA_P0           0x00FF  /* Pin 0 */
1403 +#define  SSB_SPROM8_GPIOA_P1           0xFF00  /* Pin 1 */
1404 +#define  SSB_SPROM8_GPIOA_P1_SHIFT     8
1405 +#define SSB_SPROM8_GPIOB               0x0098  /* Gen. Purpose IO # 2 and 3 */
1406 +#define  SSB_SPROM8_GPIOB_P2           0x00FF  /* Pin 2 */
1407 +#define  SSB_SPROM8_GPIOB_P3           0xFF00  /* Pin 3 */
1408 +#define  SSB_SPROM8_GPIOB_P3_SHIFT     8
1409 +#define SSB_SPROM8_ANTAVAIL            0x009C  /* Antenna available bitfields*/
1410 +#define  SSB_SPROM8_ANTAVAIL_A         0xFF00  /* A-PHY bitfield */
1411 +#define  SSB_SPROM8_ANTAVAIL_A_SHIFT   8
1412 +#define  SSB_SPROM8_ANTAVAIL_BG                0x00FF  /* B-PHY and G-PHY bitfield */
1413 +#define  SSB_SPROM8_ANTAVAIL_BG_SHIFT  0
1414 +#define SSB_SPROM8_AGAIN01             0x009E  /* Antenna Gain (in dBm Q5.2) */
1415  #define  SSB_SPROM8_AGAIN0             0x00FF  /* Antenna 0 */
1416  #define  SSB_SPROM8_AGAIN0_SHIFT       0
1417  #define  SSB_SPROM8_AGAIN1             0xFF00  /* Antenna 1 */
1418  #define  SSB_SPROM8_AGAIN1_SHIFT       8
1419 -#define SSB_SPROM8_AGAIN23             0x10A0
1420 +#define SSB_SPROM8_AGAIN23             0x00A0
1421  #define  SSB_SPROM8_AGAIN2             0x00FF  /* Antenna 2 */
1422  #define  SSB_SPROM8_AGAIN2_SHIFT       0
1423  #define  SSB_SPROM8_AGAIN3             0xFF00  /* Antenna 3 */
1424  #define  SSB_SPROM8_AGAIN3_SHIFT       8
1425 -#define SSB_SPROM8_GPIOA               0x1096  /*Gen. Purpose IO # 0 and 1 */
1426 -#define  SSB_SPROM8_GPIOA_P0           0x00FF  /* Pin 0 */
1427 -#define  SSB_SPROM8_GPIOA_P1           0xFF00  /* Pin 1 */
1428 -#define  SSB_SPROM8_GPIOA_P1_SHIFT     8
1429 -#define SSB_SPROM8_GPIOB               0x1098  /* Gen. Purpose IO # 2 and 3 */
1430 -#define  SSB_SPROM8_GPIOB_P2           0x00FF  /* Pin 2 */
1431 -#define  SSB_SPROM8_GPIOB_P3           0xFF00  /* Pin 3 */
1432 -#define  SSB_SPROM8_GPIOB_P3_SHIFT     8
1433 -#define SSB_SPROM8_RSSIPARM2G          0x10A4  /* RSSI params for 2GHz */
1434 +#define SSB_SPROM8_RSSIPARM2G          0x00A4  /* RSSI params for 2GHz */
1435  #define  SSB_SPROM8_RSSISMF2G          0x000F
1436  #define  SSB_SPROM8_RSSISMC2G          0x00F0
1437  #define  SSB_SPROM8_RSSISMC2G_SHIFT    4
1438 @@ -366,7 +412,7 @@
1439  #define  SSB_SPROM8_RSSISAV2G_SHIFT    8
1440  #define  SSB_SPROM8_BXA2G              0x1800
1441  #define  SSB_SPROM8_BXA2G_SHIFT                11
1442 -#define SSB_SPROM8_RSSIPARM5G          0x10A6  /* RSSI params for 5GHz */
1443 +#define SSB_SPROM8_RSSIPARM5G          0x00A6  /* RSSI params for 5GHz */
1444  #define  SSB_SPROM8_RSSISMF5G          0x000F
1445  #define  SSB_SPROM8_RSSISMC5G          0x00F0
1446  #define  SSB_SPROM8_RSSISMC5G_SHIFT    4
1447 @@ -374,47 +420,47 @@
1448  #define  SSB_SPROM8_RSSISAV5G_SHIFT    8
1449  #define  SSB_SPROM8_BXA5G              0x1800
1450  #define  SSB_SPROM8_BXA5G_SHIFT                11
1451 -#define SSB_SPROM8_TRI25G              0x10A8  /* TX isolation 2.4&5.3GHz */
1452 +#define SSB_SPROM8_TRI25G              0x00A8  /* TX isolation 2.4&5.3GHz */
1453  #define  SSB_SPROM8_TRI2G              0x00FF  /* TX isolation 2.4GHz */
1454  #define  SSB_SPROM8_TRI5G              0xFF00  /* TX isolation 5.3GHz */
1455  #define  SSB_SPROM8_TRI5G_SHIFT                8
1456 -#define SSB_SPROM8_TRI5GHL             0x10AA  /* TX isolation 5.2/5.8GHz */
1457 +#define SSB_SPROM8_TRI5GHL             0x00AA  /* TX isolation 5.2/5.8GHz */
1458  #define  SSB_SPROM8_TRI5GL             0x00FF  /* TX isolation 5.2GHz */
1459  #define  SSB_SPROM8_TRI5GH             0xFF00  /* TX isolation 5.8GHz */
1460  #define  SSB_SPROM8_TRI5GH_SHIFT       8
1461 -#define SSB_SPROM8_RXPO                        0x10AC  /* RX power offsets */
1462 +#define SSB_SPROM8_RXPO                        0x00AC  /* RX power offsets */
1463  #define  SSB_SPROM8_RXPO2G             0x00FF  /* 2GHz RX power offset */
1464  #define  SSB_SPROM8_RXPO5G             0xFF00  /* 5GHz RX power offset */
1465  #define  SSB_SPROM8_RXPO5G_SHIFT       8
1466 -#define SSB_SPROM8_MAXP_BG             0x10C0  /* Max Power 2GHz in path 1 */
1467 +#define SSB_SPROM8_MAXP_BG             0x00C0  /* Max Power 2GHz in path 1 */
1468  #define  SSB_SPROM8_MAXP_BG_MASK       0x00FF  /* Mask for Max Power 2GHz */
1469  #define  SSB_SPROM8_ITSSI_BG           0xFF00  /* Mask for path 1 itssi_bg */
1470  #define  SSB_SPROM8_ITSSI_BG_SHIFT     8
1471 -#define SSB_SPROM8_PA0B0               0x10C2  /* 2GHz power amp settings */
1472 -#define SSB_SPROM8_PA0B1               0x10C4
1473 -#define SSB_SPROM8_PA0B2               0x10C6
1474 -#define SSB_SPROM8_MAXP_A              0x10C8  /* Max Power 5.3GHz */
1475 +#define SSB_SPROM8_PA0B0               0x00C2  /* 2GHz power amp settings */
1476 +#define SSB_SPROM8_PA0B1               0x00C4
1477 +#define SSB_SPROM8_PA0B2               0x00C6
1478 +#define SSB_SPROM8_MAXP_A              0x00C8  /* Max Power 5.3GHz */
1479  #define  SSB_SPROM8_MAXP_A_MASK                0x00FF  /* Mask for Max Power 5.3GHz */
1480  #define  SSB_SPROM8_ITSSI_A            0xFF00  /* Mask for path 1 itssi_a */
1481  #define  SSB_SPROM8_ITSSI_A_SHIFT      8
1482 -#define SSB_SPROM8_MAXP_AHL            0x10CA  /* Max Power 5.2/5.8GHz */
1483 +#define SSB_SPROM8_MAXP_AHL            0x00CA  /* Max Power 5.2/5.8GHz */
1484  #define  SSB_SPROM8_MAXP_AH_MASK       0x00FF  /* Mask for Max Power 5.8GHz */
1485  #define  SSB_SPROM8_MAXP_AL_MASK       0xFF00  /* Mask for Max Power 5.2GHz */
1486  #define  SSB_SPROM8_MAXP_AL_SHIFT      8
1487 -#define SSB_SPROM8_PA1B0               0x10CC  /* 5.3GHz power amp settings */
1488 -#define SSB_SPROM8_PA1B1               0x10CE
1489 -#define SSB_SPROM8_PA1B2               0x10D0
1490 -#define SSB_SPROM8_PA1LOB0             0x10D2  /* 5.2GHz power amp settings */
1491 -#define SSB_SPROM8_PA1LOB1             0x10D4
1492 -#define SSB_SPROM8_PA1LOB2             0x10D6
1493 -#define SSB_SPROM8_PA1HIB0             0x10D8  /* 5.8GHz power amp settings */
1494 -#define SSB_SPROM8_PA1HIB1             0x10DA
1495 -#define SSB_SPROM8_PA1HIB2             0x10DC
1496 -#define SSB_SPROM8_CCK2GPO             0x1140  /* CCK power offset */
1497 -#define SSB_SPROM8_OFDM2GPO            0x1142  /* 2.4GHz OFDM power offset */
1498 -#define SSB_SPROM8_OFDM5GPO            0x1146  /* 5.3GHz OFDM power offset */
1499 -#define SSB_SPROM8_OFDM5GLPO           0x114A  /* 5.2GHz OFDM power offset */
1500 -#define SSB_SPROM8_OFDM5GHPO           0x114E  /* 5.8GHz OFDM power offset */
1501 +#define SSB_SPROM8_PA1B0               0x00CC  /* 5.3GHz power amp settings */
1502 +#define SSB_SPROM8_PA1B1               0x00CE
1503 +#define SSB_SPROM8_PA1B2               0x00D0
1504 +#define SSB_SPROM8_PA1LOB0             0x00D2  /* 5.2GHz power amp settings */
1505 +#define SSB_SPROM8_PA1LOB1             0x00D4
1506 +#define SSB_SPROM8_PA1LOB2             0x00D6
1507 +#define SSB_SPROM8_PA1HIB0             0x00D8  /* 5.8GHz power amp settings */
1508 +#define SSB_SPROM8_PA1HIB1             0x00DA
1509 +#define SSB_SPROM8_PA1HIB2             0x00DC
1510 +#define SSB_SPROM8_CCK2GPO             0x0140  /* CCK power offset */
1511 +#define SSB_SPROM8_OFDM2GPO            0x0142  /* 2.4GHz OFDM power offset */
1512 +#define SSB_SPROM8_OFDM5GPO            0x0146  /* 5.3GHz OFDM power offset */
1513 +#define SSB_SPROM8_OFDM5GLPO           0x014A  /* 5.2GHz OFDM power offset */
1514 +#define SSB_SPROM8_OFDM5GHPO           0x014E  /* 5.8GHz OFDM power offset */
1515
1516  /* Values for SSB_SPROM1_BINF_CCODE */
1517  enum {