1 --- a/drivers/ssb/driver_chipcommon.c
2 +++ b/drivers/ssb/driver_chipcommon.c
4 * Broadcom ChipCommon core driver
6 * Copyright 2005, Broadcom Corporation
7 - * Copyright 2006, 2007, Michael Buesch <mb@bu3sch.de>
8 + * Copyright 2006, 2007, Michael Buesch <m@bues.ch>
10 * Licensed under the GNU/GPL. See COPYING for details.
12 @@ -46,40 +46,66 @@ void ssb_chipco_set_clockmode(struct ssb
17 + /* We support SLOW only on 6..9 */
18 + if (ccdev->id.revision >= 10 && mode == SSB_CLKMODE_SLOW)
19 + mode = SSB_CLKMODE_DYNAMIC;
21 + if (cc->capabilities & SSB_CHIPCO_CAP_PMU)
22 + return; /* PMU controls clockmode, separated function needed */
23 + SSB_WARN_ON(ccdev->id.revision >= 20);
25 /* chipcommon cores prior to rev6 don't support dynamic clock control */
26 if (ccdev->id.revision < 6)
28 - /* chipcommon cores rev10 are a whole new ball game */
30 + /* ChipCommon cores rev10+ need testing */
31 if (ccdev->id.revision >= 10)
34 if (!(cc->capabilities & SSB_CHIPCO_CAP_PCTL))
38 - case SSB_CLKMODE_SLOW:
39 + case SSB_CLKMODE_SLOW: /* For revs 6..9 only */
40 tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL);
41 tmp |= SSB_CHIPCO_SLOWCLKCTL_FSLOW;
42 chipco_write32(cc, SSB_CHIPCO_SLOWCLKCTL, tmp);
44 case SSB_CLKMODE_FAST:
45 - ssb_pci_xtal(bus, SSB_GPIO_XTAL, 1); /* Force crystal on */
46 - tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL);
47 - tmp &= ~SSB_CHIPCO_SLOWCLKCTL_FSLOW;
48 - tmp |= SSB_CHIPCO_SLOWCLKCTL_IPLL;
49 - chipco_write32(cc, SSB_CHIPCO_SLOWCLKCTL, tmp);
50 + if (ccdev->id.revision < 10) {
51 + ssb_pci_xtal(bus, SSB_GPIO_XTAL, 1); /* Force crystal on */
52 + tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL);
53 + tmp &= ~SSB_CHIPCO_SLOWCLKCTL_FSLOW;
54 + tmp |= SSB_CHIPCO_SLOWCLKCTL_IPLL;
55 + chipco_write32(cc, SSB_CHIPCO_SLOWCLKCTL, tmp);
57 + chipco_write32(cc, SSB_CHIPCO_SYSCLKCTL,
58 + (chipco_read32(cc, SSB_CHIPCO_SYSCLKCTL) |
59 + SSB_CHIPCO_SYSCLKCTL_FORCEHT));
60 + /* udelay(150); TODO: not available in early init */
63 case SSB_CLKMODE_DYNAMIC:
64 - tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL);
65 - tmp &= ~SSB_CHIPCO_SLOWCLKCTL_FSLOW;
66 - tmp &= ~SSB_CHIPCO_SLOWCLKCTL_IPLL;
67 - tmp &= ~SSB_CHIPCO_SLOWCLKCTL_ENXTAL;
68 - if ((tmp & SSB_CHIPCO_SLOWCLKCTL_SRC) != SSB_CHIPCO_SLOWCLKCTL_SRC_XTAL)
69 - tmp |= SSB_CHIPCO_SLOWCLKCTL_ENXTAL;
70 - chipco_write32(cc, SSB_CHIPCO_SLOWCLKCTL, tmp);
72 - /* for dynamic control, we have to release our xtal_pu "force on" */
73 - if (tmp & SSB_CHIPCO_SLOWCLKCTL_ENXTAL)
74 - ssb_pci_xtal(bus, SSB_GPIO_XTAL, 0);
75 + if (ccdev->id.revision < 10) {
76 + tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL);
77 + tmp &= ~SSB_CHIPCO_SLOWCLKCTL_FSLOW;
78 + tmp &= ~SSB_CHIPCO_SLOWCLKCTL_IPLL;
79 + tmp &= ~SSB_CHIPCO_SLOWCLKCTL_ENXTAL;
80 + if ((tmp & SSB_CHIPCO_SLOWCLKCTL_SRC) !=
81 + SSB_CHIPCO_SLOWCLKCTL_SRC_XTAL)
82 + tmp |= SSB_CHIPCO_SLOWCLKCTL_ENXTAL;
83 + chipco_write32(cc, SSB_CHIPCO_SLOWCLKCTL, tmp);
85 + /* For dynamic control, we have to release our xtal_pu
87 + if (tmp & SSB_CHIPCO_SLOWCLKCTL_ENXTAL)
88 + ssb_pci_xtal(bus, SSB_GPIO_XTAL, 0);
90 + chipco_write32(cc, SSB_CHIPCO_SYSCLKCTL,
91 + (chipco_read32(cc, SSB_CHIPCO_SYSCLKCTL) &
92 + ~SSB_CHIPCO_SYSCLKCTL_FORCEHT));
97 @@ -209,6 +235,24 @@ static void chipco_powercontrol_init(str
101 +/* http://bcm-v4.sipsolutions.net/802.11/PmuFastPwrupDelay */
102 +static u16 pmu_fast_powerup_delay(struct ssb_chipcommon *cc)
104 + struct ssb_bus *bus = cc->dev->bus;
106 + switch (bus->chip_id) {
118 +/* http://bcm-v4.sipsolutions.net/802.11/ClkctlFastPwrupDelay */
119 static void calc_fast_powerup_delay(struct ssb_chipcommon *cc)
121 struct ssb_bus *bus = cc->dev->bus;
122 @@ -218,6 +262,12 @@ static void calc_fast_powerup_delay(stru
124 if (bus->bustype != SSB_BUSTYPE_PCI)
127 + if (cc->capabilities & SSB_CHIPCO_CAP_PMU) {
128 + cc->fast_pwrup_delay = pmu_fast_powerup_delay(cc);
132 if (!(cc->capabilities & SSB_CHIPCO_CAP_PCTL))
135 @@ -236,6 +286,12 @@ void ssb_chipcommon_init(struct ssb_chip
136 if (cc->dev->id.revision >= 11)
137 cc->status = chipco_read32(cc, SSB_CHIPCO_CHIPSTAT);
138 ssb_dprintk(KERN_INFO PFX "chipcommon status is 0x%x\n", cc->status);
140 + if (cc->dev->id.revision >= 20) {
141 + chipco_write32(cc, SSB_CHIPCO_GPIOPULLUP, 0);
142 + chipco_write32(cc, SSB_CHIPCO_GPIOPULLDOWN, 0);
146 chipco_powercontrol_init(cc);
147 ssb_chipco_set_clockmode(cc, SSB_CLKMODE_FAST);
148 @@ -373,6 +429,7 @@ u32 ssb_chipco_gpio_control(struct ssb_c
150 return chipco_write32_masked(cc, SSB_CHIPCO_GPIOCTL, mask, value);
152 +EXPORT_SYMBOL(ssb_chipco_gpio_control);
154 u32 ssb_chipco_gpio_intmask(struct ssb_chipcommon *cc, u32 mask, u32 value)
156 --- a/drivers/ssb/driver_chipcommon_pmu.c
157 +++ b/drivers/ssb/driver_chipcommon_pmu.c
159 * Sonics Silicon Backplane
160 * Broadcom ChipCommon Power Management Unit driver
162 - * Copyright 2009, Michael Buesch <mb@bu3sch.de>
163 + * Copyright 2009, Michael Buesch <m@bues.ch>
164 * Copyright 2007, Broadcom Corporation
166 * Licensed under the GNU/GPL. See COPYING for details.
168 #include <linux/ssb/ssb_regs.h>
169 #include <linux/ssb/ssb_driver_chipcommon.h>
170 #include <linux/delay.h>
171 +#ifdef CONFIG_BCM47XX
172 +#include <asm/mach-bcm47xx/nvram.h>
175 #include "ssb_private.h"
177 @@ -91,10 +94,6 @@ static void ssb_pmu0_pllinit_r0(struct s
178 u32 pmuctl, tmp, pllctl;
181 - if ((bus->chip_id == 0x5354) && !crystalfreq) {
182 - /* The 5354 crystal freq is 25MHz */
183 - crystalfreq = 25000;
186 e = pmu0_plltab_find_entry(crystalfreq);
188 @@ -320,7 +319,11 @@ static void ssb_pmu_pll_init(struct ssb_
189 u32 crystalfreq = 0; /* in kHz. 0 = keep default freq. */
191 if (bus->bustype == SSB_BUSTYPE_SSB) {
192 - /* TODO: The user may override the crystal frequency. */
193 +#ifdef CONFIG_BCM47XX
195 + if (nvram_getenv("xtalfreq", buf, sizeof(buf)) >= 0)
196 + crystalfreq = simple_strtoul(buf, NULL, 0);
200 switch (bus->chip_id) {
201 @@ -329,9 +332,19 @@ static void ssb_pmu_pll_init(struct ssb_
202 ssb_pmu1_pllinit_r0(cc, crystalfreq);
205 + ssb_pmu0_pllinit_r0(cc, crystalfreq);
208 + if (crystalfreq == 0)
209 + crystalfreq = 25000;
210 ssb_pmu0_pllinit_r0(cc, crystalfreq);
213 + if (cc->pmu.rev == 2) {
214 + chipco_write32(cc, SSB_CHIPCO_PLLCTL_ADDR, 0x0000000A);
215 + chipco_write32(cc, SSB_CHIPCO_PLLCTL_DATA, 0x380005C0);
219 ssb_printk(KERN_ERR PFX
220 "ERROR: PLL init unknown for device %04X\n",
221 @@ -411,12 +424,15 @@ static void ssb_pmu_resources_init(struc
222 u32 min_msk = 0, max_msk = 0;
224 const struct pmu_res_updown_tab_entry *updown_tab = NULL;
225 - unsigned int updown_tab_size;
226 + unsigned int updown_tab_size = 0;
227 const struct pmu_res_depend_tab_entry *depend_tab = NULL;
228 - unsigned int depend_tab_size;
229 + unsigned int depend_tab_size = 0;
231 switch (bus->chip_id) {
236 /* We keep the default settings:
239 @@ -495,9 +511,9 @@ static void ssb_pmu_resources_init(struc
240 chipco_write32(cc, SSB_CHIPCO_PMU_MAXRES_MSK, max_msk);
243 +/* http://bcm-v4.sipsolutions.net/802.11/SSB/PmuInit */
244 void ssb_pmu_init(struct ssb_chipcommon *cc)
246 - struct ssb_bus *bus = cc->dev->bus;
249 if (!(cc->capabilities & SSB_CHIPCO_CAP_PMU))
250 @@ -509,15 +525,12 @@ void ssb_pmu_init(struct ssb_chipcommon
251 ssb_dprintk(KERN_DEBUG PFX "Found rev %u PMU (capabilities 0x%08X)\n",
252 cc->pmu.rev, pmucap);
254 - if (cc->pmu.rev >= 1) {
255 - if ((bus->chip_id == 0x4325) && (bus->chip_rev < 2)) {
256 - chipco_mask32(cc, SSB_CHIPCO_PMU_CTL,
257 - ~SSB_CHIPCO_PMU_CTL_NOILPONW);
259 - chipco_set32(cc, SSB_CHIPCO_PMU_CTL,
260 - SSB_CHIPCO_PMU_CTL_NOILPONW);
263 + if (cc->pmu.rev == 1)
264 + chipco_mask32(cc, SSB_CHIPCO_PMU_CTL,
265 + ~SSB_CHIPCO_PMU_CTL_NOILPONW);
267 + chipco_set32(cc, SSB_CHIPCO_PMU_CTL,
268 + SSB_CHIPCO_PMU_CTL_NOILPONW);
269 ssb_pmu_pll_init(cc);
270 ssb_pmu_resources_init(cc);
272 @@ -600,3 +613,34 @@ void ssb_pmu_set_ldo_paref(struct ssb_ch
274 EXPORT_SYMBOL(ssb_pmu_set_ldo_voltage);
275 EXPORT_SYMBOL(ssb_pmu_set_ldo_paref);
277 +u32 ssb_pmu_get_cpu_clock(struct ssb_chipcommon *cc)
279 + struct ssb_bus *bus = cc->dev->bus;
281 + switch (bus->chip_id) {
283 + /* 5354 chip uses a non programmable PLL of frequency 240MHz */
286 + ssb_printk(KERN_ERR PFX
287 + "ERROR: PMU cpu clock unknown for device %04X\n",
293 +u32 ssb_pmu_get_controlclock(struct ssb_chipcommon *cc)
295 + struct ssb_bus *bus = cc->dev->bus;
297 + switch (bus->chip_id) {
301 + ssb_printk(KERN_ERR PFX
302 + "ERROR: PMU controlclock unknown for device %04X\n",
307 --- a/drivers/ssb/driver_gige.c
308 +++ b/drivers/ssb/driver_gige.c
310 * Broadcom Gigabit Ethernet core driver
312 * Copyright 2008, Broadcom Corporation
313 - * Copyright 2008, Michael Buesch <mb@bu3sch.de>
314 + * Copyright 2008, Michael Buesch <m@bues.ch>
316 * Licensed under the GNU/GPL. See COPYING for details.
319 #include <linux/ssb/ssb_driver_gige.h>
320 #include <linux/pci.h>
321 #include <linux/pci_regs.h>
322 +#include <linux/slab.h>
326 @@ -105,8 +106,9 @@ void gige_pcicfg_write32(struct ssb_gige
327 gige_write32(dev, SSB_GIGE_PCICFG + offset, value);
330 -static int ssb_gige_pci_read_config(struct pci_bus *bus, unsigned int devfn,
331 - int reg, int size, u32 *val)
332 +static int __devinit ssb_gige_pci_read_config(struct pci_bus *bus,
333 + unsigned int devfn, int reg,
334 + int size, u32 *val)
336 struct ssb_gige *dev = container_of(bus->ops, struct ssb_gige, pci_ops);
338 @@ -135,8 +137,9 @@ static int ssb_gige_pci_read_config(stru
339 return PCIBIOS_SUCCESSFUL;
342 -static int ssb_gige_pci_write_config(struct pci_bus *bus, unsigned int devfn,
343 - int reg, int size, u32 val)
344 +static int __devinit ssb_gige_pci_write_config(struct pci_bus *bus,
345 + unsigned int devfn, int reg,
348 struct ssb_gige *dev = container_of(bus->ops, struct ssb_gige, pci_ops);
350 @@ -165,7 +168,8 @@ static int ssb_gige_pci_write_config(str
351 return PCIBIOS_SUCCESSFUL;
354 -static int ssb_gige_probe(struct ssb_device *sdev, const struct ssb_device_id *id)
355 +static int __devinit ssb_gige_probe(struct ssb_device *sdev,
356 + const struct ssb_device_id *id)
358 struct ssb_gige *dev;
359 u32 base, tmslow, tmshigh;
360 --- a/drivers/ssb/driver_mipscore.c
361 +++ b/drivers/ssb/driver_mipscore.c
363 * Broadcom MIPS core driver
365 * Copyright 2005, Broadcom Corporation
366 - * Copyright 2006, 2007, Michael Buesch <mb@bu3sch.de>
367 + * Copyright 2006, 2007, Michael Buesch <m@bues.ch>
369 * Licensed under the GNU/GPL. See COPYING for details.
371 @@ -208,6 +208,9 @@ u32 ssb_cpu_clock(struct ssb_mipscore *m
372 struct ssb_bus *bus = mcore->dev->bus;
373 u32 pll_type, n, m, rate = 0;
375 + if (bus->chipco.capabilities & SSB_CHIPCO_CAP_PMU)
376 + return ssb_pmu_get_cpu_clock(&bus->chipco);
378 if (bus->extif.dev) {
379 ssb_extif_get_clockcontrol(&bus->extif, &pll_type, &n, &m);
380 } else if (bus->chipco.dev) {
381 @@ -270,7 +273,6 @@ void ssb_mipscore_init(struct ssb_mipsco
387 case SSB_DEV_ETHERNET:
388 case SSB_DEV_ETHERNET_GBIT:
389 @@ -281,6 +283,10 @@ void ssb_mipscore_init(struct ssb_mipsco
394 + case SSB_DEV_EXTIF:
399 ssb_dprintk(KERN_INFO PFX "after irq reconfiguration\n");
400 --- a/drivers/ssb/driver_pcicore.c
401 +++ b/drivers/ssb/driver_pcicore.c
403 * Broadcom PCI-core driver
405 * Copyright 2005, Broadcom Corporation
406 - * Copyright 2006, 2007, Michael Buesch <mb@bu3sch.de>
407 + * Copyright 2006, 2007, Michael Buesch <m@bues.ch>
409 * Licensed under the GNU/GPL. See COPYING for details.
413 #include "ssb_private.h"
415 +static u32 ssb_pcie_read(struct ssb_pcicore *pc, u32 address);
416 +static void ssb_pcie_write(struct ssb_pcicore *pc, u32 address, u32 data);
417 +static u16 ssb_pcie_mdio_read(struct ssb_pcicore *pc, u8 device, u8 address);
418 +static void ssb_pcie_mdio_write(struct ssb_pcicore *pc, u8 device,
419 + u8 address, u16 data);
422 u32 pcicore_read32(struct ssb_pcicore *pc, u16 offset)
423 @@ -69,7 +74,7 @@ static u32 get_cfgspace_addr(struct ssb_
426 /* We do only have one cardbus device behind the bridge. */
427 - if (pc->cardbusmode && (dev >= 1))
428 + if (pc->cardbusmode && (dev > 1))
432 @@ -246,20 +251,12 @@ static struct pci_controller ssb_pcicore
433 .pci_ops = &ssb_pcicore_pciops,
434 .io_resource = &ssb_pcicore_io_resource,
435 .mem_resource = &ssb_pcicore_mem_resource,
436 - .mem_offset = 0x24000000,
439 -static u32 ssb_pcicore_pcibus_iobase = 0x100;
440 -static u32 ssb_pcicore_pcibus_membase = SSB_PCI_DMA;
442 /* This function is called when doing a pci_enable_device().
443 * We must first check if the device is a device on the PCI-core bridge. */
444 int ssb_pcicore_plat_dev_init(struct pci_dev *d)
446 - struct resource *res;
450 if (d->bus->ops != &ssb_pcicore_pciops) {
451 /* This is not a device on the PCI-core bridge. */
453 @@ -268,27 +265,6 @@ int ssb_pcicore_plat_dev_init(struct pci
454 ssb_printk(KERN_INFO "PCI: Fixing up device %s\n",
457 - /* Fix up resource bases */
458 - for (pos = 0; pos < 6; pos++) {
459 - res = &d->resource[pos];
460 - if (res->flags & IORESOURCE_IO)
461 - base = &ssb_pcicore_pcibus_iobase;
463 - base = &ssb_pcicore_pcibus_membase;
464 - res->flags |= IORESOURCE_PCI_FIXED;
466 - size = res->end - res->start + 1;
467 - if (*base & (size - 1))
468 - *base = (*base + size) & ~(size - 1);
469 - res->start = *base;
470 - res->end = res->start + size - 1;
472 - pci_write_config_dword(d, PCI_BASE_ADDRESS_0 + (pos << 2), res->start);
474 - /* Fix up PCI bridge BAR0 only */
475 - if (d->bus->number == 0 && PCI_SLOT(d->devfn) == 0)
478 /* Fix up interrupt lines */
479 d->irq = ssb_mips_irq(extpci_core->dev) + 2;
480 pci_write_config_byte(d, PCI_INTERRUPT_LINE, d->irq);
481 @@ -338,7 +314,7 @@ int ssb_pcicore_pcibios_map_irq(const st
482 return ssb_mips_irq(extpci_core->dev) + 2;
485 -static void ssb_pcicore_init_hostmode(struct ssb_pcicore *pc)
486 +static void __devinit ssb_pcicore_init_hostmode(struct ssb_pcicore *pc)
490 @@ -403,7 +379,7 @@ static void ssb_pcicore_init_hostmode(st
491 register_pci_controller(&ssb_pcicore_controller);
494 -static int pcicore_is_in_hostmode(struct ssb_pcicore *pc)
495 +static int __devinit pcicore_is_in_hostmode(struct ssb_pcicore *pc)
497 struct ssb_bus *bus = pc->dev->bus;
499 @@ -432,25 +408,137 @@ static int pcicore_is_in_hostmode(struct
501 #endif /* CONFIG_SSB_PCICORE_HOSTMODE */
503 +/**************************************************
505 + **************************************************/
507 +static void __devinit ssb_pcicore_fix_sprom_core_index(struct ssb_pcicore *pc)
509 + u16 tmp = pcicore_read16(pc, SSB_PCICORE_SPROM(0));
510 + if (((tmp & 0xF000) >> 12) != pc->dev->core_index) {
512 + tmp |= (pc->dev->core_index << 12);
513 + pcicore_write16(pc, SSB_PCICORE_SPROM(0), tmp);
517 +static u8 ssb_pcicore_polarity_workaround(struct ssb_pcicore *pc)
519 + return (ssb_pcie_read(pc, 0x204) & 0x10) ? 0xC0 : 0x80;
522 +static void ssb_pcicore_serdes_workaround(struct ssb_pcicore *pc)
524 + const u8 serdes_pll_device = 0x1D;
525 + const u8 serdes_rx_device = 0x1F;
528 + ssb_pcie_mdio_write(pc, serdes_rx_device, 1 /* Control */,
529 + ssb_pcicore_polarity_workaround(pc));
530 + tmp = ssb_pcie_mdio_read(pc, serdes_pll_device, 1 /* Control */);
532 + ssb_pcie_mdio_write(pc, serdes_pll_device, 1, tmp & ~0x4000);
535 +static void ssb_pcicore_pci_setup_workarounds(struct ssb_pcicore *pc)
537 + struct ssb_device *pdev = pc->dev;
538 + struct ssb_bus *bus = pdev->bus;
541 + tmp = pcicore_read32(pc, SSB_PCICORE_SBTOPCI2);
542 + tmp |= SSB_PCICORE_SBTOPCI_PREF;
543 + tmp |= SSB_PCICORE_SBTOPCI_BURST;
544 + pcicore_write32(pc, SSB_PCICORE_SBTOPCI2, tmp);
546 + if (pdev->id.revision < 5) {
547 + tmp = ssb_read32(pdev, SSB_IMCFGLO);
548 + tmp &= ~SSB_IMCFGLO_SERTO;
550 + tmp &= ~SSB_IMCFGLO_REQTO;
551 + tmp |= 3 << SSB_IMCFGLO_REQTO_SHIFT;
552 + ssb_write32(pdev, SSB_IMCFGLO, tmp);
553 + ssb_commit_settings(bus);
554 + } else if (pdev->id.revision >= 11) {
555 + tmp = pcicore_read32(pc, SSB_PCICORE_SBTOPCI2);
556 + tmp |= SSB_PCICORE_SBTOPCI_MRM;
557 + pcicore_write32(pc, SSB_PCICORE_SBTOPCI2, tmp);
561 +static void ssb_pcicore_pcie_setup_workarounds(struct ssb_pcicore *pc)
564 + u8 rev = pc->dev->id.revision;
566 + if (rev == 0 || rev == 1) {
567 + /* TLP Workaround register. */
568 + tmp = ssb_pcie_read(pc, 0x4);
570 + ssb_pcie_write(pc, 0x4, tmp);
573 + /* DLLP Link Control register. */
574 + tmp = ssb_pcie_read(pc, 0x100);
576 + ssb_pcie_write(pc, 0x100, tmp);
580 + const u8 serdes_rx_device = 0x1F;
582 + ssb_pcie_mdio_write(pc, serdes_rx_device,
583 + 2 /* Timer */, 0x8128);
584 + ssb_pcie_mdio_write(pc, serdes_rx_device,
585 + 6 /* CDR */, 0x0100);
586 + ssb_pcie_mdio_write(pc, serdes_rx_device,
587 + 7 /* CDR BW */, 0x1466);
588 + } else if (rev == 3 || rev == 4 || rev == 5) {
589 + /* TODO: DLLP Power Management Threshold */
590 + ssb_pcicore_serdes_workaround(pc);
592 + } else if (rev == 7) {
593 + /* TODO: No PLL down */
597 + /* Miscellaneous Configuration Fixup */
598 + tmp = pcicore_read16(pc, SSB_PCICORE_SPROM(5));
599 + if (!(tmp & 0x8000))
600 + pcicore_write16(pc, SSB_PCICORE_SPROM(5),
605 /**************************************************
606 * Generic and Clientmode operation code.
607 **************************************************/
609 -static void ssb_pcicore_init_clientmode(struct ssb_pcicore *pc)
610 +static void __devinit ssb_pcicore_init_clientmode(struct ssb_pcicore *pc)
612 + struct ssb_device *pdev = pc->dev;
613 + struct ssb_bus *bus = pdev->bus;
615 + if (bus->bustype == SSB_BUSTYPE_PCI)
616 + ssb_pcicore_fix_sprom_core_index(pc);
618 /* Disable PCI interrupts. */
619 - ssb_write32(pc->dev, SSB_INTVEC, 0);
620 + ssb_write32(pdev, SSB_INTVEC, 0);
622 + /* Additional PCIe always once-executed workarounds */
623 + if (pc->dev->id.coreid == SSB_DEV_PCIE) {
624 + ssb_pcicore_serdes_workaround(pc);
626 + /* TODO: Clock Request Update */
630 -void ssb_pcicore_init(struct ssb_pcicore *pc)
631 +void __devinit ssb_pcicore_init(struct ssb_pcicore *pc)
633 struct ssb_device *dev = pc->dev;
634 - struct ssb_bus *bus;
639 if (!ssb_device_is_enabled(dev))
640 ssb_device_enable(dev, 0);
642 @@ -475,58 +563,104 @@ static void ssb_pcie_write(struct ssb_pc
643 pcicore_write32(pc, 0x134, data);
646 -static void ssb_pcie_mdio_write(struct ssb_pcicore *pc, u8 device,
647 - u8 address, u16 data)
648 +static void ssb_pcie_mdio_set_phy(struct ssb_pcicore *pc, u8 phy)
650 const u16 mdio_control = 0x128;
651 const u16 mdio_data = 0x12C;
655 + v = (1 << 30); /* Start of Transaction */
656 + v |= (1 << 28); /* Write Transaction */
657 + v |= (1 << 17); /* Turnaround */
660 + pcicore_write32(pc, mdio_data, v);
663 + for (i = 0; i < 200; i++) {
664 + v = pcicore_read32(pc, mdio_control);
665 + if (v & 0x100 /* Trans complete */)
671 +static u16 ssb_pcie_mdio_read(struct ssb_pcicore *pc, u8 device, u8 address)
673 + const u16 mdio_control = 0x128;
674 + const u16 mdio_data = 0x12C;
675 + int max_retries = 10;
680 v = 0x80; /* Enable Preamble Sequence */
681 v |= 0x2; /* MDIO Clock Divisor */
682 pcicore_write32(pc, mdio_control, v);
684 + if (pc->dev->id.revision >= 10) {
686 + ssb_pcie_mdio_set_phy(pc, device);
689 v = (1 << 30); /* Start of Transaction */
690 - v |= (1 << 28); /* Write Transaction */
691 + v |= (1 << 29); /* Read Transaction */
692 v |= (1 << 17); /* Turnaround */
693 - v |= (u32)device << 22;
694 + if (pc->dev->id.revision < 10)
695 + v |= (u32)device << 22;
696 v |= (u32)address << 18;
698 pcicore_write32(pc, mdio_data, v);
699 /* Wait for the device to complete the transaction */
701 - for (i = 0; i < 10; i++) {
702 + for (i = 0; i < max_retries; i++) {
703 v = pcicore_read32(pc, mdio_control);
704 - if (v & 0x100 /* Trans complete */)
705 + if (v & 0x100 /* Trans complete */) {
707 + ret = pcicore_read32(pc, mdio_data);
712 pcicore_write32(pc, mdio_control, 0);
716 -static void ssb_broadcast_value(struct ssb_device *dev,
717 - u32 address, u32 data)
718 +static void ssb_pcie_mdio_write(struct ssb_pcicore *pc, u8 device,
719 + u8 address, u16 data)
721 - /* This is used for both, PCI and ChipCommon core, so be careful. */
722 - BUILD_BUG_ON(SSB_PCICORE_BCAST_ADDR != SSB_CHIPCO_BCAST_ADDR);
723 - BUILD_BUG_ON(SSB_PCICORE_BCAST_DATA != SSB_CHIPCO_BCAST_DATA);
724 + const u16 mdio_control = 0x128;
725 + const u16 mdio_data = 0x12C;
726 + int max_retries = 10;
730 - ssb_write32(dev, SSB_PCICORE_BCAST_ADDR, address);
731 - ssb_read32(dev, SSB_PCICORE_BCAST_ADDR); /* flush */
732 - ssb_write32(dev, SSB_PCICORE_BCAST_DATA, data);
733 - ssb_read32(dev, SSB_PCICORE_BCAST_DATA); /* flush */
735 + v = 0x80; /* Enable Preamble Sequence */
736 + v |= 0x2; /* MDIO Clock Divisor */
737 + pcicore_write32(pc, mdio_control, v);
739 -static void ssb_commit_settings(struct ssb_bus *bus)
741 - struct ssb_device *dev;
742 + if (pc->dev->id.revision >= 10) {
744 + ssb_pcie_mdio_set_phy(pc, device);
747 - dev = bus->chipco.dev ? bus->chipco.dev : bus->pcicore.dev;
750 - /* This forces an update of the cached registers. */
751 - ssb_broadcast_value(dev, 0xFD8, 0);
752 + v = (1 << 30); /* Start of Transaction */
753 + v |= (1 << 28); /* Write Transaction */
754 + v |= (1 << 17); /* Turnaround */
755 + if (pc->dev->id.revision < 10)
756 + v |= (u32)device << 22;
757 + v |= (u32)address << 18;
759 + pcicore_write32(pc, mdio_data, v);
760 + /* Wait for the device to complete the transaction */
762 + for (i = 0; i < max_retries; i++) {
763 + v = pcicore_read32(pc, mdio_control);
764 + if (v & 0x100 /* Trans complete */)
768 + pcicore_write32(pc, mdio_control, 0);
771 int ssb_pcicore_dev_irqvecs_enable(struct ssb_pcicore *pc,
772 @@ -551,13 +685,13 @@ int ssb_pcicore_dev_irqvecs_enable(struc
773 might_sleep_if(pdev->id.coreid != SSB_DEV_PCI);
775 /* Enable interrupts for this device. */
776 - if (bus->host_pci &&
777 - ((pdev->id.revision >= 6) || (pdev->id.coreid == SSB_DEV_PCIE))) {
778 + if ((pdev->id.revision >= 6) || (pdev->id.coreid == SSB_DEV_PCIE)) {
781 /* Calculate the "coremask" for the device. */
782 coremask = (1 << dev->core_index);
784 + SSB_WARN_ON(bus->bustype != SSB_BUSTYPE_PCI);
785 err = pci_read_config_dword(bus->host_pci, SSB_PCI_IRQMASK, &tmp);
788 @@ -579,48 +713,10 @@ int ssb_pcicore_dev_irqvecs_enable(struc
791 if (pdev->id.coreid == SSB_DEV_PCI) {
792 - tmp = pcicore_read32(pc, SSB_PCICORE_SBTOPCI2);
793 - tmp |= SSB_PCICORE_SBTOPCI_PREF;
794 - tmp |= SSB_PCICORE_SBTOPCI_BURST;
795 - pcicore_write32(pc, SSB_PCICORE_SBTOPCI2, tmp);
797 - if (pdev->id.revision < 5) {
798 - tmp = ssb_read32(pdev, SSB_IMCFGLO);
799 - tmp &= ~SSB_IMCFGLO_SERTO;
801 - tmp &= ~SSB_IMCFGLO_REQTO;
802 - tmp |= 3 << SSB_IMCFGLO_REQTO_SHIFT;
803 - ssb_write32(pdev, SSB_IMCFGLO, tmp);
804 - ssb_commit_settings(bus);
805 - } else if (pdev->id.revision >= 11) {
806 - tmp = pcicore_read32(pc, SSB_PCICORE_SBTOPCI2);
807 - tmp |= SSB_PCICORE_SBTOPCI_MRM;
808 - pcicore_write32(pc, SSB_PCICORE_SBTOPCI2, tmp);
810 + ssb_pcicore_pci_setup_workarounds(pc);
812 WARN_ON(pdev->id.coreid != SSB_DEV_PCIE);
813 - //TODO: Better make defines for all these magic PCIE values.
814 - if ((pdev->id.revision == 0) || (pdev->id.revision == 1)) {
815 - /* TLP Workaround register. */
816 - tmp = ssb_pcie_read(pc, 0x4);
818 - ssb_pcie_write(pc, 0x4, tmp);
820 - if (pdev->id.revision == 0) {
821 - const u8 serdes_rx_device = 0x1F;
823 - ssb_pcie_mdio_write(pc, serdes_rx_device,
824 - 2 /* Timer */, 0x8128);
825 - ssb_pcie_mdio_write(pc, serdes_rx_device,
826 - 6 /* CDR */, 0x0100);
827 - ssb_pcie_mdio_write(pc, serdes_rx_device,
828 - 7 /* CDR BW */, 0x1466);
829 - } else if (pdev->id.revision == 1) {
830 - /* DLLP Link Control register. */
831 - tmp = ssb_pcie_read(pc, 0x100);
833 - ssb_pcie_write(pc, 0x100, tmp);
835 + ssb_pcicore_pcie_setup_workarounds(pc);
839 --- a/drivers/ssb/main.c
840 +++ b/drivers/ssb/main.c
844 * Copyright 2005, Broadcom Corporation
845 - * Copyright 2006, 2007, Michael Buesch <mb@bu3sch.de>
846 + * Copyright 2006, 2007, Michael Buesch <m@bues.ch>
848 * Licensed under the GNU/GPL. See COPYING for details.
852 #include <linux/delay.h>
853 #include <linux/io.h>
854 +#include <linux/module.h>
855 #include <linux/ssb/ssb.h>
856 #include <linux/ssb/ssb_regs.h>
857 #include <linux/ssb/ssb_driver_gige.h>
858 #include <linux/dma-mapping.h>
859 #include <linux/pci.h>
860 #include <linux/mmc/sdio_func.h>
861 +#include <linux/slab.h>
863 #include <pcmcia/cs_types.h>
864 #include <pcmcia/cs.h>
865 @@ -210,90 +212,78 @@ int ssb_bus_suspend(struct ssb_bus *bus)
866 EXPORT_SYMBOL(ssb_bus_suspend);
868 #ifdef CONFIG_SSB_SPROM
869 -int ssb_devices_freeze(struct ssb_bus *bus)
870 +/** ssb_devices_freeze - Freeze all devices on the bus.
872 + * After freezing no device driver will be handling a device
873 + * on this bus anymore. ssb_devices_thaw() must be called after
874 + * a successful freeze to reactivate the devices.
877 + * @ctx: Context structure. Pass this to ssb_devices_thaw().
879 +int ssb_devices_freeze(struct ssb_bus *bus, struct ssb_freeze_context *ctx)
881 - struct ssb_device *dev;
882 - struct ssb_driver *drv;
885 - pm_message_t state = PMSG_FREEZE;
886 + struct ssb_device *sdev;
887 + struct ssb_driver *sdrv;
890 + memset(ctx, 0, sizeof(*ctx));
892 + SSB_WARN_ON(bus->nr_devices > ARRAY_SIZE(ctx->device_frozen));
894 - /* First check that we are capable to freeze all devices. */
895 for (i = 0; i < bus->nr_devices; i++) {
896 - dev = &(bus->devices[i]);
898 - !dev->dev->driver ||
899 - !device_is_registered(dev->dev))
901 - drv = drv_to_ssb_drv(dev->dev->driver);
903 + sdev = ssb_device_get(&bus->devices[i]);
905 + if (!sdev->dev || !sdev->dev->driver ||
906 + !device_is_registered(sdev->dev)) {
907 + ssb_device_put(sdev);
909 - if (!drv->suspend) {
910 - /* Nope, can't suspend this one. */
911 - return -EOPNOTSUPP;
914 - /* Now suspend all devices */
915 - for (i = 0; i < bus->nr_devices; i++) {
916 - dev = &(bus->devices[i]);
918 - !dev->dev->driver ||
919 - !device_is_registered(dev->dev))
921 - drv = drv_to_ssb_drv(dev->dev->driver);
923 + sdrv = drv_to_ssb_drv(sdev->dev->driver);
924 + if (SSB_WARN_ON(!sdrv->remove))
926 - err = drv->suspend(dev, state);
928 - ssb_printk(KERN_ERR PFX "Failed to freeze device %s\n",
929 - dev_name(dev->dev));
932 + sdrv->remove(sdev);
933 + ctx->device_frozen[i] = 1;
938 - for (i--; i >= 0; i--) {
939 - dev = &(bus->devices[i]);
941 - !dev->dev->driver ||
942 - !device_is_registered(dev->dev))
944 - drv = drv_to_ssb_drv(dev->dev->driver);
953 -int ssb_devices_thaw(struct ssb_bus *bus)
954 +/** ssb_devices_thaw - Unfreeze all devices on the bus.
956 + * This will re-attach the device drivers and re-init the devices.
958 + * @ctx: The context structure from ssb_devices_freeze()
960 +int ssb_devices_thaw(struct ssb_freeze_context *ctx)
962 - struct ssb_device *dev;
963 - struct ssb_driver *drv;
966 + struct ssb_bus *bus = ctx->bus;
967 + struct ssb_device *sdev;
968 + struct ssb_driver *sdrv;
970 + int err, result = 0;
972 for (i = 0; i < bus->nr_devices; i++) {
973 - dev = &(bus->devices[i]);
975 - !dev->dev->driver ||
976 - !device_is_registered(dev->dev))
977 + if (!ctx->device_frozen[i])
979 - drv = drv_to_ssb_drv(dev->dev->driver);
981 + sdev = &bus->devices[i];
983 + if (SSB_WARN_ON(!sdev->dev || !sdev->dev->driver))
985 - if (SSB_WARN_ON(!drv->resume))
986 + sdrv = drv_to_ssb_drv(sdev->dev->driver);
987 + if (SSB_WARN_ON(!sdrv || !sdrv->probe))
989 - err = drv->resume(dev);
991 + err = sdrv->probe(sdev, &sdev->id);
993 ssb_printk(KERN_ERR PFX "Failed to thaw device %s\n",
994 - dev_name(dev->dev));
995 + dev_name(sdev->dev));
998 + ssb_device_put(sdev);
1004 #endif /* CONFIG_SSB_SPROM */
1006 @@ -380,6 +370,35 @@ static int ssb_device_uevent(struct devi
1007 ssb_dev->id.revision);
1010 +#define ssb_config_attr(attrib, field, format_string) \
1012 +attrib##_show(struct device *dev, struct device_attribute *attr, char *buf) \
1014 + return sprintf(buf, format_string, dev_to_ssb_dev(dev)->field); \
1017 +ssb_config_attr(core_num, core_index, "%u\n")
1018 +ssb_config_attr(coreid, id.coreid, "0x%04x\n")
1019 +ssb_config_attr(vendor, id.vendor, "0x%04x\n")
1020 +ssb_config_attr(revision, id.revision, "%u\n")
1021 +ssb_config_attr(irq, irq, "%u\n")
1023 +name_show(struct device *dev, struct device_attribute *attr, char *buf)
1025 + return sprintf(buf, "%s\n",
1026 + ssb_core_name(dev_to_ssb_dev(dev)->id.coreid));
1029 +static struct device_attribute ssb_device_attrs[] = {
1031 + __ATTR_RO(core_num),
1032 + __ATTR_RO(coreid),
1033 + __ATTR_RO(vendor),
1034 + __ATTR_RO(revision),
1039 static struct bus_type ssb_bustype = {
1041 .match = ssb_bus_match,
1042 @@ -389,6 +408,7 @@ static struct bus_type ssb_bustype = {
1043 .suspend = ssb_device_suspend,
1044 .resume = ssb_device_resume,
1045 .uevent = ssb_device_uevent,
1046 + .dev_attrs = ssb_device_attrs,
1049 static void ssb_buses_lock(void)
1050 @@ -481,6 +501,7 @@ static int ssb_devices_register(struct s
1051 #ifdef CONFIG_SSB_PCIHOST
1052 sdev->irq = bus->host_pci->irq;
1053 dev->parent = &bus->host_pci->dev;
1054 + sdev->dma_dev = dev->parent;
1057 case SSB_BUSTYPE_PCMCIA:
1058 @@ -490,13 +511,13 @@ static int ssb_devices_register(struct s
1061 case SSB_BUSTYPE_SDIO:
1062 -#ifdef CONFIG_SSB_SDIO
1063 - sdev->irq = bus->host_sdio->dev.irq;
1064 +#ifdef CONFIG_SSB_SDIOHOST
1065 dev->parent = &bus->host_sdio->dev;
1068 case SSB_BUSTYPE_SSB:
1069 dev->dma_mask = &dev->coherent_dma_mask;
1070 + sdev->dma_dev = dev;
1074 @@ -523,7 +544,7 @@ error:
1077 /* Needs ssb_buses_lock() */
1078 -static int ssb_attach_queued_buses(void)
1079 +static int __devinit ssb_attach_queued_buses(void)
1081 struct ssb_bus *bus, *n;
1083 @@ -734,9 +755,9 @@ out:
1087 -static int ssb_bus_register(struct ssb_bus *bus,
1088 - ssb_invariants_func_t get_invariants,
1089 - unsigned long baseaddr)
1090 +static int __devinit ssb_bus_register(struct ssb_bus *bus,
1091 + ssb_invariants_func_t get_invariants,
1092 + unsigned long baseaddr)
1096 @@ -817,8 +838,8 @@ err_disable_xtal:
1099 #ifdef CONFIG_SSB_PCIHOST
1100 -int ssb_bus_pcibus_register(struct ssb_bus *bus,
1101 - struct pci_dev *host_pci)
1102 +int __devinit ssb_bus_pcibus_register(struct ssb_bus *bus,
1103 + struct pci_dev *host_pci)
1107 @@ -830,6 +851,9 @@ int ssb_bus_pcibus_register(struct ssb_b
1109 ssb_printk(KERN_INFO PFX "Sonics Silicon Backplane found on "
1110 "PCI device %s\n", dev_name(&host_pci->dev));
1112 + ssb_printk(KERN_ERR PFX "Failed to register PCI version"
1113 + " of SSB with error %d\n", err);
1117 @@ -838,9 +862,9 @@ EXPORT_SYMBOL(ssb_bus_pcibus_register);
1118 #endif /* CONFIG_SSB_PCIHOST */
1120 #ifdef CONFIG_SSB_PCMCIAHOST
1121 -int ssb_bus_pcmciabus_register(struct ssb_bus *bus,
1122 - struct pcmcia_device *pcmcia_dev,
1123 - unsigned long baseaddr)
1124 +int __devinit ssb_bus_pcmciabus_register(struct ssb_bus *bus,
1125 + struct pcmcia_device *pcmcia_dev,
1126 + unsigned long baseaddr)
1130 @@ -860,8 +884,9 @@ EXPORT_SYMBOL(ssb_bus_pcmciabus_register
1131 #endif /* CONFIG_SSB_PCMCIAHOST */
1133 #ifdef CONFIG_SSB_SDIOHOST
1134 -int ssb_bus_sdiobus_register(struct ssb_bus *bus, struct sdio_func *func,
1135 - unsigned int quirks)
1136 +int __devinit ssb_bus_sdiobus_register(struct ssb_bus *bus,
1137 + struct sdio_func *func,
1138 + unsigned int quirks)
1142 @@ -881,9 +906,9 @@ int ssb_bus_sdiobus_register(struct ssb_
1143 EXPORT_SYMBOL(ssb_bus_sdiobus_register);
1144 #endif /* CONFIG_SSB_PCMCIAHOST */
1146 -int ssb_bus_ssbbus_register(struct ssb_bus *bus,
1147 - unsigned long baseaddr,
1148 - ssb_invariants_func_t get_invariants)
1149 +int __devinit ssb_bus_ssbbus_register(struct ssb_bus *bus,
1150 + unsigned long baseaddr,
1151 + ssb_invariants_func_t get_invariants)
1155 @@ -964,8 +989,8 @@ u32 ssb_calc_clock_rate(u32 plltype, u32
1157 case SSB_PLLTYPE_6: /* 100/200 or 120/240 only */
1158 if (m & SSB_CHIPCO_CLK_T6_MMASK)
1159 - return SSB_CHIPCO_CLK_T6_M0;
1160 - return SSB_CHIPCO_CLK_T6_M1;
1161 + return SSB_CHIPCO_CLK_T6_M1;
1162 + return SSB_CHIPCO_CLK_T6_M0;
1163 case SSB_PLLTYPE_1: /* 48Mhz base, 3 dividers */
1164 case SSB_PLLTYPE_3: /* 25Mhz, 2 dividers */
1165 case SSB_PLLTYPE_4: /* 48Mhz, 4 dividers */
1166 @@ -1055,6 +1080,9 @@ u32 ssb_clockspeed(struct ssb_bus *bus)
1168 u32 clkctl_n, clkctl_m;
1170 + if (bus->chipco.capabilities & SSB_CHIPCO_CAP_PMU)
1171 + return ssb_pmu_get_controlclock(&bus->chipco);
1173 if (ssb_extif_available(&bus->extif))
1174 ssb_extif_get_clockcontrol(&bus->extif, &plltype,
1175 &clkctl_n, &clkctl_m);
1176 @@ -1080,23 +1108,22 @@ static u32 ssb_tmslow_reject_bitmask(str
1178 u32 rev = ssb_read32(dev, SSB_IDLOW) & SSB_IDLOW_SSBREV;
1180 - /* The REJECT bit changed position in TMSLOW between
1181 - * Backplane revisions. */
1182 + /* The REJECT bit seems to be different for Backplane rev 2.3 */
1184 case SSB_IDLOW_SSBREV_22:
1185 - return SSB_TMSLOW_REJECT_22;
1186 + case SSB_IDLOW_SSBREV_24:
1187 + case SSB_IDLOW_SSBREV_26:
1188 + return SSB_TMSLOW_REJECT;
1189 case SSB_IDLOW_SSBREV_23:
1190 return SSB_TMSLOW_REJECT_23;
1191 - case SSB_IDLOW_SSBREV_24: /* TODO - find the proper REJECT bits */
1192 - case SSB_IDLOW_SSBREV_25: /* same here */
1193 - case SSB_IDLOW_SSBREV_26: /* same here */
1194 + case SSB_IDLOW_SSBREV_25: /* TODO - find the proper REJECT bit */
1195 case SSB_IDLOW_SSBREV_27: /* same here */
1196 - return SSB_TMSLOW_REJECT_23; /* this is a guess */
1197 + return SSB_TMSLOW_REJECT; /* this is a guess */
1199 printk(KERN_INFO "ssb: Backplane Revision 0x%.8X\n", rev);
1202 - return (SSB_TMSLOW_REJECT_22 | SSB_TMSLOW_REJECT_23);
1203 + return (SSB_TMSLOW_REJECT | SSB_TMSLOW_REJECT_23);
1206 int ssb_device_is_enabled(struct ssb_device *dev)
1207 @@ -1155,10 +1182,10 @@ void ssb_device_enable(struct ssb_device
1209 EXPORT_SYMBOL(ssb_device_enable);
1211 -/* Wait for a bit in a register to get set or unset.
1212 +/* Wait for bitmask in a register to get set or cleared.
1213 * timeout is in units of ten-microseconds */
1214 -static int ssb_wait_bit(struct ssb_device *dev, u16 reg, u32 bitmask,
1215 - int timeout, int set)
1216 +static int ssb_wait_bits(struct ssb_device *dev, u16 reg, u32 bitmask,
1217 + int timeout, int set)
1221 @@ -1166,7 +1193,7 @@ static int ssb_wait_bit(struct ssb_devic
1222 for (i = 0; i < timeout; i++) {
1223 val = ssb_read32(dev, reg);
1225 - if (val & bitmask)
1226 + if ((val & bitmask) == bitmask)
1229 if (!(val & bitmask))
1230 @@ -1183,20 +1210,38 @@ static int ssb_wait_bit(struct ssb_devic
1232 void ssb_device_disable(struct ssb_device *dev, u32 core_specific_flags)
1237 if (ssb_read32(dev, SSB_TMSLOW) & SSB_TMSLOW_RESET)
1240 reject = ssb_tmslow_reject_bitmask(dev);
1241 - ssb_write32(dev, SSB_TMSLOW, reject | SSB_TMSLOW_CLOCK);
1242 - ssb_wait_bit(dev, SSB_TMSLOW, reject, 1000, 1);
1243 - ssb_wait_bit(dev, SSB_TMSHIGH, SSB_TMSHIGH_BUSY, 1000, 0);
1244 - ssb_write32(dev, SSB_TMSLOW,
1245 - SSB_TMSLOW_FGC | SSB_TMSLOW_CLOCK |
1246 - reject | SSB_TMSLOW_RESET |
1247 - core_specific_flags);
1248 - ssb_flush_tmslow(dev);
1250 + if (ssb_read32(dev, SSB_TMSLOW) & SSB_TMSLOW_CLOCK) {
1251 + ssb_write32(dev, SSB_TMSLOW, reject | SSB_TMSLOW_CLOCK);
1252 + ssb_wait_bits(dev, SSB_TMSLOW, reject, 1000, 1);
1253 + ssb_wait_bits(dev, SSB_TMSHIGH, SSB_TMSHIGH_BUSY, 1000, 0);
1255 + if (ssb_read32(dev, SSB_IDLOW) & SSB_IDLOW_INITIATOR) {
1256 + val = ssb_read32(dev, SSB_IMSTATE);
1257 + val |= SSB_IMSTATE_REJECT;
1258 + ssb_write32(dev, SSB_IMSTATE, val);
1259 + ssb_wait_bits(dev, SSB_IMSTATE, SSB_IMSTATE_BUSY, 1000,
1263 + ssb_write32(dev, SSB_TMSLOW,
1264 + SSB_TMSLOW_FGC | SSB_TMSLOW_CLOCK |
1265 + reject | SSB_TMSLOW_RESET |
1266 + core_specific_flags);
1267 + ssb_flush_tmslow(dev);
1269 + if (ssb_read32(dev, SSB_IDLOW) & SSB_IDLOW_INITIATOR) {
1270 + val = ssb_read32(dev, SSB_IMSTATE);
1271 + val &= ~SSB_IMSTATE_REJECT;
1272 + ssb_write32(dev, SSB_IMSTATE, val);
1276 ssb_write32(dev, SSB_TMSLOW,
1277 reject | SSB_TMSLOW_RESET |
1278 @@ -1205,13 +1250,34 @@ void ssb_device_disable(struct ssb_devic
1280 EXPORT_SYMBOL(ssb_device_disable);
1282 +/* Some chipsets need routing known for PCIe and 64-bit DMA */
1283 +static bool ssb_dma_translation_special_bit(struct ssb_device *dev)
1285 + u16 chip_id = dev->bus->chip_id;
1287 + if (dev->id.coreid == SSB_DEV_80211) {
1288 + return (chip_id == 0x4322 || chip_id == 43221 ||
1289 + chip_id == 43231 || chip_id == 43222);
1295 u32 ssb_dma_translation(struct ssb_device *dev)
1297 switch (dev->bus->bustype) {
1298 case SSB_BUSTYPE_SSB:
1300 case SSB_BUSTYPE_PCI:
1301 - return SSB_PCI_DMA;
1302 + if (dev->bus->host_pci->is_pcie &&
1303 + ssb_read32(dev, SSB_TMSHIGH) & SSB_TMSHIGH_DMA64) {
1304 + return SSB_PCIE_DMA_H32;
1306 + if (ssb_dma_translation_special_bit(dev))
1307 + return SSB_PCIE_DMA_H32;
1309 + return SSB_PCI_DMA;
1312 __ssb_dma_not_implemented(dev);
1314 @@ -1328,20 +1394,20 @@ EXPORT_SYMBOL(ssb_bus_may_powerdown);
1316 int ssb_bus_powerup(struct ssb_bus *bus, bool dynamic_pctl)
1318 - struct ssb_chipcommon *cc;
1320 enum ssb_clkmode mode;
1322 err = ssb_pci_xtal(bus, SSB_GPIO_XTAL | SSB_GPIO_PLL, 1);
1325 - cc = &bus->chipco;
1326 - mode = dynamic_pctl ? SSB_CLKMODE_DYNAMIC : SSB_CLKMODE_FAST;
1327 - ssb_chipco_set_clockmode(cc, mode);
1329 #ifdef CONFIG_SSB_DEBUG
1330 bus->powered_up = 1;
1333 + mode = dynamic_pctl ? SSB_CLKMODE_DYNAMIC : SSB_CLKMODE_FAST;
1334 + ssb_chipco_set_clockmode(&bus->chipco, mode);
1338 ssb_printk(KERN_ERR PFX "Bus powerup failed\n");
1339 @@ -1349,6 +1415,37 @@ error:
1341 EXPORT_SYMBOL(ssb_bus_powerup);
1343 +static void ssb_broadcast_value(struct ssb_device *dev,
1344 + u32 address, u32 data)
1346 +#ifdef CONFIG_SSB_DRIVER_PCICORE
1347 + /* This is used for both, PCI and ChipCommon core, so be careful. */
1348 + BUILD_BUG_ON(SSB_PCICORE_BCAST_ADDR != SSB_CHIPCO_BCAST_ADDR);
1349 + BUILD_BUG_ON(SSB_PCICORE_BCAST_DATA != SSB_CHIPCO_BCAST_DATA);
1352 + ssb_write32(dev, SSB_CHIPCO_BCAST_ADDR, address);
1353 + ssb_read32(dev, SSB_CHIPCO_BCAST_ADDR); /* flush */
1354 + ssb_write32(dev, SSB_CHIPCO_BCAST_DATA, data);
1355 + ssb_read32(dev, SSB_CHIPCO_BCAST_DATA); /* flush */
1358 +void ssb_commit_settings(struct ssb_bus *bus)
1360 + struct ssb_device *dev;
1362 +#ifdef CONFIG_SSB_DRIVER_PCICORE
1363 + dev = bus->chipco.dev ? bus->chipco.dev : bus->pcicore.dev;
1365 + dev = bus->chipco.dev;
1367 + if (WARN_ON(!dev))
1369 + /* This forces an update of the cached registers. */
1370 + ssb_broadcast_value(dev, 0xFD8, 0);
1372 +EXPORT_SYMBOL(ssb_commit_settings);
1374 u32 ssb_admatch_base(u32 adm)
1377 --- a/drivers/ssb/pci.c
1378 +++ b/drivers/ssb/pci.c
1381 * Sonics Silicon Backplane PCI-Hostbus related functions.
1383 - * Copyright (C) 2005-2006 Michael Buesch <mb@bu3sch.de>
1384 + * Copyright (C) 2005-2006 Michael Buesch <m@bues.ch>
1385 * Copyright (C) 2005 Martin Langer <martin-langer@gmx.de>
1386 * Copyright (C) 2005 Stefano Brivio <st3@riseup.net>
1387 * Copyright (C) 2005 Danny van Dyk <kugelfang@gentoo.org>
1390 #include <linux/ssb/ssb.h>
1391 #include <linux/ssb/ssb_regs.h>
1392 +#include <linux/slab.h>
1393 #include <linux/pci.h>
1394 #include <linux/delay.h>
1396 @@ -167,7 +168,7 @@ err_pci:
1399 /* Get the word-offset for a SSB_SPROM_XXX define. */
1400 -#define SPOFF(offset) (((offset) - SSB_SPROM_BASE1) / sizeof(u16))
1401 +#define SPOFF(offset) ((offset) / sizeof(u16))
1402 /* Helper to extract some _offset, which is one of the SSB_SPROM_XXX defines. */
1403 #define SPEX16(_outvar, _offset, _mask, _shift) \
1404 out->_outvar = ((in[SPOFF(_offset)] & (_mask)) >> (_shift))
1405 @@ -330,7 +331,6 @@ static void sprom_extract_r123(struct ss
1412 if (out->revision == 3) /* rev 3 moved MAC */
1413 @@ -389,20 +389,52 @@ static void sprom_extract_r123(struct ss
1414 SPEX(boardflags_hi, SSB_SPROM2_BFLHI, 0xFFFF, 0);
1416 /* Extract the antenna gain values. */
1417 - gain = r123_extract_antgain(out->revision, in,
1418 - SSB_SPROM1_AGAIN_BG,
1419 - SSB_SPROM1_AGAIN_BG_SHIFT);
1420 - out->antenna_gain.ghz24.a0 = gain;
1421 - out->antenna_gain.ghz24.a1 = gain;
1422 - out->antenna_gain.ghz24.a2 = gain;
1423 - out->antenna_gain.ghz24.a3 = gain;
1424 - gain = r123_extract_antgain(out->revision, in,
1425 - SSB_SPROM1_AGAIN_A,
1426 - SSB_SPROM1_AGAIN_A_SHIFT);
1427 - out->antenna_gain.ghz5.a0 = gain;
1428 - out->antenna_gain.ghz5.a1 = gain;
1429 - out->antenna_gain.ghz5.a2 = gain;
1430 - out->antenna_gain.ghz5.a3 = gain;
1431 + out->antenna_gain.a0 = r123_extract_antgain(out->revision, in,
1432 + SSB_SPROM1_AGAIN_BG,
1433 + SSB_SPROM1_AGAIN_BG_SHIFT);
1434 + out->antenna_gain.a1 = r123_extract_antgain(out->revision, in,
1435 + SSB_SPROM1_AGAIN_A,
1436 + SSB_SPROM1_AGAIN_A_SHIFT);
1439 +/* Revs 4 5 and 8 have partially shared layout */
1440 +static void sprom_extract_r458(struct ssb_sprom *out, const u16 *in)
1442 + SPEX(txpid2g[0], SSB_SPROM4_TXPID2G01,
1443 + SSB_SPROM4_TXPID2G0, SSB_SPROM4_TXPID2G0_SHIFT);
1444 + SPEX(txpid2g[1], SSB_SPROM4_TXPID2G01,
1445 + SSB_SPROM4_TXPID2G1, SSB_SPROM4_TXPID2G1_SHIFT);
1446 + SPEX(txpid2g[2], SSB_SPROM4_TXPID2G23,
1447 + SSB_SPROM4_TXPID2G2, SSB_SPROM4_TXPID2G2_SHIFT);
1448 + SPEX(txpid2g[3], SSB_SPROM4_TXPID2G23,
1449 + SSB_SPROM4_TXPID2G3, SSB_SPROM4_TXPID2G3_SHIFT);
1451 + SPEX(txpid5gl[0], SSB_SPROM4_TXPID5GL01,
1452 + SSB_SPROM4_TXPID5GL0, SSB_SPROM4_TXPID5GL0_SHIFT);
1453 + SPEX(txpid5gl[1], SSB_SPROM4_TXPID5GL01,
1454 + SSB_SPROM4_TXPID5GL1, SSB_SPROM4_TXPID5GL1_SHIFT);
1455 + SPEX(txpid5gl[2], SSB_SPROM4_TXPID5GL23,
1456 + SSB_SPROM4_TXPID5GL2, SSB_SPROM4_TXPID5GL2_SHIFT);
1457 + SPEX(txpid5gl[3], SSB_SPROM4_TXPID5GL23,
1458 + SSB_SPROM4_TXPID5GL3, SSB_SPROM4_TXPID5GL3_SHIFT);
1460 + SPEX(txpid5g[0], SSB_SPROM4_TXPID5G01,
1461 + SSB_SPROM4_TXPID5G0, SSB_SPROM4_TXPID5G0_SHIFT);
1462 + SPEX(txpid5g[1], SSB_SPROM4_TXPID5G01,
1463 + SSB_SPROM4_TXPID5G1, SSB_SPROM4_TXPID5G1_SHIFT);
1464 + SPEX(txpid5g[2], SSB_SPROM4_TXPID5G23,
1465 + SSB_SPROM4_TXPID5G2, SSB_SPROM4_TXPID5G2_SHIFT);
1466 + SPEX(txpid5g[3], SSB_SPROM4_TXPID5G23,
1467 + SSB_SPROM4_TXPID5G3, SSB_SPROM4_TXPID5G3_SHIFT);
1469 + SPEX(txpid5gh[0], SSB_SPROM4_TXPID5GH01,
1470 + SSB_SPROM4_TXPID5GH0, SSB_SPROM4_TXPID5GH0_SHIFT);
1471 + SPEX(txpid5gh[1], SSB_SPROM4_TXPID5GH01,
1472 + SSB_SPROM4_TXPID5GH1, SSB_SPROM4_TXPID5GH1_SHIFT);
1473 + SPEX(txpid5gh[2], SSB_SPROM4_TXPID5GH23,
1474 + SSB_SPROM4_TXPID5GH2, SSB_SPROM4_TXPID5GH2_SHIFT);
1475 + SPEX(txpid5gh[3], SSB_SPROM4_TXPID5GH23,
1476 + SSB_SPROM4_TXPID5GH3, SSB_SPROM4_TXPID5GH3_SHIFT);
1479 static void sprom_extract_r45(struct ssb_sprom *out, const u16 *in)
1480 @@ -427,10 +459,14 @@ static void sprom_extract_r45(struct ssb
1481 SPEX(country_code, SSB_SPROM4_CCODE, 0xFFFF, 0);
1482 SPEX(boardflags_lo, SSB_SPROM4_BFLLO, 0xFFFF, 0);
1483 SPEX(boardflags_hi, SSB_SPROM4_BFLHI, 0xFFFF, 0);
1484 + SPEX(boardflags2_lo, SSB_SPROM4_BFL2LO, 0xFFFF, 0);
1485 + SPEX(boardflags2_hi, SSB_SPROM4_BFL2HI, 0xFFFF, 0);
1487 SPEX(country_code, SSB_SPROM5_CCODE, 0xFFFF, 0);
1488 SPEX(boardflags_lo, SSB_SPROM5_BFLLO, 0xFFFF, 0);
1489 SPEX(boardflags_hi, SSB_SPROM5_BFLHI, 0xFFFF, 0);
1490 + SPEX(boardflags2_lo, SSB_SPROM5_BFL2LO, 0xFFFF, 0);
1491 + SPEX(boardflags2_hi, SSB_SPROM5_BFL2HI, 0xFFFF, 0);
1493 SPEX(ant_available_a, SSB_SPROM4_ANTAVAIL, SSB_SPROM4_ANTAVAIL_A,
1494 SSB_SPROM4_ANTAVAIL_A_SHIFT);
1495 @@ -459,16 +495,16 @@ static void sprom_extract_r45(struct ssb
1498 /* Extract the antenna gain values. */
1499 - SPEX(antenna_gain.ghz24.a0, SSB_SPROM4_AGAIN01,
1500 + SPEX(antenna_gain.a0, SSB_SPROM4_AGAIN01,
1501 SSB_SPROM4_AGAIN0, SSB_SPROM4_AGAIN0_SHIFT);
1502 - SPEX(antenna_gain.ghz24.a1, SSB_SPROM4_AGAIN01,
1503 + SPEX(antenna_gain.a1, SSB_SPROM4_AGAIN01,
1504 SSB_SPROM4_AGAIN1, SSB_SPROM4_AGAIN1_SHIFT);
1505 - SPEX(antenna_gain.ghz24.a2, SSB_SPROM4_AGAIN23,
1506 + SPEX(antenna_gain.a2, SSB_SPROM4_AGAIN23,
1507 SSB_SPROM4_AGAIN2, SSB_SPROM4_AGAIN2_SHIFT);
1508 - SPEX(antenna_gain.ghz24.a3, SSB_SPROM4_AGAIN23,
1509 + SPEX(antenna_gain.a3, SSB_SPROM4_AGAIN23,
1510 SSB_SPROM4_AGAIN3, SSB_SPROM4_AGAIN3_SHIFT);
1511 - memcpy(&out->antenna_gain.ghz5, &out->antenna_gain.ghz24,
1512 - sizeof(out->antenna_gain.ghz5));
1514 + sprom_extract_r458(out, in);
1516 /* TODO - get remaining rev 4 stuff needed */
1518 @@ -476,7 +512,13 @@ static void sprom_extract_r45(struct ssb
1519 static void sprom_extract_r8(struct ssb_sprom *out, const u16 *in)
1524 + u16 pwr_info_offset[] = {
1525 + SSB_SROM8_PWR_INFO_CORE0, SSB_SROM8_PWR_INFO_CORE1,
1526 + SSB_SROM8_PWR_INFO_CORE2, SSB_SROM8_PWR_INFO_CORE3
1528 + BUILD_BUG_ON(ARRAY_SIZE(pwr_info_offset) !=
1529 + ARRAY_SIZE(out->core_pwr_info));
1531 /* extract the MAC address */
1532 for (i = 0; i < 3; i++) {
1533 @@ -549,16 +591,71 @@ static void sprom_extract_r8(struct ssb_
1534 SPEX32(ofdm5ghpo, SSB_SPROM8_OFDM5GHPO, 0xFFFFFFFF, 0);
1536 /* Extract the antenna gain values. */
1537 - SPEX(antenna_gain.ghz24.a0, SSB_SPROM8_AGAIN01,
1538 + SPEX(antenna_gain.a0, SSB_SPROM8_AGAIN01,
1539 SSB_SPROM8_AGAIN0, SSB_SPROM8_AGAIN0_SHIFT);
1540 - SPEX(antenna_gain.ghz24.a1, SSB_SPROM8_AGAIN01,
1541 + SPEX(antenna_gain.a1, SSB_SPROM8_AGAIN01,
1542 SSB_SPROM8_AGAIN1, SSB_SPROM8_AGAIN1_SHIFT);
1543 - SPEX(antenna_gain.ghz24.a2, SSB_SPROM8_AGAIN23,
1544 + SPEX(antenna_gain.a2, SSB_SPROM8_AGAIN23,
1545 SSB_SPROM8_AGAIN2, SSB_SPROM8_AGAIN2_SHIFT);
1546 - SPEX(antenna_gain.ghz24.a3, SSB_SPROM8_AGAIN23,
1547 + SPEX(antenna_gain.a3, SSB_SPROM8_AGAIN23,
1548 SSB_SPROM8_AGAIN3, SSB_SPROM8_AGAIN3_SHIFT);
1549 - memcpy(&out->antenna_gain.ghz5, &out->antenna_gain.ghz24,
1550 - sizeof(out->antenna_gain.ghz5));
1552 + /* Extract cores power info info */
1553 + for (i = 0; i < ARRAY_SIZE(pwr_info_offset); i++) {
1554 + o = pwr_info_offset[i];
1555 + SPEX(core_pwr_info[i].itssi_2g, o + SSB_SROM8_2G_MAXP_ITSSI,
1556 + SSB_SPROM8_2G_ITSSI, SSB_SPROM8_2G_ITSSI_SHIFT);
1557 + SPEX(core_pwr_info[i].maxpwr_2g, o + SSB_SROM8_2G_MAXP_ITSSI,
1558 + SSB_SPROM8_2G_MAXP, 0);
1560 + SPEX(core_pwr_info[i].pa_2g[0], o + SSB_SROM8_2G_PA_0, ~0, 0);
1561 + SPEX(core_pwr_info[i].pa_2g[1], o + SSB_SROM8_2G_PA_1, ~0, 0);
1562 + SPEX(core_pwr_info[i].pa_2g[2], o + SSB_SROM8_2G_PA_2, ~0, 0);
1564 + SPEX(core_pwr_info[i].itssi_5g, o + SSB_SROM8_5G_MAXP_ITSSI,
1565 + SSB_SPROM8_5G_ITSSI, SSB_SPROM8_5G_ITSSI_SHIFT);
1566 + SPEX(core_pwr_info[i].maxpwr_5g, o + SSB_SROM8_5G_MAXP_ITSSI,
1567 + SSB_SPROM8_5G_MAXP, 0);
1568 + SPEX(core_pwr_info[i].maxpwr_5gh, o + SSB_SPROM8_5GHL_MAXP,
1569 + SSB_SPROM8_5GH_MAXP, 0);
1570 + SPEX(core_pwr_info[i].maxpwr_5gl, o + SSB_SPROM8_5GHL_MAXP,
1571 + SSB_SPROM8_5GL_MAXP, SSB_SPROM8_5GL_MAXP_SHIFT);
1573 + SPEX(core_pwr_info[i].pa_5gl[0], o + SSB_SROM8_5GL_PA_0, ~0, 0);
1574 + SPEX(core_pwr_info[i].pa_5gl[1], o + SSB_SROM8_5GL_PA_1, ~0, 0);
1575 + SPEX(core_pwr_info[i].pa_5gl[2], o + SSB_SROM8_5GL_PA_2, ~0, 0);
1576 + SPEX(core_pwr_info[i].pa_5g[0], o + SSB_SROM8_5G_PA_0, ~0, 0);
1577 + SPEX(core_pwr_info[i].pa_5g[1], o + SSB_SROM8_5G_PA_1, ~0, 0);
1578 + SPEX(core_pwr_info[i].pa_5g[2], o + SSB_SROM8_5G_PA_2, ~0, 0);
1579 + SPEX(core_pwr_info[i].pa_5gh[0], o + SSB_SROM8_5GH_PA_0, ~0, 0);
1580 + SPEX(core_pwr_info[i].pa_5gh[1], o + SSB_SROM8_5GH_PA_1, ~0, 0);
1581 + SPEX(core_pwr_info[i].pa_5gh[2], o + SSB_SROM8_5GH_PA_2, ~0, 0);
1584 + /* Extract FEM info */
1585 + SPEX(fem.ghz2.tssipos, SSB_SPROM8_FEM2G,
1586 + SSB_SROM8_FEM_TSSIPOS, SSB_SROM8_FEM_TSSIPOS_SHIFT);
1587 + SPEX(fem.ghz2.extpa_gain, SSB_SPROM8_FEM2G,
1588 + SSB_SROM8_FEM_EXTPA_GAIN, SSB_SROM8_FEM_EXTPA_GAIN_SHIFT);
1589 + SPEX(fem.ghz2.pdet_range, SSB_SPROM8_FEM2G,
1590 + SSB_SROM8_FEM_PDET_RANGE, SSB_SROM8_FEM_PDET_RANGE_SHIFT);
1591 + SPEX(fem.ghz2.tr_iso, SSB_SPROM8_FEM2G,
1592 + SSB_SROM8_FEM_TR_ISO, SSB_SROM8_FEM_TR_ISO_SHIFT);
1593 + SPEX(fem.ghz2.antswlut, SSB_SPROM8_FEM2G,
1594 + SSB_SROM8_FEM_ANTSWLUT, SSB_SROM8_FEM_ANTSWLUT_SHIFT);
1596 + SPEX(fem.ghz5.tssipos, SSB_SPROM8_FEM5G,
1597 + SSB_SROM8_FEM_TSSIPOS, SSB_SROM8_FEM_TSSIPOS_SHIFT);
1598 + SPEX(fem.ghz5.extpa_gain, SSB_SPROM8_FEM5G,
1599 + SSB_SROM8_FEM_EXTPA_GAIN, SSB_SROM8_FEM_EXTPA_GAIN_SHIFT);
1600 + SPEX(fem.ghz5.pdet_range, SSB_SPROM8_FEM5G,
1601 + SSB_SROM8_FEM_PDET_RANGE, SSB_SROM8_FEM_PDET_RANGE_SHIFT);
1602 + SPEX(fem.ghz5.tr_iso, SSB_SPROM8_FEM5G,
1603 + SSB_SROM8_FEM_TR_ISO, SSB_SROM8_FEM_TR_ISO_SHIFT);
1604 + SPEX(fem.ghz5.antswlut, SSB_SPROM8_FEM5G,
1605 + SSB_SROM8_FEM_ANTSWLUT, SSB_SROM8_FEM_ANTSWLUT_SHIFT);
1607 + sprom_extract_r458(out, in);
1609 /* TODO - get remaining rev 8 stuff needed */
1611 @@ -572,37 +669,34 @@ static int sprom_extract(struct ssb_bus
1612 ssb_dprintk(KERN_DEBUG PFX "SPROM revision %d detected.\n", out->revision);
1613 memset(out->et0mac, 0xFF, 6); /* preset et0 and et1 mac */
1614 memset(out->et1mac, 0xFF, 6);
1616 if ((bus->chip_id & 0xFF00) == 0x4400) {
1617 /* Workaround: The BCM44XX chip has a stupid revision
1618 * number stored in the SPROM.
1619 * Always extract r1. */
1621 + ssb_dprintk(KERN_DEBUG PFX "SPROM treated as revision %d\n", out->revision);
1624 + switch (out->revision) {
1628 sprom_extract_r123(out, in);
1629 - } else if (bus->chip_id == 0x4321) {
1630 - /* the BCM4328 has a chipid == 0x4321 and a rev 4 SPROM */
1631 - out->revision = 4;
1635 sprom_extract_r45(out, in);
1637 - switch (out->revision) {
1641 - sprom_extract_r123(out, in);
1645 - sprom_extract_r45(out, in);
1648 - sprom_extract_r8(out, in);
1651 - ssb_printk(KERN_WARNING PFX "Unsupported SPROM"
1652 - " revision %d detected. Will extract"
1653 - " v1\n", out->revision);
1654 - out->revision = 1;
1655 - sprom_extract_r123(out, in);
1659 + sprom_extract_r8(out, in);
1662 + ssb_printk(KERN_WARNING PFX "Unsupported SPROM"
1663 + " revision %d detected. Will extract"
1664 + " v1\n", out->revision);
1665 + out->revision = 1;
1666 + sprom_extract_r123(out, in);
1669 if (out->boardflags_lo == 0xFFFF)
1670 @@ -616,15 +710,14 @@ static int sprom_extract(struct ssb_bus
1671 static int ssb_pci_sprom_get(struct ssb_bus *bus,
1672 struct ssb_sprom *sprom)
1674 - const struct ssb_sprom *fallback;
1675 - int err = -ENOMEM;
1679 if (!ssb_is_sprom_available(bus)) {
1680 ssb_printk(KERN_ERR PFX "No SPROM available!\n");
1683 - if (bus->chipco.dev) { /* can be unavailible! */
1684 + if (bus->chipco.dev) { /* can be unavailable! */
1686 * get SPROM offset: SSB_SPROM_BASE1 except for
1687 * chipcommon rev >= 31 or chip ID is 0x4312 and
1688 @@ -644,7 +737,7 @@ static int ssb_pci_sprom_get(struct ssb_
1690 buf = kcalloc(SSB_SPROMSIZE_WORDS_R123, sizeof(u16), GFP_KERNEL);
1694 bus->sprom_size = SSB_SPROMSIZE_WORDS_R123;
1695 sprom_do_read(bus, buf);
1696 err = sprom_check_crc(buf, bus->sprom_size);
1697 @@ -654,17 +747,24 @@ static int ssb_pci_sprom_get(struct ssb_
1698 buf = kcalloc(SSB_SPROMSIZE_WORDS_R4, sizeof(u16),
1703 bus->sprom_size = SSB_SPROMSIZE_WORDS_R4;
1704 sprom_do_read(bus, buf);
1705 err = sprom_check_crc(buf, bus->sprom_size);
1707 /* All CRC attempts failed.
1708 * Maybe there is no SPROM on the device?
1709 - * If we have a fallback, use that. */
1710 - fallback = ssb_get_fallback_sprom();
1712 - memcpy(sprom, fallback, sizeof(*sprom));
1713 + * Now we ask the arch code if there is some sprom
1714 + * available for this device in some other storage */
1715 + err = ssb_fill_sprom_with_fallback(bus, sprom);
1717 + ssb_printk(KERN_WARNING PFX "WARNING: Using"
1718 + " fallback SPROM failed (err %d)\n",
1721 + ssb_dprintk(KERN_DEBUG PFX "Using SPROM"
1722 + " revision %d provided by"
1723 + " platform.\n", sprom->revision);
1727 @@ -676,19 +776,15 @@ static int ssb_pci_sprom_get(struct ssb_
1735 static void ssb_pci_get_boardinfo(struct ssb_bus *bus,
1736 struct ssb_boardinfo *bi)
1738 - pci_read_config_word(bus->host_pci, PCI_SUBSYSTEM_VENDOR_ID,
1740 - pci_read_config_word(bus->host_pci, PCI_SUBSYSTEM_ID,
1742 - pci_read_config_word(bus->host_pci, PCI_REVISION_ID,
1744 + bi->vendor = bus->host_pci->subsystem_vendor;
1745 + bi->type = bus->host_pci->subsystem_device;
1746 + bi->rev = bus->host_pci->revision;
1749 int ssb_pci_get_invariants(struct ssb_bus *bus,
1750 --- a/drivers/ssb/pcihost_wrapper.c
1751 +++ b/drivers/ssb/pcihost_wrapper.c
1753 * Copyright (c) 2005 Stefano Brivio <st3@riseup.net>
1754 * Copyright (c) 2005 Danny van Dyk <kugelfang@gentoo.org>
1755 * Copyright (c) 2005 Andreas Jaggi <andreas.jaggi@waterwave.ch>
1756 - * Copyright (c) 2005-2007 Michael Buesch <mbuesch@freenet.de>
1757 + * Copyright (c) 2005-2007 Michael Buesch <m@bues.ch>
1759 * Licensed under the GNU/GPL. See COPYING for details.
1762 #include <linux/pci.h>
1763 +#include <linux/slab.h>
1764 #include <linux/ssb/ssb.h>
1767 @@ -52,12 +53,13 @@ static int ssb_pcihost_resume(struct pci
1768 # define ssb_pcihost_resume NULL
1769 #endif /* CONFIG_PM */
1771 -static int ssb_pcihost_probe(struct pci_dev *dev,
1772 - const struct pci_device_id *id)
1773 +static int __devinit ssb_pcihost_probe(struct pci_dev *dev,
1774 + const struct pci_device_id *id)
1776 struct ssb_bus *ssb;
1781 ssb = kzalloc(sizeof(*ssb), GFP_KERNEL);
1783 @@ -73,6 +75,12 @@ static int ssb_pcihost_probe(struct pci_
1784 goto err_pci_disable;
1785 pci_set_master(dev);
1787 + /* Disable the RETRY_TIMEOUT register (0x41) to keep
1788 + * PCI Tx retries from interfering with C3 CPU state */
1789 + pci_read_config_dword(dev, 0x40, &val);
1790 + if ((val & 0x0000ff00) != 0)
1791 + pci_write_config_dword(dev, 0x40, val & 0xffff00ff);
1793 err = ssb_bus_pcibus_register(ssb, dev);
1795 goto err_pci_release_regions;
1796 @@ -102,7 +110,7 @@ static void ssb_pcihost_remove(struct pc
1797 pci_set_drvdata(dev, NULL);
1800 -int ssb_pcihost_register(struct pci_driver *driver)
1801 +int __devinit ssb_pcihost_register(struct pci_driver *driver)
1803 driver->probe = ssb_pcihost_probe;
1804 driver->remove = ssb_pcihost_remove;
1805 --- a/drivers/ssb/pcmcia.c
1806 +++ b/drivers/ssb/pcmcia.c
1808 * PCMCIA-Hostbus related functions
1810 * Copyright 2006 Johannes Berg <johannes@sipsolutions.net>
1811 - * Copyright 2007-2008 Michael Buesch <mb@bu3sch.de>
1812 + * Copyright 2007-2008 Michael Buesch <m@bues.ch>
1814 * Licensed under the GNU/GPL. See COPYING for details.
1816 @@ -617,136 +617,136 @@ static int ssb_pcmcia_sprom_check_crc(co
1820 -int ssb_pcmcia_get_invariants(struct ssb_bus *bus,
1821 - struct ssb_init_invariants *iv)
1822 +static int ssb_pcmcia_get_mac(struct pcmcia_device *p_dev,
1826 + struct ssb_sprom *sprom = priv;
1828 + if (tuple->TupleData[0] != CISTPL_FUNCE_LAN_NODE_ID)
1830 + if (tuple->TupleDataLen != ETH_ALEN + 2)
1832 + if (tuple->TupleData[1] != ETH_ALEN)
1834 + memcpy(sprom->il0mac, &tuple->TupleData[2], ETH_ALEN);
1838 +static int ssb_pcmcia_do_get_invariants(struct pcmcia_device *p_dev,
1844 - unsigned char buf[32];
1845 + struct ssb_init_invariants *iv = priv;
1846 struct ssb_sprom *sprom = &iv->sprom;
1847 struct ssb_boardinfo *bi = &iv->boardinfo;
1848 const char *error_description;
1850 + GOTO_ERROR_ON(tuple->TupleDataLen < 1, "VEN tpl < 1");
1851 + switch (tuple->TupleData[0]) {
1852 + case SSB_PCMCIA_CIS_ID:
1853 + GOTO_ERROR_ON((tuple->TupleDataLen != 5) &&
1854 + (tuple->TupleDataLen != 7),
1856 + bi->vendor = tuple->TupleData[1] |
1857 + ((u16)tuple->TupleData[2] << 8);
1859 + case SSB_PCMCIA_CIS_BOARDREV:
1860 + GOTO_ERROR_ON(tuple->TupleDataLen != 2,
1861 + "boardrev tpl size");
1862 + sprom->board_rev = tuple->TupleData[1];
1864 + case SSB_PCMCIA_CIS_PA:
1865 + GOTO_ERROR_ON((tuple->TupleDataLen != 9) &&
1866 + (tuple->TupleDataLen != 10),
1868 + sprom->pa0b0 = tuple->TupleData[1] |
1869 + ((u16)tuple->TupleData[2] << 8);
1870 + sprom->pa0b1 = tuple->TupleData[3] |
1871 + ((u16)tuple->TupleData[4] << 8);
1872 + sprom->pa0b2 = tuple->TupleData[5] |
1873 + ((u16)tuple->TupleData[6] << 8);
1874 + sprom->itssi_a = tuple->TupleData[7];
1875 + sprom->itssi_bg = tuple->TupleData[7];
1876 + sprom->maxpwr_a = tuple->TupleData[8];
1877 + sprom->maxpwr_bg = tuple->TupleData[8];
1879 + case SSB_PCMCIA_CIS_OEMNAME:
1880 + /* We ignore this. */
1882 + case SSB_PCMCIA_CIS_CCODE:
1883 + GOTO_ERROR_ON(tuple->TupleDataLen != 2,
1884 + "ccode tpl size");
1885 + sprom->country_code = tuple->TupleData[1];
1887 + case SSB_PCMCIA_CIS_ANTENNA:
1888 + GOTO_ERROR_ON(tuple->TupleDataLen != 2,
1890 + sprom->ant_available_a = tuple->TupleData[1];
1891 + sprom->ant_available_bg = tuple->TupleData[1];
1893 + case SSB_PCMCIA_CIS_ANTGAIN:
1894 + GOTO_ERROR_ON(tuple->TupleDataLen != 2,
1896 + sprom->antenna_gain.a0 = tuple->TupleData[1];
1897 + sprom->antenna_gain.a1 = tuple->TupleData[1];
1898 + sprom->antenna_gain.a2 = tuple->TupleData[1];
1899 + sprom->antenna_gain.a3 = tuple->TupleData[1];
1901 + case SSB_PCMCIA_CIS_BFLAGS:
1902 + GOTO_ERROR_ON((tuple->TupleDataLen != 3) &&
1903 + (tuple->TupleDataLen != 5),
1905 + sprom->boardflags_lo = tuple->TupleData[1] |
1906 + ((u16)tuple->TupleData[2] << 8);
1908 + case SSB_PCMCIA_CIS_LEDS:
1909 + GOTO_ERROR_ON(tuple->TupleDataLen != 5,
1911 + sprom->gpio0 = tuple->TupleData[1];
1912 + sprom->gpio1 = tuple->TupleData[2];
1913 + sprom->gpio2 = tuple->TupleData[3];
1914 + sprom->gpio3 = tuple->TupleData[4];
1917 + return -ENOSPC; /* continue with next entry */
1920 + ssb_printk(KERN_ERR PFX
1921 + "PCMCIA: Failed to fetch device invariants: %s\n",
1922 + error_description);
1927 +int ssb_pcmcia_get_invariants(struct ssb_bus *bus,
1928 + struct ssb_init_invariants *iv)
1930 + struct ssb_sprom *sprom = &iv->sprom;
1933 memset(sprom, 0xFF, sizeof(*sprom));
1934 sprom->revision = 1;
1935 sprom->boardflags_lo = 0;
1936 sprom->boardflags_hi = 0;
1938 /* First fetch the MAC address. */
1939 - memset(&tuple, 0, sizeof(tuple));
1940 - tuple.DesiredTuple = CISTPL_FUNCE;
1941 - tuple.TupleData = buf;
1942 - tuple.TupleDataMax = sizeof(buf);
1943 - res = pcmcia_get_first_tuple(bus->host_pcmcia, &tuple);
1944 - GOTO_ERROR_ON(res != 0, "MAC first tpl");
1945 - res = pcmcia_get_tuple_data(bus->host_pcmcia, &tuple);
1946 - GOTO_ERROR_ON(res != 0, "MAC first tpl data");
1948 - GOTO_ERROR_ON(tuple.TupleDataLen < 1, "MAC tpl < 1");
1949 - if (tuple.TupleData[0] == CISTPL_FUNCE_LAN_NODE_ID)
1951 - res = pcmcia_get_next_tuple(bus->host_pcmcia, &tuple);
1952 - GOTO_ERROR_ON(res != 0, "MAC next tpl");
1953 - res = pcmcia_get_tuple_data(bus->host_pcmcia, &tuple);
1954 - GOTO_ERROR_ON(res != 0, "MAC next tpl data");
1955 + res = pcmcia_loop_tuple(bus->host_pcmcia, CISTPL_FUNCE,
1956 + ssb_pcmcia_get_mac, sprom);
1958 + ssb_printk(KERN_ERR PFX
1959 + "PCMCIA: Failed to fetch MAC address\n");
1962 - GOTO_ERROR_ON(tuple.TupleDataLen != ETH_ALEN + 2, "MAC tpl size");
1963 - memcpy(sprom->il0mac, &tuple.TupleData[2], ETH_ALEN);
1965 /* Fetch the vendor specific tuples. */
1966 - memset(&tuple, 0, sizeof(tuple));
1967 - tuple.DesiredTuple = SSB_PCMCIA_CIS;
1968 - tuple.TupleData = buf;
1969 - tuple.TupleDataMax = sizeof(buf);
1970 - res = pcmcia_get_first_tuple(bus->host_pcmcia, &tuple);
1971 - GOTO_ERROR_ON(res != 0, "VEN first tpl");
1972 - res = pcmcia_get_tuple_data(bus->host_pcmcia, &tuple);
1973 - GOTO_ERROR_ON(res != 0, "VEN first tpl data");
1975 - GOTO_ERROR_ON(tuple.TupleDataLen < 1, "VEN tpl < 1");
1976 - switch (tuple.TupleData[0]) {
1977 - case SSB_PCMCIA_CIS_ID:
1978 - GOTO_ERROR_ON((tuple.TupleDataLen != 5) &&
1979 - (tuple.TupleDataLen != 7),
1981 - bi->vendor = tuple.TupleData[1] |
1982 - ((u16)tuple.TupleData[2] << 8);
1984 - case SSB_PCMCIA_CIS_BOARDREV:
1985 - GOTO_ERROR_ON(tuple.TupleDataLen != 2,
1986 - "boardrev tpl size");
1987 - sprom->board_rev = tuple.TupleData[1];
1989 - case SSB_PCMCIA_CIS_PA:
1990 - GOTO_ERROR_ON((tuple.TupleDataLen != 9) &&
1991 - (tuple.TupleDataLen != 10),
1993 - sprom->pa0b0 = tuple.TupleData[1] |
1994 - ((u16)tuple.TupleData[2] << 8);
1995 - sprom->pa0b1 = tuple.TupleData[3] |
1996 - ((u16)tuple.TupleData[4] << 8);
1997 - sprom->pa0b2 = tuple.TupleData[5] |
1998 - ((u16)tuple.TupleData[6] << 8);
1999 - sprom->itssi_a = tuple.TupleData[7];
2000 - sprom->itssi_bg = tuple.TupleData[7];
2001 - sprom->maxpwr_a = tuple.TupleData[8];
2002 - sprom->maxpwr_bg = tuple.TupleData[8];
2004 - case SSB_PCMCIA_CIS_OEMNAME:
2005 - /* We ignore this. */
2007 - case SSB_PCMCIA_CIS_CCODE:
2008 - GOTO_ERROR_ON(tuple.TupleDataLen != 2,
2009 - "ccode tpl size");
2010 - sprom->country_code = tuple.TupleData[1];
2012 - case SSB_PCMCIA_CIS_ANTENNA:
2013 - GOTO_ERROR_ON(tuple.TupleDataLen != 2,
2015 - sprom->ant_available_a = tuple.TupleData[1];
2016 - sprom->ant_available_bg = tuple.TupleData[1];
2018 - case SSB_PCMCIA_CIS_ANTGAIN:
2019 - GOTO_ERROR_ON(tuple.TupleDataLen != 2,
2021 - sprom->antenna_gain.ghz24.a0 = tuple.TupleData[1];
2022 - sprom->antenna_gain.ghz24.a1 = tuple.TupleData[1];
2023 - sprom->antenna_gain.ghz24.a2 = tuple.TupleData[1];
2024 - sprom->antenna_gain.ghz24.a3 = tuple.TupleData[1];
2025 - sprom->antenna_gain.ghz5.a0 = tuple.TupleData[1];
2026 - sprom->antenna_gain.ghz5.a1 = tuple.TupleData[1];
2027 - sprom->antenna_gain.ghz5.a2 = tuple.TupleData[1];
2028 - sprom->antenna_gain.ghz5.a3 = tuple.TupleData[1];
2030 - case SSB_PCMCIA_CIS_BFLAGS:
2031 - GOTO_ERROR_ON((tuple.TupleDataLen != 3) &&
2032 - (tuple.TupleDataLen != 5),
2034 - sprom->boardflags_lo = tuple.TupleData[1] |
2035 - ((u16)tuple.TupleData[2] << 8);
2037 - case SSB_PCMCIA_CIS_LEDS:
2038 - GOTO_ERROR_ON(tuple.TupleDataLen != 5,
2040 - sprom->gpio0 = tuple.TupleData[1];
2041 - sprom->gpio1 = tuple.TupleData[2];
2042 - sprom->gpio2 = tuple.TupleData[3];
2043 - sprom->gpio3 = tuple.TupleData[4];
2046 - res = pcmcia_get_next_tuple(bus->host_pcmcia, &tuple);
2047 - if (res == -ENOSPC)
2049 - GOTO_ERROR_ON(res != 0, "VEN next tpl");
2050 - res = pcmcia_get_tuple_data(bus->host_pcmcia, &tuple);
2051 - GOTO_ERROR_ON(res != 0, "VEN next tpl data");
2053 + res = pcmcia_loop_tuple(bus->host_pcmcia, SSB_PCMCIA_CIS,
2054 + ssb_pcmcia_do_get_invariants, iv);
2055 + if ((res == 0) || (res == -ENOSPC))
2060 ssb_printk(KERN_ERR PFX
2061 - "PCMCIA: Failed to fetch device invariants: %s\n",
2062 - error_description);
2063 + "PCMCIA: Failed to fetch device invariants\n");
2067 --- a/drivers/ssb/scan.c
2068 +++ b/drivers/ssb/scan.c
2070 * Sonics Silicon Backplane
2073 - * Copyright (C) 2005-2007 Michael Buesch <mb@bu3sch.de>
2074 + * Copyright (C) 2005-2007 Michael Buesch <m@bues.ch>
2075 * Copyright (C) 2005 Martin Langer <martin-langer@gmx.de>
2076 * Copyright (C) 2005 Stefano Brivio <st3@riseup.net>
2077 * Copyright (C) 2005 Danny van Dyk <kugelfang@gentoo.org>
2078 @@ -260,7 +260,10 @@ static int we_support_multiple_80211_cor
2079 #ifdef CONFIG_SSB_PCIHOST
2080 if (bus->bustype == SSB_BUSTYPE_PCI) {
2081 if (bus->host_pci->vendor == PCI_VENDOR_ID_BROADCOM &&
2082 - bus->host_pci->device == 0x4324)
2083 + ((bus->host_pci->device == 0x4313) ||
2084 + (bus->host_pci->device == 0x431A) ||
2085 + (bus->host_pci->device == 0x4321) ||
2086 + (bus->host_pci->device == 0x4324)))
2089 #endif /* CONFIG_SSB_PCIHOST */
2090 @@ -309,8 +312,7 @@ int ssb_bus_scan(struct ssb_bus *bus,
2092 if (bus->bustype == SSB_BUSTYPE_PCI) {
2093 bus->chip_id = pcidev_to_chipid(bus->host_pci);
2094 - pci_read_config_word(bus->host_pci, PCI_REVISION_ID,
2096 + bus->chip_rev = bus->host_pci->revision;
2097 bus->chip_package = 0;
2099 bus->chip_id = 0x4710;
2100 @@ -318,6 +320,9 @@ int ssb_bus_scan(struct ssb_bus *bus,
2101 bus->chip_package = 0;
2104 + ssb_printk(KERN_INFO PFX "Found chip with id 0x%04X, rev 0x%02X and "
2105 + "package 0x%02X\n", bus->chip_id, bus->chip_rev,
2106 + bus->chip_package);
2107 if (!bus->nr_devices)
2108 bus->nr_devices = chipid_to_nrcores(bus->chip_id);
2109 if (bus->nr_devices > ARRAY_SIZE(bus->devices)) {
2110 @@ -354,7 +359,7 @@ int ssb_bus_scan(struct ssb_bus *bus,
2112 dev->ops = bus->ops;
2114 - ssb_dprintk(KERN_INFO PFX
2115 + printk(KERN_DEBUG PFX
2116 "Core %d found: %s "
2117 "(cc 0x%03X, rev 0x%02X, vendor 0x%04X)\n",
2118 i, ssb_core_name(dev->id.coreid),
2119 @@ -422,6 +427,16 @@ int ssb_bus_scan(struct ssb_bus *bus,
2120 bus->pcicore.dev = dev;
2121 #endif /* CONFIG_SSB_DRIVER_PCICORE */
2123 + case SSB_DEV_ETHERNET:
2124 + if (bus->bustype == SSB_BUSTYPE_PCI) {
2125 + if (bus->host_pci->vendor == PCI_VENDOR_ID_BROADCOM &&
2126 + (bus->host_pci->device & 0xFF00) == 0x4300) {
2127 + /* This is a dangling ethernet core on a
2128 + * wireless device. Ignore it. */
2136 --- a/drivers/ssb/sprom.c
2137 +++ b/drivers/ssb/sprom.c
2139 * Sonics Silicon Backplane
2140 * Common SPROM support routines
2142 - * Copyright (C) 2005-2008 Michael Buesch <mb@bu3sch.de>
2143 + * Copyright (C) 2005-2008 Michael Buesch <m@bues.ch>
2144 * Copyright (C) 2005 Martin Langer <martin-langer@gmx.de>
2145 * Copyright (C) 2005 Stefano Brivio <st3@riseup.net>
2146 * Copyright (C) 2005 Danny van Dyk <kugelfang@gentoo.org>
2148 #include "ssb_private.h"
2150 #include <linux/ctype.h>
2151 +#include <linux/slab.h>
2154 -static const struct ssb_sprom *fallback_sprom;
2155 +static int(*get_fallback_sprom)(struct ssb_bus *dev, struct ssb_sprom *out);
2158 static int sprom2hex(const u16 *sprom, char *buf, size_t buf_len,
2159 @@ -102,6 +103,7 @@ ssize_t ssb_attr_sprom_store(struct ssb_
2161 int res = 0, err = -ENOMEM;
2162 size_t sprom_size_words = bus->sprom_size;
2163 + struct ssb_freeze_context freeze;
2165 sprom = kcalloc(bus->sprom_size, sizeof(u16), GFP_KERNEL);
2167 @@ -123,18 +125,13 @@ ssize_t ssb_attr_sprom_store(struct ssb_
2169 if (mutex_lock_interruptible(&bus->sprom_mutex))
2171 - err = ssb_devices_freeze(bus);
2172 - if (err == -EOPNOTSUPP) {
2173 - ssb_printk(KERN_ERR PFX "SPROM write: Could not freeze devices. "
2174 - "No suspend support. Is CONFIG_PM enabled?\n");
2177 + err = ssb_devices_freeze(bus, &freeze);
2179 ssb_printk(KERN_ERR PFX "SPROM write: Could not freeze all devices\n");
2182 res = sprom_write(bus, sprom);
2183 - err = ssb_devices_thaw(bus);
2184 + err = ssb_devices_thaw(&freeze);
2186 ssb_printk(KERN_ERR PFX "SPROM write: Could not thaw all devices\n");
2188 @@ -148,36 +145,43 @@ out:
2192 - * ssb_arch_set_fallback_sprom - Set a fallback SPROM for use if no SPROM is found.
2194 - * @sprom: The SPROM data structure to register.
2195 + * ssb_arch_register_fallback_sprom - Registers a method providing a
2196 + * fallback SPROM if no SPROM is found.
2198 - * With this function the architecture implementation may register a fallback
2199 - * SPROM data structure. The fallback is only used for PCI based SSB devices,
2200 - * where no valid SPROM can be found in the shadow registers.
2201 + * @sprom_callback: The callback function.
2203 - * This function is useful for weird architectures that have a half-assed SSB device
2204 - * hardwired to their PCI bus.
2205 + * With this function the architecture implementation may register a
2206 + * callback handler which fills the SPROM data structure. The fallback is
2207 + * only used for PCI based SSB devices, where no valid SPROM can be found
2208 + * in the shadow registers.
2210 + * This function is useful for weird architectures that have a half-assed
2211 + * SSB device hardwired to their PCI bus.
2213 + * Note that it does only work with PCI attached SSB devices. PCMCIA
2214 + * devices currently don't use this fallback.
2215 + * Architectures must provide the SPROM for native SSB devices anyway, so
2216 + * the fallback also isn't used for native devices.
2218 - * Note that it does only work with PCI attached SSB devices. PCMCIA devices currently
2219 - * don't use this fallback.
2220 - * Architectures must provide the SPROM for native SSB devices anyway,
2221 - * so the fallback also isn't used for native devices.
2223 - * This function is available for architecture code, only. So it is not exported.
2224 + * This function is available for architecture code, only. So it is not
2227 -int ssb_arch_set_fallback_sprom(const struct ssb_sprom *sprom)
2228 +int ssb_arch_register_fallback_sprom(int (*sprom_callback)(struct ssb_bus *bus,
2229 + struct ssb_sprom *out))
2231 - if (fallback_sprom)
2232 + if (get_fallback_sprom)
2234 - fallback_sprom = sprom;
2235 + get_fallback_sprom = sprom_callback;
2240 -const struct ssb_sprom *ssb_get_fallback_sprom(void)
2241 +int ssb_fill_sprom_with_fallback(struct ssb_bus *bus, struct ssb_sprom *out)
2243 - return fallback_sprom;
2244 + if (!get_fallback_sprom)
2247 + return get_fallback_sprom(bus, out);
2250 /* http://bcm-v4.sipsolutions.net/802.11/IsSpromAvailable */
2251 @@ -188,7 +192,7 @@ bool ssb_is_sprom_available(struct ssb_b
2252 /* this routine differs from specs as we do not access SPROM directly
2254 if (bus->bustype == SSB_BUSTYPE_PCI &&
2255 - bus->chipco.dev && /* can be unavailible! */
2256 + bus->chipco.dev && /* can be unavailable! */
2257 bus->chipco.dev->id.revision >= 31)
2258 return bus->chipco.capabilities & SSB_CHIPCO_CAP_SPROM;
2260 --- a/drivers/ssb/ssb_private.h
2261 +++ b/drivers/ssb/ssb_private.h
2262 @@ -171,24 +171,33 @@ ssize_t ssb_attr_sprom_store(struct ssb_
2263 const char *buf, size_t count,
2264 int (*sprom_check_crc)(const u16 *sprom, size_t size),
2265 int (*sprom_write)(struct ssb_bus *bus, const u16 *sprom));
2266 -extern const struct ssb_sprom *ssb_get_fallback_sprom(void);
2267 +extern int ssb_fill_sprom_with_fallback(struct ssb_bus *bus,
2268 + struct ssb_sprom *out);
2272 extern u32 ssb_calc_clock_rate(u32 plltype, u32 n, u32 m);
2273 -extern int ssb_devices_freeze(struct ssb_bus *bus);
2274 -extern int ssb_devices_thaw(struct ssb_bus *bus);
2275 extern struct ssb_bus *ssb_pci_dev_to_bus(struct pci_dev *pdev);
2276 int ssb_for_each_bus_call(unsigned long data,
2277 int (*func)(struct ssb_bus *bus, unsigned long data));
2278 extern struct ssb_bus *ssb_pcmcia_dev_to_bus(struct pcmcia_device *pdev);
2280 +struct ssb_freeze_context {
2281 + /* Pointer to the bus */
2282 + struct ssb_bus *bus;
2283 + /* Boolean list to indicate whether a device is frozen on this bus. */
2284 + bool device_frozen[SSB_MAX_NR_CORES];
2286 +extern int ssb_devices_freeze(struct ssb_bus *bus, struct ssb_freeze_context *ctx);
2287 +extern int ssb_devices_thaw(struct ssb_freeze_context *ctx);
2291 /* b43_pci_bridge.c */
2292 #ifdef CONFIG_SSB_B43_PCI_BRIDGE
2293 extern int __init b43_pci_ssb_bridge_init(void);
2294 extern void __exit b43_pci_ssb_bridge_exit(void);
2295 -#else /* CONFIG_SSB_B43_PCI_BRIDGR */
2296 +#else /* CONFIG_SSB_B43_PCI_BRIDGE */
2297 static inline int b43_pci_ssb_bridge_init(void)
2300 @@ -196,6 +205,10 @@ static inline int b43_pci_ssb_bridge_ini
2301 static inline void b43_pci_ssb_bridge_exit(void)
2304 -#endif /* CONFIG_SSB_PCIHOST */
2305 +#endif /* CONFIG_SSB_B43_PCI_BRIDGE */
2307 +/* driver_chipcommon_pmu.c */
2308 +extern u32 ssb_pmu_get_cpu_clock(struct ssb_chipcommon *cc);
2309 +extern u32 ssb_pmu_get_controlclock(struct ssb_chipcommon *cc);
2311 #endif /* LINUX_SSB_PRIVATE_H_ */
2312 --- a/include/linux/ssb/ssb.h
2313 +++ b/include/linux/ssb/ssb.h
2314 @@ -16,6 +16,12 @@ struct pcmcia_device;
2318 +struct ssb_sprom_core_pwr_info {
2319 + u8 itssi_2g, itssi_5g;
2320 + u8 maxpwr_2g, maxpwr_5gl, maxpwr_5g, maxpwr_5gh;
2321 + u16 pa_2g[4], pa_5gl[4], pa_5g[4], pa_5gh[4];
2326 u8 il0mac[6]; /* MAC address for 802.11b/g */
2327 @@ -25,8 +31,13 @@ struct ssb_sprom {
2328 u8 et1phyaddr; /* MII address for enet1 */
2329 u8 et0mdcport; /* MDIO for enet0 */
2330 u8 et1mdcport; /* MDIO for enet1 */
2331 - u8 board_rev; /* Board revision number from SPROM. */
2332 + u16 board_rev; /* Board revision number from SPROM. */
2333 + u16 board_num; /* Board number from SPROM. */
2334 + u16 board_type; /* Board type from SPROM. */
2335 u8 country_code; /* Country Code */
2336 + char alpha2[2]; /* Country Code as two chars like EU or US */
2337 + u8 leddc_on_time; /* LED Powersave Duty Cycle On Count */
2338 + u8 leddc_off_time; /* LED Powersave Duty Cycle Off Count */
2339 u8 ant_available_a; /* 2GHz antenna available bits (up to 4) */
2340 u8 ant_available_bg; /* 5GHz antenna available bits (up to 4) */
2342 @@ -45,18 +56,22 @@ struct ssb_sprom {
2343 u8 gpio1; /* GPIO pin 1 */
2344 u8 gpio2; /* GPIO pin 2 */
2345 u8 gpio3; /* GPIO pin 3 */
2346 - u16 maxpwr_bg; /* 2.4GHz Amplifier Max Power (in dBm Q5.2) */
2347 - u16 maxpwr_al; /* 5.2GHz Amplifier Max Power (in dBm Q5.2) */
2348 - u16 maxpwr_a; /* 5.3GHz Amplifier Max Power (in dBm Q5.2) */
2349 - u16 maxpwr_ah; /* 5.8GHz Amplifier Max Power (in dBm Q5.2) */
2350 + u8 maxpwr_bg; /* 2.4GHz Amplifier Max Power (in dBm Q5.2) */
2351 + u8 maxpwr_al; /* 5.2GHz Amplifier Max Power (in dBm Q5.2) */
2352 + u8 maxpwr_a; /* 5.3GHz Amplifier Max Power (in dBm Q5.2) */
2353 + u8 maxpwr_ah; /* 5.8GHz Amplifier Max Power (in dBm Q5.2) */
2354 u8 itssi_a; /* Idle TSSI Target for A-PHY */
2355 u8 itssi_bg; /* Idle TSSI Target for B/G-PHY */
2356 u8 tri2g; /* 2.4GHz TX isolation */
2357 u8 tri5gl; /* 5.2GHz TX isolation */
2358 u8 tri5g; /* 5.3GHz TX isolation */
2359 u8 tri5gh; /* 5.8GHz TX isolation */
2360 - u8 rxpo2g; /* 2GHz RX power offset */
2361 - u8 rxpo5g; /* 5GHz RX power offset */
2362 + u8 txpid2g[4]; /* 2GHz TX power index */
2363 + u8 txpid5gl[4]; /* 4.9 - 5.1GHz TX power index */
2364 + u8 txpid5g[4]; /* 5.1 - 5.5GHz TX power index */
2365 + u8 txpid5gh[4]; /* 5.5 - ...GHz TX power index */
2366 + s8 rxpo2g; /* 2GHz RX power offset */
2367 + s8 rxpo5g; /* 5GHz RX power offset */
2368 u8 rssisav2g; /* 2GHz RSSI params */
2371 @@ -76,26 +91,104 @@ struct ssb_sprom {
2372 u16 boardflags2_hi; /* Board flags (bits 48-63) */
2373 /* TODO store board flags in a single u64 */
2375 + struct ssb_sprom_core_pwr_info core_pwr_info[4];
2377 /* Antenna gain values for up to 4 antennas
2378 * on each band. Values in dBm/4 (Q5.2). Negative gain means the
2379 * loss in the connectors is bigger than the gain. */
2382 - s8 a0, a1, a2, a3;
2383 - } ghz24; /* 2.4GHz band */
2385 - s8 a0, a1, a2, a3;
2386 - } ghz5; /* 5GHz band */
2387 + s8 a0, a1, a2, a3;
2390 - /* TODO - add any parameters needed from rev 2, 3, 4, 5 or 8 SPROMs */
2393 + u8 tssipos, extpa_gain, pdet_range, tr_iso, antswlut;
2396 + u8 tssipos, extpa_gain, pdet_range, tr_iso, antswlut;
2406 + u8 rxgainerr2ga[3];
2407 + u8 rxgainerr5gla[3];
2408 + u8 rxgainerr5gma[3];
2409 + u8 rxgainerr5gha[3];
2410 + u8 rxgainerr5gua[3];
2412 + u8 noiselvl2ga[3];
2413 + u8 noiselvl5gla[3];
2414 + u8 noiselvl5gma[3];
2415 + u8 noiselvl5gha[3];
2416 + u8 noiselvl5gua[3];
2431 + u8 tempsense_slope;
2433 + u8 tempsense_option;
2434 + u8 freqoffset_corr;
2439 + u8 phycal_tempdelta;
2441 + u8 temps_hysteresis;
2444 + u8 pcieingress_war;
2446 + /* power per rate from sromrev 9 */
2448 + u16 cckbw20ul2gpo;
2449 + u32 legofdmbw202gpo;
2450 + u32 legofdmbw20ul2gpo;
2451 + u32 legofdmbw205glpo;
2452 + u32 legofdmbw20ul5glpo;
2453 + u32 legofdmbw205gmpo;
2454 + u32 legofdmbw20ul5gmpo;
2455 + u32 legofdmbw205ghpo;
2456 + u32 legofdmbw20ul5ghpo;
2458 + u32 mcsbw20ul2gpo;
2461 + u32 mcsbw20ul5glpo;
2464 + u32 mcsbw20ul5gmpo;
2467 + u32 mcsbw20ul5ghpo;
2470 + u16 legofdm40duppo;
2475 /* Information about the PCB the circuitry is soldered on. */
2476 struct ssb_boardinfo {
2484 @@ -167,7 +260,7 @@ struct ssb_device {
2485 * is an optimization. */
2486 const struct ssb_bus_ops *ops;
2488 - struct device *dev;
2489 + struct device *dev, *dma_dev;
2491 struct ssb_bus *bus;
2492 struct ssb_device_id id;
2493 @@ -225,10 +318,9 @@ struct ssb_driver {
2494 #define drv_to_ssb_drv(_drv) container_of(_drv, struct ssb_driver, drv)
2496 extern int __ssb_driver_register(struct ssb_driver *drv, struct module *owner);
2497 -static inline int ssb_driver_register(struct ssb_driver *drv)
2499 - return __ssb_driver_register(drv, THIS_MODULE);
2501 +#define ssb_driver_register(drv) \
2502 + __ssb_driver_register(drv, THIS_MODULE)
2504 extern void ssb_driver_unregister(struct ssb_driver *drv);
2507 @@ -269,7 +361,8 @@ struct ssb_bus {
2509 const struct ssb_bus_ops *ops;
2511 - /* The core in the basic address register window. (PCI bus only) */
2512 + /* The core currently mapped into the MMIO window.
2513 + * Not valid on all host-buses. So don't use outside of SSB. */
2514 struct ssb_device *mapped_device;
2516 /* Currently mapped PCMCIA segment. (bustype == SSB_BUSTYPE_PCMCIA only) */
2517 @@ -281,14 +374,17 @@ struct ssb_bus {
2518 * On PCMCIA-host busses this is used to protect the whole MMIO access. */
2519 spinlock_t bar_lock;
2521 - /* The bus this backplane is running on. */
2522 + /* The host-bus this backplane is running on. */
2523 enum ssb_bustype bustype;
2524 - /* Pointer to the PCI bus (only valid if bustype == SSB_BUSTYPE_PCI). */
2525 - struct pci_dev *host_pci;
2526 - /* Pointer to the PCMCIA device (only if bustype == SSB_BUSTYPE_PCMCIA). */
2527 - struct pcmcia_device *host_pcmcia;
2528 - /* Pointer to the SDIO device (only if bustype == SSB_BUSTYPE_SDIO). */
2529 - struct sdio_func *host_sdio;
2530 + /* Pointers to the host-bus. Check bustype before using any of these pointers. */
2532 + /* Pointer to the PCI bus (only valid if bustype == SSB_BUSTYPE_PCI). */
2533 + struct pci_dev *host_pci;
2534 + /* Pointer to the PCMCIA device (only if bustype == SSB_BUSTYPE_PCMCIA). */
2535 + struct pcmcia_device *host_pcmcia;
2536 + /* Pointer to the SDIO device (only if bustype == SSB_BUSTYPE_SDIO). */
2537 + struct sdio_func *host_sdio;
2540 /* See enum ssb_quirks */
2541 unsigned int quirks;
2542 @@ -300,7 +396,7 @@ struct ssb_bus {
2544 /* ID information about the Chip. */
2549 u16 sprom_size; /* number of words in sprom */
2551 @@ -396,7 +492,9 @@ extern bool ssb_is_sprom_available(struc
2553 /* Set a fallback SPROM.
2554 * See kdoc at the function definition for complete documentation. */
2555 -extern int ssb_arch_set_fallback_sprom(const struct ssb_sprom *sprom);
2556 +extern int ssb_arch_register_fallback_sprom(
2557 + int (*sprom_callback)(struct ssb_bus *bus,
2558 + struct ssb_sprom *out));
2560 /* Suspend a SSB bus.
2561 * Call this from the parent bus suspend routine. */
2562 @@ -667,6 +765,7 @@ extern int ssb_bus_may_powerdown(struct
2563 * Otherwise static always-on powercontrol will be used. */
2564 extern int ssb_bus_powerup(struct ssb_bus *bus, bool dynamic_pctl);
2566 +extern void ssb_commit_settings(struct ssb_bus *bus);
2568 /* Various helper functions */
2569 extern u32 ssb_admatch_base(u32 adm);
2570 --- a/include/linux/ssb/ssb_regs.h
2571 +++ b/include/linux/ssb/ssb_regs.h
2573 #define SSB_IMSTATE_AP_RSV 0x00000030 /* Reserved */
2574 #define SSB_IMSTATE_IBE 0x00020000 /* In Band Error */
2575 #define SSB_IMSTATE_TO 0x00040000 /* Timeout */
2576 +#define SSB_IMSTATE_BUSY 0x01800000 /* Busy (Backplane rev >= 2.3 only) */
2577 +#define SSB_IMSTATE_REJECT 0x02000000 /* Reject (Backplane rev >= 2.3 only) */
2578 #define SSB_INTVEC 0x0F94 /* SB Interrupt Mask */
2579 #define SSB_INTVEC_PCI 0x00000001 /* Enable interrupts for PCI */
2580 #define SSB_INTVEC_ENET0 0x00000002 /* Enable interrupts for enet 0 */
2582 #define SSB_INTVEC_ENET1 0x00000040 /* Enable interrupts for enet 1 */
2583 #define SSB_TMSLOW 0x0F98 /* SB Target State Low */
2584 #define SSB_TMSLOW_RESET 0x00000001 /* Reset */
2585 -#define SSB_TMSLOW_REJECT_22 0x00000002 /* Reject (Backplane rev 2.2) */
2586 +#define SSB_TMSLOW_REJECT 0x00000002 /* Reject (Standard Backplane) */
2587 #define SSB_TMSLOW_REJECT_23 0x00000004 /* Reject (Backplane rev 2.3) */
2588 #define SSB_TMSLOW_CLOCK 0x00010000 /* Clock Enable */
2589 #define SSB_TMSLOW_FGC 0x00020000 /* Force Gated Clocks On */
2590 @@ -172,25 +174,25 @@
2591 #define SSB_SPROMSIZE_BYTES_R4 (SSB_SPROMSIZE_WORDS_R4 * sizeof(u16))
2592 #define SSB_SPROM_BASE1 0x1000
2593 #define SSB_SPROM_BASE31 0x0800
2594 -#define SSB_SPROM_REVISION 0x107E
2595 +#define SSB_SPROM_REVISION 0x007E
2596 #define SSB_SPROM_REVISION_REV 0x00FF /* SPROM Revision number */
2597 #define SSB_SPROM_REVISION_CRC 0xFF00 /* SPROM CRC8 value */
2598 #define SSB_SPROM_REVISION_CRC_SHIFT 8
2600 /* SPROM Revision 1 */
2601 -#define SSB_SPROM1_SPID 0x1004 /* Subsystem Product ID for PCI */
2602 -#define SSB_SPROM1_SVID 0x1006 /* Subsystem Vendor ID for PCI */
2603 -#define SSB_SPROM1_PID 0x1008 /* Product ID for PCI */
2604 -#define SSB_SPROM1_IL0MAC 0x1048 /* 6 bytes MAC address for 802.11b/g */
2605 -#define SSB_SPROM1_ET0MAC 0x104E /* 6 bytes MAC address for Ethernet */
2606 -#define SSB_SPROM1_ET1MAC 0x1054 /* 6 bytes MAC address for 802.11a */
2607 -#define SSB_SPROM1_ETHPHY 0x105A /* Ethernet PHY settings */
2608 +#define SSB_SPROM1_SPID 0x0004 /* Subsystem Product ID for PCI */
2609 +#define SSB_SPROM1_SVID 0x0006 /* Subsystem Vendor ID for PCI */
2610 +#define SSB_SPROM1_PID 0x0008 /* Product ID for PCI */
2611 +#define SSB_SPROM1_IL0MAC 0x0048 /* 6 bytes MAC address for 802.11b/g */
2612 +#define SSB_SPROM1_ET0MAC 0x004E /* 6 bytes MAC address for Ethernet */
2613 +#define SSB_SPROM1_ET1MAC 0x0054 /* 6 bytes MAC address for 802.11a */
2614 +#define SSB_SPROM1_ETHPHY 0x005A /* Ethernet PHY settings */
2615 #define SSB_SPROM1_ETHPHY_ET0A 0x001F /* MII Address for enet0 */
2616 #define SSB_SPROM1_ETHPHY_ET1A 0x03E0 /* MII Address for enet1 */
2617 #define SSB_SPROM1_ETHPHY_ET1A_SHIFT 5
2618 #define SSB_SPROM1_ETHPHY_ET0M (1<<14) /* MDIO for enet0 */
2619 #define SSB_SPROM1_ETHPHY_ET1M (1<<15) /* MDIO for enet1 */
2620 -#define SSB_SPROM1_BINF 0x105C /* Board info */
2621 +#define SSB_SPROM1_BINF 0x005C /* Board info */
2622 #define SSB_SPROM1_BINF_BREV 0x00FF /* Board Revision */
2623 #define SSB_SPROM1_BINF_CCODE 0x0F00 /* Country Code */
2624 #define SSB_SPROM1_BINF_CCODE_SHIFT 8
2625 @@ -198,63 +200,63 @@
2626 #define SSB_SPROM1_BINF_ANTBG_SHIFT 12
2627 #define SSB_SPROM1_BINF_ANTA 0xC000 /* Available A-PHY antennas */
2628 #define SSB_SPROM1_BINF_ANTA_SHIFT 14
2629 -#define SSB_SPROM1_PA0B0 0x105E
2630 -#define SSB_SPROM1_PA0B1 0x1060
2631 -#define SSB_SPROM1_PA0B2 0x1062
2632 -#define SSB_SPROM1_GPIOA 0x1064 /* General Purpose IO pins 0 and 1 */
2633 +#define SSB_SPROM1_PA0B0 0x005E
2634 +#define SSB_SPROM1_PA0B1 0x0060
2635 +#define SSB_SPROM1_PA0B2 0x0062
2636 +#define SSB_SPROM1_GPIOA 0x0064 /* General Purpose IO pins 0 and 1 */
2637 #define SSB_SPROM1_GPIOA_P0 0x00FF /* Pin 0 */
2638 #define SSB_SPROM1_GPIOA_P1 0xFF00 /* Pin 1 */
2639 #define SSB_SPROM1_GPIOA_P1_SHIFT 8
2640 -#define SSB_SPROM1_GPIOB 0x1066 /* General Purpuse IO pins 2 and 3 */
2641 +#define SSB_SPROM1_GPIOB 0x0066 /* General Purpuse IO pins 2 and 3 */
2642 #define SSB_SPROM1_GPIOB_P2 0x00FF /* Pin 2 */
2643 #define SSB_SPROM1_GPIOB_P3 0xFF00 /* Pin 3 */
2644 #define SSB_SPROM1_GPIOB_P3_SHIFT 8
2645 -#define SSB_SPROM1_MAXPWR 0x1068 /* Power Amplifier Max Power */
2646 +#define SSB_SPROM1_MAXPWR 0x0068 /* Power Amplifier Max Power */
2647 #define SSB_SPROM1_MAXPWR_BG 0x00FF /* B-PHY and G-PHY (in dBm Q5.2) */
2648 #define SSB_SPROM1_MAXPWR_A 0xFF00 /* A-PHY (in dBm Q5.2) */
2649 #define SSB_SPROM1_MAXPWR_A_SHIFT 8
2650 -#define SSB_SPROM1_PA1B0 0x106A
2651 -#define SSB_SPROM1_PA1B1 0x106C
2652 -#define SSB_SPROM1_PA1B2 0x106E
2653 -#define SSB_SPROM1_ITSSI 0x1070 /* Idle TSSI Target */
2654 +#define SSB_SPROM1_PA1B0 0x006A
2655 +#define SSB_SPROM1_PA1B1 0x006C
2656 +#define SSB_SPROM1_PA1B2 0x006E
2657 +#define SSB_SPROM1_ITSSI 0x0070 /* Idle TSSI Target */
2658 #define SSB_SPROM1_ITSSI_BG 0x00FF /* B-PHY and G-PHY*/
2659 #define SSB_SPROM1_ITSSI_A 0xFF00 /* A-PHY */
2660 #define SSB_SPROM1_ITSSI_A_SHIFT 8
2661 -#define SSB_SPROM1_BFLLO 0x1072 /* Boardflags (low 16 bits) */
2662 -#define SSB_SPROM1_AGAIN 0x1074 /* Antenna Gain (in dBm Q5.2) */
2663 +#define SSB_SPROM1_BFLLO 0x0072 /* Boardflags (low 16 bits) */
2664 +#define SSB_SPROM1_AGAIN 0x0074 /* Antenna Gain (in dBm Q5.2) */
2665 #define SSB_SPROM1_AGAIN_BG 0x00FF /* B-PHY and G-PHY */
2666 #define SSB_SPROM1_AGAIN_BG_SHIFT 0
2667 #define SSB_SPROM1_AGAIN_A 0xFF00 /* A-PHY */
2668 #define SSB_SPROM1_AGAIN_A_SHIFT 8
2670 /* SPROM Revision 2 (inherits from rev 1) */
2671 -#define SSB_SPROM2_BFLHI 0x1038 /* Boardflags (high 16 bits) */
2672 -#define SSB_SPROM2_MAXP_A 0x103A /* A-PHY Max Power */
2673 +#define SSB_SPROM2_BFLHI 0x0038 /* Boardflags (high 16 bits) */
2674 +#define SSB_SPROM2_MAXP_A 0x003A /* A-PHY Max Power */
2675 #define SSB_SPROM2_MAXP_A_HI 0x00FF /* Max Power High */
2676 #define SSB_SPROM2_MAXP_A_LO 0xFF00 /* Max Power Low */
2677 #define SSB_SPROM2_MAXP_A_LO_SHIFT 8
2678 -#define SSB_SPROM2_PA1LOB0 0x103C /* A-PHY PowerAmplifier Low Settings */
2679 -#define SSB_SPROM2_PA1LOB1 0x103E /* A-PHY PowerAmplifier Low Settings */
2680 -#define SSB_SPROM2_PA1LOB2 0x1040 /* A-PHY PowerAmplifier Low Settings */
2681 -#define SSB_SPROM2_PA1HIB0 0x1042 /* A-PHY PowerAmplifier High Settings */
2682 -#define SSB_SPROM2_PA1HIB1 0x1044 /* A-PHY PowerAmplifier High Settings */
2683 -#define SSB_SPROM2_PA1HIB2 0x1046 /* A-PHY PowerAmplifier High Settings */
2684 -#define SSB_SPROM2_OPO 0x1078 /* OFDM Power Offset from CCK Level */
2685 +#define SSB_SPROM2_PA1LOB0 0x003C /* A-PHY PowerAmplifier Low Settings */
2686 +#define SSB_SPROM2_PA1LOB1 0x003E /* A-PHY PowerAmplifier Low Settings */
2687 +#define SSB_SPROM2_PA1LOB2 0x0040 /* A-PHY PowerAmplifier Low Settings */
2688 +#define SSB_SPROM2_PA1HIB0 0x0042 /* A-PHY PowerAmplifier High Settings */
2689 +#define SSB_SPROM2_PA1HIB1 0x0044 /* A-PHY PowerAmplifier High Settings */
2690 +#define SSB_SPROM2_PA1HIB2 0x0046 /* A-PHY PowerAmplifier High Settings */
2691 +#define SSB_SPROM2_OPO 0x0078 /* OFDM Power Offset from CCK Level */
2692 #define SSB_SPROM2_OPO_VALUE 0x00FF
2693 #define SSB_SPROM2_OPO_UNUSED 0xFF00
2694 -#define SSB_SPROM2_CCODE 0x107C /* Two char Country Code */
2695 +#define SSB_SPROM2_CCODE 0x007C /* Two char Country Code */
2697 /* SPROM Revision 3 (inherits most data from rev 2) */
2698 -#define SSB_SPROM3_IL0MAC 0x104A /* 6 bytes MAC address for 802.11b/g */
2699 -#define SSB_SPROM3_OFDMAPO 0x102C /* A-PHY OFDM Mid Power Offset (4 bytes, BigEndian) */
2700 -#define SSB_SPROM3_OFDMALPO 0x1030 /* A-PHY OFDM Low Power Offset (4 bytes, BigEndian) */
2701 -#define SSB_SPROM3_OFDMAHPO 0x1034 /* A-PHY OFDM High Power Offset (4 bytes, BigEndian) */
2702 -#define SSB_SPROM3_GPIOLDC 0x1042 /* GPIO LED Powersave Duty Cycle (4 bytes, BigEndian) */
2703 +#define SSB_SPROM3_OFDMAPO 0x002C /* A-PHY OFDM Mid Power Offset (4 bytes, BigEndian) */
2704 +#define SSB_SPROM3_OFDMALPO 0x0030 /* A-PHY OFDM Low Power Offset (4 bytes, BigEndian) */
2705 +#define SSB_SPROM3_OFDMAHPO 0x0034 /* A-PHY OFDM High Power Offset (4 bytes, BigEndian) */
2706 +#define SSB_SPROM3_GPIOLDC 0x0042 /* GPIO LED Powersave Duty Cycle (4 bytes, BigEndian) */
2707 #define SSB_SPROM3_GPIOLDC_OFF 0x0000FF00 /* Off Count */
2708 #define SSB_SPROM3_GPIOLDC_OFF_SHIFT 8
2709 #define SSB_SPROM3_GPIOLDC_ON 0x00FF0000 /* On Count */
2710 #define SSB_SPROM3_GPIOLDC_ON_SHIFT 16
2711 -#define SSB_SPROM3_CCKPO 0x1078 /* CCK Power Offset */
2712 +#define SSB_SPROM3_IL0MAC 0x004A /* 6 bytes MAC address for 802.11b/g */
2713 +#define SSB_SPROM3_CCKPO 0x0078 /* CCK Power Offset */
2714 #define SSB_SPROM3_CCKPO_1M 0x000F /* 1M Rate PO */
2715 #define SSB_SPROM3_CCKPO_2M 0x00F0 /* 2M Rate PO */
2716 #define SSB_SPROM3_CCKPO_2M_SHIFT 4
2717 @@ -265,100 +267,144 @@
2718 #define SSB_SPROM3_OFDMGPO 0x107A /* G-PHY OFDM Power Offset (4 bytes, BigEndian) */
2720 /* SPROM Revision 4 */
2721 -#define SSB_SPROM4_IL0MAC 0x104C /* 6 byte MAC address for a/b/g/n */
2722 -#define SSB_SPROM4_ETHPHY 0x105A /* Ethernet PHY settings ?? */
2723 +#define SSB_SPROM4_BFLLO 0x0044 /* Boardflags (low 16 bits) */
2724 +#define SSB_SPROM4_BFLHI 0x0046 /* Board Flags Hi */
2725 +#define SSB_SPROM4_BFL2LO 0x0048 /* Board flags 2 (low 16 bits) */
2726 +#define SSB_SPROM4_BFL2HI 0x004A /* Board flags 2 Hi */
2727 +#define SSB_SPROM4_IL0MAC 0x004C /* 6 byte MAC address for a/b/g/n */
2728 +#define SSB_SPROM4_CCODE 0x0052 /* Country Code (2 bytes) */
2729 +#define SSB_SPROM4_GPIOA 0x0056 /* Gen. Purpose IO # 0 and 1 */
2730 +#define SSB_SPROM4_GPIOA_P0 0x00FF /* Pin 0 */
2731 +#define SSB_SPROM4_GPIOA_P1 0xFF00 /* Pin 1 */
2732 +#define SSB_SPROM4_GPIOA_P1_SHIFT 8
2733 +#define SSB_SPROM4_GPIOB 0x0058 /* Gen. Purpose IO # 2 and 3 */
2734 +#define SSB_SPROM4_GPIOB_P2 0x00FF /* Pin 2 */
2735 +#define SSB_SPROM4_GPIOB_P3 0xFF00 /* Pin 3 */
2736 +#define SSB_SPROM4_GPIOB_P3_SHIFT 8
2737 +#define SSB_SPROM4_ETHPHY 0x005A /* Ethernet PHY settings ?? */
2738 #define SSB_SPROM4_ETHPHY_ET0A 0x001F /* MII Address for enet0 */
2739 #define SSB_SPROM4_ETHPHY_ET1A 0x03E0 /* MII Address for enet1 */
2740 #define SSB_SPROM4_ETHPHY_ET1A_SHIFT 5
2741 #define SSB_SPROM4_ETHPHY_ET0M (1<<14) /* MDIO for enet0 */
2742 #define SSB_SPROM4_ETHPHY_ET1M (1<<15) /* MDIO for enet1 */
2743 -#define SSB_SPROM4_CCODE 0x1052 /* Country Code (2 bytes) */
2744 -#define SSB_SPROM4_ANTAVAIL 0x105D /* Antenna available bitfields */
2745 -#define SSB_SPROM4_ANTAVAIL_A 0x00FF /* A-PHY bitfield */
2746 -#define SSB_SPROM4_ANTAVAIL_A_SHIFT 0
2747 -#define SSB_SPROM4_ANTAVAIL_BG 0xFF00 /* B-PHY and G-PHY bitfield */
2748 -#define SSB_SPROM4_ANTAVAIL_BG_SHIFT 8
2749 -#define SSB_SPROM4_BFLLO 0x1044 /* Boardflags (low 16 bits) */
2750 -#define SSB_SPROM4_AGAIN01 0x105E /* Antenna Gain (in dBm Q5.2) */
2751 +#define SSB_SPROM4_ANTAVAIL 0x005D /* Antenna available bitfields */
2752 +#define SSB_SPROM4_ANTAVAIL_A 0x00FF /* A-PHY bitfield */
2753 +#define SSB_SPROM4_ANTAVAIL_A_SHIFT 0
2754 +#define SSB_SPROM4_ANTAVAIL_BG 0xFF00 /* B-PHY and G-PHY bitfield */
2755 +#define SSB_SPROM4_ANTAVAIL_BG_SHIFT 8
2756 +#define SSB_SPROM4_AGAIN01 0x005E /* Antenna Gain (in dBm Q5.2) */
2757 #define SSB_SPROM4_AGAIN0 0x00FF /* Antenna 0 */
2758 #define SSB_SPROM4_AGAIN0_SHIFT 0
2759 #define SSB_SPROM4_AGAIN1 0xFF00 /* Antenna 1 */
2760 #define SSB_SPROM4_AGAIN1_SHIFT 8
2761 -#define SSB_SPROM4_AGAIN23 0x1060
2762 +#define SSB_SPROM4_AGAIN23 0x0060
2763 #define SSB_SPROM4_AGAIN2 0x00FF /* Antenna 2 */
2764 #define SSB_SPROM4_AGAIN2_SHIFT 0
2765 #define SSB_SPROM4_AGAIN3 0xFF00 /* Antenna 3 */
2766 #define SSB_SPROM4_AGAIN3_SHIFT 8
2767 -#define SSB_SPROM4_BFLHI 0x1046 /* Board Flags Hi */
2768 -#define SSB_SPROM4_MAXP_BG 0x1080 /* Max Power BG in path 1 */
2769 +#define SSB_SPROM4_TXPID2G01 0x0062 /* TX Power Index 2GHz */
2770 +#define SSB_SPROM4_TXPID2G0 0x00FF
2771 +#define SSB_SPROM4_TXPID2G0_SHIFT 0
2772 +#define SSB_SPROM4_TXPID2G1 0xFF00
2773 +#define SSB_SPROM4_TXPID2G1_SHIFT 8
2774 +#define SSB_SPROM4_TXPID2G23 0x0064 /* TX Power Index 2GHz */
2775 +#define SSB_SPROM4_TXPID2G2 0x00FF
2776 +#define SSB_SPROM4_TXPID2G2_SHIFT 0
2777 +#define SSB_SPROM4_TXPID2G3 0xFF00
2778 +#define SSB_SPROM4_TXPID2G3_SHIFT 8
2779 +#define SSB_SPROM4_TXPID5G01 0x0066 /* TX Power Index 5GHz middle subband */
2780 +#define SSB_SPROM4_TXPID5G0 0x00FF
2781 +#define SSB_SPROM4_TXPID5G0_SHIFT 0
2782 +#define SSB_SPROM4_TXPID5G1 0xFF00
2783 +#define SSB_SPROM4_TXPID5G1_SHIFT 8
2784 +#define SSB_SPROM4_TXPID5G23 0x0068 /* TX Power Index 5GHz middle subband */
2785 +#define SSB_SPROM4_TXPID5G2 0x00FF
2786 +#define SSB_SPROM4_TXPID5G2_SHIFT 0
2787 +#define SSB_SPROM4_TXPID5G3 0xFF00
2788 +#define SSB_SPROM4_TXPID5G3_SHIFT 8
2789 +#define SSB_SPROM4_TXPID5GL01 0x006A /* TX Power Index 5GHz low subband */
2790 +#define SSB_SPROM4_TXPID5GL0 0x00FF
2791 +#define SSB_SPROM4_TXPID5GL0_SHIFT 0
2792 +#define SSB_SPROM4_TXPID5GL1 0xFF00
2793 +#define SSB_SPROM4_TXPID5GL1_SHIFT 8
2794 +#define SSB_SPROM4_TXPID5GL23 0x006C /* TX Power Index 5GHz low subband */
2795 +#define SSB_SPROM4_TXPID5GL2 0x00FF
2796 +#define SSB_SPROM4_TXPID5GL2_SHIFT 0
2797 +#define SSB_SPROM4_TXPID5GL3 0xFF00
2798 +#define SSB_SPROM4_TXPID5GL3_SHIFT 8
2799 +#define SSB_SPROM4_TXPID5GH01 0x006E /* TX Power Index 5GHz high subband */
2800 +#define SSB_SPROM4_TXPID5GH0 0x00FF
2801 +#define SSB_SPROM4_TXPID5GH0_SHIFT 0
2802 +#define SSB_SPROM4_TXPID5GH1 0xFF00
2803 +#define SSB_SPROM4_TXPID5GH1_SHIFT 8
2804 +#define SSB_SPROM4_TXPID5GH23 0x0070 /* TX Power Index 5GHz high subband */
2805 +#define SSB_SPROM4_TXPID5GH2 0x00FF
2806 +#define SSB_SPROM4_TXPID5GH2_SHIFT 0
2807 +#define SSB_SPROM4_TXPID5GH3 0xFF00
2808 +#define SSB_SPROM4_TXPID5GH3_SHIFT 8
2809 +#define SSB_SPROM4_MAXP_BG 0x0080 /* Max Power BG in path 1 */
2810 #define SSB_SPROM4_MAXP_BG_MASK 0x00FF /* Mask for Max Power BG */
2811 #define SSB_SPROM4_ITSSI_BG 0xFF00 /* Mask for path 1 itssi_bg */
2812 #define SSB_SPROM4_ITSSI_BG_SHIFT 8
2813 -#define SSB_SPROM4_MAXP_A 0x108A /* Max Power A in path 1 */
2814 +#define SSB_SPROM4_MAXP_A 0x008A /* Max Power A in path 1 */
2815 #define SSB_SPROM4_MAXP_A_MASK 0x00FF /* Mask for Max Power A */
2816 #define SSB_SPROM4_ITSSI_A 0xFF00 /* Mask for path 1 itssi_a */
2817 #define SSB_SPROM4_ITSSI_A_SHIFT 8
2818 -#define SSB_SPROM4_GPIOA 0x1056 /* Gen. Purpose IO # 0 and 1 */
2819 -#define SSB_SPROM4_GPIOA_P0 0x00FF /* Pin 0 */
2820 -#define SSB_SPROM4_GPIOA_P1 0xFF00 /* Pin 1 */
2821 -#define SSB_SPROM4_GPIOA_P1_SHIFT 8
2822 -#define SSB_SPROM4_GPIOB 0x1058 /* Gen. Purpose IO # 2 and 3 */
2823 -#define SSB_SPROM4_GPIOB_P2 0x00FF /* Pin 2 */
2824 -#define SSB_SPROM4_GPIOB_P3 0xFF00 /* Pin 3 */
2825 -#define SSB_SPROM4_GPIOB_P3_SHIFT 8
2826 -#define SSB_SPROM4_PA0B0 0x1082 /* The paXbY locations are */
2827 -#define SSB_SPROM4_PA0B1 0x1084 /* only guesses */
2828 -#define SSB_SPROM4_PA0B2 0x1086
2829 -#define SSB_SPROM4_PA1B0 0x108E
2830 -#define SSB_SPROM4_PA1B1 0x1090
2831 -#define SSB_SPROM4_PA1B2 0x1092
2832 +#define SSB_SPROM4_PA0B0 0x0082 /* The paXbY locations are */
2833 +#define SSB_SPROM4_PA0B1 0x0084 /* only guesses */
2834 +#define SSB_SPROM4_PA0B2 0x0086
2835 +#define SSB_SPROM4_PA1B0 0x008E
2836 +#define SSB_SPROM4_PA1B1 0x0090
2837 +#define SSB_SPROM4_PA1B2 0x0092
2839 /* SPROM Revision 5 (inherits most data from rev 4) */
2840 -#define SSB_SPROM5_BFLLO 0x104A /* Boardflags (low 16 bits) */
2841 -#define SSB_SPROM5_BFLHI 0x104C /* Board Flags Hi */
2842 -#define SSB_SPROM5_IL0MAC 0x1052 /* 6 byte MAC address for a/b/g/n */
2843 -#define SSB_SPROM5_CCODE 0x1044 /* Country Code (2 bytes) */
2844 -#define SSB_SPROM5_GPIOA 0x1076 /* Gen. Purpose IO # 0 and 1 */
2845 +#define SSB_SPROM5_CCODE 0x0044 /* Country Code (2 bytes) */
2846 +#define SSB_SPROM5_BFLLO 0x004A /* Boardflags (low 16 bits) */
2847 +#define SSB_SPROM5_BFLHI 0x004C /* Board Flags Hi */
2848 +#define SSB_SPROM5_BFL2LO 0x004E /* Board flags 2 (low 16 bits) */
2849 +#define SSB_SPROM5_BFL2HI 0x0050 /* Board flags 2 Hi */
2850 +#define SSB_SPROM5_IL0MAC 0x0052 /* 6 byte MAC address for a/b/g/n */
2851 +#define SSB_SPROM5_GPIOA 0x0076 /* Gen. Purpose IO # 0 and 1 */
2852 #define SSB_SPROM5_GPIOA_P0 0x00FF /* Pin 0 */
2853 #define SSB_SPROM5_GPIOA_P1 0xFF00 /* Pin 1 */
2854 #define SSB_SPROM5_GPIOA_P1_SHIFT 8
2855 -#define SSB_SPROM5_GPIOB 0x1078 /* Gen. Purpose IO # 2 and 3 */
2856 +#define SSB_SPROM5_GPIOB 0x0078 /* Gen. Purpose IO # 2 and 3 */
2857 #define SSB_SPROM5_GPIOB_P2 0x00FF /* Pin 2 */
2858 #define SSB_SPROM5_GPIOB_P3 0xFF00 /* Pin 3 */
2859 #define SSB_SPROM5_GPIOB_P3_SHIFT 8
2861 /* SPROM Revision 8 */
2862 -#define SSB_SPROM8_BOARDREV 0x1082 /* Board revision */
2863 -#define SSB_SPROM8_BFLLO 0x1084 /* Board flags (bits 0-15) */
2864 -#define SSB_SPROM8_BFLHI 0x1086 /* Board flags (bits 16-31) */
2865 -#define SSB_SPROM8_BFL2LO 0x1088 /* Board flags (bits 32-47) */
2866 -#define SSB_SPROM8_BFL2HI 0x108A /* Board flags (bits 48-63) */
2867 -#define SSB_SPROM8_IL0MAC 0x108C /* 6 byte MAC address */
2868 -#define SSB_SPROM8_CCODE 0x1092 /* 2 byte country code */
2869 -#define SSB_SPROM8_ANTAVAIL 0x109C /* Antenna available bitfields*/
2870 -#define SSB_SPROM8_ANTAVAIL_A 0xFF00 /* A-PHY bitfield */
2871 -#define SSB_SPROM8_ANTAVAIL_A_SHIFT 8
2872 -#define SSB_SPROM8_ANTAVAIL_BG 0x00FF /* B-PHY and G-PHY bitfield */
2873 -#define SSB_SPROM8_ANTAVAIL_BG_SHIFT 0
2874 -#define SSB_SPROM8_AGAIN01 0x109E /* Antenna Gain (in dBm Q5.2) */
2875 +#define SSB_SPROM8_BOARDREV 0x0082 /* Board revision */
2876 +#define SSB_SPROM8_BFLLO 0x0084 /* Board flags (bits 0-15) */
2877 +#define SSB_SPROM8_BFLHI 0x0086 /* Board flags (bits 16-31) */
2878 +#define SSB_SPROM8_BFL2LO 0x0088 /* Board flags (bits 32-47) */
2879 +#define SSB_SPROM8_BFL2HI 0x008A /* Board flags (bits 48-63) */
2880 +#define SSB_SPROM8_IL0MAC 0x008C /* 6 byte MAC address */
2881 +#define SSB_SPROM8_CCODE 0x0092 /* 2 byte country code */
2882 +#define SSB_SPROM8_GPIOA 0x0096 /*Gen. Purpose IO # 0 and 1 */
2883 +#define SSB_SPROM8_GPIOA_P0 0x00FF /* Pin 0 */
2884 +#define SSB_SPROM8_GPIOA_P1 0xFF00 /* Pin 1 */
2885 +#define SSB_SPROM8_GPIOA_P1_SHIFT 8
2886 +#define SSB_SPROM8_GPIOB 0x0098 /* Gen. Purpose IO # 2 and 3 */
2887 +#define SSB_SPROM8_GPIOB_P2 0x00FF /* Pin 2 */
2888 +#define SSB_SPROM8_GPIOB_P3 0xFF00 /* Pin 3 */
2889 +#define SSB_SPROM8_GPIOB_P3_SHIFT 8
2890 +#define SSB_SPROM8_ANTAVAIL 0x009C /* Antenna available bitfields*/
2891 +#define SSB_SPROM8_ANTAVAIL_A 0xFF00 /* A-PHY bitfield */
2892 +#define SSB_SPROM8_ANTAVAIL_A_SHIFT 8
2893 +#define SSB_SPROM8_ANTAVAIL_BG 0x00FF /* B-PHY and G-PHY bitfield */
2894 +#define SSB_SPROM8_ANTAVAIL_BG_SHIFT 0
2895 +#define SSB_SPROM8_AGAIN01 0x009E /* Antenna Gain (in dBm Q5.2) */
2896 #define SSB_SPROM8_AGAIN0 0x00FF /* Antenna 0 */
2897 #define SSB_SPROM8_AGAIN0_SHIFT 0
2898 #define SSB_SPROM8_AGAIN1 0xFF00 /* Antenna 1 */
2899 #define SSB_SPROM8_AGAIN1_SHIFT 8
2900 -#define SSB_SPROM8_AGAIN23 0x10A0
2901 +#define SSB_SPROM8_AGAIN23 0x00A0
2902 #define SSB_SPROM8_AGAIN2 0x00FF /* Antenna 2 */
2903 #define SSB_SPROM8_AGAIN2_SHIFT 0
2904 #define SSB_SPROM8_AGAIN3 0xFF00 /* Antenna 3 */
2905 #define SSB_SPROM8_AGAIN3_SHIFT 8
2906 -#define SSB_SPROM8_GPIOA 0x1096 /*Gen. Purpose IO # 0 and 1 */
2907 -#define SSB_SPROM8_GPIOA_P0 0x00FF /* Pin 0 */
2908 -#define SSB_SPROM8_GPIOA_P1 0xFF00 /* Pin 1 */
2909 -#define SSB_SPROM8_GPIOA_P1_SHIFT 8
2910 -#define SSB_SPROM8_GPIOB 0x1098 /* Gen. Purpose IO # 2 and 3 */
2911 -#define SSB_SPROM8_GPIOB_P2 0x00FF /* Pin 2 */
2912 -#define SSB_SPROM8_GPIOB_P3 0xFF00 /* Pin 3 */
2913 -#define SSB_SPROM8_GPIOB_P3_SHIFT 8
2914 -#define SSB_SPROM8_RSSIPARM2G 0x10A4 /* RSSI params for 2GHz */
2915 +#define SSB_SPROM8_RSSIPARM2G 0x00A4 /* RSSI params for 2GHz */
2916 #define SSB_SPROM8_RSSISMF2G 0x000F
2917 #define SSB_SPROM8_RSSISMC2G 0x00F0
2918 #define SSB_SPROM8_RSSISMC2G_SHIFT 4
2920 #define SSB_SPROM8_RSSISAV2G_SHIFT 8
2921 #define SSB_SPROM8_BXA2G 0x1800
2922 #define SSB_SPROM8_BXA2G_SHIFT 11
2923 -#define SSB_SPROM8_RSSIPARM5G 0x10A6 /* RSSI params for 5GHz */
2924 +#define SSB_SPROM8_RSSIPARM5G 0x00A6 /* RSSI params for 5GHz */
2925 #define SSB_SPROM8_RSSISMF5G 0x000F
2926 #define SSB_SPROM8_RSSISMC5G 0x00F0
2927 #define SSB_SPROM8_RSSISMC5G_SHIFT 4
2928 @@ -374,47 +420,138 @@
2929 #define SSB_SPROM8_RSSISAV5G_SHIFT 8
2930 #define SSB_SPROM8_BXA5G 0x1800
2931 #define SSB_SPROM8_BXA5G_SHIFT 11
2932 -#define SSB_SPROM8_TRI25G 0x10A8 /* TX isolation 2.4&5.3GHz */
2933 +#define SSB_SPROM8_TRI25G 0x00A8 /* TX isolation 2.4&5.3GHz */
2934 #define SSB_SPROM8_TRI2G 0x00FF /* TX isolation 2.4GHz */
2935 #define SSB_SPROM8_TRI5G 0xFF00 /* TX isolation 5.3GHz */
2936 #define SSB_SPROM8_TRI5G_SHIFT 8
2937 -#define SSB_SPROM8_TRI5GHL 0x10AA /* TX isolation 5.2/5.8GHz */
2938 +#define SSB_SPROM8_TRI5GHL 0x00AA /* TX isolation 5.2/5.8GHz */
2939 #define SSB_SPROM8_TRI5GL 0x00FF /* TX isolation 5.2GHz */
2940 #define SSB_SPROM8_TRI5GH 0xFF00 /* TX isolation 5.8GHz */
2941 #define SSB_SPROM8_TRI5GH_SHIFT 8
2942 -#define SSB_SPROM8_RXPO 0x10AC /* RX power offsets */
2943 +#define SSB_SPROM8_RXPO 0x00AC /* RX power offsets */
2944 #define SSB_SPROM8_RXPO2G 0x00FF /* 2GHz RX power offset */
2945 #define SSB_SPROM8_RXPO5G 0xFF00 /* 5GHz RX power offset */
2946 #define SSB_SPROM8_RXPO5G_SHIFT 8
2947 -#define SSB_SPROM8_MAXP_BG 0x10C0 /* Max Power 2GHz in path 1 */
2948 +#define SSB_SPROM8_FEM2G 0x00AE
2949 +#define SSB_SPROM8_FEM5G 0x00B0
2950 +#define SSB_SROM8_FEM_TSSIPOS 0x0001
2951 +#define SSB_SROM8_FEM_TSSIPOS_SHIFT 0
2952 +#define SSB_SROM8_FEM_EXTPA_GAIN 0x0006
2953 +#define SSB_SROM8_FEM_EXTPA_GAIN_SHIFT 1
2954 +#define SSB_SROM8_FEM_PDET_RANGE 0x00F8
2955 +#define SSB_SROM8_FEM_PDET_RANGE_SHIFT 3
2956 +#define SSB_SROM8_FEM_TR_ISO 0x0700
2957 +#define SSB_SROM8_FEM_TR_ISO_SHIFT 8
2958 +#define SSB_SROM8_FEM_ANTSWLUT 0xF800
2959 +#define SSB_SROM8_FEM_ANTSWLUT_SHIFT 11
2960 +#define SSB_SPROM8_THERMAL 0x00B2
2961 +#define SSB_SPROM8_MPWR_RAWTS 0x00B4
2962 +#define SSB_SPROM8_TS_SLP_OPT_CORRX 0x00B6
2963 +#define SSB_SPROM8_FOC_HWIQ_IQSWP 0x00B8
2964 +#define SSB_SPROM8_PHYCAL_TEMPDELTA 0x00BA
2966 +/* There are 4 blocks with power info sharing the same layout */
2967 +#define SSB_SROM8_PWR_INFO_CORE0 0x00C0
2968 +#define SSB_SROM8_PWR_INFO_CORE1 0x00E0
2969 +#define SSB_SROM8_PWR_INFO_CORE2 0x0100
2970 +#define SSB_SROM8_PWR_INFO_CORE3 0x0120
2972 +#define SSB_SROM8_2G_MAXP_ITSSI 0x00
2973 +#define SSB_SPROM8_2G_MAXP 0x00FF
2974 +#define SSB_SPROM8_2G_ITSSI 0xFF00
2975 +#define SSB_SPROM8_2G_ITSSI_SHIFT 8
2976 +#define SSB_SROM8_2G_PA_0 0x02 /* 2GHz power amp settings */
2977 +#define SSB_SROM8_2G_PA_1 0x04
2978 +#define SSB_SROM8_2G_PA_2 0x06
2979 +#define SSB_SROM8_5G_MAXP_ITSSI 0x08 /* 5GHz ITSSI and 5.3GHz Max Power */
2980 +#define SSB_SPROM8_5G_MAXP 0x00FF
2981 +#define SSB_SPROM8_5G_ITSSI 0xFF00
2982 +#define SSB_SPROM8_5G_ITSSI_SHIFT 8
2983 +#define SSB_SPROM8_5GHL_MAXP 0x0A /* 5.2GHz and 5.8GHz Max Power */
2984 +#define SSB_SPROM8_5GH_MAXP 0x00FF
2985 +#define SSB_SPROM8_5GL_MAXP 0xFF00
2986 +#define SSB_SPROM8_5GL_MAXP_SHIFT 8
2987 +#define SSB_SROM8_5G_PA_0 0x0C /* 5.3GHz power amp settings */
2988 +#define SSB_SROM8_5G_PA_1 0x0E
2989 +#define SSB_SROM8_5G_PA_2 0x10
2990 +#define SSB_SROM8_5GL_PA_0 0x12 /* 5.2GHz power amp settings */
2991 +#define SSB_SROM8_5GL_PA_1 0x14
2992 +#define SSB_SROM8_5GL_PA_2 0x16
2993 +#define SSB_SROM8_5GH_PA_0 0x18 /* 5.8GHz power amp settings */
2994 +#define SSB_SROM8_5GH_PA_1 0x1A
2995 +#define SSB_SROM8_5GH_PA_2 0x1C
2997 +/* TODO: Make it deprecated */
2998 +#define SSB_SPROM8_MAXP_BG 0x00C0 /* Max Power 2GHz in path 1 */
2999 #define SSB_SPROM8_MAXP_BG_MASK 0x00FF /* Mask for Max Power 2GHz */
3000 #define SSB_SPROM8_ITSSI_BG 0xFF00 /* Mask for path 1 itssi_bg */
3001 #define SSB_SPROM8_ITSSI_BG_SHIFT 8
3002 -#define SSB_SPROM8_PA0B0 0x10C2 /* 2GHz power amp settings */
3003 -#define SSB_SPROM8_PA0B1 0x10C4
3004 -#define SSB_SPROM8_PA0B2 0x10C6
3005 -#define SSB_SPROM8_MAXP_A 0x10C8 /* Max Power 5.3GHz */
3006 +#define SSB_SPROM8_PA0B0 0x00C2 /* 2GHz power amp settings */
3007 +#define SSB_SPROM8_PA0B1 0x00C4
3008 +#define SSB_SPROM8_PA0B2 0x00C6
3009 +#define SSB_SPROM8_MAXP_A 0x00C8 /* Max Power 5.3GHz */
3010 #define SSB_SPROM8_MAXP_A_MASK 0x00FF /* Mask for Max Power 5.3GHz */
3011 #define SSB_SPROM8_ITSSI_A 0xFF00 /* Mask for path 1 itssi_a */
3012 #define SSB_SPROM8_ITSSI_A_SHIFT 8
3013 -#define SSB_SPROM8_MAXP_AHL 0x10CA /* Max Power 5.2/5.8GHz */
3014 +#define SSB_SPROM8_MAXP_AHL 0x00CA /* Max Power 5.2/5.8GHz */
3015 #define SSB_SPROM8_MAXP_AH_MASK 0x00FF /* Mask for Max Power 5.8GHz */
3016 #define SSB_SPROM8_MAXP_AL_MASK 0xFF00 /* Mask for Max Power 5.2GHz */
3017 #define SSB_SPROM8_MAXP_AL_SHIFT 8
3018 -#define SSB_SPROM8_PA1B0 0x10CC /* 5.3GHz power amp settings */
3019 -#define SSB_SPROM8_PA1B1 0x10CE
3020 -#define SSB_SPROM8_PA1B2 0x10D0
3021 -#define SSB_SPROM8_PA1LOB0 0x10D2 /* 5.2GHz power amp settings */
3022 -#define SSB_SPROM8_PA1LOB1 0x10D4
3023 -#define SSB_SPROM8_PA1LOB2 0x10D6
3024 -#define SSB_SPROM8_PA1HIB0 0x10D8 /* 5.8GHz power amp settings */
3025 -#define SSB_SPROM8_PA1HIB1 0x10DA
3026 -#define SSB_SPROM8_PA1HIB2 0x10DC
3027 -#define SSB_SPROM8_CCK2GPO 0x1140 /* CCK power offset */
3028 -#define SSB_SPROM8_OFDM2GPO 0x1142 /* 2.4GHz OFDM power offset */
3029 -#define SSB_SPROM8_OFDM5GPO 0x1146 /* 5.3GHz OFDM power offset */
3030 -#define SSB_SPROM8_OFDM5GLPO 0x114A /* 5.2GHz OFDM power offset */
3031 -#define SSB_SPROM8_OFDM5GHPO 0x114E /* 5.8GHz OFDM power offset */
3032 +#define SSB_SPROM8_PA1B0 0x00CC /* 5.3GHz power amp settings */
3033 +#define SSB_SPROM8_PA1B1 0x00CE
3034 +#define SSB_SPROM8_PA1B2 0x00D0
3035 +#define SSB_SPROM8_PA1LOB0 0x00D2 /* 5.2GHz power amp settings */
3036 +#define SSB_SPROM8_PA1LOB1 0x00D4
3037 +#define SSB_SPROM8_PA1LOB2 0x00D6
3038 +#define SSB_SPROM8_PA1HIB0 0x00D8 /* 5.8GHz power amp settings */
3039 +#define SSB_SPROM8_PA1HIB1 0x00DA
3040 +#define SSB_SPROM8_PA1HIB2 0x00DC
3042 +#define SSB_SPROM8_CCK2GPO 0x0140 /* CCK power offset */
3043 +#define SSB_SPROM8_OFDM2GPO 0x0142 /* 2.4GHz OFDM power offset */
3044 +#define SSB_SPROM8_OFDM5GPO 0x0146 /* 5.3GHz OFDM power offset */
3045 +#define SSB_SPROM8_OFDM5GLPO 0x014A /* 5.2GHz OFDM power offset */
3046 +#define SSB_SPROM8_OFDM5GHPO 0x014E /* 5.8GHz OFDM power offset */
3048 +/* Values for boardflags_lo read from SPROM */
3049 +#define SSB_BFL_BTCOEXIST 0x0001 /* implements Bluetooth coexistance */
3050 +#define SSB_BFL_PACTRL 0x0002 /* GPIO 9 controlling the PA */
3051 +#define SSB_BFL_AIRLINEMODE 0x0004 /* implements GPIO 13 radio disable indication */
3052 +#define SSB_BFL_RSSI 0x0008 /* software calculates nrssi slope. */
3053 +#define SSB_BFL_ENETSPI 0x0010 /* has ephy roboswitch spi */
3054 +#define SSB_BFL_XTAL_NOSLOW 0x0020 /* no slow clock available */
3055 +#define SSB_BFL_CCKHIPWR 0x0040 /* can do high power CCK transmission */
3056 +#define SSB_BFL_ENETADM 0x0080 /* has ADMtek switch */
3057 +#define SSB_BFL_ENETVLAN 0x0100 /* can do vlan */
3058 +#define SSB_BFL_AFTERBURNER 0x0200 /* supports Afterburner mode */
3059 +#define SSB_BFL_NOPCI 0x0400 /* board leaves PCI floating */
3060 +#define SSB_BFL_FEM 0x0800 /* supports the Front End Module */
3061 +#define SSB_BFL_EXTLNA 0x1000 /* has an external LNA */
3062 +#define SSB_BFL_HGPA 0x2000 /* had high gain PA */
3063 +#define SSB_BFL_BTCMOD 0x4000 /* BFL_BTCOEXIST is given in alternate GPIOs */
3064 +#define SSB_BFL_ALTIQ 0x8000 /* alternate I/Q settings */
3066 +/* Values for boardflags_hi read from SPROM */
3067 +#define SSB_BFH_NOPA 0x0001 /* has no PA */
3068 +#define SSB_BFH_RSSIINV 0x0002 /* RSSI uses positive slope (not TSSI) */
3069 +#define SSB_BFH_PAREF 0x0004 /* uses the PARef LDO */
3070 +#define SSB_BFH_3TSWITCH 0x0008 /* uses a triple throw switch shared with bluetooth */
3071 +#define SSB_BFH_PHASESHIFT 0x0010 /* can support phase shifter */
3072 +#define SSB_BFH_BUCKBOOST 0x0020 /* has buck/booster */
3073 +#define SSB_BFH_FEM_BT 0x0040 /* has FEM and switch to share antenna with bluetooth */
3075 +/* Values for boardflags2_lo read from SPROM */
3076 +#define SSB_BFL2_RXBB_INT_REG_DIS 0x0001 /* external RX BB regulator present */
3077 +#define SSB_BFL2_APLL_WAR 0x0002 /* alternative A-band PLL settings implemented */
3078 +#define SSB_BFL2_TXPWRCTRL_EN 0x0004 /* permits enabling TX Power Control */
3079 +#define SSB_BFL2_2X4_DIV 0x0008 /* 2x4 diversity switch */
3080 +#define SSB_BFL2_5G_PWRGAIN 0x0010 /* supports 5G band power gain */
3081 +#define SSB_BFL2_PCIEWAR_OVR 0x0020 /* overrides ASPM and Clkreq settings */
3082 +#define SSB_BFL2_CAESERS_BRD 0x0040 /* is Caesers board (unused) */
3083 +#define SSB_BFL2_BTC3WIRE 0x0080 /* used 3-wire bluetooth coexist */
3084 +#define SSB_BFL2_SKWRKFEM_BRD 0x0100 /* 4321mcm93 uses Skyworks FEM */
3085 +#define SSB_BFL2_SPUR_WAR 0x0200 /* has a workaround for clock-harmonic spurs */
3086 +#define SSB_BFL2_GPLL_WAR 0x0400 /* altenative G-band PLL settings implemented */
3088 /* Values for SSB_SPROM1_BINF_CCODE */
3090 --- a/include/linux/ssb/ssb_driver_chipcommon.h
3091 +++ b/include/linux/ssb/ssb_driver_chipcommon.h
3093 * gpio interface, extbus, and support for serial and parallel flashes.
3095 * Copyright 2005, Broadcom Corporation
3096 - * Copyright 2006, Michael Buesch <mb@bu3sch.de>
3097 + * Copyright 2006, Michael Buesch <m@bues.ch>
3099 * Licensed under the GPL version 2. See COPYING for details.
3102 #define SSB_CHIPCO_FLASHDATA 0x0048
3103 #define SSB_CHIPCO_BCAST_ADDR 0x0050
3104 #define SSB_CHIPCO_BCAST_DATA 0x0054
3105 +#define SSB_CHIPCO_GPIOPULLUP 0x0058 /* Rev >= 20 only */
3106 +#define SSB_CHIPCO_GPIOPULLDOWN 0x005C /* Rev >= 20 only */
3107 #define SSB_CHIPCO_GPIOIN 0x0060
3108 #define SSB_CHIPCO_GPIOOUT 0x0064
3109 #define SSB_CHIPCO_GPIOOUTEN 0x0068
3111 #define SSB_CHIPCO_GPIOIRQ 0x0074
3112 #define SSB_CHIPCO_WATCHDOG 0x0080
3113 #define SSB_CHIPCO_GPIOTIMER 0x0088 /* LED powersave (corerev >= 16) */
3114 +#define SSB_CHIPCO_GPIOTIMER_OFFTIME 0x0000FFFF
3115 +#define SSB_CHIPCO_GPIOTIMER_OFFTIME_SHIFT 0
3116 +#define SSB_CHIPCO_GPIOTIMER_ONTIME 0xFFFF0000
3117 #define SSB_CHIPCO_GPIOTIMER_ONTIME_SHIFT 16
3118 #define SSB_CHIPCO_GPIOTOUTM 0x008C /* LED powersave (corerev >= 16) */
3119 #define SSB_CHIPCO_CLOCK_N 0x0090
3120 @@ -189,8 +194,10 @@
3121 #define SSB_CHIPCO_CLKCTLST_HAVEALPREQ 0x00000008 /* ALP available request */
3122 #define SSB_CHIPCO_CLKCTLST_HAVEHTREQ 0x00000010 /* HT available request */
3123 #define SSB_CHIPCO_CLKCTLST_HWCROFF 0x00000020 /* Force HW clock request off */
3124 -#define SSB_CHIPCO_CLKCTLST_HAVEHT 0x00010000 /* HT available */
3125 -#define SSB_CHIPCO_CLKCTLST_HAVEALP 0x00020000 /* APL available */
3126 +#define SSB_CHIPCO_CLKCTLST_HAVEALP 0x00010000 /* ALP available */
3127 +#define SSB_CHIPCO_CLKCTLST_HAVEHT 0x00020000 /* HT available */
3128 +#define SSB_CHIPCO_CLKCTLST_4328A0_HAVEHT 0x00010000 /* 4328a0 has reversed bits */
3129 +#define SSB_CHIPCO_CLKCTLST_4328A0_HAVEALP 0x00020000 /* 4328a0 has reversed bits */
3130 #define SSB_CHIPCO_HW_WORKAROUND 0x01E4 /* Hardware workaround (rev >= 20) */
3131 #define SSB_CHIPCO_UART0_DATA 0x0300
3132 #define SSB_CHIPCO_UART0_IMR 0x0304
3133 --- a/drivers/ssb/b43_pci_bridge.c
3134 +++ b/drivers/ssb/b43_pci_bridge.c
3136 * because of its small size we include it in the SSB core
3137 * instead of creating a standalone module.
3139 - * Copyright 2007 Michael Buesch <mb@bu3sch.de>
3140 + * Copyright 2007 Michael Buesch <m@bues.ch>
3142 * Licensed under the GNU/GPL. See COPYING for details.
3145 #include <linux/pci.h>
3146 +#include <linux/module.h>
3147 #include <linux/ssb/ssb.h>
3149 #include "ssb_private.h"
3150 --- a/drivers/ssb/driver_extif.c
3151 +++ b/drivers/ssb/driver_extif.c
3153 * Broadcom EXTIF core driver
3155 * Copyright 2005, Broadcom Corporation
3156 - * Copyright 2006, 2007, Michael Buesch <mb@bu3sch.de>
3157 + * Copyright 2006, 2007, Michael Buesch <m@bues.ch>
3158 * Copyright 2006, 2007, Felix Fietkau <nbd@openwrt.org>
3159 * Copyright 2007, Aurelien Jarno <aurelien@aurel32.net>
3161 --- a/drivers/ssb/embedded.c
3162 +++ b/drivers/ssb/embedded.c
3164 * Embedded systems support code
3166 * Copyright 2005-2008, Broadcom Corporation
3167 - * Copyright 2006-2008, Michael Buesch <mb@bu3sch.de>
3168 + * Copyright 2006-2008, Michael Buesch <m@bues.ch>
3170 * Licensed under the GNU/GPL. See COPYING for details.
3172 --- a/drivers/ssb/sdio.c
3173 +++ b/drivers/ssb/sdio.c
3176 * Based on drivers/ssb/pcmcia.c
3177 * Copyright 2006 Johannes Berg <johannes@sipsolutions.net>
3178 - * Copyright 2007-2008 Michael Buesch <mb@bu3sch.de>
3179 + * Copyright 2007-2008 Michael Buesch <m@bues.ch>
3181 * Licensed under the GNU/GPL. See COPYING for details.
3183 @@ -551,14 +551,10 @@ int ssb_sdio_get_invariants(struct ssb_b
3184 case SSB_SDIO_CIS_ANTGAIN:
3185 GOTO_ERROR_ON(tuple->size != 2,
3187 - sprom->antenna_gain.ghz24.a0 = tuple->data[1];
3188 - sprom->antenna_gain.ghz24.a1 = tuple->data[1];
3189 - sprom->antenna_gain.ghz24.a2 = tuple->data[1];
3190 - sprom->antenna_gain.ghz24.a3 = tuple->data[1];
3191 - sprom->antenna_gain.ghz5.a0 = tuple->data[1];
3192 - sprom->antenna_gain.ghz5.a1 = tuple->data[1];
3193 - sprom->antenna_gain.ghz5.a2 = tuple->data[1];
3194 - sprom->antenna_gain.ghz5.a3 = tuple->data[1];
3195 + sprom->antenna_gain.a0 = tuple->data[1];
3196 + sprom->antenna_gain.a1 = tuple->data[1];
3197 + sprom->antenna_gain.a2 = tuple->data[1];
3198 + sprom->antenna_gain.a3 = tuple->data[1];
3200 case SSB_SDIO_CIS_BFLAGS:
3201 GOTO_ERROR_ON((tuple->size != 3) &&
3202 --- a/include/linux/ssb/ssb_driver_gige.h
3203 +++ b/include/linux/ssb/ssb_driver_gige.h
3205 #define LINUX_SSB_DRIVER_GIGE_H_
3207 #include <linux/ssb/ssb.h>
3208 +#include <linux/bug.h>
3209 #include <linux/pci.h>
3210 #include <linux/spinlock.h>