target/linux/generic/files/drivers/net/phy/rtl8366s.c

   1 /*
   2  * Platform driver for the Realtek RTL8366S ethernet switch
   3  *
   4  * Copyright (C) 2009-2010 Gabor Juhos <juhosg@openwrt.org>
   5  * Copyright (C) 2010 Antti Seppälä <a.seppala@gmail.com>
   6  *
   7  * This program is free software; you can redistribute it and/or modify it
   8  * under the terms of the GNU General Public License version 2 as published
   9  * by the Free Software Foundation.
  10  */
  11
  12 #include <linux/kernel.h>
  13 #include <linux/module.h>
  14 #include <linux/init.h>
  15 #include <linux/platform_device.h>
  16 #include <linux/delay.h>
  17 #include <linux/skbuff.h>
  18 #include <linux/rtl8366s.h>
  19
  20 #include "rtl8366_smi.h"
  21
  22 #define RTL8366S_DRIVER_DESC    "Realtek RTL8366S ethernet switch driver"
  23 #define RTL8366S_DRIVER_VER     "0.2.2"
  24
  25 #define RTL8366S_PHY_NO_MAX     4
  26 #define RTL8366S_PHY_PAGE_MAX   7
  27 #define RTL8366S_PHY_ADDR_MAX   31
  28 #define RTL8366S_PHY_WAN        4
  29
  30 /* Switch Global Configuration register */
  31 #define RTL8366S_SGCR                           0x0000
  32 #define RTL8366S_SGCR_EN_BC_STORM_CTRL          BIT(0)
  33 #define RTL8366S_SGCR_MAX_LENGTH(_x)            (_x << 4)
  34 #define RTL8366S_SGCR_MAX_LENGTH_MASK           RTL8366S_SGCR_MAX_LENGTH(0x3)
  35 #define RTL8366S_SGCR_MAX_LENGTH_1522           RTL8366S_SGCR_MAX_LENGTH(0x0)
  36 #define RTL8366S_SGCR_MAX_LENGTH_1536           RTL8366S_SGCR_MAX_LENGTH(0x1)
  37 #define RTL8366S_SGCR_MAX_LENGTH_1552           RTL8366S_SGCR_MAX_LENGTH(0x2)
  38 #define RTL8366S_SGCR_MAX_LENGTH_16000          RTL8366S_SGCR_MAX_LENGTH(0x3)
  39 #define RTL8366S_SGCR_EN_VLAN                   BIT(13)
  40
  41 /* Port Enable Control register */
  42 #define RTL8366S_PECR                           0x0001
  43
  44 /* Switch Security Control registers */
  45 #define RTL8366S_SSCR0                          0x0002
  46 #define RTL8366S_SSCR1                          0x0003
  47 #define RTL8366S_SSCR2                          0x0004
  48 #define RTL8366S_SSCR2_DROP_UNKNOWN_DA          BIT(0)
  49
  50 #define RTL8366S_RESET_CTRL_REG                 0x0100
  51 #define RTL8366S_CHIP_CTRL_RESET_HW             1
  52 #define RTL8366S_CHIP_CTRL_RESET_SW             (1 << 1)
  53
  54 #define RTL8366S_CHIP_VERSION_CTRL_REG          0x0104
  55 #define RTL8366S_CHIP_VERSION_MASK              0xf
  56 #define RTL8366S_CHIP_ID_REG                    0x0105
  57 #define RTL8366S_CHIP_ID_8366                   0x8366
  58
  59 /* PHY registers control */
  60 #define RTL8366S_PHY_ACCESS_CTRL_REG            0x8028
  61 #define RTL8366S_PHY_ACCESS_DATA_REG            0x8029
  62
  63 #define RTL8366S_PHY_CTRL_READ                  1
  64 #define RTL8366S_PHY_CTRL_WRITE                 0
  65
  66 #define RTL8366S_PHY_REG_MASK                   0x1f
  67 #define RTL8366S_PHY_PAGE_OFFSET                5
  68 #define RTL8366S_PHY_PAGE_MASK                  (0x7 << 5)
  69 #define RTL8366S_PHY_NO_OFFSET                  9
  70 #define RTL8366S_PHY_NO_MASK                    (0x1f << 9)
  71
  72 /* LED control registers */
  73 #define RTL8366S_LED_BLINKRATE_REG              0x0420
  74 #define RTL8366S_LED_BLINKRATE_BIT              0
  75 #define RTL8366S_LED_BLINKRATE_MASK             0x0007
  76
  77 #define RTL8366S_LED_CTRL_REG                   0x0421
  78 #define RTL8366S_LED_0_1_CTRL_REG               0x0422
  79 #define RTL8366S_LED_2_3_CTRL_REG               0x0423
  80
  81 #define RTL8366S_MIB_COUNT                      33
  82 #define RTL8366S_GLOBAL_MIB_COUNT               1
  83 #define RTL8366S_MIB_COUNTER_PORT_OFFSET        0x0040
  84 #define RTL8366S_MIB_COUNTER_BASE               0x1000
  85 #define RTL8366S_MIB_COUNTER_PORT_OFFSET2       0x0008
  86 #define RTL8366S_MIB_COUNTER_BASE2              0x1180
  87 #define RTL8366S_MIB_CTRL_REG                   0x11F0
  88 #define RTL8366S_MIB_CTRL_USER_MASK             0x01FF
  89 #define RTL8366S_MIB_CTRL_BUSY_MASK             0x0001
  90 #define RTL8366S_MIB_CTRL_RESET_MASK            0x0002
  91
  92 #define RTL8366S_MIB_CTRL_GLOBAL_RESET_MASK     0x0004
  93 #define RTL8366S_MIB_CTRL_PORT_RESET_BIT        0x0003
  94 #define RTL8366S_MIB_CTRL_PORT_RESET_MASK       0x01FC
  95
  96
  97 #define RTL8366S_PORT_VLAN_CTRL_BASE            0x0058
  98 #define RTL8366S_PORT_VLAN_CTRL_REG(_p)  \
  99                 (RTL8366S_PORT_VLAN_CTRL_BASE + (_p) / 4)
 100 #define RTL8366S_PORT_VLAN_CTRL_MASK            0xf
 101 #define RTL8366S_PORT_VLAN_CTRL_SHIFT(_p)       (4 * ((_p) % 4))
 102
 103
 104 #define RTL8366S_VLAN_TABLE_READ_BASE           0x018B
 105 #define RTL8366S_VLAN_TABLE_WRITE_BASE          0x0185
 106
 107 #define RTL8366S_VLAN_TB_CTRL_REG               0x010F
 108
 109 #define RTL8366S_TABLE_ACCESS_CTRL_REG          0x0180
 110 #define RTL8366S_TABLE_VLAN_READ_CTRL           0x0E01
 111 #define RTL8366S_TABLE_VLAN_WRITE_CTRL          0x0F01
 112
 113 #define RTL8366S_VLAN_MC_BASE(_x)               (0x0016 + (_x) * 2)
 114
 115 #define RTL8366S_VLAN_MEMBERINGRESS_REG         0x0379
 116
 117 #define RTL8366S_PORT_LINK_STATUS_BASE          0x0060
 118 #define RTL8366S_PORT_STATUS_SPEED_MASK         0x0003
 119 #define RTL8366S_PORT_STATUS_DUPLEX_MASK        0x0004
 120 #define RTL8366S_PORT_STATUS_LINK_MASK          0x0010
 121 #define RTL8366S_PORT_STATUS_TXPAUSE_MASK       0x0020
 122 #define RTL8366S_PORT_STATUS_RXPAUSE_MASK       0x0040
 123 #define RTL8366S_PORT_STATUS_AN_MASK            0x0080
 124
 125
 126 #define RTL8366S_PORT_NUM_CPU           5
 127 #define RTL8366S_NUM_PORTS              6
 128 #define RTL8366S_NUM_VLANS              16
 129 #define RTL8366S_NUM_LEDGROUPS          4
 130 #define RTL8366S_NUM_VIDS               4096
 131 #define RTL8366S_PRIORITYMAX            7
 132 #define RTL8366S_FIDMAX                 7
 133
 134
 135 #define RTL8366S_PORT_1                 (1 << 0) /* In userspace port 0 */
 136 #define RTL8366S_PORT_2                 (1 << 1) /* In userspace port 1 */
 137 #define RTL8366S_PORT_3                 (1 << 2) /* In userspace port 2 */
 138 #define RTL8366S_PORT_4                 (1 << 3) /* In userspace port 3 */
 139
 140 #define RTL8366S_PORT_UNKNOWN           (1 << 4) /* No known connection */
 141 #define RTL8366S_PORT_CPU               (1 << 5) /* CPU port */
 142
 143 #define RTL8366S_PORT_ALL               (RTL8366S_PORT_1 |      \
 144                                          RTL8366S_PORT_2 |      \
 145                                          RTL8366S_PORT_3 |      \
 146                                          RTL8366S_PORT_4 |      \
 147                                          RTL8366S_PORT_UNKNOWN | \
 148                                          RTL8366S_PORT_CPU)
 149
 150 #define RTL8366S_PORT_ALL_BUT_CPU       (RTL8366S_PORT_1 |      \
 151                                          RTL8366S_PORT_2 |      \
 152                                          RTL8366S_PORT_3 |      \
 153                                          RTL8366S_PORT_4 |      \
 154                                          RTL8366S_PORT_UNKNOWN)
 155
 156 #define RTL8366S_PORT_ALL_EXTERNAL      (RTL8366S_PORT_1 |      \
 157                                          RTL8366S_PORT_2 |      \
 158                                          RTL8366S_PORT_3 |      \
 159                                          RTL8366S_PORT_4)
 160
 161 #define RTL8366S_PORT_ALL_INTERNAL      (RTL8366S_PORT_UNKNOWN | \
 162                                          RTL8366S_PORT_CPU)
 163
 164 #define RTL8366S_VLAN_VID_MASK          0xfff
 165 #define RTL8366S_VLAN_PRIORITY_SHIFT    12
 166 #define RTL8366S_VLAN_PRIORITY_MASK     0x7
 167 #define RTL8366S_VLAN_MEMBER_MASK       0x3f
 168 #define RTL8366S_VLAN_UNTAG_SHIFT       6
 169 #define RTL8366S_VLAN_UNTAG_MASK        0x3f
 170 #define RTL8366S_VLAN_FID_SHIFT         12
 171 #define RTL8366S_VLAN_FID_MASK          0x7
 172
 173 static struct rtl8366_mib_counter rtl8366s_mib_counters[] = {
 174         { 0,  0, 4, "IfInOctets"                                },
 175         { 0,  4, 4, "EtherStatsOctets"                          },
 176         { 0,  8, 2, "EtherStatsUnderSizePkts"                   },
 177         { 0, 10, 2, "EtherFragments"                            },
 178         { 0, 12, 2, "EtherStatsPkts64Octets"                    },
 179         { 0, 14, 2, "EtherStatsPkts65to127Octets"               },
 180         { 0, 16, 2, "EtherStatsPkts128to255Octets"              },
 181         { 0, 18, 2, "EtherStatsPkts256to511Octets"              },
 182         { 0, 20, 2, "EtherStatsPkts512to1023Octets"             },
 183         { 0, 22, 2, "EtherStatsPkts1024to1518Octets"            },
 184         { 0, 24, 2, "EtherOversizeStats"                        },
 185         { 0, 26, 2, "EtherStatsJabbers"                         },
 186         { 0, 28, 2, "IfInUcastPkts"                             },
 187         { 0, 30, 2, "EtherStatsMulticastPkts"                   },
 188         { 0, 32, 2, "EtherStatsBroadcastPkts"                   },
 189         { 0, 34, 2, "EtherStatsDropEvents"                      },
 190         { 0, 36, 2, "Dot3StatsFCSErrors"                        },
 191         { 0, 38, 2, "Dot3StatsSymbolErrors"                     },
 192         { 0, 40, 2, "Dot3InPauseFrames"                         },
 193         { 0, 42, 2, "Dot3ControlInUnknownOpcodes"               },
 194         { 0, 44, 4, "IfOutOctets"                               },
 195         { 0, 48, 2, "Dot3StatsSingleCollisionFrames"            },
 196         { 0, 50, 2, "Dot3StatMultipleCollisionFrames"           },
 197         { 0, 52, 2, "Dot3sDeferredTransmissions"                },
 198         { 0, 54, 2, "Dot3StatsLateCollisions"                   },
 199         { 0, 56, 2, "EtherStatsCollisions"                      },
 200         { 0, 58, 2, "Dot3StatsExcessiveCollisions"              },
 201         { 0, 60, 2, "Dot3OutPauseFrames"                        },
 202         { 0, 62, 2, "Dot1dBasePortDelayExceededDiscards"        },
 203
 204         /*
 205          * The following counters are accessible at a different
 206          * base address.
 207          */
 208         { 1,  0, 2, "Dot1dTpPortInDiscards"                     },
 209         { 1,  2, 2, "IfOutUcastPkts"                            },
 210         { 1,  4, 2, "IfOutMulticastPkts"                        },
 211         { 1,  6, 2, "IfOutBroadcastPkts"                        },
 212 };
 213
 214 #define REG_WR(_smi, _reg, _val)                                        \
 215         do {                                                            \
 216                 err = rtl8366_smi_write_reg(_smi, _reg, _val);          \
 217                 if (err)                                                \
 218                         return err;                                     \
 219         } while (0)
 220
 221 #define REG_RMW(_smi, _reg, _mask, _val)                                \
 222         do {                                                            \
 223                 err = rtl8366_smi_rmwr(_smi, _reg, _mask, _val);        \
 224                 if (err)                                                \
 225                         return err;                                     \
 226         } while (0)
 227
 228 static int rtl8366s_reset_chip(struct rtl8366_smi *smi)
 229 {
 230         int timeout = 10;
 231         u32 data;
 232
 233         rtl8366_smi_write_reg(smi, RTL8366S_RESET_CTRL_REG,
 234                               RTL8366S_CHIP_CTRL_RESET_HW);
 235         do {
 236                 msleep(1);
 237                 if (rtl8366_smi_read_reg(smi, RTL8366S_RESET_CTRL_REG, &data))
 238                         return -EIO;
 239
 240                 if (!(data & RTL8366S_CHIP_CTRL_RESET_HW))
 241                         break;
 242         } while (--timeout);
 243
 244         if (!timeout) {
 245                 printk("Timeout waiting for the switch to reset\n");
 246                 return -EIO;
 247         }
 248
 249         return 0;
 250 }
 251
 252 static int rtl8366s_hw_init(struct rtl8366_smi *smi)
 253 {
 254         int err;
 255
 256         /* set maximum packet length to 1536 bytes */
 257         REG_RMW(smi, RTL8366S_SGCR, RTL8366S_SGCR_MAX_LENGTH_MASK,
 258                 RTL8366S_SGCR_MAX_LENGTH_1536);
 259
 260         /* enable learning for all ports */
 261         REG_WR(smi, RTL8366S_SSCR0, 0);
 262
 263         /* enable auto ageing for all ports */
 264         REG_WR(smi, RTL8366S_SSCR1, 0);
 265
 266         /*
 267          * discard VLAN tagged packets if the port is not a member of
 268          * the VLAN with which the packets is associated.
 269          */
 270         REG_WR(smi, RTL8366S_VLAN_MEMBERINGRESS_REG, RTL8366S_PORT_ALL);
 271
 272         /* don't drop packets whose DA has not been learned */
 273         REG_RMW(smi, RTL8366S_SSCR2, RTL8366S_SSCR2_DROP_UNKNOWN_DA, 0);
 274
 275         return 0;
 276 }
 277
 278 static int rtl8366s_read_phy_reg(struct rtl8366_smi *smi,
 279                                  u32 phy_no, u32 page, u32 addr, u32 *data)
 280 {
 281         u32 reg;
 282         int ret;
 283
 284         if (phy_no > RTL8366S_PHY_NO_MAX)
 285                 return -EINVAL;
 286
 287         if (page > RTL8366S_PHY_PAGE_MAX)
 288                 return -EINVAL;
 289
 290         if (addr > RTL8366S_PHY_ADDR_MAX)
 291                 return -EINVAL;
 292
 293         ret = rtl8366_smi_write_reg(smi, RTL8366S_PHY_ACCESS_CTRL_REG,
 294                                     RTL8366S_PHY_CTRL_READ);
 295         if (ret)
 296                 return ret;
 297
 298         reg = 0x8000 | (1 << (phy_no + RTL8366S_PHY_NO_OFFSET)) |
 299               ((page << RTL8366S_PHY_PAGE_OFFSET) & RTL8366S_PHY_PAGE_MASK) |
 300               (addr & RTL8366S_PHY_REG_MASK);
 301
 302         ret = rtl8366_smi_write_reg(smi, reg, 0);
 303         if (ret)
 304                 return ret;
 305
 306         ret = rtl8366_smi_read_reg(smi, RTL8366S_PHY_ACCESS_DATA_REG, data);
 307         if (ret)
 308                 return ret;
 309
 310         return 0;
 311 }
 312
 313 static int rtl8366s_write_phy_reg(struct rtl8366_smi *smi,
 314                                   u32 phy_no, u32 page, u32 addr, u32 data)
 315 {
 316         u32 reg;
 317         int ret;
 318
 319         if (phy_no > RTL8366S_PHY_NO_MAX)
 320                 return -EINVAL;
 321
 322         if (page > RTL8366S_PHY_PAGE_MAX)
 323                 return -EINVAL;
 324
 325         if (addr > RTL8366S_PHY_ADDR_MAX)
 326                 return -EINVAL;
 327
 328         ret = rtl8366_smi_write_reg(smi, RTL8366S_PHY_ACCESS_CTRL_REG,
 329                                     RTL8366S_PHY_CTRL_WRITE);
 330         if (ret)
 331                 return ret;
 332
 333         reg = 0x8000 | (1 << (phy_no + RTL8366S_PHY_NO_OFFSET)) |
 334               ((page << RTL8366S_PHY_PAGE_OFFSET) & RTL8366S_PHY_PAGE_MASK) |
 335               (addr & RTL8366S_PHY_REG_MASK);
 336
 337         ret = rtl8366_smi_write_reg(smi, reg, data);
 338         if (ret)
 339                 return ret;
 340
 341         return 0;
 342 }
 343
 344 static int rtl8366_get_mib_counter(struct rtl8366_smi *smi, int counter,
 345                                    int port, unsigned long long *val)
 346 {
 347         int i;
 348         int err;
 349         u32 addr, data;
 350         u64 mibvalue;
 351
 352         if (port > RTL8366S_NUM_PORTS || counter >= RTL8366S_MIB_COUNT)
 353                 return -EINVAL;
 354
 355         switch (rtl8366s_mib_counters[counter].base) {
 356         case 0:
 357                 addr = RTL8366S_MIB_COUNTER_BASE +
 358                        RTL8366S_MIB_COUNTER_PORT_OFFSET * port;
 359                 break;
 360
 361         case 1:
 362                 addr = RTL8366S_MIB_COUNTER_BASE2 +
 363                         RTL8366S_MIB_COUNTER_PORT_OFFSET2 * port;
 364                 break;
 365
 366         default:
 367                 return -EINVAL;
 368         }
 369
 370         addr += rtl8366s_mib_counters[counter].offset;
 371
 372         /*
 373          * Writing access counter address first
 374          * then ASIC will prepare 64bits counter wait for being retrived
 375          */
 376         data = 0; /* writing data will be discard by ASIC */
 377         err = rtl8366_smi_write_reg(smi, addr, data);
 378         if (err)
 379                 return err;
 380
 381         /* read MIB control register */
 382         err =  rtl8366_smi_read_reg(smi, RTL8366S_MIB_CTRL_REG, &data);
 383         if (err)
 384                 return err;
 385
 386         if (data & RTL8366S_MIB_CTRL_BUSY_MASK)
 387                 return -EBUSY;
 388
 389         if (data & RTL8366S_MIB_CTRL_RESET_MASK)
 390                 return -EIO;
 391
 392         mibvalue = 0;
 393         for (i = rtl8366s_mib_counters[counter].length; i > 0; i--) {
 394                 err = rtl8366_smi_read_reg(smi, addr + (i - 1), &data);
 395                 if (err)
 396                         return err;
 397
 398                 mibvalue = (mibvalue << 16) | (data & 0xFFFF);
 399         }
 400
 401         *val = mibvalue;
 402         return 0;
 403 }
 404
 405 static int rtl8366s_get_vlan_4k(struct rtl8366_smi *smi, u32 vid,
 406                                 struct rtl8366_vlan_4k *vlan4k)
 407 {
 408         u32 data[2];
 409         int err;
 410         int i;
 411
 412         memset(vlan4k, '\0', sizeof(struct rtl8366_vlan_4k));
 413
 414         if (vid >= RTL8366S_NUM_VIDS)
 415                 return -EINVAL;
 416
 417         /* write VID */
 418         err = rtl8366_smi_write_reg(smi, RTL8366S_VLAN_TABLE_WRITE_BASE,
 419                                     vid & RTL8366S_VLAN_VID_MASK);
 420         if (err)
 421                 return err;
 422
 423         /* write table access control word */
 424         err = rtl8366_smi_write_reg(smi, RTL8366S_TABLE_ACCESS_CTRL_REG,
 425                                     RTL8366S_TABLE_VLAN_READ_CTRL);
 426         if (err)
 427                 return err;
 428
 429         for (i = 0; i < 2; i++) {
 430                 err = rtl8366_smi_read_reg(smi,
 431                                            RTL8366S_VLAN_TABLE_READ_BASE + i,
 432                                            &data[i]);
 433                 if (err)
 434                         return err;
 435         }
 436
 437         vlan4k->vid = vid;
 438         vlan4k->untag = (data[1] >> RTL8366S_VLAN_UNTAG_SHIFT) &
 439                         RTL8366S_VLAN_UNTAG_MASK;
 440         vlan4k->member = data[1] & RTL8366S_VLAN_MEMBER_MASK;
 441         vlan4k->fid = (data[1] >> RTL8366S_VLAN_FID_SHIFT) &
 442                         RTL8366S_VLAN_FID_MASK;
 443
 444         return 0;
 445 }
 446
 447 static int rtl8366s_set_vlan_4k(struct rtl8366_smi *smi,
 448                                 const struct rtl8366_vlan_4k *vlan4k)
 449 {
 450         u32 data[2];
 451         int err;
 452         int i;
 453
 454         if (vlan4k->vid >= RTL8366S_NUM_VIDS ||
 455             vlan4k->member > RTL8366S_VLAN_MEMBER_MASK ||
 456             vlan4k->untag > RTL8366S_VLAN_UNTAG_MASK ||
 457             vlan4k->fid > RTL8366S_FIDMAX)
 458                 return -EINVAL;
 459
 460         data[0] = vlan4k->vid & RTL8366S_VLAN_VID_MASK;
 461         data[1] = (vlan4k->member & RTL8366S_VLAN_MEMBER_MASK) |
 462                   ((vlan4k->untag & RTL8366S_VLAN_UNTAG_MASK) <<
 463                         RTL8366S_VLAN_UNTAG_SHIFT) |
 464                   ((vlan4k->fid & RTL8366S_VLAN_FID_MASK) <<
 465                         RTL8366S_VLAN_FID_SHIFT);
 466
 467         for (i = 0; i < 2; i++) {
 468                 err = rtl8366_smi_write_reg(smi,
 469                                             RTL8366S_VLAN_TABLE_WRITE_BASE + i,
 470                                             data[i]);
 471                 if (err)
 472                         return err;
 473         }
 474
 475         /* write table access control word */
 476         err = rtl8366_smi_write_reg(smi, RTL8366S_TABLE_ACCESS_CTRL_REG,
 477                                     RTL8366S_TABLE_VLAN_WRITE_CTRL);
 478
 479         return err;
 480 }
 481
 482 static int rtl8366s_get_vlan_mc(struct rtl8366_smi *smi, u32 index,
 483                                 struct rtl8366_vlan_mc *vlanmc)
 484 {
 485         u32 data[2];
 486         int err;
 487         int i;
 488
 489         memset(vlanmc, '\0', sizeof(struct rtl8366_vlan_mc));
 490
 491         if (index >= RTL8366S_NUM_VLANS)
 492                 return -EINVAL;
 493
 494         for (i = 0; i < 2; i++) {
 495                 err = rtl8366_smi_read_reg(smi,
 496                                            RTL8366S_VLAN_MC_BASE(index) + i,
 497                                            &data[i]);
 498                 if (err)
 499                         return err;
 500         }
 501
 502         vlanmc->vid = data[0] & RTL8366S_VLAN_VID_MASK;
 503         vlanmc->priority = (data[0] >> RTL8366S_VLAN_PRIORITY_SHIFT) &
 504                            RTL8366S_VLAN_PRIORITY_MASK;
 505         vlanmc->untag = (data[1] >> RTL8366S_VLAN_UNTAG_SHIFT) &
 506                         RTL8366S_VLAN_UNTAG_MASK;
 507         vlanmc->member = data[1] & RTL8366S_VLAN_MEMBER_MASK;
 508         vlanmc->fid = (data[1] >> RTL8366S_VLAN_FID_SHIFT) &
 509                       RTL8366S_VLAN_FID_MASK;
 510
 511         return 0;
 512 }
 513
 514 static int rtl8366s_set_vlan_mc(struct rtl8366_smi *smi, u32 index,
 515                                 const struct rtl8366_vlan_mc *vlanmc)
 516 {
 517         u32 data[2];
 518         int err;
 519         int i;
 520
 521         if (index >= RTL8366S_NUM_VLANS ||
 522             vlanmc->vid >= RTL8366S_NUM_VIDS ||
 523             vlanmc->priority > RTL8366S_PRIORITYMAX ||
 524             vlanmc->member > RTL8366S_VLAN_MEMBER_MASK ||
 525             vlanmc->untag > RTL8366S_VLAN_UNTAG_MASK ||
 526             vlanmc->fid > RTL8366S_FIDMAX)
 527                 return -EINVAL;
 528
 529         data[0] = (vlanmc->vid & RTL8366S_VLAN_VID_MASK) |
 530                   ((vlanmc->priority & RTL8366S_VLAN_PRIORITY_MASK) <<
 531                         RTL8366S_VLAN_PRIORITY_SHIFT);
 532         data[1] = (vlanmc->member & RTL8366S_VLAN_MEMBER_MASK) |
 533                   ((vlanmc->untag & RTL8366S_VLAN_UNTAG_MASK) <<
 534                         RTL8366S_VLAN_UNTAG_SHIFT) |
 535                   ((vlanmc->fid & RTL8366S_VLAN_FID_MASK) <<
 536                         RTL8366S_VLAN_FID_SHIFT);
 537
 538         for (i = 0; i < 2; i++) {
 539                 err = rtl8366_smi_write_reg(smi,
 540                                             RTL8366S_VLAN_MC_BASE(index) + i,
 541                                             data[i]);
 542                 if (err)
 543                         return err;
 544         }
 545
 546         return 0;
 547 }
 548
 549 static int rtl8366s_get_mc_index(struct rtl8366_smi *smi, int port, int *val)
 550 {
 551         u32 data;
 552         int err;
 553
 554         if (port >= RTL8366S_NUM_PORTS)
 555                 return -EINVAL;
 556
 557         err = rtl8366_smi_read_reg(smi, RTL8366S_PORT_VLAN_CTRL_REG(port),
 558                                    &data);
 559         if (err)
 560                 return err;
 561
 562         *val = (data >> RTL8366S_PORT_VLAN_CTRL_SHIFT(port)) &
 563                RTL8366S_PORT_VLAN_CTRL_MASK;
 564
 565         return 0;
 566 }
 567
 568 static int rtl8366s_set_mc_index(struct rtl8366_smi *smi, int port, int index)
 569 {
 570         if (port >= RTL8366S_NUM_PORTS || index >= RTL8366S_NUM_VLANS)
 571                 return -EINVAL;
 572
 573         return rtl8366_smi_rmwr(smi, RTL8366S_PORT_VLAN_CTRL_REG(port),
 574                                 RTL8366S_PORT_VLAN_CTRL_MASK <<
 575                                         RTL8366S_PORT_VLAN_CTRL_SHIFT(port),
 576                                 (index & RTL8366S_PORT_VLAN_CTRL_MASK) <<
 577                                         RTL8366S_PORT_VLAN_CTRL_SHIFT(port));
 578 }
 579
 580 static int rtl8366s_enable_vlan(struct rtl8366_smi *smi, int enable)
 581 {
 582         return rtl8366_smi_rmwr(smi, RTL8366S_SGCR, RTL8366S_SGCR_EN_VLAN,
 583                                 (enable) ? RTL8366S_SGCR_EN_VLAN : 0);
 584 }
 585
 586 static int rtl8366s_enable_vlan4k(struct rtl8366_smi *smi, int enable)
 587 {
 588         return rtl8366_smi_rmwr(smi, RTL8366S_VLAN_TB_CTRL_REG,
 589                                 1, (enable) ? 1 : 0);
 590 }
 591
 592 static int rtl8366s_is_vlan_valid(struct rtl8366_smi *smi, unsigned vlan)
 593 {
 594         unsigned max = RTL8366S_NUM_VLANS;
 595
 596         if (smi->vlan4k_enabled)
 597                 max = RTL8366S_NUM_VIDS - 1;
 598
 599         if (vlan == 0 || vlan >= max)
 600                 return 0;
 601
 602         return 1;
 603 }
 604
 605 static int rtl8366s_enable_port(struct rtl8366_smi *smi, int port, int enable)
 606 {
 607         return rtl8366_smi_rmwr(smi, RTL8366S_PECR, (1 << port),
 608                                 (enable) ? 0 : (1 << port));
 609 }
 610
 611 static int rtl8366s_sw_reset_mibs(struct switch_dev *dev,
 612                                   const struct switch_attr *attr,
 613                                   struct switch_val *val)
 614 {
 615         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
 616
 617         return rtl8366_smi_rmwr(smi, RTL8366S_MIB_CTRL_REG, 0, (1 << 2));
 618 }
 619
 620 static int rtl8366s_sw_get_blinkrate(struct switch_dev *dev,
 621                                      const struct switch_attr *attr,
 622                                      struct switch_val *val)
 623 {
 624         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
 625         u32 data;
 626
 627         rtl8366_smi_read_reg(smi, RTL8366S_LED_BLINKRATE_REG, &data);
 628
 629         val->value.i = (data & (RTL8366S_LED_BLINKRATE_MASK));
 630
 631         return 0;
 632 }
 633
 634 static int rtl8366s_sw_set_blinkrate(struct switch_dev *dev,
 635                                     const struct switch_attr *attr,
 636                                     struct switch_val *val)
 637 {
 638         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
 639
 640         if (val->value.i >= 6)
 641                 return -EINVAL;
 642
 643         return rtl8366_smi_rmwr(smi, RTL8366S_LED_BLINKRATE_REG,
 644                                 RTL8366S_LED_BLINKRATE_MASK,
 645                                 val->value.i);
 646 }
 647
 648 static int rtl8366s_sw_get_learning_enable(struct switch_dev *dev,
 649                                            const struct switch_attr *attr,
 650                                            struct switch_val *val)
 651 {
 652         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
 653         u32 data;
 654
 655         rtl8366_smi_read_reg(smi,RTL8366S_SSCR0, &data);
 656         val->value.i = !data;
 657
 658         return 0;
 659 }
 660
 661
 662 static int rtl8366s_sw_set_learning_enable(struct switch_dev *dev,
 663                                            const struct switch_attr *attr,
 664                                            struct switch_val *val)
 665 {
 666         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
 667         u32 portmask = 0;
 668         int err = 0;
 669
 670         if (!val->value.i)
 671                 portmask = RTL8366S_PORT_ALL;
 672
 673         /* set learning for all ports */
 674         REG_WR(smi, RTL8366S_SSCR0, portmask);
 675
 676         /* set auto ageing for all ports */
 677         REG_WR(smi, RTL8366S_SSCR1, portmask);
 678
 679         return 0;
 680 }
 681
 682
 683 static const char *rtl8366s_speed_str(unsigned speed)
 684 {
 685         switch (speed) {
 686         case 0:
 687                 return "10baseT";
 688         case 1:
 689                 return "100baseT";
 690         case 2:
 691                 return "1000baseT";
 692         }
 693
 694         return "unknown";
 695 }
 696
 697 static int rtl8366s_sw_get_port_link(struct switch_dev *dev,
 698                                      const struct switch_attr *attr,
 699                                      struct switch_val *val)
 700 {
 701         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
 702         u32 len = 0, data = 0;
 703
 704         if (val->port_vlan >= RTL8366S_NUM_PORTS)
 705                 return -EINVAL;
 706
 707         memset(smi->buf, '\0', sizeof(smi->buf));
 708         rtl8366_smi_read_reg(smi, RTL8366S_PORT_LINK_STATUS_BASE +
 709                              (val->port_vlan / 2), &data);
 710
 711         if (val->port_vlan % 2)
 712                 data = data >> 8;
 713
 714         if (data & RTL8366S_PORT_STATUS_LINK_MASK) {
 715                 len = snprintf(smi->buf, sizeof(smi->buf),
 716                                 "port:%d link:up speed:%s %s-duplex %s%s%s",
 717                                 val->port_vlan,
 718                                 rtl8366s_speed_str(data &
 719                                           RTL8366S_PORT_STATUS_SPEED_MASK),
 720                                 (data & RTL8366S_PORT_STATUS_DUPLEX_MASK) ?
 721                                         "full" : "half",
 722                                 (data & RTL8366S_PORT_STATUS_TXPAUSE_MASK) ?
 723                                         "tx-pause ": "",
 724                                 (data & RTL8366S_PORT_STATUS_RXPAUSE_MASK) ?
 725                                         "rx-pause " : "",
 726                                 (data & RTL8366S_PORT_STATUS_AN_MASK) ?
 727                                         "nway ": "");
 728         } else {
 729                 len = snprintf(smi->buf, sizeof(smi->buf), "port:%d link: down",
 730                                 val->port_vlan);
 731         }
 732
 733         val->value.s = smi->buf;
 734         val->len = len;
 735
 736         return 0;
 737 }
 738
 739 static int rtl8366s_sw_set_port_led(struct switch_dev *dev,
 740                                     const struct switch_attr *attr,
 741                                     struct switch_val *val)
 742 {
 743         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
 744         u32 data;
 745         u32 mask;
 746         u32 reg;
 747
 748         if (val->port_vlan >= RTL8366S_NUM_PORTS ||
 749             (1 << val->port_vlan) == RTL8366S_PORT_UNKNOWN)
 750                 return -EINVAL;
 751
 752         if (val->port_vlan == RTL8366S_PORT_NUM_CPU) {
 753                 reg = RTL8366S_LED_BLINKRATE_REG;
 754                 mask = 0xF << 4;
 755                 data = val->value.i << 4;
 756         } else {
 757                 reg = RTL8366S_LED_CTRL_REG;
 758                 mask = 0xF << (val->port_vlan * 4),
 759                 data = val->value.i << (val->port_vlan * 4);
 760         }
 761
 762         return rtl8366_smi_rmwr(smi, reg, mask, data);
 763 }
 764
 765 static int rtl8366s_sw_get_port_led(struct switch_dev *dev,
 766                                     const struct switch_attr *attr,
 767                                     struct switch_val *val)
 768 {
 769         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
 770         u32 data = 0;
 771
 772         if (val->port_vlan >= RTL8366S_NUM_LEDGROUPS)
 773                 return -EINVAL;
 774
 775         rtl8366_smi_read_reg(smi, RTL8366S_LED_CTRL_REG, &data);
 776         val->value.i = (data >> (val->port_vlan * 4)) & 0x000F;
 777
 778         return 0;
 779 }
 780
 781 static int rtl8366s_sw_reset_port_mibs(struct switch_dev *dev,
 782                                        const struct switch_attr *attr,
 783                                        struct switch_val *val)
 784 {
 785         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
 786
 787         if (val->port_vlan >= RTL8366S_NUM_PORTS)
 788                 return -EINVAL;
 789
 790
 791         return rtl8366_smi_rmwr(smi, RTL8366S_MIB_CTRL_REG,
 792                                 0, (1 << (val->port_vlan + 3)));
 793 }
 794
 795 static int rtl8366s_sw_reset_switch(struct switch_dev *dev)
 796 {
 797         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
 798         int err;
 799
 800         err = rtl8366s_reset_chip(smi);
 801         if (err)
 802                 return err;
 803
 804         err = rtl8366s_hw_init(smi);
 805         if (err)
 806                 return err;
 807
 808         err = rtl8366_reset_vlan(smi);
 809         if (err)
 810                 return err;
 811
 812         return rtl8366_enable_all_ports(smi, 1);
 813 }
 814
 815 static struct switch_attr rtl8366s_globals[] = {
 816         {
 817                 .type = SWITCH_TYPE_INT,
 818                 .name = "enable_learning",
 819                 .description = "Enable learning, enable aging",
 820                 .set = rtl8366s_sw_set_learning_enable,
 821                 .get = rtl8366s_sw_get_learning_enable,
 822                 .max = 1,
 823         }, {
 824                 .type = SWITCH_TYPE_INT,
 825                 .name = "enable_vlan",
 826                 .description = "Enable VLAN mode",
 827                 .set = rtl8366_sw_set_vlan_enable,
 828                 .get = rtl8366_sw_get_vlan_enable,
 829                 .max = 1,
 830                 .ofs = 1
 831         }, {
 832                 .type = SWITCH_TYPE_INT,
 833                 .name = "enable_vlan4k",
 834                 .description = "Enable VLAN 4K mode",
 835                 .set = rtl8366_sw_set_vlan_enable,
 836                 .get = rtl8366_sw_get_vlan_enable,
 837                 .max = 1,
 838                 .ofs = 2
 839         }, {
 840                 .type = SWITCH_TYPE_NOVAL,
 841                 .name = "reset_mibs",
 842                 .description = "Reset all MIB counters",
 843                 .set = rtl8366s_sw_reset_mibs,
 844         }, {
 845                 .type = SWITCH_TYPE_INT,
 846                 .name = "blinkrate",
 847                 .description = "Get/Set LED blinking rate (0 = 43ms, 1 = 84ms,"
 848                 " 2 = 120ms, 3 = 170ms, 4 = 340ms, 5 = 670ms)",
 849                 .set = rtl8366s_sw_set_blinkrate,
 850                 .get = rtl8366s_sw_get_blinkrate,
 851                 .max = 5
 852         },
 853 };
 854
 855 static struct switch_attr rtl8366s_port[] = {
 856         {
 857                 .type = SWITCH_TYPE_STRING,
 858                 .name = "link",
 859                 .description = "Get port link information",
 860                 .max = 1,
 861                 .set = NULL,
 862                 .get = rtl8366s_sw_get_port_link,
 863         }, {
 864                 .type = SWITCH_TYPE_NOVAL,
 865                 .name = "reset_mib",
 866                 .description = "Reset single port MIB counters",
 867                 .set = rtl8366s_sw_reset_port_mibs,
 868         }, {
 869                 .type = SWITCH_TYPE_STRING,
 870                 .name = "mib",
 871                 .description = "Get MIB counters for port",
 872                 .max = 33,
 873                 .set = NULL,
 874                 .get = rtl8366_sw_get_port_mib,
 875         }, {
 876                 .type = SWITCH_TYPE_INT,
 877                 .name = "led",
 878                 .description = "Get/Set port group (0 - 3) led mode (0 - 15)",
 879                 .max = 15,
 880                 .set = rtl8366s_sw_set_port_led,
 881                 .get = rtl8366s_sw_get_port_led,
 882         },
 883 };
 884
 885 static struct switch_attr rtl8366s_vlan[] = {
 886         {
 887                 .type = SWITCH_TYPE_STRING,
 888                 .name = "info",
 889                 .description = "Get vlan information",
 890                 .max = 1,
 891                 .set = NULL,
 892                 .get = rtl8366_sw_get_vlan_info,
 893         }, {
 894                 .type = SWITCH_TYPE_INT,
 895                 .name = "fid",
 896                 .description = "Get/Set vlan FID",
 897                 .max = RTL8366S_FIDMAX,
 898                 .set = rtl8366_sw_set_vlan_fid,
 899                 .get = rtl8366_sw_get_vlan_fid,
 900         },
 901 };
 902
 903 static const struct switch_dev_ops rtl8366_ops = {
 904         .attr_global = {
 905                 .attr = rtl8366s_globals,
 906                 .n_attr = ARRAY_SIZE(rtl8366s_globals),
 907         },
 908         .attr_port = {
 909                 .attr = rtl8366s_port,
 910                 .n_attr = ARRAY_SIZE(rtl8366s_port),
 911         },
 912         .attr_vlan = {
 913                 .attr = rtl8366s_vlan,
 914                 .n_attr = ARRAY_SIZE(rtl8366s_vlan),
 915         },
 916
 917         .get_vlan_ports = rtl8366_sw_get_vlan_ports,
 918         .set_vlan_ports = rtl8366_sw_set_vlan_ports,
 919         .get_port_pvid = rtl8366_sw_get_port_pvid,
 920         .set_port_pvid = rtl8366_sw_set_port_pvid,
 921         .reset_switch = rtl8366s_sw_reset_switch,
 922 };
 923
 924 static int rtl8366s_switch_init(struct rtl8366_smi *smi)
 925 {
 926         struct switch_dev *dev = &smi->sw_dev;
 927         int err;
 928
 929         dev->name = "RTL8366S";
 930         dev->cpu_port = RTL8366S_PORT_NUM_CPU;
 931         dev->ports = RTL8366S_NUM_PORTS;
 932         dev->vlans = RTL8366S_NUM_VIDS;
 933         dev->ops = &rtl8366_ops;
 934         dev->devname = dev_name(smi->parent);
 935
 936         err = register_switch(dev, NULL);
 937         if (err)
 938                 dev_err(smi->parent, "switch registration failed\n");
 939
 940         return err;
 941 }
 942
 943 static void rtl8366s_switch_cleanup(struct rtl8366_smi *smi)
 944 {
 945         unregister_switch(&smi->sw_dev);
 946 }
 947
 948 static int rtl8366s_mii_read(struct mii_bus *bus, int addr, int reg)
 949 {
 950         struct rtl8366_smi *smi = bus->priv;
 951         u32 val = 0;
 952         int err;
 953
 954         err = rtl8366s_read_phy_reg(smi, addr, 0, reg, &val);
 955         if (err)
 956                 return 0xffff;
 957
 958         return val;
 959 }
 960
 961 static int rtl8366s_mii_write(struct mii_bus *bus, int addr, int reg, u16 val)
 962 {
 963         struct rtl8366_smi *smi = bus->priv;
 964         u32 t;
 965         int err;
 966
 967         err = rtl8366s_write_phy_reg(smi, addr, 0, reg, val);
 968         /* flush write */
 969         (void) rtl8366s_read_phy_reg(smi, addr, 0, reg, &t);
 970
 971         return err;
 972 }
 973
 974 static int rtl8366s_mii_bus_match(struct mii_bus *bus)
 975 {
 976         return (bus->read == rtl8366s_mii_read &&
 977                 bus->write == rtl8366s_mii_write);
 978 }
 979
 980 static int rtl8366s_setup(struct rtl8366_smi *smi)
 981 {
 982         int ret;
 983
 984         ret = rtl8366s_reset_chip(smi);
 985         if (ret)
 986                 return ret;
 987
 988         ret = rtl8366s_hw_init(smi);
 989         return ret;
 990 }
 991
 992 static int rtl8366s_detect(struct rtl8366_smi *smi)
 993 {
 994         u32 chip_id = 0;
 995         u32 chip_ver = 0;
 996         int ret;
 997
 998         ret = rtl8366_smi_read_reg(smi, RTL8366S_CHIP_ID_REG, &chip_id);
 999         if (ret) {
1000                 dev_err(smi->parent, "unable to read chip id\n");
1001                 return ret;
1002         }
1003
1004         switch (chip_id) {
1005         case RTL8366S_CHIP_ID_8366:
1006                 break;
1007         default:
1008                 dev_err(smi->parent, "unknown chip id (%04x)\n", chip_id);
1009                 return -ENODEV;
1010         }
1011
1012         ret = rtl8366_smi_read_reg(smi, RTL8366S_CHIP_VERSION_CTRL_REG,
1013                                    &chip_ver);
1014         if (ret) {
1015                 dev_err(smi->parent, "unable to read chip version\n");
1016                 return ret;
1017         }
1018
1019         dev_info(smi->parent, "RTL%04x ver. %u chip found\n",
1020                  chip_id, chip_ver & RTL8366S_CHIP_VERSION_MASK);
1021
1022         return 0;
1023 }
1024
1025 static struct rtl8366_smi_ops rtl8366s_smi_ops = {
1026         .detect         = rtl8366s_detect,
1027         .setup          = rtl8366s_setup,
1028
1029         .mii_read       = rtl8366s_mii_read,
1030         .mii_write      = rtl8366s_mii_write,
1031
1032         .get_vlan_mc    = rtl8366s_get_vlan_mc,
1033         .set_vlan_mc    = rtl8366s_set_vlan_mc,
1034         .get_vlan_4k    = rtl8366s_get_vlan_4k,
1035         .set_vlan_4k    = rtl8366s_set_vlan_4k,
1036         .get_mc_index   = rtl8366s_get_mc_index,
1037         .set_mc_index   = rtl8366s_set_mc_index,
1038         .get_mib_counter = rtl8366_get_mib_counter,
1039         .is_vlan_valid  = rtl8366s_is_vlan_valid,
1040         .enable_vlan    = rtl8366s_enable_vlan,
1041         .enable_vlan4k  = rtl8366s_enable_vlan4k,
1042         .enable_port    = rtl8366s_enable_port,
1043 };
1044
1045 static int __devinit rtl8366s_probe(struct platform_device *pdev)
1046 {
1047         static int rtl8366_smi_version_printed;
1048         struct rtl8366s_platform_data *pdata;
1049         struct rtl8366_smi *smi;
1050         int err;
1051
1052         if (!rtl8366_smi_version_printed++)
1053                 printk(KERN_NOTICE RTL8366S_DRIVER_DESC
1054                        " version " RTL8366S_DRIVER_VER"\n");
1055
1056         pdata = pdev->dev.platform_data;
1057         if (!pdata) {
1058                 dev_err(&pdev->dev, "no platform data specified\n");
1059                 err = -EINVAL;
1060                 goto err_out;
1061         }
1062
1063         smi = rtl8366_smi_alloc(&pdev->dev);
1064         if (!smi) {
1065                 err = -ENOMEM;
1066                 goto err_out;
1067         }
1068
1069         smi->gpio_sda = pdata->gpio_sda;
1070         smi->gpio_sck = pdata->gpio_sck;
1071         smi->ops = &rtl8366s_smi_ops;
1072         smi->cpu_port = RTL8366S_PORT_NUM_CPU;
1073         smi->num_ports = RTL8366S_NUM_PORTS;
1074         smi->num_vlan_mc = RTL8366S_NUM_VLANS;
1075         smi->mib_counters = rtl8366s_mib_counters;
1076         smi->num_mib_counters = ARRAY_SIZE(rtl8366s_mib_counters);
1077
1078         err = rtl8366_smi_init(smi);
1079         if (err)
1080                 goto err_free_smi;
1081
1082         platform_set_drvdata(pdev, smi);
1083
1084         err = rtl8366s_switch_init(smi);
1085         if (err)
1086                 goto err_clear_drvdata;
1087
1088         return 0;
1089
1090  err_clear_drvdata:
1091         platform_set_drvdata(pdev, NULL);
1092         rtl8366_smi_cleanup(smi);
1093  err_free_smi:
1094         kfree(smi);
1095  err_out:
1096         return err;
1097 }
1098
1099 static int rtl8366s_phy_config_init(struct phy_device *phydev)
1100 {
1101         if (!rtl8366s_mii_bus_match(phydev->bus))
1102                 return -EINVAL;
1103
1104         return 0;
1105 }
1106
1107 static int rtl8366s_phy_config_aneg(struct phy_device *phydev)
1108 {
1109         /* phy 4 might be connected to a second mac, allow aneg config */
1110         if (phydev->addr == RTL8366S_PHY_WAN)
1111                 return genphy_config_aneg(phydev);
1112
1113         return 0;
1114 }
1115
1116 static struct phy_driver rtl8366s_phy_driver = {
1117         .phy_id         = 0x001cc960,
1118         .name           = "Realtek RTL8366S",
1119         .phy_id_mask    = 0x1ffffff0,
1120         .features       = PHY_GBIT_FEATURES,
1121         .config_aneg    = rtl8366s_phy_config_aneg,
1122         .config_init    = rtl8366s_phy_config_init,
1123         .read_status    = genphy_read_status,
1124         .driver         = {
1125                 .owner = THIS_MODULE,
1126         },
1127 };
1128
1129 static int __devexit rtl8366s_remove(struct platform_device *pdev)
1130 {
1131         struct rtl8366_smi *smi = platform_get_drvdata(pdev);
1132
1133         if (smi) {
1134                 rtl8366s_switch_cleanup(smi);
1135                 platform_set_drvdata(pdev, NULL);
1136                 rtl8366_smi_cleanup(smi);
1137                 kfree(smi);
1138         }
1139
1140         return 0;
1141 }
1142
1143 static struct platform_driver rtl8366s_driver = {
1144         .driver = {
1145                 .name           = RTL8366S_DRIVER_NAME,
1146                 .owner          = THIS_MODULE,
1147         },
1148         .probe          = rtl8366s_probe,
1149         .remove         = __devexit_p(rtl8366s_remove),
1150 };
1151
1152 static int __init rtl8366s_module_init(void)
1153 {
1154         int ret;
1155         ret = platform_driver_register(&rtl8366s_driver);
1156         if (ret)
1157                 return ret;
1158
1159         ret = phy_driver_register(&rtl8366s_phy_driver);
1160         if (ret)
1161                 goto err_platform_unregister;
1162
1163         return 0;
1164
1165  err_platform_unregister:
1166         platform_driver_unregister(&rtl8366s_driver);
1167         return ret;
1168 }
1169 module_init(rtl8366s_module_init);
1170
1171 static void __exit rtl8366s_module_exit(void)
1172 {
1173         phy_driver_unregister(&rtl8366s_phy_driver);
1174         platform_driver_unregister(&rtl8366s_driver);
1175 }
1176 module_exit(rtl8366s_module_exit);
1177
1178 MODULE_DESCRIPTION(RTL8366S_DRIVER_DESC);
1179 MODULE_VERSION(RTL8366S_DRIVER_VER);
1180 MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
1181 MODULE_AUTHOR("Antti Seppälä <a.seppala@gmail.com>");
1182 MODULE_LICENSE("GPL v2");
1183 MODULE_ALIAS("platform:" RTL8366S_DRIVER_NAME);