target/linux/generic/files/drivers/net/phy/rtl8366rb.c

   1 /*
   2  * Platform driver for the Realtek RTL8366RB ethernet switch
   3  *
   4  * Copyright (C) 2009-2010 Gabor Juhos <juhosg@openwrt.org>
   5  * Copyright (C) 2010 Antti Seppälä <a.seppala@gmail.com>
   6  * Copyright (C) 2010 Roman Yeryomin <roman@advem.lv>
   7  *
   8  * This program is free software; you can redistribute it and/or modify it
   9  * under the terms of the GNU General Public License version 2 as published
  10  * by the Free Software Foundation.
  11  */
  12
  13 #include <linux/kernel.h>
  14 #include <linux/module.h>
  15 #include <linux/init.h>
  16 #include <linux/platform_device.h>
  17 #include <linux/delay.h>
  18 #include <linux/skbuff.h>
  19 #include <linux/rtl8366rb.h>
  20
  21 #include "rtl8366_smi.h"
  22
  23 #define RTL8366RB_DRIVER_DESC   "Realtek RTL8366RB ethernet switch driver"
  24 #define RTL8366RB_DRIVER_VER    "0.2.3"
  25
  26 #define RTL8366RB_PHY_NO_MAX    4
  27 #define RTL8366RB_PHY_PAGE_MAX  7
  28 #define RTL8366RB_PHY_ADDR_MAX  31
  29 #define RTL8366RB_PHY_WAN       4
  30
  31 /* Switch Global Configuration register */
  32 #define RTL8366RB_SGCR                          0x0000
  33 #define RTL8366RB_SGCR_EN_BC_STORM_CTRL         BIT(0)
  34 #define RTL8366RB_SGCR_MAX_LENGTH(_x)           (_x << 4)
  35 #define RTL8366RB_SGCR_MAX_LENGTH_MASK          RTL8366RB_SGCR_MAX_LENGTH(0x3)
  36 #define RTL8366RB_SGCR_MAX_LENGTH_1522          RTL8366RB_SGCR_MAX_LENGTH(0x0)
  37 #define RTL8366RB_SGCR_MAX_LENGTH_1536          RTL8366RB_SGCR_MAX_LENGTH(0x1)
  38 #define RTL8366RB_SGCR_MAX_LENGTH_1552          RTL8366RB_SGCR_MAX_LENGTH(0x2)
  39 #define RTL8366RB_SGCR_MAX_LENGTH_9216          RTL8366RB_SGCR_MAX_LENGTH(0x3)
  40 #define RTL8366RB_SGCR_EN_VLAN                  BIT(13)
  41 #define RTL8366RB_SGCR_EN_VLAN_4KTB             BIT(14)
  42
  43 /* Port Enable Control register */
  44 #define RTL8366RB_PECR                          0x0001
  45
  46 /* Switch Security Control registers */
  47 #define RTL8366RB_SSCR0                         0x0002
  48 #define RTL8366RB_SSCR1                         0x0003
  49 #define RTL8366RB_SSCR2                         0x0004
  50 #define RTL8366RB_SSCR2_DROP_UNKNOWN_DA         BIT(0)
  51
  52 #define RTL8366RB_RESET_CTRL_REG                0x0100
  53 #define RTL8366RB_CHIP_CTRL_RESET_HW            1
  54 #define RTL8366RB_CHIP_CTRL_RESET_SW            (1 << 1)
  55
  56 #define RTL8366RB_CHIP_VERSION_CTRL_REG         0x050A
  57 #define RTL8366RB_CHIP_VERSION_MASK             0xf
  58 #define RTL8366RB_CHIP_ID_REG                   0x0509
  59 #define RTL8366RB_CHIP_ID_8366                  0x5937
  60
  61 /* PHY registers control */
  62 #define RTL8366RB_PHY_ACCESS_CTRL_REG           0x8000
  63 #define RTL8366RB_PHY_ACCESS_DATA_REG           0x8002
  64
  65 #define RTL8366RB_PHY_CTRL_READ                 1
  66 #define RTL8366RB_PHY_CTRL_WRITE                0
  67
  68 #define RTL8366RB_PHY_REG_MASK                  0x1f
  69 #define RTL8366RB_PHY_PAGE_OFFSET               5
  70 #define RTL8366RB_PHY_PAGE_MASK                 (0xf << 5)
  71 #define RTL8366RB_PHY_NO_OFFSET                 9
  72 #define RTL8366RB_PHY_NO_MASK                   (0x1f << 9)
  73
  74 #define RTL8366RB_VLAN_INGRESS_CTRL2_REG        0x037f
  75
  76 /* LED control registers */
  77 #define RTL8366RB_LED_BLINKRATE_REG             0x0430
  78 #define RTL8366RB_LED_BLINKRATE_BIT             0
  79 #define RTL8366RB_LED_BLINKRATE_MASK            0x0007
  80
  81 #define RTL8366RB_LED_CTRL_REG                  0x0431
  82 #define RTL8366RB_LED_0_1_CTRL_REG              0x0432
  83 #define RTL8366RB_LED_2_3_CTRL_REG              0x0433
  84
  85 #define RTL8366RB_MIB_COUNT                     33
  86 #define RTL8366RB_GLOBAL_MIB_COUNT              1
  87 #define RTL8366RB_MIB_COUNTER_PORT_OFFSET       0x0050
  88 #define RTL8366RB_MIB_COUNTER_BASE              0x1000
  89 #define RTL8366RB_MIB_CTRL_REG                  0x13F0
  90 #define RTL8366RB_MIB_CTRL_USER_MASK            0x0FFC
  91 #define RTL8366RB_MIB_CTRL_BUSY_MASK            BIT(0)
  92 #define RTL8366RB_MIB_CTRL_RESET_MASK           BIT(1)
  93 #define RTL8366RB_MIB_CTRL_PORT_RESET(_p)       BIT(2 + (_p))
  94 #define RTL8366RB_MIB_CTRL_GLOBAL_RESET         BIT(11)
  95
  96 #define RTL8366RB_PORT_VLAN_CTRL_BASE           0x0063
  97 #define RTL8366RB_PORT_VLAN_CTRL_REG(_p)  \
  98                 (RTL8366RB_PORT_VLAN_CTRL_BASE + (_p) / 4)
  99 #define RTL8366RB_PORT_VLAN_CTRL_MASK           0xf
 100 #define RTL8366RB_PORT_VLAN_CTRL_SHIFT(_p)      (4 * ((_p) % 4))
 101
 102
 103 #define RTL8366RB_VLAN_TABLE_READ_BASE          0x018C
 104 #define RTL8366RB_VLAN_TABLE_WRITE_BASE         0x0185
 105
 106
 107 #define RTL8366RB_TABLE_ACCESS_CTRL_REG         0x0180
 108 #define RTL8366RB_TABLE_VLAN_READ_CTRL          0x0E01
 109 #define RTL8366RB_TABLE_VLAN_WRITE_CTRL         0x0F01
 110
 111 #define RTL8366RB_VLAN_MC_BASE(_x)              (0x0020 + (_x) * 3)
 112
 113
 114 #define RTL8366RB_PORT_LINK_STATUS_BASE         0x0014
 115 #define RTL8366RB_PORT_STATUS_SPEED_MASK        0x0003
 116 #define RTL8366RB_PORT_STATUS_DUPLEX_MASK       0x0004
 117 #define RTL8366RB_PORT_STATUS_LINK_MASK         0x0010
 118 #define RTL8366RB_PORT_STATUS_TXPAUSE_MASK      0x0020
 119 #define RTL8366RB_PORT_STATUS_RXPAUSE_MASK      0x0040
 120 #define RTL8366RB_PORT_STATUS_AN_MASK           0x0080
 121
 122
 123 #define RTL8366RB_PORT_NUM_CPU          5
 124 #define RTL8366RB_NUM_PORTS             6
 125 #define RTL8366RB_NUM_VLANS             16
 126 #define RTL8366RB_NUM_LEDGROUPS         4
 127 #define RTL8366RB_NUM_VIDS              4096
 128 #define RTL8366RB_PRIORITYMAX           7
 129 #define RTL8366RB_FIDMAX                7
 130
 131
 132 #define RTL8366RB_PORT_1                (1 << 0) /* In userspace port 0 */
 133 #define RTL8366RB_PORT_2                (1 << 1) /* In userspace port 1 */
 134 #define RTL8366RB_PORT_3                (1 << 2) /* In userspace port 2 */
 135 #define RTL8366RB_PORT_4                (1 << 3) /* In userspace port 3 */
 136 #define RTL8366RB_PORT_5                (1 << 4) /* In userspace port 4 */
 137
 138 #define RTL8366RB_PORT_CPU              (1 << 5) /* CPU port */
 139
 140 #define RTL8366RB_PORT_ALL              (RTL8366RB_PORT_1 |     \
 141                                          RTL8366RB_PORT_2 |     \
 142                                          RTL8366RB_PORT_3 |     \
 143                                          RTL8366RB_PORT_4 |     \
 144                                          RTL8366RB_PORT_5 |     \
 145                                          RTL8366RB_PORT_CPU)
 146
 147 #define RTL8366RB_PORT_ALL_BUT_CPU      (RTL8366RB_PORT_1 |     \
 148                                          RTL8366RB_PORT_2 |     \
 149                                          RTL8366RB_PORT_3 |     \
 150                                          RTL8366RB_PORT_4 |     \
 151                                          RTL8366RB_PORT_5)
 152
 153 #define RTL8366RB_PORT_ALL_EXTERNAL     (RTL8366RB_PORT_1 |     \
 154                                          RTL8366RB_PORT_2 |     \
 155                                          RTL8366RB_PORT_3 |     \
 156                                          RTL8366RB_PORT_4)
 157
 158 #define RTL8366RB_PORT_ALL_INTERNAL      RTL8366RB_PORT_CPU
 159
 160 #define RTL8366RB_VLAN_VID_MASK         0xfff
 161 #define RTL8366RB_VLAN_PRIORITY_SHIFT   12
 162 #define RTL8366RB_VLAN_PRIORITY_MASK    0x7
 163 #define RTL8366RB_VLAN_UNTAG_SHIFT      8
 164 #define RTL8366RB_VLAN_UNTAG_MASK       0xff
 165 #define RTL8366RB_VLAN_MEMBER_MASK      0xff
 166 #define RTL8366RB_VLAN_FID_MASK         0x7
 167
 168
 169 /* Port ingress bandwidth control */
 170 #define RTL8366RB_IB_BASE               0x0200
 171 #define RTL8366RB_IB_REG(pnum)          (RTL8366RB_IB_BASE + pnum)
 172 #define RTL8366RB_IB_BDTH_MASK          0x3fff
 173 #define RTL8366RB_IB_PREIFG_OFFSET      14
 174 #define RTL8366RB_IB_PREIFG_MASK        (1 << RTL8366RB_IB_PREIFG_OFFSET)
 175
 176 /* Port egress bandwidth control */
 177 #define RTL8366RB_EB_BASE               0x02d1
 178 #define RTL8366RB_EB_REG(pnum)          (RTL8366RB_EB_BASE + pnum)
 179 #define RTL8366RB_EB_BDTH_MASK          0x3fff
 180 #define RTL8366RB_EB_PREIFG_REG 0x02f8
 181 #define RTL8366RB_EB_PREIFG_OFFSET      9
 182 #define RTL8366RB_EB_PREIFG_MASK        (1 << RTL8366RB_EB_PREIFG_OFFSET)
 183
 184 #define RTL8366RB_BDTH_SW_MAX           1048512
 185 #define RTL8366RB_BDTH_UNIT             64
 186 #define RTL8366RB_BDTH_REG_DEFAULT      16383
 187
 188 /* QOS */
 189 #define RTL8366RB_QOS_BIT               15
 190 #define RTL8366RB_QOS_MASK              (1 << RTL8366RB_QOS_BIT)
 191 /* Include/Exclude Preamble and IFG (20 bytes). 0:Exclude, 1:Include. */
 192 #define RTL8366RB_QOS_DEFAULT_PREIFG    1
 193
 194
 195 static struct rtl8366_mib_counter rtl8366rb_mib_counters[] = {
 196         { 0,  0, 4, "IfInOctets"                                },
 197         { 0,  4, 4, "EtherStatsOctets"                          },
 198         { 0,  8, 2, "EtherStatsUnderSizePkts"                   },
 199         { 0, 10, 2, "EtherFragments"                            },
 200         { 0, 12, 2, "EtherStatsPkts64Octets"                    },
 201         { 0, 14, 2, "EtherStatsPkts65to127Octets"               },
 202         { 0, 16, 2, "EtherStatsPkts128to255Octets"              },
 203         { 0, 18, 2, "EtherStatsPkts256to511Octets"              },
 204         { 0, 20, 2, "EtherStatsPkts512to1023Octets"             },
 205         { 0, 22, 2, "EtherStatsPkts1024to1518Octets"            },
 206         { 0, 24, 2, "EtherOversizeStats"                        },
 207         { 0, 26, 2, "EtherStatsJabbers"                         },
 208         { 0, 28, 2, "IfInUcastPkts"                             },
 209         { 0, 30, 2, "EtherStatsMulticastPkts"                   },
 210         { 0, 32, 2, "EtherStatsBroadcastPkts"                   },
 211         { 0, 34, 2, "EtherStatsDropEvents"                      },
 212         { 0, 36, 2, "Dot3StatsFCSErrors"                        },
 213         { 0, 38, 2, "Dot3StatsSymbolErrors"                     },
 214         { 0, 40, 2, "Dot3InPauseFrames"                         },
 215         { 0, 42, 2, "Dot3ControlInUnknownOpcodes"               },
 216         { 0, 44, 4, "IfOutOctets"                               },
 217         { 0, 48, 2, "Dot3StatsSingleCollisionFrames"            },
 218         { 0, 50, 2, "Dot3StatMultipleCollisionFrames"           },
 219         { 0, 52, 2, "Dot3sDeferredTransmissions"                },
 220         { 0, 54, 2, "Dot3StatsLateCollisions"                   },
 221         { 0, 56, 2, "EtherStatsCollisions"                      },
 222         { 0, 58, 2, "Dot3StatsExcessiveCollisions"              },
 223         { 0, 60, 2, "Dot3OutPauseFrames"                        },
 224         { 0, 62, 2, "Dot1dBasePortDelayExceededDiscards"        },
 225         { 0, 64, 2, "Dot1dTpPortInDiscards"                     },
 226         { 0, 66, 2, "IfOutUcastPkts"                            },
 227         { 0, 68, 2, "IfOutMulticastPkts"                        },
 228         { 0, 70, 2, "IfOutBroadcastPkts"                        },
 229 };
 230
 231 #define REG_WR(_smi, _reg, _val)                                        \
 232         do {                                                            \
 233                 err = rtl8366_smi_write_reg(_smi, _reg, _val);          \
 234                 if (err)                                                \
 235                         return err;                                     \
 236         } while (0)
 237
 238 #define REG_RMW(_smi, _reg, _mask, _val)                                \
 239         do {                                                            \
 240                 err = rtl8366_smi_rmwr(_smi, _reg, _mask, _val);        \
 241                 if (err)                                                \
 242                         return err;                                     \
 243         } while (0)
 244
 245 static int rtl8366rb_reset_chip(struct rtl8366_smi *smi)
 246 {
 247         int timeout = 10;
 248         u32 data;
 249
 250         rtl8366_smi_write_reg(smi, RTL8366RB_RESET_CTRL_REG,
 251                               RTL8366RB_CHIP_CTRL_RESET_HW);
 252         do {
 253                 msleep(1);
 254                 if (rtl8366_smi_read_reg(smi, RTL8366RB_RESET_CTRL_REG, &data))
 255                         return -EIO;
 256
 257                 if (!(data & RTL8366RB_CHIP_CTRL_RESET_HW))
 258                         break;
 259         } while (--timeout);
 260
 261         if (!timeout) {
 262                 printk("Timeout waiting for the switch to reset\n");
 263                 return -EIO;
 264         }
 265
 266         return 0;
 267 }
 268
 269 static int rtl8366rb_hw_init(struct rtl8366_smi *smi)
 270 {
 271         int err;
 272
 273         /* set maximum packet length to 1536 bytes */
 274         REG_RMW(smi, RTL8366RB_SGCR, RTL8366RB_SGCR_MAX_LENGTH_MASK,
 275                 RTL8366RB_SGCR_MAX_LENGTH_1536);
 276
 277         /* enable learning for all ports */
 278         REG_WR(smi, RTL8366RB_SSCR0, 0);
 279
 280         /* enable auto ageing for all ports */
 281         REG_WR(smi, RTL8366RB_SSCR1, 0);
 282
 283         /*
 284          * discard VLAN tagged packets if the port is not a member of
 285          * the VLAN with which the packets is associated.
 286          */
 287         REG_WR(smi, RTL8366RB_VLAN_INGRESS_CTRL2_REG, RTL8366RB_PORT_ALL);
 288
 289         /* don't drop packets whose DA has not been learned */
 290         REG_RMW(smi, RTL8366RB_SSCR2, RTL8366RB_SSCR2_DROP_UNKNOWN_DA, 0);
 291
 292         return 0;
 293 }
 294
 295 static int rtl8366rb_read_phy_reg(struct rtl8366_smi *smi,
 296                                  u32 phy_no, u32 page, u32 addr, u32 *data)
 297 {
 298         u32 reg;
 299         int ret;
 300
 301         if (phy_no > RTL8366RB_PHY_NO_MAX)
 302                 return -EINVAL;
 303
 304         if (page > RTL8366RB_PHY_PAGE_MAX)
 305                 return -EINVAL;
 306
 307         if (addr > RTL8366RB_PHY_ADDR_MAX)
 308                 return -EINVAL;
 309
 310         ret = rtl8366_smi_write_reg(smi, RTL8366RB_PHY_ACCESS_CTRL_REG,
 311                                     RTL8366RB_PHY_CTRL_READ);
 312         if (ret)
 313                 return ret;
 314
 315         reg = 0x8000 | (1 << (phy_no + RTL8366RB_PHY_NO_OFFSET)) |
 316               ((page << RTL8366RB_PHY_PAGE_OFFSET) & RTL8366RB_PHY_PAGE_MASK) |
 317               (addr & RTL8366RB_PHY_REG_MASK);
 318
 319         ret = rtl8366_smi_write_reg(smi, reg, 0);
 320         if (ret)
 321                 return ret;
 322
 323         ret = rtl8366_smi_read_reg(smi, RTL8366RB_PHY_ACCESS_DATA_REG, data);
 324         if (ret)
 325                 return ret;
 326
 327         return 0;
 328 }
 329
 330 static int rtl8366rb_write_phy_reg(struct rtl8366_smi *smi,
 331                                   u32 phy_no, u32 page, u32 addr, u32 data)
 332 {
 333         u32 reg;
 334         int ret;
 335
 336         if (phy_no > RTL8366RB_PHY_NO_MAX)
 337                 return -EINVAL;
 338
 339         if (page > RTL8366RB_PHY_PAGE_MAX)
 340                 return -EINVAL;
 341
 342         if (addr > RTL8366RB_PHY_ADDR_MAX)
 343                 return -EINVAL;
 344
 345         ret = rtl8366_smi_write_reg(smi, RTL8366RB_PHY_ACCESS_CTRL_REG,
 346                                     RTL8366RB_PHY_CTRL_WRITE);
 347         if (ret)
 348                 return ret;
 349
 350         reg = 0x8000 | (1 << (phy_no + RTL8366RB_PHY_NO_OFFSET)) |
 351               ((page << RTL8366RB_PHY_PAGE_OFFSET) & RTL8366RB_PHY_PAGE_MASK) |
 352               (addr & RTL8366RB_PHY_REG_MASK);
 353
 354         ret = rtl8366_smi_write_reg(smi, reg, data);
 355         if (ret)
 356                 return ret;
 357
 358         return 0;
 359 }
 360
 361 static int rtl8366rb_get_mib_counter(struct rtl8366_smi *smi, int counter,
 362                                      int port, unsigned long long *val)
 363 {
 364         int i;
 365         int err;
 366         u32 addr, data;
 367         u64 mibvalue;
 368
 369         if (port > RTL8366RB_NUM_PORTS || counter >= RTL8366RB_MIB_COUNT)
 370                 return -EINVAL;
 371
 372         addr = RTL8366RB_MIB_COUNTER_BASE +
 373                RTL8366RB_MIB_COUNTER_PORT_OFFSET * (port) +
 374                rtl8366rb_mib_counters[counter].offset;
 375
 376         /*
 377          * Writing access counter address first
 378          * then ASIC will prepare 64bits counter wait for being retrived
 379          */
 380         data = 0; /* writing data will be discard by ASIC */
 381         err = rtl8366_smi_write_reg(smi, addr, data);
 382         if (err)
 383                 return err;
 384
 385         /* read MIB control register */
 386         err =  rtl8366_smi_read_reg(smi, RTL8366RB_MIB_CTRL_REG, &data);
 387         if (err)
 388                 return err;
 389
 390         if (data & RTL8366RB_MIB_CTRL_BUSY_MASK)
 391                 return -EBUSY;
 392
 393         if (data & RTL8366RB_MIB_CTRL_RESET_MASK)
 394                 return -EIO;
 395
 396         mibvalue = 0;
 397         for (i = rtl8366rb_mib_counters[counter].length; i > 0; i--) {
 398                 err = rtl8366_smi_read_reg(smi, addr + (i - 1), &data);
 399                 if (err)
 400                         return err;
 401
 402                 mibvalue = (mibvalue << 16) | (data & 0xFFFF);
 403         }
 404
 405         *val = mibvalue;
 406         return 0;
 407 }
 408
 409 static int rtl8366rb_get_vlan_4k(struct rtl8366_smi *smi, u32 vid,
 410                                  struct rtl8366_vlan_4k *vlan4k)
 411 {
 412         u32 data[3];
 413         int err;
 414         int i;
 415
 416         memset(vlan4k, '\0', sizeof(struct rtl8366_vlan_4k));
 417
 418         if (vid >= RTL8366RB_NUM_VIDS)
 419                 return -EINVAL;
 420
 421         /* write VID */
 422         err = rtl8366_smi_write_reg(smi, RTL8366RB_VLAN_TABLE_WRITE_BASE,
 423                                     vid & RTL8366RB_VLAN_VID_MASK);
 424         if (err)
 425                 return err;
 426
 427         /* write table access control word */
 428         err = rtl8366_smi_write_reg(smi, RTL8366RB_TABLE_ACCESS_CTRL_REG,
 429                                     RTL8366RB_TABLE_VLAN_READ_CTRL);
 430         if (err)
 431                 return err;
 432
 433         for (i = 0; i < 3; i++) {
 434                 err = rtl8366_smi_read_reg(smi,
 435                                            RTL8366RB_VLAN_TABLE_READ_BASE + i,
 436                                            &data[i]);
 437                 if (err)
 438                         return err;
 439         }
 440
 441         vlan4k->vid = vid;
 442         vlan4k->untag = (data[1] >> RTL8366RB_VLAN_UNTAG_SHIFT) &
 443                         RTL8366RB_VLAN_UNTAG_MASK;
 444         vlan4k->member = data[1] & RTL8366RB_VLAN_MEMBER_MASK;
 445         vlan4k->fid = data[2] & RTL8366RB_VLAN_FID_MASK;
 446
 447         return 0;
 448 }
 449
 450 static int rtl8366rb_set_vlan_4k(struct rtl8366_smi *smi,
 451                                  const struct rtl8366_vlan_4k *vlan4k)
 452 {
 453         u32 data[3];
 454         int err;
 455         int i;
 456
 457         if (vlan4k->vid >= RTL8366RB_NUM_VIDS ||
 458             vlan4k->member > RTL8366RB_VLAN_MEMBER_MASK ||
 459             vlan4k->untag > RTL8366RB_VLAN_UNTAG_MASK ||
 460             vlan4k->fid > RTL8366RB_FIDMAX)
 461                 return -EINVAL;
 462
 463         data[0] = vlan4k->vid & RTL8366RB_VLAN_VID_MASK;
 464         data[1] = (vlan4k->member & RTL8366RB_VLAN_MEMBER_MASK) |
 465                   ((vlan4k->untag & RTL8366RB_VLAN_UNTAG_MASK) <<
 466                         RTL8366RB_VLAN_UNTAG_SHIFT);
 467         data[2] = vlan4k->fid & RTL8366RB_VLAN_FID_MASK;
 468
 469         for (i = 0; i < 3; i++) {
 470                 err = rtl8366_smi_write_reg(smi,
 471                                             RTL8366RB_VLAN_TABLE_WRITE_BASE + i,
 472                                             data[i]);
 473                 if (err)
 474                         return err;
 475         }
 476
 477         /* write table access control word */
 478         err = rtl8366_smi_write_reg(smi, RTL8366RB_TABLE_ACCESS_CTRL_REG,
 479                                     RTL8366RB_TABLE_VLAN_WRITE_CTRL);
 480
 481         return err;
 482 }
 483
 484 static int rtl8366rb_get_vlan_mc(struct rtl8366_smi *smi, u32 index,
 485                                  struct rtl8366_vlan_mc *vlanmc)
 486 {
 487         u32 data[3];
 488         int err;
 489         int i;
 490
 491         memset(vlanmc, '\0', sizeof(struct rtl8366_vlan_mc));
 492
 493         if (index >= RTL8366RB_NUM_VLANS)
 494                 return -EINVAL;
 495
 496         for (i = 0; i < 3; i++) {
 497                 err = rtl8366_smi_read_reg(smi,
 498                                            RTL8366RB_VLAN_MC_BASE(index) + i,
 499                                            &data[i]);
 500                 if (err)
 501                         return err;
 502         }
 503
 504         vlanmc->vid = data[0] & RTL8366RB_VLAN_VID_MASK;
 505         vlanmc->priority = (data[0] >> RTL8366RB_VLAN_PRIORITY_SHIFT) &
 506                            RTL8366RB_VLAN_PRIORITY_MASK;
 507         vlanmc->untag = (data[1] >> RTL8366RB_VLAN_UNTAG_SHIFT) &
 508                         RTL8366RB_VLAN_UNTAG_MASK;
 509         vlanmc->member = data[1] & RTL8366RB_VLAN_MEMBER_MASK;
 510         vlanmc->fid = data[2] & RTL8366RB_VLAN_FID_MASK;
 511
 512         return 0;
 513 }
 514
 515 static int rtl8366rb_set_vlan_mc(struct rtl8366_smi *smi, u32 index,
 516                                  const struct rtl8366_vlan_mc *vlanmc)
 517 {
 518         u32 data[3];
 519         int err;
 520         int i;
 521
 522         if (index >= RTL8366RB_NUM_VLANS ||
 523             vlanmc->vid >= RTL8366RB_NUM_VIDS ||
 524             vlanmc->priority > RTL8366RB_PRIORITYMAX ||
 525             vlanmc->member > RTL8366RB_VLAN_MEMBER_MASK ||
 526             vlanmc->untag > RTL8366RB_VLAN_UNTAG_MASK ||
 527             vlanmc->fid > RTL8366RB_FIDMAX)
 528                 return -EINVAL;
 529
 530         data[0] = (vlanmc->vid & RTL8366RB_VLAN_VID_MASK) |
 531                   ((vlanmc->priority & RTL8366RB_VLAN_PRIORITY_MASK) <<
 532                         RTL8366RB_VLAN_PRIORITY_SHIFT);
 533         data[1] = (vlanmc->member & RTL8366RB_VLAN_MEMBER_MASK) |
 534                   ((vlanmc->untag & RTL8366RB_VLAN_UNTAG_MASK) <<
 535                         RTL8366RB_VLAN_UNTAG_SHIFT);
 536         data[2] = vlanmc->fid & RTL8366RB_VLAN_FID_MASK;
 537
 538         for (i = 0; i < 3; i++) {
 539                 err = rtl8366_smi_write_reg(smi,
 540                                             RTL8366RB_VLAN_MC_BASE(index) + i,
 541                                             data[i]);
 542                 if (err)
 543                         return err;
 544         }
 545
 546         return 0;
 547 }
 548
 549 static int rtl8366rb_get_mc_index(struct rtl8366_smi *smi, int port, int *val)
 550 {
 551         u32 data;
 552         int err;
 553
 554         if (port >= RTL8366RB_NUM_PORTS)
 555                 return -EINVAL;
 556
 557         err = rtl8366_smi_read_reg(smi, RTL8366RB_PORT_VLAN_CTRL_REG(port),
 558                                    &data);
 559         if (err)
 560                 return err;
 561
 562         *val = (data >> RTL8366RB_PORT_VLAN_CTRL_SHIFT(port)) &
 563                RTL8366RB_PORT_VLAN_CTRL_MASK;
 564
 565         return 0;
 566
 567 }
 568
 569 static int rtl8366rb_set_mc_index(struct rtl8366_smi *smi, int port, int index)
 570 {
 571         if (port >= RTL8366RB_NUM_PORTS || index >= RTL8366RB_NUM_VLANS)
 572                 return -EINVAL;
 573
 574         return rtl8366_smi_rmwr(smi, RTL8366RB_PORT_VLAN_CTRL_REG(port),
 575                                 RTL8366RB_PORT_VLAN_CTRL_MASK <<
 576                                         RTL8366RB_PORT_VLAN_CTRL_SHIFT(port),
 577                                 (index & RTL8366RB_PORT_VLAN_CTRL_MASK) <<
 578                                         RTL8366RB_PORT_VLAN_CTRL_SHIFT(port));
 579 }
 580
 581 static int rtl8366rb_is_vlan_valid(struct rtl8366_smi *smi, unsigned vlan)
 582 {
 583         unsigned max = RTL8366RB_NUM_VLANS;
 584
 585         if (smi->vlan4k_enabled)
 586                 max = RTL8366RB_NUM_VIDS - 1;
 587
 588         if (vlan == 0 || vlan >= max)
 589                 return 0;
 590
 591         return 1;
 592 }
 593
 594 static int rtl8366rb_enable_vlan(struct rtl8366_smi *smi, int enable)
 595 {
 596         return rtl8366_smi_rmwr(smi, RTL8366RB_SGCR, RTL8366RB_SGCR_EN_VLAN,
 597                                 (enable) ? RTL8366RB_SGCR_EN_VLAN : 0);
 598 }
 599
 600 static int rtl8366rb_enable_vlan4k(struct rtl8366_smi *smi, int enable)
 601 {
 602         return rtl8366_smi_rmwr(smi, RTL8366RB_SGCR,
 603                                 RTL8366RB_SGCR_EN_VLAN_4KTB,
 604                                 (enable) ? RTL8366RB_SGCR_EN_VLAN_4KTB : 0);
 605 }
 606
 607 static int rtl8366rb_enable_port(struct rtl8366_smi *smi, int port, int enable)
 608 {
 609         return rtl8366_smi_rmwr(smi, RTL8366RB_PECR, (1 << port),
 610                                 (enable) ? 0 : (1 << port));
 611 }
 612
 613 static int rtl8366rb_sw_reset_mibs(struct switch_dev *dev,
 614                                   const struct switch_attr *attr,
 615                                   struct switch_val *val)
 616 {
 617         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
 618
 619         return rtl8366_smi_rmwr(smi, RTL8366RB_MIB_CTRL_REG, 0,
 620                                 RTL8366RB_MIB_CTRL_GLOBAL_RESET);
 621 }
 622
 623 static int rtl8366rb_sw_get_blinkrate(struct switch_dev *dev,
 624                                      const struct switch_attr *attr,
 625                                      struct switch_val *val)
 626 {
 627         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
 628         u32 data;
 629
 630         rtl8366_smi_read_reg(smi, RTL8366RB_LED_BLINKRATE_REG, &data);
 631
 632         val->value.i = (data & (RTL8366RB_LED_BLINKRATE_MASK));
 633
 634         return 0;
 635 }
 636
 637 static int rtl8366rb_sw_set_blinkrate(struct switch_dev *dev,
 638                                     const struct switch_attr *attr,
 639                                     struct switch_val *val)
 640 {
 641         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
 642
 643         if (val->value.i >= 6)
 644                 return -EINVAL;
 645
 646         return rtl8366_smi_rmwr(smi, RTL8366RB_LED_BLINKRATE_REG,
 647                                 RTL8366RB_LED_BLINKRATE_MASK,
 648                                 val->value.i);
 649 }
 650
 651 static int rtl8366rb_sw_get_learning_enable(struct switch_dev *dev,
 652                                        const struct switch_attr *attr,
 653                                        struct switch_val *val)
 654 {
 655         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
 656         u32 data;
 657
 658         rtl8366_smi_read_reg(smi, RTL8366RB_SSCR0, &data);
 659         val->value.i = !data;
 660
 661         return 0;
 662 }
 663
 664
 665 static int rtl8366rb_sw_set_learning_enable(struct switch_dev *dev,
 666                                        const struct switch_attr *attr,
 667                                        struct switch_val *val)
 668 {
 669         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
 670         u32 portmask = 0;
 671         int err = 0;
 672
 673         if (!val->value.i)
 674                 portmask = RTL8366RB_PORT_ALL;
 675
 676         /* set learning for all ports */
 677         REG_WR(smi, RTL8366RB_SSCR0, portmask);
 678
 679         /* set auto ageing for all ports */
 680         REG_WR(smi, RTL8366RB_SSCR1, portmask);
 681
 682         return 0;
 683 }
 684
 685
 686 static const char *rtl8366rb_speed_str(unsigned speed)
 687 {
 688         switch (speed) {
 689         case 0:
 690                 return "10baseT";
 691         case 1:
 692                 return "100baseT";
 693         case 2:
 694                 return "1000baseT";
 695         }
 696
 697         return "unknown";
 698 }
 699
 700 static int rtl8366rb_sw_get_port_link(struct switch_dev *dev,
 701                                      const struct switch_attr *attr,
 702                                      struct switch_val *val)
 703 {
 704         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
 705         u32 len = 0, data = 0;
 706
 707         if (val->port_vlan >= RTL8366RB_NUM_PORTS)
 708                 return -EINVAL;
 709
 710         memset(smi->buf, '\0', sizeof(smi->buf));
 711         rtl8366_smi_read_reg(smi, RTL8366RB_PORT_LINK_STATUS_BASE +
 712                              (val->port_vlan / 2), &data);
 713
 714         if (val->port_vlan % 2)
 715                 data = data >> 8;
 716
 717         if (data & RTL8366RB_PORT_STATUS_LINK_MASK) {
 718                 len = snprintf(smi->buf, sizeof(smi->buf),
 719                                 "port:%d link:up speed:%s %s-duplex %s%s%s",
 720                                 val->port_vlan,
 721                                 rtl8366rb_speed_str(data &
 722                                           RTL8366RB_PORT_STATUS_SPEED_MASK),
 723                                 (data & RTL8366RB_PORT_STATUS_DUPLEX_MASK) ?
 724                                         "full" : "half",
 725                                 (data & RTL8366RB_PORT_STATUS_TXPAUSE_MASK) ?
 726                                         "tx-pause ": "",
 727                                 (data & RTL8366RB_PORT_STATUS_RXPAUSE_MASK) ?
 728                                         "rx-pause " : "",
 729                                 (data & RTL8366RB_PORT_STATUS_AN_MASK) ?
 730                                         "nway ": "");
 731         } else {
 732                 len = snprintf(smi->buf, sizeof(smi->buf), "port:%d link: down",
 733                                 val->port_vlan);
 734         }
 735
 736         val->value.s = smi->buf;
 737         val->len = len;
 738
 739         return 0;
 740 }
 741
 742 static int rtl8366rb_sw_set_port_led(struct switch_dev *dev,
 743                                     const struct switch_attr *attr,
 744                                     struct switch_val *val)
 745 {
 746         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
 747         u32 data;
 748         u32 mask;
 749         u32 reg;
 750
 751         if (val->port_vlan >= RTL8366RB_NUM_PORTS)
 752                 return -EINVAL;
 753
 754         if (val->port_vlan == RTL8366RB_PORT_NUM_CPU) {
 755                 reg = RTL8366RB_LED_BLINKRATE_REG;
 756                 mask = 0xF << 4;
 757                 data = val->value.i << 4;
 758         } else {
 759                 reg = RTL8366RB_LED_CTRL_REG;
 760                 mask = 0xF << (val->port_vlan * 4),
 761                 data = val->value.i << (val->port_vlan * 4);
 762         }
 763
 764         return rtl8366_smi_rmwr(smi, reg, mask, data);
 765 }
 766
 767 static int rtl8366rb_sw_get_port_led(struct switch_dev *dev,
 768                                     const struct switch_attr *attr,
 769                                     struct switch_val *val)
 770 {
 771         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
 772         u32 data = 0;
 773
 774         if (val->port_vlan >= RTL8366RB_NUM_LEDGROUPS)
 775                 return -EINVAL;
 776
 777         rtl8366_smi_read_reg(smi, RTL8366RB_LED_CTRL_REG, &data);
 778         val->value.i = (data >> (val->port_vlan * 4)) & 0x000F;
 779
 780         return 0;
 781 }
 782
 783 static int rtl8366rb_sw_set_port_disable(struct switch_dev *dev,
 784                                     const struct switch_attr *attr,
 785                                     struct switch_val *val)
 786 {
 787         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
 788         u32 mask, data;
 789
 790         if (val->port_vlan >= RTL8366RB_NUM_PORTS)
 791                 return -EINVAL;
 792
 793         mask = 1 << val->port_vlan ;
 794         if (val->value.i)
 795                 data = mask;
 796         else
 797                 data = 0;
 798
 799         return rtl8366_smi_rmwr(smi, RTL8366RB_PECR, mask, data);
 800 }
 801
 802 static int rtl8366rb_sw_get_port_disable(struct switch_dev *dev,
 803                                     const struct switch_attr *attr,
 804                                     struct switch_val *val)
 805 {
 806         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
 807         u32 data;
 808
 809         if (val->port_vlan >= RTL8366RB_NUM_PORTS)
 810                 return -EINVAL;
 811
 812         rtl8366_smi_read_reg(smi, RTL8366RB_PECR, &data);
 813         if (data & (1 << val->port_vlan))
 814                 val->value.i = 1;
 815         else
 816                 val->value.i = 0;
 817
 818         return 0;
 819 }
 820
 821 static int rtl8366rb_sw_set_port_rate_in(struct switch_dev *dev,
 822                                     const struct switch_attr *attr,
 823                                     struct switch_val *val)
 824 {
 825         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
 826
 827         if (val->port_vlan >= RTL8366RB_NUM_PORTS)
 828                 return -EINVAL;
 829
 830         if (val->value.i > 0 && val->value.i < RTL8366RB_BDTH_SW_MAX)
 831                 val->value.i = (val->value.i - 1) / RTL8366RB_BDTH_UNIT;
 832         else
 833                 val->value.i = RTL8366RB_BDTH_REG_DEFAULT;
 834
 835         return rtl8366_smi_rmwr(smi, RTL8366RB_IB_REG(val->port_vlan),
 836                 RTL8366RB_IB_BDTH_MASK | RTL8366RB_IB_PREIFG_MASK,
 837                 val->value.i |
 838                 (RTL8366RB_QOS_DEFAULT_PREIFG << RTL8366RB_IB_PREIFG_OFFSET));
 839
 840 }
 841
 842 static int rtl8366rb_sw_get_port_rate_in(struct switch_dev *dev,
 843                                     const struct switch_attr *attr,
 844                                     struct switch_val *val)
 845 {
 846         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
 847         u32 data;
 848
 849         if (val->port_vlan >= RTL8366RB_NUM_PORTS)
 850                 return -EINVAL;
 851
 852         rtl8366_smi_read_reg(smi, RTL8366RB_IB_REG(val->port_vlan), &data);
 853         data &= RTL8366RB_IB_BDTH_MASK;
 854         if (data < RTL8366RB_IB_BDTH_MASK)
 855                 data += 1;
 856
 857         val->value.i = (int)data * RTL8366RB_BDTH_UNIT;
 858
 859         return 0;
 860 }
 861
 862 static int rtl8366rb_sw_set_port_rate_out(struct switch_dev *dev,
 863                                     const struct switch_attr *attr,
 864                                     struct switch_val *val)
 865 {
 866         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
 867
 868         if (val->port_vlan >= RTL8366RB_NUM_PORTS)
 869                 return -EINVAL;
 870
 871         rtl8366_smi_rmwr(smi, RTL8366RB_EB_PREIFG_REG,
 872                 RTL8366RB_EB_PREIFG_MASK,
 873                 (RTL8366RB_QOS_DEFAULT_PREIFG << RTL8366RB_EB_PREIFG_OFFSET));
 874
 875         if (val->value.i > 0 && val->value.i < RTL8366RB_BDTH_SW_MAX)
 876                 val->value.i = (val->value.i - 1) / RTL8366RB_BDTH_UNIT;
 877         else
 878                 val->value.i = RTL8366RB_BDTH_REG_DEFAULT;
 879
 880         return rtl8366_smi_rmwr(smi, RTL8366RB_EB_REG(val->port_vlan),
 881                         RTL8366RB_EB_BDTH_MASK, val->value.i );
 882
 883 }
 884
 885 static int rtl8366rb_sw_get_port_rate_out(struct switch_dev *dev,
 886                                     const struct switch_attr *attr,
 887                                     struct switch_val *val)
 888 {
 889         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
 890         u32 data;
 891
 892         if (val->port_vlan >= RTL8366RB_NUM_PORTS)
 893                 return -EINVAL;
 894
 895         rtl8366_smi_read_reg(smi, RTL8366RB_EB_REG(val->port_vlan), &data);
 896         data &= RTL8366RB_EB_BDTH_MASK;
 897         if (data < RTL8366RB_EB_BDTH_MASK)
 898                 data += 1;
 899
 900         val->value.i = (int)data * RTL8366RB_BDTH_UNIT;
 901
 902         return 0;
 903 }
 904
 905 static int rtl8366rb_sw_set_qos_enable(struct switch_dev *dev,
 906                                     const struct switch_attr *attr,
 907                                     struct switch_val *val)
 908 {
 909         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
 910         u32 data;
 911
 912         if (val->value.i)
 913                 data = RTL8366RB_QOS_MASK;
 914         else
 915                 data = 0;
 916
 917         return rtl8366_smi_rmwr(smi, RTL8366RB_SGCR, RTL8366RB_QOS_MASK, data);
 918 }
 919
 920 static int rtl8366rb_sw_get_qos_enable(struct switch_dev *dev,
 921                                     const struct switch_attr *attr,
 922                                     struct switch_val *val)
 923 {
 924         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
 925         u32 data;
 926
 927         rtl8366_smi_read_reg(smi, RTL8366RB_SGCR, &data);
 928         if (data & RTL8366RB_QOS_MASK)
 929                 val->value.i = 1;
 930         else
 931                 val->value.i = 0;
 932
 933         return 0;
 934 }
 935
 936 static int rtl8366rb_sw_reset_port_mibs(struct switch_dev *dev,
 937                                        const struct switch_attr *attr,
 938                                        struct switch_val *val)
 939 {
 940         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
 941
 942         if (val->port_vlan >= RTL8366RB_NUM_PORTS)
 943                 return -EINVAL;
 944
 945         return rtl8366_smi_rmwr(smi, RTL8366RB_MIB_CTRL_REG, 0,
 946                                 RTL8366RB_MIB_CTRL_PORT_RESET(val->port_vlan));
 947 }
 948
 949 static int rtl8366rb_sw_reset_switch(struct switch_dev *dev)
 950 {
 951         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
 952         int err;
 953
 954         err = rtl8366rb_reset_chip(smi);
 955         if (err)
 956                 return err;
 957
 958         err = rtl8366rb_hw_init(smi);
 959         if (err)
 960                 return err;
 961
 962         err = rtl8366_reset_vlan(smi);
 963         if (err)
 964                 return err;
 965
 966         err = rtl8366_enable_vlan(smi, 1);
 967         if (err)
 968                 return err;
 969
 970         return rtl8366_enable_all_ports(smi, 1);
 971 }
 972
 973 static struct switch_attr rtl8366rb_globals[] = {
 974         {
 975                 .type = SWITCH_TYPE_INT,
 976                 .name = "enable_learning",
 977                 .description = "Enable learning, enable aging",
 978                 .set = rtl8366rb_sw_set_learning_enable,
 979                 .get = rtl8366rb_sw_get_learning_enable,
 980                 .max = 1
 981         }, {
 982                 .type = SWITCH_TYPE_INT,
 983                 .name = "enable_vlan",
 984                 .description = "Enable VLAN mode",
 985                 .set = rtl8366_sw_set_vlan_enable,
 986                 .get = rtl8366_sw_get_vlan_enable,
 987                 .max = 1,
 988                 .ofs = 1
 989         }, {
 990                 .type = SWITCH_TYPE_INT,
 991                 .name = "enable_vlan4k",
 992                 .description = "Enable VLAN 4K mode",
 993                 .set = rtl8366_sw_set_vlan_enable,
 994                 .get = rtl8366_sw_get_vlan_enable,
 995                 .max = 1,
 996                 .ofs = 2
 997         }, {
 998                 .type = SWITCH_TYPE_NOVAL,
 999                 .name = "reset_mibs",
1000                 .description = "Reset all MIB counters",
1001                 .set = rtl8366rb_sw_reset_mibs,
1002         }, {
1003                 .type = SWITCH_TYPE_INT,
1004                 .name = "blinkrate",
1005                 .description = "Get/Set LED blinking rate (0 = 43ms, 1 = 84ms,"
1006                 " 2 = 120ms, 3 = 170ms, 4 = 340ms, 5 = 670ms)",
1007                 .set = rtl8366rb_sw_set_blinkrate,
1008                 .get = rtl8366rb_sw_get_blinkrate,
1009                 .max = 5
1010         }, {
1011                 .type = SWITCH_TYPE_INT,
1012                 .name = "enable_qos",
1013                 .description = "Enable QOS",
1014                 .set = rtl8366rb_sw_set_qos_enable,
1015                 .get = rtl8366rb_sw_get_qos_enable,
1016                 .max = 1
1017         },
1018 };
1019
1020 static struct switch_attr rtl8366rb_port[] = {
1021         {
1022                 .type = SWITCH_TYPE_STRING,
1023                 .name = "link",
1024                 .description = "Get port link information",
1025                 .max = 1,
1026                 .set = NULL,
1027                 .get = rtl8366rb_sw_get_port_link,
1028         }, {
1029                 .type = SWITCH_TYPE_NOVAL,
1030                 .name = "reset_mib",
1031                 .description = "Reset single port MIB counters",
1032                 .set = rtl8366rb_sw_reset_port_mibs,
1033         }, {
1034                 .type = SWITCH_TYPE_STRING,
1035                 .name = "mib",
1036                 .description = "Get MIB counters for port",
1037                 .max = 33,
1038                 .set = NULL,
1039                 .get = rtl8366_sw_get_port_mib,
1040         }, {
1041                 .type = SWITCH_TYPE_INT,
1042                 .name = "led",
1043                 .description = "Get/Set port group (0 - 3) led mode (0 - 15)",
1044                 .max = 15,
1045                 .set = rtl8366rb_sw_set_port_led,
1046                 .get = rtl8366rb_sw_get_port_led,
1047         }, {
1048                 .type = SWITCH_TYPE_INT,
1049                 .name = "disable",
1050                 .description = "Get/Set port state (enabled or disabled)",
1051                 .max = 1,
1052                 .set = rtl8366rb_sw_set_port_disable,
1053                 .get = rtl8366rb_sw_get_port_disable,
1054         }, {
1055                 .type = SWITCH_TYPE_INT,
1056                 .name = "rate_in",
1057                 .description = "Get/Set port ingress (incoming) bandwidth limit in kbps",
1058                 .max = RTL8366RB_BDTH_SW_MAX,
1059                 .set = rtl8366rb_sw_set_port_rate_in,
1060                 .get = rtl8366rb_sw_get_port_rate_in,
1061         }, {
1062                 .type = SWITCH_TYPE_INT,
1063                 .name = "rate_out",
1064                 .description = "Get/Set port egress (outgoing) bandwidth limit in kbps",
1065                 .max = RTL8366RB_BDTH_SW_MAX,
1066                 .set = rtl8366rb_sw_set_port_rate_out,
1067                 .get = rtl8366rb_sw_get_port_rate_out,
1068         },
1069 };
1070
1071 static struct switch_attr rtl8366rb_vlan[] = {
1072         {
1073                 .type = SWITCH_TYPE_STRING,
1074                 .name = "info",
1075                 .description = "Get vlan information",
1076                 .max = 1,
1077                 .set = NULL,
1078                 .get = rtl8366_sw_get_vlan_info,
1079         }, {
1080                 .type = SWITCH_TYPE_INT,
1081                 .name = "fid",
1082                 .description = "Get/Set vlan FID",
1083                 .max = RTL8366RB_FIDMAX,
1084                 .set = rtl8366_sw_set_vlan_fid,
1085                 .get = rtl8366_sw_get_vlan_fid,
1086         },
1087 };
1088
1089 static const struct switch_dev_ops rtl8366_ops = {
1090         .attr_global = {
1091                 .attr = rtl8366rb_globals,
1092                 .n_attr = ARRAY_SIZE(rtl8366rb_globals),
1093         },
1094         .attr_port = {
1095                 .attr = rtl8366rb_port,
1096                 .n_attr = ARRAY_SIZE(rtl8366rb_port),
1097         },
1098         .attr_vlan = {
1099                 .attr = rtl8366rb_vlan,
1100                 .n_attr = ARRAY_SIZE(rtl8366rb_vlan),
1101         },
1102
1103         .get_vlan_ports = rtl8366_sw_get_vlan_ports,
1104         .set_vlan_ports = rtl8366_sw_set_vlan_ports,
1105         .get_port_pvid = rtl8366_sw_get_port_pvid,
1106         .set_port_pvid = rtl8366_sw_set_port_pvid,
1107         .reset_switch = rtl8366rb_sw_reset_switch,
1108 };
1109
1110 static int rtl8366rb_switch_init(struct rtl8366_smi *smi)
1111 {
1112         struct switch_dev *dev = &smi->sw_dev;
1113         int err;
1114
1115         dev->name = "RTL8366RB";
1116         dev->cpu_port = RTL8366RB_PORT_NUM_CPU;
1117         dev->ports = RTL8366RB_NUM_PORTS;
1118         dev->vlans = RTL8366RB_NUM_VIDS;
1119         dev->ops = &rtl8366_ops;
1120         dev->devname = dev_name(smi->parent);
1121
1122         err = register_switch(dev, NULL);
1123         if (err)
1124                 dev_err(smi->parent, "switch registration failed\n");
1125
1126         return err;
1127 }
1128
1129 static void rtl8366rb_switch_cleanup(struct rtl8366_smi *smi)
1130 {
1131         unregister_switch(&smi->sw_dev);
1132 }
1133
1134 static int rtl8366rb_mii_read(struct mii_bus *bus, int addr, int reg)
1135 {
1136         struct rtl8366_smi *smi = bus->priv;
1137         u32 val = 0;
1138         int err;
1139
1140         err = rtl8366rb_read_phy_reg(smi, addr, 0, reg, &val);
1141         if (err)
1142                 return 0xffff;
1143
1144         return val;
1145 }
1146
1147 static int rtl8366rb_mii_write(struct mii_bus *bus, int addr, int reg, u16 val)
1148 {
1149         struct rtl8366_smi *smi = bus->priv;
1150         u32 t;
1151         int err;
1152
1153         err = rtl8366rb_write_phy_reg(smi, addr, 0, reg, val);
1154         /* flush write */
1155         (void) rtl8366rb_read_phy_reg(smi, addr, 0, reg, &t);
1156
1157         return err;
1158 }
1159
1160 static int rtl8366rb_mii_bus_match(struct mii_bus *bus)
1161 {
1162         return (bus->read == rtl8366rb_mii_read &&
1163                 bus->write == rtl8366rb_mii_write);
1164 }
1165
1166 static int rtl8366rb_setup(struct rtl8366_smi *smi)
1167 {
1168         int ret;
1169
1170         ret = rtl8366rb_reset_chip(smi);
1171         if (ret)
1172                 return ret;
1173
1174         ret = rtl8366rb_hw_init(smi);
1175         return ret;
1176 }
1177
1178 static int rtl8366rb_detect(struct rtl8366_smi *smi)
1179 {
1180         u32 chip_id = 0;
1181         u32 chip_ver = 0;
1182         int ret;
1183
1184         ret = rtl8366_smi_read_reg(smi, RTL8366RB_CHIP_ID_REG, &chip_id);
1185         if (ret) {
1186                 dev_err(smi->parent, "unable to read chip id\n");
1187                 return ret;
1188         }
1189
1190         switch (chip_id) {
1191         case RTL8366RB_CHIP_ID_8366:
1192                 break;
1193         default:
1194                 dev_err(smi->parent, "unknown chip id (%04x)\n", chip_id);
1195                 return -ENODEV;
1196         }
1197
1198         ret = rtl8366_smi_read_reg(smi, RTL8366RB_CHIP_VERSION_CTRL_REG,
1199                                    &chip_ver);
1200         if (ret) {
1201                 dev_err(smi->parent, "unable to read chip version\n");
1202                 return ret;
1203         }
1204
1205         dev_info(smi->parent, "RTL%04x ver. %u chip found\n",
1206                  chip_id, chip_ver & RTL8366RB_CHIP_VERSION_MASK);
1207
1208         return 0;
1209 }
1210
1211 static struct rtl8366_smi_ops rtl8366rb_smi_ops = {
1212         .detect         = rtl8366rb_detect,
1213         .setup          = rtl8366rb_setup,
1214
1215         .mii_read       = rtl8366rb_mii_read,
1216         .mii_write      = rtl8366rb_mii_write,
1217
1218         .get_vlan_mc    = rtl8366rb_get_vlan_mc,
1219         .set_vlan_mc    = rtl8366rb_set_vlan_mc,
1220         .get_vlan_4k    = rtl8366rb_get_vlan_4k,
1221         .set_vlan_4k    = rtl8366rb_set_vlan_4k,
1222         .get_mc_index   = rtl8366rb_get_mc_index,
1223         .set_mc_index   = rtl8366rb_set_mc_index,
1224         .get_mib_counter = rtl8366rb_get_mib_counter,
1225         .is_vlan_valid  = rtl8366rb_is_vlan_valid,
1226         .enable_vlan    = rtl8366rb_enable_vlan,
1227         .enable_vlan4k  = rtl8366rb_enable_vlan4k,
1228         .enable_port    = rtl8366rb_enable_port,
1229 };
1230
1231 static int __devinit rtl8366rb_probe(struct platform_device *pdev)
1232 {
1233         static int rtl8366_smi_version_printed;
1234         struct rtl8366rb_platform_data *pdata;
1235         struct rtl8366_smi *smi;
1236         int err;
1237
1238         if (!rtl8366_smi_version_printed++)
1239                 printk(KERN_NOTICE RTL8366RB_DRIVER_DESC
1240                        " version " RTL8366RB_DRIVER_VER"\n");
1241
1242         pdata = pdev->dev.platform_data;
1243         if (!pdata) {
1244                 dev_err(&pdev->dev, "no platform data specified\n");
1245                 err = -EINVAL;
1246                 goto err_out;
1247         }
1248
1249         smi = rtl8366_smi_alloc(&pdev->dev);
1250         if (!smi) {
1251                 err = -ENOMEM;
1252                 goto err_out;
1253         }
1254
1255         smi->gpio_sda = pdata->gpio_sda;
1256         smi->gpio_sck = pdata->gpio_sck;
1257         smi->ops = &rtl8366rb_smi_ops;
1258         smi->cpu_port = RTL8366RB_PORT_NUM_CPU;
1259         smi->num_ports = RTL8366RB_NUM_PORTS;
1260         smi->num_vlan_mc = RTL8366RB_NUM_VLANS;
1261         smi->mib_counters = rtl8366rb_mib_counters;
1262         smi->num_mib_counters = ARRAY_SIZE(rtl8366rb_mib_counters);
1263
1264         err = rtl8366_smi_init(smi);
1265         if (err)
1266                 goto err_free_smi;
1267
1268         platform_set_drvdata(pdev, smi);
1269
1270         err = rtl8366rb_switch_init(smi);
1271         if (err)
1272                 goto err_clear_drvdata;
1273
1274         return 0;
1275
1276  err_clear_drvdata:
1277         platform_set_drvdata(pdev, NULL);
1278         rtl8366_smi_cleanup(smi);
1279  err_free_smi:
1280         kfree(smi);
1281  err_out:
1282         return err;
1283 }
1284
1285 static int rtl8366rb_phy_config_init(struct phy_device *phydev)
1286 {
1287         if (!rtl8366rb_mii_bus_match(phydev->bus))
1288                 return -EINVAL;
1289
1290         return 0;
1291 }
1292
1293 static int rtl8366rb_phy_config_aneg(struct phy_device *phydev)
1294 {
1295         /* phy 4 might be connected to a second mac, allow aneg config */
1296         if (phydev->addr == RTL8366RB_PHY_WAN)
1297                 return genphy_config_aneg(phydev);
1298
1299         return 0;
1300 }
1301
1302 static struct phy_driver rtl8366rb_phy_driver = {
1303         .phy_id         = 0x001cc960,
1304         .name           = "Realtek RTL8366RB",
1305         .phy_id_mask    = 0x1ffffff0,
1306         .features       = PHY_GBIT_FEATURES,
1307         .config_aneg    = rtl8366rb_phy_config_aneg,
1308         .config_init    = rtl8366rb_phy_config_init,
1309         .read_status    = genphy_read_status,
1310         .driver         = {
1311                 .owner = THIS_MODULE,
1312         },
1313 };
1314
1315 static int __devexit rtl8366rb_remove(struct platform_device *pdev)
1316 {
1317         struct rtl8366_smi *smi = platform_get_drvdata(pdev);
1318
1319         if (smi) {
1320                 rtl8366rb_switch_cleanup(smi);
1321                 platform_set_drvdata(pdev, NULL);
1322                 rtl8366_smi_cleanup(smi);
1323                 kfree(smi);
1324         }
1325
1326         return 0;
1327 }
1328
1329 static struct platform_driver rtl8366rb_driver = {
1330         .driver = {
1331                 .name           = RTL8366RB_DRIVER_NAME,
1332                 .owner          = THIS_MODULE,
1333         },
1334         .probe          = rtl8366rb_probe,
1335         .remove         = __devexit_p(rtl8366rb_remove),
1336 };
1337
1338 static int __init rtl8366rb_module_init(void)
1339 {
1340         int ret;
1341         ret = platform_driver_register(&rtl8366rb_driver);
1342         if (ret)
1343                 return ret;
1344
1345         ret = phy_driver_register(&rtl8366rb_phy_driver);
1346         if (ret)
1347                 goto err_platform_unregister;
1348
1349         return 0;
1350
1351  err_platform_unregister:
1352         platform_driver_unregister(&rtl8366rb_driver);
1353         return ret;
1354 }
1355 module_init(rtl8366rb_module_init);
1356
1357 static void __exit rtl8366rb_module_exit(void)
1358 {
1359         phy_driver_unregister(&rtl8366rb_phy_driver);
1360         platform_driver_unregister(&rtl8366rb_driver);
1361 }
1362 module_exit(rtl8366rb_module_exit);
1363
1364 MODULE_DESCRIPTION(RTL8366RB_DRIVER_DESC);
1365 MODULE_VERSION(RTL8366RB_DRIVER_VER);
1366 MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
1367 MODULE_AUTHOR("Antti Seppälä <a.seppala@gmail.com>");
1368 MODULE_AUTHOR("Roman Yeryomin <roman@advem.lv>");
1369 MODULE_LICENSE("GPL v2");
1370 MODULE_ALIAS("platform:" RTL8366RB_DRIVER_NAME);