target/linux/generic/files/drivers/net/phy/rtl8366rb.c

   1 /*
   2  * Platform driver for the Realtek RTL8366S ethernet switch
   3  *
   4  * Copyright (C) 2009-2010 Gabor Juhos <juhosg@openwrt.org>
   5  * Copyright (C) 2010 Antti Seppälä <a.seppala@gmail.com>
   6  *
   7  * This program is free software; you can redistribute it and/or modify it
   8  * under the terms of the GNU General Public License version 2 as published
   9  * by the Free Software Foundation.
  10  */
  11
  12 #include <linux/kernel.h>
  13 #include <linux/module.h>
  14 #include <linux/init.h>
  15 #include <linux/platform_device.h>
  16 #include <linux/delay.h>
  17 #include <linux/skbuff.h>
  18 #include <linux/switch.h>
  19 #include <linux/rtl8366rb.h>
  20
  21 #include "rtl8366_smi.h"
  22
  23 #define RTL8366RB_DRIVER_DESC   "Realtek RTL8366RB ethernet switch driver"
  24 #define RTL8366RB_DRIVER_VER    "0.2.2"
  25
  26 #define RTL8366RB_PHY_NO_MAX    4
  27 #define RTL8366RB_PHY_PAGE_MAX  7
  28 #define RTL8366RB_PHY_ADDR_MAX  31
  29
  30 /* Switch Global Configuration register */
  31 #define RTL8366RB_SGCR                          0x0000
  32 #define RTL8366RB_SGCR_EN_BC_STORM_CTRL         BIT(0)
  33 #define RTL8366RB_SGCR_MAX_LENGTH(_x)           (_x << 4)
  34 #define RTL8366RB_SGCR_MAX_LENGTH_MASK          RTL8366RB_SGCR_MAX_LENGTH(0x3)
  35 #define RTL8366RB_SGCR_MAX_LENGTH_1522          RTL8366RB_SGCR_MAX_LENGTH(0x0)
  36 #define RTL8366RB_SGCR_MAX_LENGTH_1536          RTL8366RB_SGCR_MAX_LENGTH(0x1)
  37 #define RTL8366RB_SGCR_MAX_LENGTH_1552          RTL8366RB_SGCR_MAX_LENGTH(0x2)
  38 #define RTL8366RB_SGCR_MAX_LENGTH_9216          RTL8366RB_SGCR_MAX_LENGTH(0x3)
  39 #define RTL8366RB_SGCR_EN_VLAN                  BIT(13)
  40 #define RTL8366RB_SGCR_EN_VLAN_4KTB             BIT(14)
  41
  42 /* Port Enable Control register */
  43 #define RTL8366RB_PECR                          0x0001
  44
  45 /* Switch Security Control registers */
  46 #define RTL8366RB_SSCR0                         0x0002
  47 #define RTL8366RB_SSCR1                         0x0003
  48 #define RTL8366RB_SSCR2                         0x0004
  49 #define RTL8366RB_SSCR2_DROP_UNKNOWN_DA         BIT(0)
  50
  51 #define RTL8366RB_RESET_CTRL_REG                0x0100
  52 #define RTL8366RB_CHIP_CTRL_RESET_HW            1
  53 #define RTL8366RB_CHIP_CTRL_RESET_SW            (1 << 1)
  54
  55 #define RTL8366RB_CHIP_VERSION_CTRL_REG         0x050A
  56 #define RTL8366RB_CHIP_VERSION_MASK             0xf
  57 #define RTL8366RB_CHIP_ID_REG                   0x0509
  58 #define RTL8366RB_CHIP_ID_8366                  0x5937
  59
  60 /* PHY registers control */
  61 #define RTL8366RB_PHY_ACCESS_CTRL_REG           0x8000
  62 #define RTL8366RB_PHY_ACCESS_DATA_REG           0x8002
  63
  64 #define RTL8366RB_PHY_CTRL_READ                 1
  65 #define RTL8366RB_PHY_CTRL_WRITE                0
  66
  67 #define RTL8366RB_PHY_REG_MASK                  0x1f
  68 #define RTL8366RB_PHY_PAGE_OFFSET               5
  69 #define RTL8366RB_PHY_PAGE_MASK                 (0xf << 5)
  70 #define RTL8366RB_PHY_NO_OFFSET                 9
  71 #define RTL8366RB_PHY_NO_MASK                   (0x1f << 9)
  72
  73 #define RTL8366RB_VLAN_INGRESS_CTRL2_REG        0x037f
  74
  75 /* LED control registers */
  76 #define RTL8366RB_LED_BLINKRATE_REG             0x0430
  77 #define RTL8366RB_LED_BLINKRATE_BIT             0
  78 #define RTL8366RB_LED_BLINKRATE_MASK            0x0007
  79
  80 #define RTL8366RB_LED_CTRL_REG                  0x0431
  81 #define RTL8366RB_LED_0_1_CTRL_REG              0x0432
  82 #define RTL8366RB_LED_2_3_CTRL_REG              0x0433
  83
  84 #define RTL8366RB_MIB_COUNT                     33
  85 #define RTL8366RB_GLOBAL_MIB_COUNT              1
  86 #define RTL8366RB_MIB_COUNTER_PORT_OFFSET       0x0050
  87 #define RTL8366RB_MIB_COUNTER_BASE              0x1000
  88 #define RTL8366RB_MIB_CTRL_REG                  0x13F0
  89 #define RTL8366RB_MIB_CTRL_USER_MASK            0x0FFC
  90 #define RTL8366RB_MIB_CTRL_BUSY_MASK            BIT(0)
  91 #define RTL8366RB_MIB_CTRL_RESET_MASK           BIT(1)
  92 #define RTL8366RB_MIB_CTRL_PORT_RESET(_p)       BIT(2 + (_p))
  93 #define RTL8366RB_MIB_CTRL_GLOBAL_RESET         BIT(11)
  94
  95 #define RTL8366RB_PORT_VLAN_CTRL_BASE           0x0063
  96 #define RTL8366RB_PORT_VLAN_CTRL_REG(_p)  \
  97                 (RTL8366RB_PORT_VLAN_CTRL_BASE + (_p) / 4)
  98 #define RTL8366RB_PORT_VLAN_CTRL_MASK           0xf
  99 #define RTL8366RB_PORT_VLAN_CTRL_SHIFT(_p)      (4 * ((_p) % 4))
 100
 101
 102 #define RTL8366RB_VLAN_TABLE_READ_BASE          0x018C
 103 #define RTL8366RB_VLAN_TABLE_WRITE_BASE         0x0185
 104
 105
 106 #define RTL8366RB_TABLE_ACCESS_CTRL_REG         0x0180
 107 #define RTL8366RB_TABLE_VLAN_READ_CTRL          0x0E01
 108 #define RTL8366RB_TABLE_VLAN_WRITE_CTRL         0x0F01
 109
 110 #define RTL8366RB_VLAN_MC_BASE(_x)              (0x0020 + (_x) * 3)
 111
 112
 113 #define RTL8366RB_PORT_LINK_STATUS_BASE         0x0014
 114 #define RTL8366RB_PORT_STATUS_SPEED_MASK        0x0003
 115 #define RTL8366RB_PORT_STATUS_DUPLEX_MASK       0x0004
 116 #define RTL8366RB_PORT_STATUS_LINK_MASK         0x0010
 117 #define RTL8366RB_PORT_STATUS_TXPAUSE_MASK      0x0020
 118 #define RTL8366RB_PORT_STATUS_RXPAUSE_MASK      0x0040
 119 #define RTL8366RB_PORT_STATUS_AN_MASK           0x0080
 120
 121
 122 #define RTL8366RB_PORT_NUM_CPU          5
 123 #define RTL8366RB_NUM_PORTS             6
 124 #define RTL8366RB_NUM_VLANS             16
 125 #define RTL8366RB_NUM_LEDGROUPS         4
 126 #define RTL8366RB_NUM_VIDS              4096
 127 #define RTL8366RB_PRIORITYMAX           7
 128 #define RTL8366RB_FIDMAX                7
 129
 130
 131 #define RTL8366RB_PORT_1                (1 << 0) /* In userspace port 0 */
 132 #define RTL8366RB_PORT_2                (1 << 1) /* In userspace port 1 */
 133 #define RTL8366RB_PORT_3                (1 << 2) /* In userspace port 2 */
 134 #define RTL8366RB_PORT_4                (1 << 3) /* In userspace port 3 */
 135 #define RTL8366RB_PORT_5                (1 << 4) /* In userspace port 4 */
 136
 137 #define RTL8366RB_PORT_CPU              (1 << 5) /* CPU port */
 138
 139 #define RTL8366RB_PORT_ALL              (RTL8366RB_PORT_1 |     \
 140                                          RTL8366RB_PORT_2 |     \
 141                                          RTL8366RB_PORT_3 |     \
 142                                          RTL8366RB_PORT_4 |     \
 143                                          RTL8366RB_PORT_5 |     \
 144                                          RTL8366RB_PORT_CPU)
 145
 146 #define RTL8366RB_PORT_ALL_BUT_CPU      (RTL8366RB_PORT_1 |     \
 147                                          RTL8366RB_PORT_2 |     \
 148                                          RTL8366RB_PORT_3 |     \
 149                                          RTL8366RB_PORT_4 |     \
 150                                          RTL8366RB_PORT_5)
 151
 152 #define RTL8366RB_PORT_ALL_EXTERNAL     (RTL8366RB_PORT_1 |     \
 153                                          RTL8366RB_PORT_2 |     \
 154                                          RTL8366RB_PORT_3 |     \
 155                                          RTL8366RB_PORT_4)
 156
 157 #define RTL8366RB_PORT_ALL_INTERNAL      RTL8366RB_PORT_CPU
 158
 159 #define RTL8366RB_VLAN_VID_MASK         0xfff
 160 #define RTL8366RB_VLAN_PRIORITY_SHIFT   12
 161 #define RTL8366RB_VLAN_PRIORITY_MASK    0x7
 162 #define RTL8366RB_VLAN_UNTAG_SHIFT      8
 163 #define RTL8366RB_VLAN_UNTAG_MASK       0xff
 164 #define RTL8366RB_VLAN_MEMBER_MASK      0xff
 165 #define RTL8366RB_VLAN_FID_MASK         0x7
 166
 167 struct rtl8366rb {
 168         struct device           *parent;
 169         struct rtl8366_smi      smi;
 170         struct switch_dev       dev;
 171 };
 172
 173 static struct rtl8366_mib_counter rtl8366rb_mib_counters[] = {
 174         { 0,  0, 4, "IfInOctets"                                },
 175         { 0,  4, 4, "EtherStatsOctets"                          },
 176         { 0,  8, 2, "EtherStatsUnderSizePkts"                   },
 177         { 0, 10, 2, "EtherFragments"                            },
 178         { 0, 12, 2, "EtherStatsPkts64Octets"                    },
 179         { 0, 14, 2, "EtherStatsPkts65to127Octets"               },
 180         { 0, 16, 2, "EtherStatsPkts128to255Octets"              },
 181         { 0, 18, 2, "EtherStatsPkts256to511Octets"              },
 182         { 0, 20, 2, "EtherStatsPkts512to1023Octets"             },
 183         { 0, 22, 2, "EtherStatsPkts1024to1518Octets"            },
 184         { 0, 24, 2, "EtherOversizeStats"                        },
 185         { 0, 26, 2, "EtherStatsJabbers"                         },
 186         { 0, 28, 2, "IfInUcastPkts"                             },
 187         { 0, 30, 2, "EtherStatsMulticastPkts"                   },
 188         { 0, 32, 2, "EtherStatsBroadcastPkts"                   },
 189         { 0, 34, 2, "EtherStatsDropEvents"                      },
 190         { 0, 36, 2, "Dot3StatsFCSErrors"                        },
 191         { 0, 38, 2, "Dot3StatsSymbolErrors"                     },
 192         { 0, 40, 2, "Dot3InPauseFrames"                         },
 193         { 0, 42, 2, "Dot3ControlInUnknownOpcodes"               },
 194         { 0, 44, 4, "IfOutOctets"                               },
 195         { 0, 48, 2, "Dot3StatsSingleCollisionFrames"            },
 196         { 0, 50, 2, "Dot3StatMultipleCollisionFrames"           },
 197         { 0, 52, 2, "Dot3sDeferredTransmissions"                },
 198         { 0, 54, 2, "Dot3StatsLateCollisions"                   },
 199         { 0, 56, 2, "EtherStatsCollisions"                      },
 200         { 0, 58, 2, "Dot3StatsExcessiveCollisions"              },
 201         { 0, 60, 2, "Dot3OutPauseFrames"                        },
 202         { 0, 62, 2, "Dot1dBasePortDelayExceededDiscards"        },
 203         { 0, 64, 2, "Dot1dTpPortInDiscards"                     },
 204         { 0, 66, 2, "IfOutUcastPkts"                            },
 205         { 0, 68, 2, "IfOutMulticastPkts"                        },
 206         { 0, 70, 2, "IfOutBroadcastPkts"                        },
 207 };
 208
 209 #define REG_WR(_smi, _reg, _val)                                        \
 210         do {                                                            \
 211                 err = rtl8366_smi_write_reg(_smi, _reg, _val);          \
 212                 if (err)                                                \
 213                         return err;                                     \
 214         } while (0)
 215
 216 #define REG_RMW(_smi, _reg, _mask, _val)                                \
 217         do {                                                            \
 218                 err = rtl8366_smi_rmwr(_smi, _reg, _mask, _val);        \
 219                 if (err)                                                \
 220                         return err;                                     \
 221         } while (0)
 222
 223 static inline struct rtl8366rb *smi_to_rtl8366rb(struct rtl8366_smi *smi)
 224 {
 225         return container_of(smi, struct rtl8366rb, smi);
 226 }
 227
 228 static inline struct rtl8366rb *sw_to_rtl8366rb(struct switch_dev *sw)
 229 {
 230         return container_of(sw, struct rtl8366rb, dev);
 231 }
 232
 233 static inline struct rtl8366_smi *sw_to_rtl8366_smi(struct switch_dev *sw)
 234 {
 235         struct rtl8366rb *rtl = sw_to_rtl8366rb(sw);
 236         return &rtl->smi;
 237 }
 238
 239 static int rtl8366rb_reset_chip(struct rtl8366_smi *smi)
 240 {
 241         int timeout = 10;
 242         u32 data;
 243
 244         rtl8366_smi_write_reg(smi, RTL8366RB_RESET_CTRL_REG,
 245                               RTL8366RB_CHIP_CTRL_RESET_HW);
 246         do {
 247                 msleep(1);
 248                 if (rtl8366_smi_read_reg(smi, RTL8366RB_RESET_CTRL_REG, &data))
 249                         return -EIO;
 250
 251                 if (!(data & RTL8366RB_CHIP_CTRL_RESET_HW))
 252                         break;
 253         } while (--timeout);
 254
 255         if (!timeout) {
 256                 printk("Timeout waiting for the switch to reset\n");
 257                 return -EIO;
 258         }
 259
 260         return 0;
 261 }
 262
 263 static int rtl8366rb_hw_init(struct rtl8366_smi *smi)
 264 {
 265         int err;
 266
 267         /* set maximum packet length to 1536 bytes */
 268         REG_RMW(smi, RTL8366RB_SGCR, RTL8366RB_SGCR_MAX_LENGTH_MASK,
 269                 RTL8366RB_SGCR_MAX_LENGTH_1536);
 270
 271         /* enable all ports */
 272         REG_WR(smi, RTL8366RB_PECR, 0);
 273
 274         /* disable learning for all ports */
 275         REG_WR(smi, RTL8366RB_SSCR0, RTL8366RB_PORT_ALL);
 276
 277         /* disable auto ageing for all ports */
 278         REG_WR(smi, RTL8366RB_SSCR1, RTL8366RB_PORT_ALL);
 279
 280         /*
 281          * discard VLAN tagged packets if the port is not a member of
 282          * the VLAN with which the packets is associated.
 283          */
 284         REG_WR(smi, RTL8366RB_VLAN_INGRESS_CTRL2_REG, RTL8366RB_PORT_ALL);
 285
 286         /* don't drop packets whose DA has not been learned */
 287         REG_RMW(smi, RTL8366RB_SSCR2, RTL8366RB_SSCR2_DROP_UNKNOWN_DA, 0);
 288
 289         return 0;
 290 }
 291
 292 static int rtl8366rb_read_phy_reg(struct rtl8366_smi *smi,
 293                                  u32 phy_no, u32 page, u32 addr, u32 *data)
 294 {
 295         u32 reg;
 296         int ret;
 297
 298         if (phy_no > RTL8366RB_PHY_NO_MAX)
 299                 return -EINVAL;
 300
 301         if (page > RTL8366RB_PHY_PAGE_MAX)
 302                 return -EINVAL;
 303
 304         if (addr > RTL8366RB_PHY_ADDR_MAX)
 305                 return -EINVAL;
 306
 307         ret = rtl8366_smi_write_reg(smi, RTL8366RB_PHY_ACCESS_CTRL_REG,
 308                                     RTL8366RB_PHY_CTRL_READ);
 309         if (ret)
 310                 return ret;
 311
 312         reg = 0x8000 | (1 << (phy_no + RTL8366RB_PHY_NO_OFFSET)) |
 313               ((page << RTL8366RB_PHY_PAGE_OFFSET) & RTL8366RB_PHY_PAGE_MASK) |
 314               (addr & RTL8366RB_PHY_REG_MASK);
 315
 316         ret = rtl8366_smi_write_reg(smi, reg, 0);
 317         if (ret)
 318                 return ret;
 319
 320         ret = rtl8366_smi_read_reg(smi, RTL8366RB_PHY_ACCESS_DATA_REG, data);
 321         if (ret)
 322                 return ret;
 323
 324         return 0;
 325 }
 326
 327 static int rtl8366rb_write_phy_reg(struct rtl8366_smi *smi,
 328                                   u32 phy_no, u32 page, u32 addr, u32 data)
 329 {
 330         u32 reg;
 331         int ret;
 332
 333         if (phy_no > RTL8366RB_PHY_NO_MAX)
 334                 return -EINVAL;
 335
 336         if (page > RTL8366RB_PHY_PAGE_MAX)
 337                 return -EINVAL;
 338
 339         if (addr > RTL8366RB_PHY_ADDR_MAX)
 340                 return -EINVAL;
 341
 342         ret = rtl8366_smi_write_reg(smi, RTL8366RB_PHY_ACCESS_CTRL_REG,
 343                                     RTL8366RB_PHY_CTRL_WRITE);
 344         if (ret)
 345                 return ret;
 346
 347         reg = 0x8000 | (1 << (phy_no + RTL8366RB_PHY_NO_OFFSET)) |
 348               ((page << RTL8366RB_PHY_PAGE_OFFSET) & RTL8366RB_PHY_PAGE_MASK) |
 349               (addr & RTL8366RB_PHY_REG_MASK);
 350
 351         ret = rtl8366_smi_write_reg(smi, reg, data);
 352         if (ret)
 353                 return ret;
 354
 355         return 0;
 356 }
 357
 358 static int rtl8366rb_get_mib_counter(struct rtl8366_smi *smi, int counter,
 359                                      int port, unsigned long long *val)
 360 {
 361         int i;
 362         int err;
 363         u32 addr, data;
 364         u64 mibvalue;
 365
 366         if (port > RTL8366RB_NUM_PORTS || counter >= RTL8366RB_MIB_COUNT)
 367                 return -EINVAL;
 368
 369         addr = RTL8366RB_MIB_COUNTER_BASE +
 370                RTL8366RB_MIB_COUNTER_PORT_OFFSET * (port) +
 371                rtl8366rb_mib_counters[counter].offset;
 372
 373         /*
 374          * Writing access counter address first
 375          * then ASIC will prepare 64bits counter wait for being retrived
 376          */
 377         data = 0; /* writing data will be discard by ASIC */
 378         err = rtl8366_smi_write_reg(smi, addr, data);
 379         if (err)
 380                 return err;
 381
 382         /* read MIB control register */
 383         err =  rtl8366_smi_read_reg(smi, RTL8366RB_MIB_CTRL_REG, &data);
 384         if (err)
 385                 return err;
 386
 387         if (data & RTL8366RB_MIB_CTRL_BUSY_MASK)
 388                 return -EBUSY;
 389
 390         if (data & RTL8366RB_MIB_CTRL_RESET_MASK)
 391                 return -EIO;
 392
 393         mibvalue = 0;
 394         for (i = rtl8366rb_mib_counters[counter].length; i > 0; i--) {
 395                 err = rtl8366_smi_read_reg(smi, addr + (i - 1), &data);
 396                 if (err)
 397                         return err;
 398
 399                 mibvalue = (mibvalue << 16) | (data & 0xFFFF);
 400         }
 401
 402         *val = mibvalue;
 403         return 0;
 404 }
 405
 406 static int rtl8366rb_get_vlan_4k(struct rtl8366_smi *smi, u32 vid,
 407                                  struct rtl8366_vlan_4k *vlan4k)
 408 {
 409         u32 data[3];
 410         int err;
 411         int i;
 412
 413         memset(vlan4k, '\0', sizeof(struct rtl8366_vlan_4k));
 414
 415         if (vid >= RTL8366RB_NUM_VIDS)
 416                 return -EINVAL;
 417
 418         /* write VID */
 419         err = rtl8366_smi_write_reg(smi, RTL8366RB_VLAN_TABLE_WRITE_BASE,
 420                                     vid & RTL8366RB_VLAN_VID_MASK);
 421         if (err)
 422                 return err;
 423
 424         /* write table access control word */
 425         err = rtl8366_smi_write_reg(smi, RTL8366RB_TABLE_ACCESS_CTRL_REG,
 426                                     RTL8366RB_TABLE_VLAN_READ_CTRL);
 427         if (err)
 428                 return err;
 429
 430         for (i = 0; i < 3; i++) {
 431                 err = rtl8366_smi_read_reg(smi,
 432                                            RTL8366RB_VLAN_TABLE_READ_BASE + i,
 433                                            &data[i]);
 434                 if (err)
 435                         return err;
 436         }
 437
 438         vlan4k->vid = vid;
 439         vlan4k->untag = (data[1] >> RTL8366RB_VLAN_UNTAG_SHIFT) &
 440                         RTL8366RB_VLAN_UNTAG_MASK;
 441         vlan4k->member = data[1] & RTL8366RB_VLAN_MEMBER_MASK;
 442         vlan4k->fid = data[2] & RTL8366RB_VLAN_FID_MASK;
 443
 444         return 0;
 445 }
 446
 447 static int rtl8366rb_set_vlan_4k(struct rtl8366_smi *smi,
 448                                  const struct rtl8366_vlan_4k *vlan4k)
 449 {
 450         u32 data[3];
 451         int err;
 452         int i;
 453
 454         if (vlan4k->vid >= RTL8366RB_NUM_VIDS ||
 455             vlan4k->member > RTL8366RB_PORT_ALL ||
 456             vlan4k->untag > RTL8366RB_PORT_ALL ||
 457             vlan4k->fid > RTL8366RB_FIDMAX)
 458                 return -EINVAL;
 459
 460         data[0] = vlan4k->vid & RTL8366RB_VLAN_VID_MASK;
 461         data[1] = (vlan4k->member & RTL8366RB_VLAN_MEMBER_MASK) |
 462                   ((vlan4k->untag & RTL8366RB_VLAN_UNTAG_MASK) <<
 463                         RTL8366RB_VLAN_UNTAG_SHIFT);
 464         data[2] = vlan4k->fid & RTL8366RB_VLAN_FID_MASK;
 465
 466         for (i = 0; i < 3; i++) {
 467                 err = rtl8366_smi_write_reg(smi,
 468                                             RTL8366RB_VLAN_TABLE_WRITE_BASE + i,
 469                                             data[i]);
 470                 if (err)
 471                         return err;
 472         }
 473
 474         /* write table access control word */
 475         err = rtl8366_smi_write_reg(smi, RTL8366RB_TABLE_ACCESS_CTRL_REG,
 476                                     RTL8366RB_TABLE_VLAN_WRITE_CTRL);
 477
 478         return err;
 479 }
 480
 481 static int rtl8366rb_get_vlan_mc(struct rtl8366_smi *smi, u32 index,
 482                                  struct rtl8366_vlan_mc *vlanmc)
 483 {
 484         u32 data[3];
 485         int err;
 486         int i;
 487
 488         memset(vlanmc, '\0', sizeof(struct rtl8366_vlan_mc));
 489
 490         if (index >= RTL8366RB_NUM_VLANS)
 491                 return -EINVAL;
 492
 493         for (i = 0; i < 3; i++) {
 494                 err = rtl8366_smi_read_reg(smi,
 495                                            RTL8366RB_VLAN_MC_BASE(index) + i,
 496                                            &data[i]);
 497                 if (err)
 498                         return err;
 499         }
 500
 501         vlanmc->vid = data[0] & RTL8366RB_VLAN_VID_MASK;
 502         vlanmc->priority = (data[0] >> RTL8366RB_VLAN_PRIORITY_SHIFT) &
 503                            RTL8366RB_VLAN_PRIORITY_MASK;
 504         vlanmc->untag = (data[1] >> RTL8366RB_VLAN_UNTAG_SHIFT) &
 505                         RTL8366RB_VLAN_UNTAG_MASK;
 506         vlanmc->member = data[1] & RTL8366RB_VLAN_MEMBER_MASK;
 507         vlanmc->fid = data[2] & RTL8366RB_VLAN_FID_MASK;
 508
 509         return 0;
 510 }
 511
 512 static int rtl8366rb_set_vlan_mc(struct rtl8366_smi *smi, u32 index,
 513                                  const struct rtl8366_vlan_mc *vlanmc)
 514 {
 515         u32 data[3];
 516         int err;
 517         int i;
 518
 519         if (index >= RTL8366RB_NUM_VLANS ||
 520             vlanmc->vid >= RTL8366RB_NUM_VIDS ||
 521             vlanmc->priority > RTL8366RB_PRIORITYMAX ||
 522             vlanmc->member > RTL8366RB_PORT_ALL ||
 523             vlanmc->untag > RTL8366RB_PORT_ALL ||
 524             vlanmc->fid > RTL8366RB_FIDMAX)
 525                 return -EINVAL;
 526
 527         data[0] = (vlanmc->vid & RTL8366RB_VLAN_VID_MASK) |
 528                   ((vlanmc->priority & RTL8366RB_VLAN_PRIORITY_MASK) <<
 529                         RTL8366RB_VLAN_PRIORITY_SHIFT);
 530         data[1] = (vlanmc->member & RTL8366RB_VLAN_MEMBER_MASK) |
 531                   ((vlanmc->untag & RTL8366RB_VLAN_UNTAG_MASK) <<
 532                         RTL8366RB_VLAN_UNTAG_SHIFT);
 533         data[2] = vlanmc->fid & RTL8366RB_VLAN_FID_MASK;
 534
 535         for (i = 0; i < 3; i++) {
 536                 err = rtl8366_smi_write_reg(smi,
 537                                             RTL8366RB_VLAN_MC_BASE(index) + i,
 538                                             data[i]);
 539                 if (err)
 540                         return err;
 541         }
 542
 543         return 0;
 544 }
 545
 546 static int rtl8366rb_get_mc_index(struct rtl8366_smi *smi, int port, int *val)
 547 {
 548         u32 data;
 549         int err;
 550
 551         if (port >= RTL8366RB_NUM_PORTS)
 552                 return -EINVAL;
 553
 554         err = rtl8366_smi_read_reg(smi, RTL8366RB_PORT_VLAN_CTRL_REG(port),
 555                                    &data);
 556         if (err)
 557                 return err;
 558
 559         *val = (data >> RTL8366RB_PORT_VLAN_CTRL_SHIFT(port)) &
 560                RTL8366RB_PORT_VLAN_CTRL_MASK;
 561
 562         return 0;
 563
 564 }
 565
 566 static int rtl8366rb_set_mc_index(struct rtl8366_smi *smi, int port, int index)
 567 {
 568         if (port >= RTL8366RB_NUM_PORTS || index >= RTL8366RB_NUM_VLANS)
 569                 return -EINVAL;
 570
 571         return rtl8366_smi_rmwr(smi, RTL8366RB_PORT_VLAN_CTRL_REG(port),
 572                                 RTL8366RB_PORT_VLAN_CTRL_MASK <<
 573                                         RTL8366RB_PORT_VLAN_CTRL_SHIFT(port),
 574                                 (index & RTL8366RB_PORT_VLAN_CTRL_MASK) <<
 575                                         RTL8366RB_PORT_VLAN_CTRL_SHIFT(port));
 576 }
 577
 578 static int rtl8366rb_vlan_set_vlan(struct rtl8366_smi *smi, int enable)
 579 {
 580         return rtl8366_smi_rmwr(smi, RTL8366RB_SGCR, RTL8366RB_SGCR_EN_VLAN,
 581                                 (enable) ? RTL8366RB_SGCR_EN_VLAN : 0);
 582 }
 583
 584 static int rtl8366rb_vlan_set_4ktable(struct rtl8366_smi *smi, int enable)
 585 {
 586         return rtl8366_smi_rmwr(smi, RTL8366RB_SGCR,
 587                                 RTL8366RB_SGCR_EN_VLAN_4KTB,
 588                                 (enable) ? RTL8366RB_SGCR_EN_VLAN_4KTB : 0);
 589 }
 590
 591 static int rtl8366rb_sw_reset_mibs(struct switch_dev *dev,
 592                                   const struct switch_attr *attr,
 593                                   struct switch_val *val)
 594 {
 595         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
 596
 597         return rtl8366_smi_rmwr(smi, RTL8366RB_MIB_CTRL_REG, 0,
 598                                 RTL8366RB_MIB_CTRL_GLOBAL_RESET);
 599 }
 600
 601 static int rtl8366rb_sw_get_vlan_enable(struct switch_dev *dev,
 602                                        const struct switch_attr *attr,
 603                                        struct switch_val *val)
 604 {
 605         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
 606         u32 data;
 607
 608         if (attr->ofs == 1) {
 609                 rtl8366_smi_read_reg(smi, RTL8366RB_SGCR, &data);
 610
 611                 if (data & RTL8366RB_SGCR_EN_VLAN)
 612                         val->value.i = 1;
 613                 else
 614                         val->value.i = 0;
 615         } else if (attr->ofs == 2) {
 616                 rtl8366_smi_read_reg(smi, RTL8366RB_SGCR, &data);
 617
 618                 if (data & RTL8366RB_SGCR_EN_VLAN_4KTB)
 619                         val->value.i = 1;
 620                 else
 621                         val->value.i = 0;
 622         }
 623
 624         return 0;
 625 }
 626
 627 static int rtl8366rb_sw_get_blinkrate(struct switch_dev *dev,
 628                                      const struct switch_attr *attr,
 629                                      struct switch_val *val)
 630 {
 631         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
 632         u32 data;
 633
 634         rtl8366_smi_read_reg(smi, RTL8366RB_LED_BLINKRATE_REG, &data);
 635
 636         val->value.i = (data & (RTL8366RB_LED_BLINKRATE_MASK));
 637
 638         return 0;
 639 }
 640
 641 static int rtl8366rb_sw_set_blinkrate(struct switch_dev *dev,
 642                                     const struct switch_attr *attr,
 643                                     struct switch_val *val)
 644 {
 645         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
 646
 647         if (val->value.i >= 6)
 648                 return -EINVAL;
 649
 650         return rtl8366_smi_rmwr(smi, RTL8366RB_LED_BLINKRATE_REG,
 651                                 RTL8366RB_LED_BLINKRATE_MASK,
 652                                 val->value.i);
 653 }
 654
 655 static int rtl8366rb_sw_set_vlan_enable(struct switch_dev *dev,
 656                                        const struct switch_attr *attr,
 657                                        struct switch_val *val)
 658 {
 659         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
 660
 661         if (attr->ofs == 1)
 662                 return rtl8366rb_vlan_set_vlan(smi, val->value.i);
 663         else
 664                 return rtl8366rb_vlan_set_4ktable(smi, val->value.i);
 665 }
 666
 667 static const char *rtl8366rb_speed_str(unsigned speed)
 668 {
 669         switch (speed) {
 670         case 0:
 671                 return "10baseT";
 672         case 1:
 673                 return "100baseT";
 674         case 2:
 675                 return "1000baseT";
 676         }
 677
 678         return "unknown";
 679 }
 680
 681 static int rtl8366rb_sw_get_port_link(struct switch_dev *dev,
 682                                      const struct switch_attr *attr,
 683                                      struct switch_val *val)
 684 {
 685         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
 686         u32 len = 0, data = 0;
 687
 688         if (val->port_vlan >= RTL8366RB_NUM_PORTS)
 689                 return -EINVAL;
 690
 691         memset(smi->buf, '\0', sizeof(smi->buf));
 692         rtl8366_smi_read_reg(smi, RTL8366RB_PORT_LINK_STATUS_BASE +
 693                              (val->port_vlan / 2), &data);
 694
 695         if (val->port_vlan % 2)
 696                 data = data >> 8;
 697
 698         if (data & RTL8366RB_PORT_STATUS_LINK_MASK) {
 699                 len = snprintf(smi->buf, sizeof(smi->buf),
 700                                 "port:%d link:up speed:%s %s-duplex %s%s%s",
 701                                 val->port_vlan,
 702                                 rtl8366rb_speed_str(data &
 703                                           RTL8366RB_PORT_STATUS_SPEED_MASK),
 704                                 (data & RTL8366RB_PORT_STATUS_DUPLEX_MASK) ?
 705                                         "full" : "half",
 706                                 (data & RTL8366RB_PORT_STATUS_TXPAUSE_MASK) ?
 707                                         "tx-pause ": "",
 708                                 (data & RTL8366RB_PORT_STATUS_RXPAUSE_MASK) ?
 709                                         "rx-pause " : "",
 710                                 (data & RTL8366RB_PORT_STATUS_AN_MASK) ?
 711                                         "nway ": "");
 712         } else {
 713                 len = snprintf(smi->buf, sizeof(smi->buf), "port:%d link: down",
 714                                 val->port_vlan);
 715         }
 716
 717         val->value.s = smi->buf;
 718         val->len = len;
 719
 720         return 0;
 721 }
 722
 723 static int rtl8366rb_sw_get_vlan_info(struct switch_dev *dev,
 724                                      const struct switch_attr *attr,
 725                                      struct switch_val *val)
 726 {
 727         int i;
 728         u32 len = 0;
 729         struct rtl8366_vlan_4k vlan4k;
 730         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
 731         char *buf = smi->buf;
 732         int err;
 733
 734         if (val->port_vlan == 0 || val->port_vlan >= RTL8366RB_NUM_VLANS)
 735                 return -EINVAL;
 736
 737         memset(buf, '\0', sizeof(smi->buf));
 738
 739         err = rtl8366rb_get_vlan_4k(smi, val->port_vlan, &vlan4k);
 740         if (err)
 741                 return err;
 742
 743         len += snprintf(buf + len, sizeof(smi->buf) - len,
 744                         "VLAN %d: Ports: '", vlan4k.vid);
 745
 746         for (i = 0; i < RTL8366RB_NUM_PORTS; i++) {
 747                 if (!(vlan4k.member & (1 << i)))
 748                         continue;
 749
 750                 len += snprintf(buf + len, sizeof(smi->buf) - len, "%d%s", i,
 751                                 (vlan4k.untag & (1 << i)) ? "" : "t");
 752         }
 753
 754         len += snprintf(buf + len, sizeof(smi->buf) - len,
 755                         "', members=%04x, untag=%04x, fid=%u",
 756                         vlan4k.member, vlan4k.untag, vlan4k.fid);
 757
 758         val->value.s = buf;
 759         val->len = len;
 760
 761         return 0;
 762 }
 763
 764 static int rtl8366rb_sw_set_port_led(struct switch_dev *dev,
 765                                     const struct switch_attr *attr,
 766                                     struct switch_val *val)
 767 {
 768         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
 769         u32 data;
 770         u32 mask;
 771         u32 reg;
 772
 773         if (val->port_vlan >= RTL8366RB_NUM_PORTS)
 774                 return -EINVAL;
 775
 776         if (val->port_vlan == RTL8366RB_PORT_NUM_CPU) {
 777                 reg = RTL8366RB_LED_BLINKRATE_REG;
 778                 mask = 0xF << 4;
 779                 data = val->value.i << 4;
 780         } else {
 781                 reg = RTL8366RB_LED_CTRL_REG;
 782                 mask = 0xF << (val->port_vlan * 4),
 783                 data = val->value.i << (val->port_vlan * 4);
 784         }
 785
 786         return rtl8366_smi_rmwr(smi, RTL8366RB_LED_BLINKRATE_REG, mask, data);
 787 }
 788
 789 static int rtl8366rb_sw_get_port_led(struct switch_dev *dev,
 790                                     const struct switch_attr *attr,
 791                                     struct switch_val *val)
 792 {
 793         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
 794         u32 data = 0;
 795
 796         if (val->port_vlan >= RTL8366RB_NUM_LEDGROUPS)
 797                 return -EINVAL;
 798
 799         rtl8366_smi_read_reg(smi, RTL8366RB_LED_CTRL_REG, &data);
 800         val->value.i = (data >> (val->port_vlan * 4)) & 0x000F;
 801
 802         return 0;
 803 }
 804
 805 static int rtl8366rb_sw_reset_port_mibs(struct switch_dev *dev,
 806                                        const struct switch_attr *attr,
 807                                        struct switch_val *val)
 808 {
 809         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
 810
 811         if (val->port_vlan >= RTL8366RB_NUM_PORTS)
 812                 return -EINVAL;
 813
 814         return rtl8366_smi_rmwr(smi, RTL8366RB_MIB_CTRL_REG, 0,
 815                                 RTL8366RB_MIB_CTRL_PORT_RESET(val->port_vlan));
 816 }
 817
 818 static int rtl8366rb_sw_get_port_mib(struct switch_dev *dev,
 819                                     const struct switch_attr *attr,
 820                                     struct switch_val *val)
 821 {
 822         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
 823         int i, len = 0;
 824         unsigned long long counter = 0;
 825         char *buf = smi->buf;
 826
 827         if (val->port_vlan >= RTL8366RB_NUM_PORTS)
 828                 return -EINVAL;
 829
 830         len += snprintf(buf + len, sizeof(smi->buf) - len,
 831                         "Port %d MIB counters\n",
 832                         val->port_vlan);
 833
 834         for (i = 0; i < ARRAY_SIZE(rtl8366rb_mib_counters); ++i) {
 835                 len += snprintf(buf + len, sizeof(smi->buf) - len,
 836                                 "%-36s: ", rtl8366rb_mib_counters[i].name);
 837                 if (!rtl8366rb_get_mib_counter(smi, i, val->port_vlan, &counter))
 838                         len += snprintf(buf + len, sizeof(smi->buf) - len,
 839                                         "%llu\n", counter);
 840                 else
 841                         len += snprintf(buf + len, sizeof(smi->buf) - len,
 842                                         "%s\n", "error");
 843         }
 844
 845         val->value.s = buf;
 846         val->len = len;
 847         return 0;
 848 }
 849
 850 static int rtl8366rb_sw_get_vlan_ports(struct switch_dev *dev,
 851                                       struct switch_val *val)
 852 {
 853         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
 854         struct switch_port *port;
 855         struct rtl8366_vlan_4k vlan4k;
 856         int i;
 857
 858         if (val->port_vlan == 0 || val->port_vlan >= RTL8366RB_NUM_VLANS)
 859                 return -EINVAL;
 860
 861         rtl8366rb_get_vlan_4k(smi, val->port_vlan, &vlan4k);
 862
 863         port = &val->value.ports[0];
 864         val->len = 0;
 865         for (i = 0; i < RTL8366RB_NUM_PORTS; i++) {
 866                 if (!(vlan4k.member & BIT(i)))
 867                         continue;
 868
 869                 port->id = i;
 870                 port->flags = (vlan4k.untag & BIT(i)) ?
 871                                         0 : BIT(SWITCH_PORT_FLAG_TAGGED);
 872                 val->len++;
 873                 port++;
 874         }
 875         return 0;
 876 }
 877
 878 static int rtl8366rb_sw_set_vlan_ports(struct switch_dev *dev,
 879                                       struct switch_val *val)
 880 {
 881         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
 882         struct switch_port *port;
 883         u32 member = 0;
 884         u32 untag = 0;
 885         int i;
 886
 887         if (val->port_vlan == 0 || val->port_vlan >= RTL8366RB_NUM_VLANS)
 888                 return -EINVAL;
 889
 890         port = &val->value.ports[0];
 891         for (i = 0; i < val->len; i++, port++) {
 892                 member |= BIT(port->id);
 893
 894                 if (!(port->flags & BIT(SWITCH_PORT_FLAG_TAGGED)))
 895                         untag |= BIT(port->id);
 896         }
 897
 898         return rtl8366_set_vlan(smi, val->port_vlan, member, untag, 0);
 899 }
 900
 901 static int rtl8366rb_sw_get_port_pvid(struct switch_dev *dev, int port, int *val)
 902 {
 903         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
 904         return rtl8366_get_pvid(smi, port, val);
 905 }
 906
 907 static int rtl8366rb_sw_set_port_pvid(struct switch_dev *dev, int port, int val)
 908 {
 909         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
 910         return rtl8366_set_pvid(smi, port, val);
 911 }
 912
 913 static int rtl8366rb_sw_reset_switch(struct switch_dev *dev)
 914 {
 915         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
 916         int err;
 917
 918         err = rtl8366rb_reset_chip(smi);
 919         if (err)
 920                 return err;
 921
 922         err = rtl8366rb_hw_init(smi);
 923         if (err)
 924                 return err;
 925
 926         return rtl8366_reset_vlan(smi);
 927 }
 928
 929 static struct switch_attr rtl8366rb_globals[] = {
 930         {
 931                 .type = SWITCH_TYPE_INT,
 932                 .name = "enable_vlan",
 933                 .description = "Enable VLAN mode",
 934                 .set = rtl8366rb_sw_set_vlan_enable,
 935                 .get = rtl8366rb_sw_get_vlan_enable,
 936                 .max = 1,
 937                 .ofs = 1
 938         }, {
 939                 .type = SWITCH_TYPE_INT,
 940                 .name = "enable_vlan4k",
 941                 .description = "Enable VLAN 4K mode",
 942                 .set = rtl8366rb_sw_set_vlan_enable,
 943                 .get = rtl8366rb_sw_get_vlan_enable,
 944                 .max = 1,
 945                 .ofs = 2
 946         }, {
 947                 .type = SWITCH_TYPE_NOVAL,
 948                 .name = "reset_mibs",
 949                 .description = "Reset all MIB counters",
 950                 .set = rtl8366rb_sw_reset_mibs,
 951         }, {
 952                 .type = SWITCH_TYPE_INT,
 953                 .name = "blinkrate",
 954                 .description = "Get/Set LED blinking rate (0 = 43ms, 1 = 84ms,"
 955                 " 2 = 120ms, 3 = 170ms, 4 = 340ms, 5 = 670ms)",
 956                 .set = rtl8366rb_sw_set_blinkrate,
 957                 .get = rtl8366rb_sw_get_blinkrate,
 958                 .max = 5
 959         },
 960 };
 961
 962 static struct switch_attr rtl8366rb_port[] = {
 963         {
 964                 .type = SWITCH_TYPE_STRING,
 965                 .name = "link",
 966                 .description = "Get port link information",
 967                 .max = 1,
 968                 .set = NULL,
 969                 .get = rtl8366rb_sw_get_port_link,
 970         }, {
 971                 .type = SWITCH_TYPE_NOVAL,
 972                 .name = "reset_mib",
 973                 .description = "Reset single port MIB counters",
 974                 .set = rtl8366rb_sw_reset_port_mibs,
 975         }, {
 976                 .type = SWITCH_TYPE_STRING,
 977                 .name = "mib",
 978                 .description = "Get MIB counters for port",
 979                 .max = 33,
 980                 .set = NULL,
 981                 .get = rtl8366rb_sw_get_port_mib,
 982         }, {
 983                 .type = SWITCH_TYPE_INT,
 984                 .name = "led",
 985                 .description = "Get/Set port group (0 - 3) led mode (0 - 15)",
 986                 .max = 15,
 987                 .set = rtl8366rb_sw_set_port_led,
 988                 .get = rtl8366rb_sw_get_port_led,
 989         },
 990 };
 991
 992 static struct switch_attr rtl8366rb_vlan[] = {
 993         {
 994                 .type = SWITCH_TYPE_STRING,
 995                 .name = "info",
 996                 .description = "Get vlan information",
 997                 .max = 1,
 998                 .set = NULL,
 999                 .get = rtl8366rb_sw_get_vlan_info,
1000         },
1001 };
1002
1003 /* template */
1004 static struct switch_dev rtl8366_switch_dev = {
1005         .name = "RTL8366S",
1006         .cpu_port = RTL8366RB_PORT_NUM_CPU,
1007         .ports = RTL8366RB_NUM_PORTS,
1008         .vlans = RTL8366RB_NUM_VLANS,
1009         .attr_global = {
1010                 .attr = rtl8366rb_globals,
1011                 .n_attr = ARRAY_SIZE(rtl8366rb_globals),
1012         },
1013         .attr_port = {
1014                 .attr = rtl8366rb_port,
1015                 .n_attr = ARRAY_SIZE(rtl8366rb_port),
1016         },
1017         .attr_vlan = {
1018                 .attr = rtl8366rb_vlan,
1019                 .n_attr = ARRAY_SIZE(rtl8366rb_vlan),
1020         },
1021
1022         .get_vlan_ports = rtl8366rb_sw_get_vlan_ports,
1023         .set_vlan_ports = rtl8366rb_sw_set_vlan_ports,
1024         .get_port_pvid = rtl8366rb_sw_get_port_pvid,
1025         .set_port_pvid = rtl8366rb_sw_set_port_pvid,
1026         .reset_switch = rtl8366rb_sw_reset_switch,
1027 };
1028
1029 static int rtl8366rb_switch_init(struct rtl8366rb *rtl)
1030 {
1031         struct switch_dev *dev = &rtl->dev;
1032         int err;
1033
1034         memcpy(dev, &rtl8366_switch_dev, sizeof(struct switch_dev));
1035         dev->priv = rtl;
1036         dev->devname = dev_name(rtl->parent);
1037
1038         err = register_switch(dev, NULL);
1039         if (err)
1040                 dev_err(rtl->parent, "switch registration failed\n");
1041
1042         return err;
1043 }
1044
1045 static void rtl8366rb_switch_cleanup(struct rtl8366rb *rtl)
1046 {
1047         unregister_switch(&rtl->dev);
1048 }
1049
1050 static int rtl8366rb_mii_read(struct mii_bus *bus, int addr, int reg)
1051 {
1052         struct rtl8366_smi *smi = bus->priv;
1053         u32 val = 0;
1054         int err;
1055
1056         err = rtl8366rb_read_phy_reg(smi, addr, 0, reg, &val);
1057         if (err)
1058                 return 0xffff;
1059
1060         return val;
1061 }
1062
1063 static int rtl8366rb_mii_write(struct mii_bus *bus, int addr, int reg, u16 val)
1064 {
1065         struct rtl8366_smi *smi = bus->priv;
1066         u32 t;
1067         int err;
1068
1069         err = rtl8366rb_write_phy_reg(smi, addr, 0, reg, val);
1070         /* flush write */
1071         (void) rtl8366rb_read_phy_reg(smi, addr, 0, reg, &t);
1072
1073         return err;
1074 }
1075
1076 static int rtl8366rb_mii_bus_match(struct mii_bus *bus)
1077 {
1078         return (bus->read == rtl8366rb_mii_read &&
1079                 bus->write == rtl8366rb_mii_write);
1080 }
1081
1082 static int rtl8366rb_setup(struct rtl8366rb *rtl)
1083 {
1084         struct rtl8366_smi *smi = &rtl->smi;
1085         int ret;
1086
1087         ret = rtl8366rb_reset_chip(smi);
1088         if (ret)
1089                 return ret;
1090
1091         ret = rtl8366rb_hw_init(smi);
1092         return ret;
1093 }
1094
1095 static int rtl8366rb_detect(struct rtl8366_smi *smi)
1096 {
1097         u32 chip_id = 0;
1098         u32 chip_ver = 0;
1099         int ret;
1100
1101         ret = rtl8366_smi_read_reg(smi, RTL8366RB_CHIP_ID_REG, &chip_id);
1102         if (ret) {
1103                 dev_err(smi->parent, "unable to read chip id\n");
1104                 return ret;
1105         }
1106
1107         switch (chip_id) {
1108         case RTL8366RB_CHIP_ID_8366:
1109                 break;
1110         default:
1111                 dev_err(smi->parent, "unknown chip id (%04x)\n", chip_id);
1112                 return -ENODEV;
1113         }
1114
1115         ret = rtl8366_smi_read_reg(smi, RTL8366RB_CHIP_VERSION_CTRL_REG,
1116                                    &chip_ver);
1117         if (ret) {
1118                 dev_err(smi->parent, "unable to read chip version\n");
1119                 return ret;
1120         }
1121
1122         dev_info(smi->parent, "RTL%04x ver. %u chip found\n",
1123                  chip_id, chip_ver & RTL8366RB_CHIP_VERSION_MASK);
1124
1125         return 0;
1126 }
1127
1128 static struct rtl8366_smi_ops rtl8366rb_smi_ops = {
1129         .detect         = rtl8366rb_detect,
1130         .mii_read       = rtl8366rb_mii_read,
1131         .mii_write      = rtl8366rb_mii_write,
1132
1133         .get_vlan_mc    = rtl8366rb_get_vlan_mc,
1134         .set_vlan_mc    = rtl8366rb_set_vlan_mc,
1135         .get_vlan_4k    = rtl8366rb_get_vlan_4k,
1136         .set_vlan_4k    = rtl8366rb_set_vlan_4k,
1137         .get_mc_index   = rtl8366rb_get_mc_index,
1138         .set_mc_index   = rtl8366rb_set_mc_index,
1139         .get_mib_counter = rtl8366rb_get_mib_counter,
1140 };
1141
1142 static int __init rtl8366rb_probe(struct platform_device *pdev)
1143 {
1144         static int rtl8366_smi_version_printed;
1145         struct rtl8366rb_platform_data *pdata;
1146         struct rtl8366rb *rtl;
1147         struct rtl8366_smi *smi;
1148         int err;
1149
1150         if (!rtl8366_smi_version_printed++)
1151                 printk(KERN_NOTICE RTL8366RB_DRIVER_DESC
1152                        " version " RTL8366RB_DRIVER_VER"\n");
1153
1154         pdata = pdev->dev.platform_data;
1155         if (!pdata) {
1156                 dev_err(&pdev->dev, "no platform data specified\n");
1157                 err = -EINVAL;
1158                 goto err_out;
1159         }
1160
1161         rtl = kzalloc(sizeof(*rtl), GFP_KERNEL);
1162         if (!rtl) {
1163                 dev_err(&pdev->dev, "no memory for private data\n");
1164                 err = -ENOMEM;
1165                 goto err_out;
1166         }
1167
1168         rtl->parent = &pdev->dev;
1169
1170         smi = &rtl->smi;
1171         smi->parent = &pdev->dev;
1172         smi->gpio_sda = pdata->gpio_sda;
1173         smi->gpio_sck = pdata->gpio_sck;
1174         smi->ops = &rtl8366rb_smi_ops;
1175         smi->cpu_port = RTL8366RB_PORT_NUM_CPU;
1176         smi->num_ports = RTL8366RB_NUM_PORTS;
1177         smi->num_vlan_mc = RTL8366RB_NUM_VLANS;
1178         smi->mib_counters = rtl8366rb_mib_counters;
1179         smi->num_mib_counters = ARRAY_SIZE(rtl8366rb_mib_counters);
1180
1181         err = rtl8366_smi_init(smi);
1182         if (err)
1183                 goto err_free_rtl;
1184
1185         platform_set_drvdata(pdev, rtl);
1186
1187         err = rtl8366rb_setup(rtl);
1188         if (err)
1189                 goto err_clear_drvdata;
1190
1191         err = rtl8366rb_switch_init(rtl);
1192         if (err)
1193                 goto err_clear_drvdata;
1194
1195         return 0;
1196
1197  err_clear_drvdata:
1198         platform_set_drvdata(pdev, NULL);
1199         rtl8366_smi_cleanup(smi);
1200  err_free_rtl:
1201         kfree(rtl);
1202  err_out:
1203         return err;
1204 }
1205
1206 static int rtl8366rb_phy_config_init(struct phy_device *phydev)
1207 {
1208         if (!rtl8366rb_mii_bus_match(phydev->bus))
1209                 return -EINVAL;
1210
1211         return 0;
1212 }
1213
1214 static int rtl8366rb_phy_config_aneg(struct phy_device *phydev)
1215 {
1216         return 0;
1217 }
1218
1219 static struct phy_driver rtl8366rb_phy_driver = {
1220         .phy_id         = 0x001cc960,
1221         .name           = "Realtek RTL8366RB",
1222         .phy_id_mask    = 0x1ffffff0,
1223         .features       = PHY_GBIT_FEATURES,
1224         .config_aneg    = rtl8366rb_phy_config_aneg,
1225         .config_init    = rtl8366rb_phy_config_init,
1226         .read_status    = genphy_read_status,
1227         .driver         = {
1228                 .owner = THIS_MODULE,
1229         },
1230 };
1231
1232 static int __devexit rtl8366rb_remove(struct platform_device *pdev)
1233 {
1234         struct rtl8366rb *rtl = platform_get_drvdata(pdev);
1235
1236         if (rtl) {
1237                 rtl8366rb_switch_cleanup(rtl);
1238                 platform_set_drvdata(pdev, NULL);
1239                 rtl8366_smi_cleanup(&rtl->smi);
1240                 kfree(rtl);
1241         }
1242
1243         return 0;
1244 }
1245
1246 static struct platform_driver rtl8366rb_driver = {
1247         .driver = {
1248                 .name           = RTL8366RB_DRIVER_NAME,
1249                 .owner          = THIS_MODULE,
1250         },
1251         .probe          = rtl8366rb_probe,
1252         .remove         = __devexit_p(rtl8366rb_remove),
1253 };
1254
1255 static int __init rtl8366rb_module_init(void)
1256 {
1257         int ret;
1258         ret = platform_driver_register(&rtl8366rb_driver);
1259         if (ret)
1260                 return ret;
1261
1262         ret = phy_driver_register(&rtl8366rb_phy_driver);
1263         if (ret)
1264                 goto err_platform_unregister;
1265
1266         return 0;
1267
1268  err_platform_unregister:
1269         platform_driver_unregister(&rtl8366rb_driver);
1270         return ret;
1271 }
1272 module_init(rtl8366rb_module_init);
1273
1274 static void __exit rtl8366rb_module_exit(void)
1275 {
1276         phy_driver_unregister(&rtl8366rb_phy_driver);
1277         platform_driver_unregister(&rtl8366rb_driver);
1278 }
1279 module_exit(rtl8366rb_module_exit);
1280
1281 MODULE_DESCRIPTION(RTL8366RB_DRIVER_DESC);
1282 MODULE_VERSION(RTL8366RB_DRIVER_VER);
1283 MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
1284 MODULE_AUTHOR("Antti Seppälä <a.seppala@gmail.com>");
1285 MODULE_LICENSE("GPL v2");
1286 MODULE_ALIAS("platform:" RTL8366RB_DRIVER_NAME);