2 * Platform driver for the Realtek RTL8366RB ethernet switch
4 * Copyright (C) 2009-2010 Gabor Juhos <juhosg@openwrt.org>
5 * Copyright (C) 2010 Antti Seppälä <a.seppala@gmail.com>
6 * Copyright (C) 2010 Roman Yeryomin <roman@advem.lv>
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License version 2 as published
10 * by the Free Software Foundation.
13 #include <linux/kernel.h>
14 #include <linux/module.h>
15 #include <linux/init.h>
17 #include <linux/of_platform.h>
18 #include <linux/delay.h>
19 #include <linux/skbuff.h>
20 #include <linux/rtl8366.h>
22 #include "rtl8366_smi.h"
24 #define RTL8366RB_DRIVER_DESC "Realtek RTL8366RB ethernet switch driver"
25 #define RTL8366RB_DRIVER_VER "0.2.3"
27 #define RTL8366RB_PHY_NO_MAX 4
28 #define RTL8366RB_PHY_PAGE_MAX 7
29 #define RTL8366RB_PHY_ADDR_MAX 31
31 /* Switch Global Configuration register */
32 #define RTL8366RB_SGCR 0x0000
33 #define RTL8366RB_SGCR_EN_BC_STORM_CTRL BIT(0)
34 #define RTL8366RB_SGCR_MAX_LENGTH(_x) (_x << 4)
35 #define RTL8366RB_SGCR_MAX_LENGTH_MASK RTL8366RB_SGCR_MAX_LENGTH(0x3)
36 #define RTL8366RB_SGCR_MAX_LENGTH_1522 RTL8366RB_SGCR_MAX_LENGTH(0x0)
37 #define RTL8366RB_SGCR_MAX_LENGTH_1536 RTL8366RB_SGCR_MAX_LENGTH(0x1)
38 #define RTL8366RB_SGCR_MAX_LENGTH_1552 RTL8366RB_SGCR_MAX_LENGTH(0x2)
39 #define RTL8366RB_SGCR_MAX_LENGTH_9216 RTL8366RB_SGCR_MAX_LENGTH(0x3)
40 #define RTL8366RB_SGCR_EN_VLAN BIT(13)
41 #define RTL8366RB_SGCR_EN_VLAN_4KTB BIT(14)
43 /* Port Enable Control register */
44 #define RTL8366RB_PECR 0x0001
46 /* Switch Security Control registers */
47 #define RTL8366RB_SSCR0 0x0002
48 #define RTL8366RB_SSCR1 0x0003
49 #define RTL8366RB_SSCR2 0x0004
50 #define RTL8366RB_SSCR2_DROP_UNKNOWN_DA BIT(0)
52 #define RTL8366RB_RESET_CTRL_REG 0x0100
53 #define RTL8366RB_CHIP_CTRL_RESET_HW 1
54 #define RTL8366RB_CHIP_CTRL_RESET_SW (1 << 1)
56 #define RTL8366RB_CHIP_VERSION_CTRL_REG 0x050A
57 #define RTL8366RB_CHIP_VERSION_MASK 0xf
58 #define RTL8366RB_CHIP_ID_REG 0x0509
59 #define RTL8366RB_CHIP_ID_8366 0x5937
61 /* PHY registers control */
62 #define RTL8366RB_PHY_ACCESS_CTRL_REG 0x8000
63 #define RTL8366RB_PHY_ACCESS_DATA_REG 0x8002
65 #define RTL8366RB_PHY_CTRL_READ 1
66 #define RTL8366RB_PHY_CTRL_WRITE 0
68 #define RTL8366RB_PHY_REG_MASK 0x1f
69 #define RTL8366RB_PHY_PAGE_OFFSET 5
70 #define RTL8366RB_PHY_PAGE_MASK (0xf << 5)
71 #define RTL8366RB_PHY_NO_OFFSET 9
72 #define RTL8366RB_PHY_NO_MASK (0x1f << 9)
74 #define RTL8366RB_VLAN_INGRESS_CTRL2_REG 0x037f
76 /* LED control registers */
77 #define RTL8366RB_LED_BLINKRATE_REG 0x0430
78 #define RTL8366RB_LED_BLINKRATE_BIT 0
79 #define RTL8366RB_LED_BLINKRATE_MASK 0x0007
81 #define RTL8366RB_LED_CTRL_REG 0x0431
82 #define RTL8366RB_LED_0_1_CTRL_REG 0x0432
83 #define RTL8366RB_LED_2_3_CTRL_REG 0x0433
85 #define RTL8366RB_MIB_COUNT 33
86 #define RTL8366RB_GLOBAL_MIB_COUNT 1
87 #define RTL8366RB_MIB_COUNTER_PORT_OFFSET 0x0050
88 #define RTL8366RB_MIB_COUNTER_BASE 0x1000
89 #define RTL8366RB_MIB_CTRL_REG 0x13F0
90 #define RTL8366RB_MIB_CTRL_USER_MASK 0x0FFC
91 #define RTL8366RB_MIB_CTRL_BUSY_MASK BIT(0)
92 #define RTL8366RB_MIB_CTRL_RESET_MASK BIT(1)
93 #define RTL8366RB_MIB_CTRL_PORT_RESET(_p) BIT(2 + (_p))
94 #define RTL8366RB_MIB_CTRL_GLOBAL_RESET BIT(11)
96 #define RTL8366RB_PORT_VLAN_CTRL_BASE 0x0063
97 #define RTL8366RB_PORT_VLAN_CTRL_REG(_p) \
98 (RTL8366RB_PORT_VLAN_CTRL_BASE + (_p) / 4)
99 #define RTL8366RB_PORT_VLAN_CTRL_MASK 0xf
100 #define RTL8366RB_PORT_VLAN_CTRL_SHIFT(_p) (4 * ((_p) % 4))
103 #define RTL8366RB_VLAN_TABLE_READ_BASE 0x018C
104 #define RTL8366RB_VLAN_TABLE_WRITE_BASE 0x0185
107 #define RTL8366RB_TABLE_ACCESS_CTRL_REG 0x0180
108 #define RTL8366RB_TABLE_VLAN_READ_CTRL 0x0E01
109 #define RTL8366RB_TABLE_VLAN_WRITE_CTRL 0x0F01
111 #define RTL8366RB_VLAN_MC_BASE(_x) (0x0020 + (_x) * 3)
114 #define RTL8366RB_PORT_LINK_STATUS_BASE 0x0014
115 #define RTL8366RB_PORT_STATUS_SPEED_MASK 0x0003
116 #define RTL8366RB_PORT_STATUS_DUPLEX_MASK 0x0004
117 #define RTL8366RB_PORT_STATUS_LINK_MASK 0x0010
118 #define RTL8366RB_PORT_STATUS_TXPAUSE_MASK 0x0020
119 #define RTL8366RB_PORT_STATUS_RXPAUSE_MASK 0x0040
120 #define RTL8366RB_PORT_STATUS_AN_MASK 0x0080
123 #define RTL8366RB_PORT_NUM_CPU 5
124 #define RTL8366RB_NUM_PORTS 6
125 #define RTL8366RB_NUM_VLANS 16
126 #define RTL8366RB_NUM_LEDGROUPS 4
127 #define RTL8366RB_NUM_VIDS 4096
128 #define RTL8366RB_PRIORITYMAX 7
129 #define RTL8366RB_FIDMAX 7
132 #define RTL8366RB_PORT_1 (1 << 0) /* In userspace port 0 */
133 #define RTL8366RB_PORT_2 (1 << 1) /* In userspace port 1 */
134 #define RTL8366RB_PORT_3 (1 << 2) /* In userspace port 2 */
135 #define RTL8366RB_PORT_4 (1 << 3) /* In userspace port 3 */
136 #define RTL8366RB_PORT_5 (1 << 4) /* In userspace port 4 */
138 #define RTL8366RB_PORT_CPU (1 << 5) /* CPU port */
140 #define RTL8366RB_PORT_ALL (RTL8366RB_PORT_1 | \
147 #define RTL8366RB_PORT_ALL_BUT_CPU (RTL8366RB_PORT_1 | \
153 #define RTL8366RB_PORT_ALL_EXTERNAL (RTL8366RB_PORT_1 | \
158 #define RTL8366RB_PORT_ALL_INTERNAL RTL8366RB_PORT_CPU
160 #define RTL8366RB_VLAN_VID_MASK 0xfff
161 #define RTL8366RB_VLAN_PRIORITY_SHIFT 12
162 #define RTL8366RB_VLAN_PRIORITY_MASK 0x7
163 #define RTL8366RB_VLAN_UNTAG_SHIFT 8
164 #define RTL8366RB_VLAN_UNTAG_MASK 0xff
165 #define RTL8366RB_VLAN_MEMBER_MASK 0xff
166 #define RTL8366RB_VLAN_FID_MASK 0x7
169 /* Port ingress bandwidth control */
170 #define RTL8366RB_IB_BASE 0x0200
171 #define RTL8366RB_IB_REG(pnum) (RTL8366RB_IB_BASE + pnum)
172 #define RTL8366RB_IB_BDTH_MASK 0x3fff
173 #define RTL8366RB_IB_PREIFG_OFFSET 14
174 #define RTL8366RB_IB_PREIFG_MASK (1 << RTL8366RB_IB_PREIFG_OFFSET)
176 /* Port egress bandwidth control */
177 #define RTL8366RB_EB_BASE 0x02d1
178 #define RTL8366RB_EB_REG(pnum) (RTL8366RB_EB_BASE + pnum)
179 #define RTL8366RB_EB_BDTH_MASK 0x3fff
180 #define RTL8366RB_EB_PREIFG_REG 0x02f8
181 #define RTL8366RB_EB_PREIFG_OFFSET 9
182 #define RTL8366RB_EB_PREIFG_MASK (1 << RTL8366RB_EB_PREIFG_OFFSET)
184 #define RTL8366RB_BDTH_SW_MAX 1048512
185 #define RTL8366RB_BDTH_UNIT 64
186 #define RTL8366RB_BDTH_REG_DEFAULT 16383
189 #define RTL8366RB_QOS_BIT 15
190 #define RTL8366RB_QOS_MASK (1 << RTL8366RB_QOS_BIT)
191 /* Include/Exclude Preamble and IFG (20 bytes). 0:Exclude, 1:Include. */
192 #define RTL8366RB_QOS_DEFAULT_PREIFG 1
195 static struct rtl8366_mib_counter rtl8366rb_mib_counters[] = {
196 { 0, 0, 4, "IfInOctets" },
197 { 0, 4, 4, "EtherStatsOctets" },
198 { 0, 8, 2, "EtherStatsUnderSizePkts" },
199 { 0, 10, 2, "EtherFragments" },
200 { 0, 12, 2, "EtherStatsPkts64Octets" },
201 { 0, 14, 2, "EtherStatsPkts65to127Octets" },
202 { 0, 16, 2, "EtherStatsPkts128to255Octets" },
203 { 0, 18, 2, "EtherStatsPkts256to511Octets" },
204 { 0, 20, 2, "EtherStatsPkts512to1023Octets" },
205 { 0, 22, 2, "EtherStatsPkts1024to1518Octets" },
206 { 0, 24, 2, "EtherOversizeStats" },
207 { 0, 26, 2, "EtherStatsJabbers" },
208 { 0, 28, 2, "IfInUcastPkts" },
209 { 0, 30, 2, "EtherStatsMulticastPkts" },
210 { 0, 32, 2, "EtherStatsBroadcastPkts" },
211 { 0, 34, 2, "EtherStatsDropEvents" },
212 { 0, 36, 2, "Dot3StatsFCSErrors" },
213 { 0, 38, 2, "Dot3StatsSymbolErrors" },
214 { 0, 40, 2, "Dot3InPauseFrames" },
215 { 0, 42, 2, "Dot3ControlInUnknownOpcodes" },
216 { 0, 44, 4, "IfOutOctets" },
217 { 0, 48, 2, "Dot3StatsSingleCollisionFrames" },
218 { 0, 50, 2, "Dot3StatMultipleCollisionFrames" },
219 { 0, 52, 2, "Dot3sDeferredTransmissions" },
220 { 0, 54, 2, "Dot3StatsLateCollisions" },
221 { 0, 56, 2, "EtherStatsCollisions" },
222 { 0, 58, 2, "Dot3StatsExcessiveCollisions" },
223 { 0, 60, 2, "Dot3OutPauseFrames" },
224 { 0, 62, 2, "Dot1dBasePortDelayExceededDiscards" },
225 { 0, 64, 2, "Dot1dTpPortInDiscards" },
226 { 0, 66, 2, "IfOutUcastPkts" },
227 { 0, 68, 2, "IfOutMulticastPkts" },
228 { 0, 70, 2, "IfOutBroadcastPkts" },
231 #define REG_WR(_smi, _reg, _val) \
233 err = rtl8366_smi_write_reg(_smi, _reg, _val); \
238 #define REG_RMW(_smi, _reg, _mask, _val) \
240 err = rtl8366_smi_rmwr(_smi, _reg, _mask, _val); \
245 static int rtl8366rb_reset_chip(struct rtl8366_smi *smi)
250 rtl8366_smi_write_reg_noack(smi, RTL8366RB_RESET_CTRL_REG,
251 RTL8366RB_CHIP_CTRL_RESET_HW);
254 if (rtl8366_smi_read_reg(smi, RTL8366RB_RESET_CTRL_REG, &data))
257 if (!(data & RTL8366RB_CHIP_CTRL_RESET_HW))
262 printk("Timeout waiting for the switch to reset\n");
269 static int rtl8366rb_setup(struct rtl8366_smi *smi)
273 /* set maximum packet length to 1536 bytes */
274 REG_RMW(smi, RTL8366RB_SGCR, RTL8366RB_SGCR_MAX_LENGTH_MASK,
275 RTL8366RB_SGCR_MAX_LENGTH_1536);
277 /* enable learning for all ports */
278 REG_WR(smi, RTL8366RB_SSCR0, 0);
280 /* enable auto ageing for all ports */
281 REG_WR(smi, RTL8366RB_SSCR1, 0);
284 * discard VLAN tagged packets if the port is not a member of
285 * the VLAN with which the packets is associated.
287 REG_WR(smi, RTL8366RB_VLAN_INGRESS_CTRL2_REG, RTL8366RB_PORT_ALL);
289 /* don't drop packets whose DA has not been learned */
290 REG_RMW(smi, RTL8366RB_SSCR2, RTL8366RB_SSCR2_DROP_UNKNOWN_DA, 0);
295 static int rtl8366rb_read_phy_reg(struct rtl8366_smi *smi,
296 u32 phy_no, u32 page, u32 addr, u32 *data)
301 if (phy_no > RTL8366RB_PHY_NO_MAX)
304 if (page > RTL8366RB_PHY_PAGE_MAX)
307 if (addr > RTL8366RB_PHY_ADDR_MAX)
310 ret = rtl8366_smi_write_reg(smi, RTL8366RB_PHY_ACCESS_CTRL_REG,
311 RTL8366RB_PHY_CTRL_READ);
315 reg = 0x8000 | (1 << (phy_no + RTL8366RB_PHY_NO_OFFSET)) |
316 ((page << RTL8366RB_PHY_PAGE_OFFSET) & RTL8366RB_PHY_PAGE_MASK) |
317 (addr & RTL8366RB_PHY_REG_MASK);
319 ret = rtl8366_smi_write_reg(smi, reg, 0);
323 ret = rtl8366_smi_read_reg(smi, RTL8366RB_PHY_ACCESS_DATA_REG, data);
330 static int rtl8366rb_write_phy_reg(struct rtl8366_smi *smi,
331 u32 phy_no, u32 page, u32 addr, u32 data)
336 if (phy_no > RTL8366RB_PHY_NO_MAX)
339 if (page > RTL8366RB_PHY_PAGE_MAX)
342 if (addr > RTL8366RB_PHY_ADDR_MAX)
345 ret = rtl8366_smi_write_reg(smi, RTL8366RB_PHY_ACCESS_CTRL_REG,
346 RTL8366RB_PHY_CTRL_WRITE);
350 reg = 0x8000 | (1 << (phy_no + RTL8366RB_PHY_NO_OFFSET)) |
351 ((page << RTL8366RB_PHY_PAGE_OFFSET) & RTL8366RB_PHY_PAGE_MASK) |
352 (addr & RTL8366RB_PHY_REG_MASK);
354 ret = rtl8366_smi_write_reg(smi, reg, data);
361 static int rtl8366rb_get_mib_counter(struct rtl8366_smi *smi, int counter,
362 int port, unsigned long long *val)
369 if (port > RTL8366RB_NUM_PORTS || counter >= RTL8366RB_MIB_COUNT)
372 addr = RTL8366RB_MIB_COUNTER_BASE +
373 RTL8366RB_MIB_COUNTER_PORT_OFFSET * (port) +
374 rtl8366rb_mib_counters[counter].offset;
377 * Writing access counter address first
378 * then ASIC will prepare 64bits counter wait for being retrived
380 data = 0; /* writing data will be discard by ASIC */
381 err = rtl8366_smi_write_reg(smi, addr, data);
385 /* read MIB control register */
386 err = rtl8366_smi_read_reg(smi, RTL8366RB_MIB_CTRL_REG, &data);
390 if (data & RTL8366RB_MIB_CTRL_BUSY_MASK)
393 if (data & RTL8366RB_MIB_CTRL_RESET_MASK)
397 for (i = rtl8366rb_mib_counters[counter].length; i > 0; i--) {
398 err = rtl8366_smi_read_reg(smi, addr + (i - 1), &data);
402 mibvalue = (mibvalue << 16) | (data & 0xFFFF);
409 static int rtl8366rb_get_vlan_4k(struct rtl8366_smi *smi, u32 vid,
410 struct rtl8366_vlan_4k *vlan4k)
416 memset(vlan4k, '\0', sizeof(struct rtl8366_vlan_4k));
418 if (vid >= RTL8366RB_NUM_VIDS)
422 err = rtl8366_smi_write_reg(smi, RTL8366RB_VLAN_TABLE_WRITE_BASE,
423 vid & RTL8366RB_VLAN_VID_MASK);
427 /* write table access control word */
428 err = rtl8366_smi_write_reg(smi, RTL8366RB_TABLE_ACCESS_CTRL_REG,
429 RTL8366RB_TABLE_VLAN_READ_CTRL);
433 for (i = 0; i < 3; i++) {
434 err = rtl8366_smi_read_reg(smi,
435 RTL8366RB_VLAN_TABLE_READ_BASE + i,
442 vlan4k->untag = (data[1] >> RTL8366RB_VLAN_UNTAG_SHIFT) &
443 RTL8366RB_VLAN_UNTAG_MASK;
444 vlan4k->member = data[1] & RTL8366RB_VLAN_MEMBER_MASK;
445 vlan4k->fid = data[2] & RTL8366RB_VLAN_FID_MASK;
450 static int rtl8366rb_set_vlan_4k(struct rtl8366_smi *smi,
451 const struct rtl8366_vlan_4k *vlan4k)
457 if (vlan4k->vid >= RTL8366RB_NUM_VIDS ||
458 vlan4k->member > RTL8366RB_VLAN_MEMBER_MASK ||
459 vlan4k->untag > RTL8366RB_VLAN_UNTAG_MASK ||
460 vlan4k->fid > RTL8366RB_FIDMAX)
463 data[0] = vlan4k->vid & RTL8366RB_VLAN_VID_MASK;
464 data[1] = (vlan4k->member & RTL8366RB_VLAN_MEMBER_MASK) |
465 ((vlan4k->untag & RTL8366RB_VLAN_UNTAG_MASK) <<
466 RTL8366RB_VLAN_UNTAG_SHIFT);
467 data[2] = vlan4k->fid & RTL8366RB_VLAN_FID_MASK;
469 for (i = 0; i < 3; i++) {
470 err = rtl8366_smi_write_reg(smi,
471 RTL8366RB_VLAN_TABLE_WRITE_BASE + i,
477 /* write table access control word */
478 err = rtl8366_smi_write_reg(smi, RTL8366RB_TABLE_ACCESS_CTRL_REG,
479 RTL8366RB_TABLE_VLAN_WRITE_CTRL);
484 static int rtl8366rb_get_vlan_mc(struct rtl8366_smi *smi, u32 index,
485 struct rtl8366_vlan_mc *vlanmc)
491 memset(vlanmc, '\0', sizeof(struct rtl8366_vlan_mc));
493 if (index >= RTL8366RB_NUM_VLANS)
496 for (i = 0; i < 3; i++) {
497 err = rtl8366_smi_read_reg(smi,
498 RTL8366RB_VLAN_MC_BASE(index) + i,
504 vlanmc->vid = data[0] & RTL8366RB_VLAN_VID_MASK;
505 vlanmc->priority = (data[0] >> RTL8366RB_VLAN_PRIORITY_SHIFT) &
506 RTL8366RB_VLAN_PRIORITY_MASK;
507 vlanmc->untag = (data[1] >> RTL8366RB_VLAN_UNTAG_SHIFT) &
508 RTL8366RB_VLAN_UNTAG_MASK;
509 vlanmc->member = data[1] & RTL8366RB_VLAN_MEMBER_MASK;
510 vlanmc->fid = data[2] & RTL8366RB_VLAN_FID_MASK;
515 static int rtl8366rb_set_vlan_mc(struct rtl8366_smi *smi, u32 index,
516 const struct rtl8366_vlan_mc *vlanmc)
522 if (index >= RTL8366RB_NUM_VLANS ||
523 vlanmc->vid >= RTL8366RB_NUM_VIDS ||
524 vlanmc->priority > RTL8366RB_PRIORITYMAX ||
525 vlanmc->member > RTL8366RB_VLAN_MEMBER_MASK ||
526 vlanmc->untag > RTL8366RB_VLAN_UNTAG_MASK ||
527 vlanmc->fid > RTL8366RB_FIDMAX)
530 data[0] = (vlanmc->vid & RTL8366RB_VLAN_VID_MASK) |
531 ((vlanmc->priority & RTL8366RB_VLAN_PRIORITY_MASK) <<
532 RTL8366RB_VLAN_PRIORITY_SHIFT);
533 data[1] = (vlanmc->member & RTL8366RB_VLAN_MEMBER_MASK) |
534 ((vlanmc->untag & RTL8366RB_VLAN_UNTAG_MASK) <<
535 RTL8366RB_VLAN_UNTAG_SHIFT);
536 data[2] = vlanmc->fid & RTL8366RB_VLAN_FID_MASK;
538 for (i = 0; i < 3; i++) {
539 err = rtl8366_smi_write_reg(smi,
540 RTL8366RB_VLAN_MC_BASE(index) + i,
549 static int rtl8366rb_get_mc_index(struct rtl8366_smi *smi, int port, int *val)
554 if (port >= RTL8366RB_NUM_PORTS)
557 err = rtl8366_smi_read_reg(smi, RTL8366RB_PORT_VLAN_CTRL_REG(port),
562 *val = (data >> RTL8366RB_PORT_VLAN_CTRL_SHIFT(port)) &
563 RTL8366RB_PORT_VLAN_CTRL_MASK;
569 static int rtl8366rb_set_mc_index(struct rtl8366_smi *smi, int port, int index)
571 if (port >= RTL8366RB_NUM_PORTS || index >= RTL8366RB_NUM_VLANS)
574 return rtl8366_smi_rmwr(smi, RTL8366RB_PORT_VLAN_CTRL_REG(port),
575 RTL8366RB_PORT_VLAN_CTRL_MASK <<
576 RTL8366RB_PORT_VLAN_CTRL_SHIFT(port),
577 (index & RTL8366RB_PORT_VLAN_CTRL_MASK) <<
578 RTL8366RB_PORT_VLAN_CTRL_SHIFT(port));
581 static int rtl8366rb_is_vlan_valid(struct rtl8366_smi *smi, unsigned vlan)
583 unsigned max = RTL8366RB_NUM_VLANS;
585 if (smi->vlan4k_enabled)
586 max = RTL8366RB_NUM_VIDS - 1;
588 if (vlan == 0 || vlan >= max)
594 static int rtl8366rb_enable_vlan(struct rtl8366_smi *smi, int enable)
596 return rtl8366_smi_rmwr(smi, RTL8366RB_SGCR, RTL8366RB_SGCR_EN_VLAN,
597 (enable) ? RTL8366RB_SGCR_EN_VLAN : 0);
600 static int rtl8366rb_enable_vlan4k(struct rtl8366_smi *smi, int enable)
602 return rtl8366_smi_rmwr(smi, RTL8366RB_SGCR,
603 RTL8366RB_SGCR_EN_VLAN_4KTB,
604 (enable) ? RTL8366RB_SGCR_EN_VLAN_4KTB : 0);
607 static int rtl8366rb_enable_port(struct rtl8366_smi *smi, int port, int enable)
609 return rtl8366_smi_rmwr(smi, RTL8366RB_PECR, (1 << port),
610 (enable) ? 0 : (1 << port));
613 static int rtl8366rb_sw_reset_mibs(struct switch_dev *dev,
614 const struct switch_attr *attr,
615 struct switch_val *val)
617 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
619 return rtl8366_smi_rmwr(smi, RTL8366RB_MIB_CTRL_REG, 0,
620 RTL8366RB_MIB_CTRL_GLOBAL_RESET);
623 static int rtl8366rb_sw_get_blinkrate(struct switch_dev *dev,
624 const struct switch_attr *attr,
625 struct switch_val *val)
627 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
630 rtl8366_smi_read_reg(smi, RTL8366RB_LED_BLINKRATE_REG, &data);
632 val->value.i = (data & (RTL8366RB_LED_BLINKRATE_MASK));
637 static int rtl8366rb_sw_set_blinkrate(struct switch_dev *dev,
638 const struct switch_attr *attr,
639 struct switch_val *val)
641 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
643 if (val->value.i >= 6)
646 return rtl8366_smi_rmwr(smi, RTL8366RB_LED_BLINKRATE_REG,
647 RTL8366RB_LED_BLINKRATE_MASK,
651 static int rtl8366rb_sw_get_learning_enable(struct switch_dev *dev,
652 const struct switch_attr *attr,
653 struct switch_val *val)
655 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
658 rtl8366_smi_read_reg(smi, RTL8366RB_SSCR0, &data);
659 val->value.i = !data;
665 static int rtl8366rb_sw_set_learning_enable(struct switch_dev *dev,
666 const struct switch_attr *attr,
667 struct switch_val *val)
669 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
674 portmask = RTL8366RB_PORT_ALL;
676 /* set learning for all ports */
677 REG_WR(smi, RTL8366RB_SSCR0, portmask);
679 /* set auto ageing for all ports */
680 REG_WR(smi, RTL8366RB_SSCR1, portmask);
685 static int rtl8366rb_sw_get_port_link(struct switch_dev *dev,
687 struct switch_port_link *link)
689 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
693 if (port >= RTL8366RB_NUM_PORTS)
696 rtl8366_smi_read_reg(smi, RTL8366RB_PORT_LINK_STATUS_BASE + (port / 2),
702 link->link = !!(data & RTL8366RB_PORT_STATUS_LINK_MASK);
706 link->duplex = !!(data & RTL8366RB_PORT_STATUS_DUPLEX_MASK);
707 link->rx_flow = !!(data & RTL8366RB_PORT_STATUS_RXPAUSE_MASK);
708 link->tx_flow = !!(data & RTL8366RB_PORT_STATUS_TXPAUSE_MASK);
709 link->aneg = !!(data & RTL8366RB_PORT_STATUS_AN_MASK);
711 speed = (data & RTL8366RB_PORT_STATUS_SPEED_MASK);
714 link->speed = SWITCH_PORT_SPEED_10;
717 link->speed = SWITCH_PORT_SPEED_100;
720 link->speed = SWITCH_PORT_SPEED_1000;
723 link->speed = SWITCH_PORT_SPEED_UNKNOWN;
730 static int rtl8366rb_sw_set_port_led(struct switch_dev *dev,
731 const struct switch_attr *attr,
732 struct switch_val *val)
734 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
739 if (val->port_vlan >= RTL8366RB_NUM_PORTS)
742 if (val->port_vlan == RTL8366RB_PORT_NUM_CPU) {
743 reg = RTL8366RB_LED_BLINKRATE_REG;
745 data = val->value.i << 4;
747 reg = RTL8366RB_LED_CTRL_REG;
748 mask = 0xF << (val->port_vlan * 4),
749 data = val->value.i << (val->port_vlan * 4);
752 return rtl8366_smi_rmwr(smi, reg, mask, data);
755 static int rtl8366rb_sw_get_port_led(struct switch_dev *dev,
756 const struct switch_attr *attr,
757 struct switch_val *val)
759 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
762 if (val->port_vlan >= RTL8366RB_NUM_LEDGROUPS)
765 rtl8366_smi_read_reg(smi, RTL8366RB_LED_CTRL_REG, &data);
766 val->value.i = (data >> (val->port_vlan * 4)) & 0x000F;
771 static int rtl8366rb_sw_set_port_disable(struct switch_dev *dev,
772 const struct switch_attr *attr,
773 struct switch_val *val)
775 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
778 if (val->port_vlan >= RTL8366RB_NUM_PORTS)
781 mask = 1 << val->port_vlan ;
787 return rtl8366_smi_rmwr(smi, RTL8366RB_PECR, mask, data);
790 static int rtl8366rb_sw_get_port_disable(struct switch_dev *dev,
791 const struct switch_attr *attr,
792 struct switch_val *val)
794 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
797 if (val->port_vlan >= RTL8366RB_NUM_PORTS)
800 rtl8366_smi_read_reg(smi, RTL8366RB_PECR, &data);
801 if (data & (1 << val->port_vlan))
809 static int rtl8366rb_sw_set_port_rate_in(struct switch_dev *dev,
810 const struct switch_attr *attr,
811 struct switch_val *val)
813 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
815 if (val->port_vlan >= RTL8366RB_NUM_PORTS)
818 if (val->value.i > 0 && val->value.i < RTL8366RB_BDTH_SW_MAX)
819 val->value.i = (val->value.i - 1) / RTL8366RB_BDTH_UNIT;
821 val->value.i = RTL8366RB_BDTH_REG_DEFAULT;
823 return rtl8366_smi_rmwr(smi, RTL8366RB_IB_REG(val->port_vlan),
824 RTL8366RB_IB_BDTH_MASK | RTL8366RB_IB_PREIFG_MASK,
826 (RTL8366RB_QOS_DEFAULT_PREIFG << RTL8366RB_IB_PREIFG_OFFSET));
830 static int rtl8366rb_sw_get_port_rate_in(struct switch_dev *dev,
831 const struct switch_attr *attr,
832 struct switch_val *val)
834 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
837 if (val->port_vlan >= RTL8366RB_NUM_PORTS)
840 rtl8366_smi_read_reg(smi, RTL8366RB_IB_REG(val->port_vlan), &data);
841 data &= RTL8366RB_IB_BDTH_MASK;
842 if (data < RTL8366RB_IB_BDTH_MASK)
845 val->value.i = (int)data * RTL8366RB_BDTH_UNIT;
850 static int rtl8366rb_sw_set_port_rate_out(struct switch_dev *dev,
851 const struct switch_attr *attr,
852 struct switch_val *val)
854 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
856 if (val->port_vlan >= RTL8366RB_NUM_PORTS)
859 rtl8366_smi_rmwr(smi, RTL8366RB_EB_PREIFG_REG,
860 RTL8366RB_EB_PREIFG_MASK,
861 (RTL8366RB_QOS_DEFAULT_PREIFG << RTL8366RB_EB_PREIFG_OFFSET));
863 if (val->value.i > 0 && val->value.i < RTL8366RB_BDTH_SW_MAX)
864 val->value.i = (val->value.i - 1) / RTL8366RB_BDTH_UNIT;
866 val->value.i = RTL8366RB_BDTH_REG_DEFAULT;
868 return rtl8366_smi_rmwr(smi, RTL8366RB_EB_REG(val->port_vlan),
869 RTL8366RB_EB_BDTH_MASK, val->value.i );
873 static int rtl8366rb_sw_get_port_rate_out(struct switch_dev *dev,
874 const struct switch_attr *attr,
875 struct switch_val *val)
877 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
880 if (val->port_vlan >= RTL8366RB_NUM_PORTS)
883 rtl8366_smi_read_reg(smi, RTL8366RB_EB_REG(val->port_vlan), &data);
884 data &= RTL8366RB_EB_BDTH_MASK;
885 if (data < RTL8366RB_EB_BDTH_MASK)
888 val->value.i = (int)data * RTL8366RB_BDTH_UNIT;
893 static int rtl8366rb_sw_set_qos_enable(struct switch_dev *dev,
894 const struct switch_attr *attr,
895 struct switch_val *val)
897 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
901 data = RTL8366RB_QOS_MASK;
905 return rtl8366_smi_rmwr(smi, RTL8366RB_SGCR, RTL8366RB_QOS_MASK, data);
908 static int rtl8366rb_sw_get_qos_enable(struct switch_dev *dev,
909 const struct switch_attr *attr,
910 struct switch_val *val)
912 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
915 rtl8366_smi_read_reg(smi, RTL8366RB_SGCR, &data);
916 if (data & RTL8366RB_QOS_MASK)
924 static int rtl8366rb_sw_reset_port_mibs(struct switch_dev *dev,
925 const struct switch_attr *attr,
926 struct switch_val *val)
928 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
930 if (val->port_vlan >= RTL8366RB_NUM_PORTS)
933 return rtl8366_smi_rmwr(smi, RTL8366RB_MIB_CTRL_REG, 0,
934 RTL8366RB_MIB_CTRL_PORT_RESET(val->port_vlan));
937 static struct switch_attr rtl8366rb_globals[] = {
939 .type = SWITCH_TYPE_INT,
940 .name = "enable_learning",
941 .description = "Enable learning, enable aging",
942 .set = rtl8366rb_sw_set_learning_enable,
943 .get = rtl8366rb_sw_get_learning_enable,
946 .type = SWITCH_TYPE_INT,
947 .name = "enable_vlan",
948 .description = "Enable VLAN mode",
949 .set = rtl8366_sw_set_vlan_enable,
950 .get = rtl8366_sw_get_vlan_enable,
954 .type = SWITCH_TYPE_INT,
955 .name = "enable_vlan4k",
956 .description = "Enable VLAN 4K mode",
957 .set = rtl8366_sw_set_vlan_enable,
958 .get = rtl8366_sw_get_vlan_enable,
962 .type = SWITCH_TYPE_NOVAL,
963 .name = "reset_mibs",
964 .description = "Reset all MIB counters",
965 .set = rtl8366rb_sw_reset_mibs,
967 .type = SWITCH_TYPE_INT,
969 .description = "Get/Set LED blinking rate (0 = 43ms, 1 = 84ms,"
970 " 2 = 120ms, 3 = 170ms, 4 = 340ms, 5 = 670ms)",
971 .set = rtl8366rb_sw_set_blinkrate,
972 .get = rtl8366rb_sw_get_blinkrate,
975 .type = SWITCH_TYPE_INT,
976 .name = "enable_qos",
977 .description = "Enable QOS",
978 .set = rtl8366rb_sw_set_qos_enable,
979 .get = rtl8366rb_sw_get_qos_enable,
984 static struct switch_attr rtl8366rb_port[] = {
986 .type = SWITCH_TYPE_NOVAL,
988 .description = "Reset single port MIB counters",
989 .set = rtl8366rb_sw_reset_port_mibs,
991 .type = SWITCH_TYPE_STRING,
993 .description = "Get MIB counters for port",
996 .get = rtl8366_sw_get_port_mib,
998 .type = SWITCH_TYPE_INT,
1000 .description = "Get/Set port group (0 - 3) led mode (0 - 15)",
1002 .set = rtl8366rb_sw_set_port_led,
1003 .get = rtl8366rb_sw_get_port_led,
1005 .type = SWITCH_TYPE_INT,
1007 .description = "Get/Set port state (enabled or disabled)",
1009 .set = rtl8366rb_sw_set_port_disable,
1010 .get = rtl8366rb_sw_get_port_disable,
1012 .type = SWITCH_TYPE_INT,
1014 .description = "Get/Set port ingress (incoming) bandwidth limit in kbps",
1015 .max = RTL8366RB_BDTH_SW_MAX,
1016 .set = rtl8366rb_sw_set_port_rate_in,
1017 .get = rtl8366rb_sw_get_port_rate_in,
1019 .type = SWITCH_TYPE_INT,
1021 .description = "Get/Set port egress (outgoing) bandwidth limit in kbps",
1022 .max = RTL8366RB_BDTH_SW_MAX,
1023 .set = rtl8366rb_sw_set_port_rate_out,
1024 .get = rtl8366rb_sw_get_port_rate_out,
1028 static struct switch_attr rtl8366rb_vlan[] = {
1030 .type = SWITCH_TYPE_STRING,
1032 .description = "Get vlan information",
1035 .get = rtl8366_sw_get_vlan_info,
1037 .type = SWITCH_TYPE_INT,
1039 .description = "Get/Set vlan FID",
1040 .max = RTL8366RB_FIDMAX,
1041 .set = rtl8366_sw_set_vlan_fid,
1042 .get = rtl8366_sw_get_vlan_fid,
1046 static const struct switch_dev_ops rtl8366_ops = {
1048 .attr = rtl8366rb_globals,
1049 .n_attr = ARRAY_SIZE(rtl8366rb_globals),
1052 .attr = rtl8366rb_port,
1053 .n_attr = ARRAY_SIZE(rtl8366rb_port),
1056 .attr = rtl8366rb_vlan,
1057 .n_attr = ARRAY_SIZE(rtl8366rb_vlan),
1060 .get_vlan_ports = rtl8366_sw_get_vlan_ports,
1061 .set_vlan_ports = rtl8366_sw_set_vlan_ports,
1062 .get_port_pvid = rtl8366_sw_get_port_pvid,
1063 .set_port_pvid = rtl8366_sw_set_port_pvid,
1064 .reset_switch = rtl8366_sw_reset_switch,
1065 .get_port_link = rtl8366rb_sw_get_port_link,
1068 static int rtl8366rb_switch_init(struct rtl8366_smi *smi)
1070 struct switch_dev *dev = &smi->sw_dev;
1073 dev->name = "RTL8366RB";
1074 dev->cpu_port = RTL8366RB_PORT_NUM_CPU;
1075 dev->ports = RTL8366RB_NUM_PORTS;
1076 dev->vlans = RTL8366RB_NUM_VIDS;
1077 dev->ops = &rtl8366_ops;
1078 dev->alias = dev_name(smi->parent);
1080 err = register_switch(dev, NULL);
1082 dev_err(smi->parent, "switch registration failed\n");
1087 static void rtl8366rb_switch_cleanup(struct rtl8366_smi *smi)
1089 unregister_switch(&smi->sw_dev);
1092 static int rtl8366rb_mii_read(struct mii_bus *bus, int addr, int reg)
1094 struct rtl8366_smi *smi = bus->priv;
1098 err = rtl8366rb_read_phy_reg(smi, addr, 0, reg, &val);
1105 static int rtl8366rb_mii_write(struct mii_bus *bus, int addr, int reg, u16 val)
1107 struct rtl8366_smi *smi = bus->priv;
1111 err = rtl8366rb_write_phy_reg(smi, addr, 0, reg, val);
1113 (void) rtl8366rb_read_phy_reg(smi, addr, 0, reg, &t);
1118 static int rtl8366rb_detect(struct rtl8366_smi *smi)
1124 ret = rtl8366_smi_read_reg(smi, RTL8366RB_CHIP_ID_REG, &chip_id);
1126 dev_err(smi->parent, "unable to read chip id\n");
1131 case RTL8366RB_CHIP_ID_8366:
1134 dev_err(smi->parent, "unknown chip id (%04x)\n", chip_id);
1138 ret = rtl8366_smi_read_reg(smi, RTL8366RB_CHIP_VERSION_CTRL_REG,
1141 dev_err(smi->parent, "unable to read chip version\n");
1145 dev_info(smi->parent, "RTL%04x ver. %u chip found\n",
1146 chip_id, chip_ver & RTL8366RB_CHIP_VERSION_MASK);
1151 static struct rtl8366_smi_ops rtl8366rb_smi_ops = {
1152 .detect = rtl8366rb_detect,
1153 .reset_chip = rtl8366rb_reset_chip,
1154 .setup = rtl8366rb_setup,
1156 .mii_read = rtl8366rb_mii_read,
1157 .mii_write = rtl8366rb_mii_write,
1159 .get_vlan_mc = rtl8366rb_get_vlan_mc,
1160 .set_vlan_mc = rtl8366rb_set_vlan_mc,
1161 .get_vlan_4k = rtl8366rb_get_vlan_4k,
1162 .set_vlan_4k = rtl8366rb_set_vlan_4k,
1163 .get_mc_index = rtl8366rb_get_mc_index,
1164 .set_mc_index = rtl8366rb_set_mc_index,
1165 .get_mib_counter = rtl8366rb_get_mib_counter,
1166 .is_vlan_valid = rtl8366rb_is_vlan_valid,
1167 .enable_vlan = rtl8366rb_enable_vlan,
1168 .enable_vlan4k = rtl8366rb_enable_vlan4k,
1169 .enable_port = rtl8366rb_enable_port,
1172 static int __devinit rtl8366rb_probe(struct platform_device *pdev)
1174 static int rtl8366_smi_version_printed;
1175 struct rtl8366_platform_data *pdata;
1176 struct rtl8366_smi *smi;
1179 if (!rtl8366_smi_version_printed++)
1180 printk(KERN_NOTICE RTL8366RB_DRIVER_DESC
1181 " version " RTL8366RB_DRIVER_VER"\n");
1183 smi = rtl8366_smi_probe(pdev);
1187 smi->clk_delay = 10;
1188 smi->cmd_read = 0xa9;
1189 smi->cmd_write = 0xa8;
1190 smi->ops = &rtl8366rb_smi_ops;
1191 smi->cpu_port = RTL8366RB_PORT_NUM_CPU;
1192 smi->num_ports = RTL8366RB_NUM_PORTS;
1193 smi->num_vlan_mc = RTL8366RB_NUM_VLANS;
1194 smi->mib_counters = rtl8366rb_mib_counters;
1195 smi->num_mib_counters = ARRAY_SIZE(rtl8366rb_mib_counters);
1197 err = rtl8366_smi_init(smi);
1201 platform_set_drvdata(pdev, smi);
1203 err = rtl8366rb_switch_init(smi);
1205 goto err_clear_drvdata;
1210 platform_set_drvdata(pdev, NULL);
1211 rtl8366_smi_cleanup(smi);
1218 static int __devexit rtl8366rb_remove(struct platform_device *pdev)
1220 struct rtl8366_smi *smi = platform_get_drvdata(pdev);
1223 rtl8366rb_switch_cleanup(smi);
1224 platform_set_drvdata(pdev, NULL);
1225 rtl8366_smi_cleanup(smi);
1233 static const struct of_device_id rtl8366rb_match[] = {
1234 { .compatible = "rtl8366rb" },
1237 MODULE_DEVICE_TABLE(of, rtl8366rb_match);
1240 static struct platform_driver rtl8366rb_driver = {
1242 .name = RTL8366RB_DRIVER_NAME,
1243 .owner = THIS_MODULE,
1244 .of_match_table = of_match_ptr(rtl8366rb_match),
1246 .probe = rtl8366rb_probe,
1247 .remove = __devexit_p(rtl8366rb_remove),
1250 static int __init rtl8366rb_module_init(void)
1252 return platform_driver_register(&rtl8366rb_driver);
1254 module_init(rtl8366rb_module_init);
1256 static void __exit rtl8366rb_module_exit(void)
1258 platform_driver_unregister(&rtl8366rb_driver);
1260 module_exit(rtl8366rb_module_exit);
1262 MODULE_DESCRIPTION(RTL8366RB_DRIVER_DESC);
1263 MODULE_VERSION(RTL8366RB_DRIVER_VER);
1264 MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
1265 MODULE_AUTHOR("Antti Seppälä <a.seppala@gmail.com>");
1266 MODULE_AUTHOR("Roman Yeryomin <roman@advem.lv>");
1267 MODULE_LICENSE("GPL v2");
1268 MODULE_ALIAS("platform:" RTL8366RB_DRIVER_NAME);