2 * Platform driver for the Realtek RTL8366S ethernet switch
4 * Copyright (C) 2009-2010 Gabor Juhos <juhosg@openwrt.org>
5 * Copyright (C) 2010 Antti Seppälä <a.seppala@gmail.com>
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License version 2 as published
9 * by the Free Software Foundation.
12 #include <linux/kernel.h>
13 #include <linux/module.h>
14 #include <linux/init.h>
15 #include <linux/platform_device.h>
16 #include <linux/delay.h>
17 #include <linux/skbuff.h>
18 #include <linux/rtl8366rb.h>
20 #include "rtl8366_smi.h"
22 #define RTL8366RB_DRIVER_DESC "Realtek RTL8366RB ethernet switch driver"
23 #define RTL8366RB_DRIVER_VER "0.2.2"
25 #define RTL8366RB_PHY_NO_MAX 4
26 #define RTL8366RB_PHY_PAGE_MAX 7
27 #define RTL8366RB_PHY_ADDR_MAX 31
29 /* Switch Global Configuration register */
30 #define RTL8366RB_SGCR 0x0000
31 #define RTL8366RB_SGCR_EN_BC_STORM_CTRL BIT(0)
32 #define RTL8366RB_SGCR_MAX_LENGTH(_x) (_x << 4)
33 #define RTL8366RB_SGCR_MAX_LENGTH_MASK RTL8366RB_SGCR_MAX_LENGTH(0x3)
34 #define RTL8366RB_SGCR_MAX_LENGTH_1522 RTL8366RB_SGCR_MAX_LENGTH(0x0)
35 #define RTL8366RB_SGCR_MAX_LENGTH_1536 RTL8366RB_SGCR_MAX_LENGTH(0x1)
36 #define RTL8366RB_SGCR_MAX_LENGTH_1552 RTL8366RB_SGCR_MAX_LENGTH(0x2)
37 #define RTL8366RB_SGCR_MAX_LENGTH_9216 RTL8366RB_SGCR_MAX_LENGTH(0x3)
38 #define RTL8366RB_SGCR_EN_VLAN BIT(13)
39 #define RTL8366RB_SGCR_EN_VLAN_4KTB BIT(14)
41 /* Port Enable Control register */
42 #define RTL8366RB_PECR 0x0001
44 /* Switch Security Control registers */
45 #define RTL8366RB_SSCR0 0x0002
46 #define RTL8366RB_SSCR1 0x0003
47 #define RTL8366RB_SSCR2 0x0004
48 #define RTL8366RB_SSCR2_DROP_UNKNOWN_DA BIT(0)
50 #define RTL8366RB_RESET_CTRL_REG 0x0100
51 #define RTL8366RB_CHIP_CTRL_RESET_HW 1
52 #define RTL8366RB_CHIP_CTRL_RESET_SW (1 << 1)
54 #define RTL8366RB_CHIP_VERSION_CTRL_REG 0x050A
55 #define RTL8366RB_CHIP_VERSION_MASK 0xf
56 #define RTL8366RB_CHIP_ID_REG 0x0509
57 #define RTL8366RB_CHIP_ID_8366 0x5937
59 /* PHY registers control */
60 #define RTL8366RB_PHY_ACCESS_CTRL_REG 0x8000
61 #define RTL8366RB_PHY_ACCESS_DATA_REG 0x8002
63 #define RTL8366RB_PHY_CTRL_READ 1
64 #define RTL8366RB_PHY_CTRL_WRITE 0
66 #define RTL8366RB_PHY_REG_MASK 0x1f
67 #define RTL8366RB_PHY_PAGE_OFFSET 5
68 #define RTL8366RB_PHY_PAGE_MASK (0xf << 5)
69 #define RTL8366RB_PHY_NO_OFFSET 9
70 #define RTL8366RB_PHY_NO_MASK (0x1f << 9)
72 #define RTL8366RB_VLAN_INGRESS_CTRL2_REG 0x037f
74 /* LED control registers */
75 #define RTL8366RB_LED_BLINKRATE_REG 0x0430
76 #define RTL8366RB_LED_BLINKRATE_BIT 0
77 #define RTL8366RB_LED_BLINKRATE_MASK 0x0007
79 #define RTL8366RB_LED_CTRL_REG 0x0431
80 #define RTL8366RB_LED_0_1_CTRL_REG 0x0432
81 #define RTL8366RB_LED_2_3_CTRL_REG 0x0433
83 #define RTL8366RB_MIB_COUNT 33
84 #define RTL8366RB_GLOBAL_MIB_COUNT 1
85 #define RTL8366RB_MIB_COUNTER_PORT_OFFSET 0x0050
86 #define RTL8366RB_MIB_COUNTER_BASE 0x1000
87 #define RTL8366RB_MIB_CTRL_REG 0x13F0
88 #define RTL8366RB_MIB_CTRL_USER_MASK 0x0FFC
89 #define RTL8366RB_MIB_CTRL_BUSY_MASK BIT(0)
90 #define RTL8366RB_MIB_CTRL_RESET_MASK BIT(1)
91 #define RTL8366RB_MIB_CTRL_PORT_RESET(_p) BIT(2 + (_p))
92 #define RTL8366RB_MIB_CTRL_GLOBAL_RESET BIT(11)
94 #define RTL8366RB_PORT_VLAN_CTRL_BASE 0x0063
95 #define RTL8366RB_PORT_VLAN_CTRL_REG(_p) \
96 (RTL8366RB_PORT_VLAN_CTRL_BASE + (_p) / 4)
97 #define RTL8366RB_PORT_VLAN_CTRL_MASK 0xf
98 #define RTL8366RB_PORT_VLAN_CTRL_SHIFT(_p) (4 * ((_p) % 4))
101 #define RTL8366RB_VLAN_TABLE_READ_BASE 0x018C
102 #define RTL8366RB_VLAN_TABLE_WRITE_BASE 0x0185
105 #define RTL8366RB_TABLE_ACCESS_CTRL_REG 0x0180
106 #define RTL8366RB_TABLE_VLAN_READ_CTRL 0x0E01
107 #define RTL8366RB_TABLE_VLAN_WRITE_CTRL 0x0F01
109 #define RTL8366RB_VLAN_MC_BASE(_x) (0x0020 + (_x) * 3)
112 #define RTL8366RB_PORT_LINK_STATUS_BASE 0x0014
113 #define RTL8366RB_PORT_STATUS_SPEED_MASK 0x0003
114 #define RTL8366RB_PORT_STATUS_DUPLEX_MASK 0x0004
115 #define RTL8366RB_PORT_STATUS_LINK_MASK 0x0010
116 #define RTL8366RB_PORT_STATUS_TXPAUSE_MASK 0x0020
117 #define RTL8366RB_PORT_STATUS_RXPAUSE_MASK 0x0040
118 #define RTL8366RB_PORT_STATUS_AN_MASK 0x0080
121 #define RTL8366RB_PORT_NUM_CPU 5
122 #define RTL8366RB_NUM_PORTS 6
123 #define RTL8366RB_NUM_VLANS 16
124 #define RTL8366RB_NUM_LEDGROUPS 4
125 #define RTL8366RB_NUM_VIDS 4096
126 #define RTL8366RB_PRIORITYMAX 7
127 #define RTL8366RB_FIDMAX 7
130 #define RTL8366RB_PORT_1 (1 << 0) /* In userspace port 0 */
131 #define RTL8366RB_PORT_2 (1 << 1) /* In userspace port 1 */
132 #define RTL8366RB_PORT_3 (1 << 2) /* In userspace port 2 */
133 #define RTL8366RB_PORT_4 (1 << 3) /* In userspace port 3 */
134 #define RTL8366RB_PORT_5 (1 << 4) /* In userspace port 4 */
136 #define RTL8366RB_PORT_CPU (1 << 5) /* CPU port */
138 #define RTL8366RB_PORT_ALL (RTL8366RB_PORT_1 | \
145 #define RTL8366RB_PORT_ALL_BUT_CPU (RTL8366RB_PORT_1 | \
151 #define RTL8366RB_PORT_ALL_EXTERNAL (RTL8366RB_PORT_1 | \
156 #define RTL8366RB_PORT_ALL_INTERNAL RTL8366RB_PORT_CPU
158 #define RTL8366RB_VLAN_VID_MASK 0xfff
159 #define RTL8366RB_VLAN_PRIORITY_SHIFT 12
160 #define RTL8366RB_VLAN_PRIORITY_MASK 0x7
161 #define RTL8366RB_VLAN_UNTAG_SHIFT 8
162 #define RTL8366RB_VLAN_UNTAG_MASK 0xff
163 #define RTL8366RB_VLAN_MEMBER_MASK 0xff
164 #define RTL8366RB_VLAN_FID_MASK 0x7
166 static struct rtl8366_mib_counter rtl8366rb_mib_counters[] = {
167 { 0, 0, 4, "IfInOctets" },
168 { 0, 4, 4, "EtherStatsOctets" },
169 { 0, 8, 2, "EtherStatsUnderSizePkts" },
170 { 0, 10, 2, "EtherFragments" },
171 { 0, 12, 2, "EtherStatsPkts64Octets" },
172 { 0, 14, 2, "EtherStatsPkts65to127Octets" },
173 { 0, 16, 2, "EtherStatsPkts128to255Octets" },
174 { 0, 18, 2, "EtherStatsPkts256to511Octets" },
175 { 0, 20, 2, "EtherStatsPkts512to1023Octets" },
176 { 0, 22, 2, "EtherStatsPkts1024to1518Octets" },
177 { 0, 24, 2, "EtherOversizeStats" },
178 { 0, 26, 2, "EtherStatsJabbers" },
179 { 0, 28, 2, "IfInUcastPkts" },
180 { 0, 30, 2, "EtherStatsMulticastPkts" },
181 { 0, 32, 2, "EtherStatsBroadcastPkts" },
182 { 0, 34, 2, "EtherStatsDropEvents" },
183 { 0, 36, 2, "Dot3StatsFCSErrors" },
184 { 0, 38, 2, "Dot3StatsSymbolErrors" },
185 { 0, 40, 2, "Dot3InPauseFrames" },
186 { 0, 42, 2, "Dot3ControlInUnknownOpcodes" },
187 { 0, 44, 4, "IfOutOctets" },
188 { 0, 48, 2, "Dot3StatsSingleCollisionFrames" },
189 { 0, 50, 2, "Dot3StatMultipleCollisionFrames" },
190 { 0, 52, 2, "Dot3sDeferredTransmissions" },
191 { 0, 54, 2, "Dot3StatsLateCollisions" },
192 { 0, 56, 2, "EtherStatsCollisions" },
193 { 0, 58, 2, "Dot3StatsExcessiveCollisions" },
194 { 0, 60, 2, "Dot3OutPauseFrames" },
195 { 0, 62, 2, "Dot1dBasePortDelayExceededDiscards" },
196 { 0, 64, 2, "Dot1dTpPortInDiscards" },
197 { 0, 66, 2, "IfOutUcastPkts" },
198 { 0, 68, 2, "IfOutMulticastPkts" },
199 { 0, 70, 2, "IfOutBroadcastPkts" },
202 #define REG_WR(_smi, _reg, _val) \
204 err = rtl8366_smi_write_reg(_smi, _reg, _val); \
209 #define REG_RMW(_smi, _reg, _mask, _val) \
211 err = rtl8366_smi_rmwr(_smi, _reg, _mask, _val); \
216 static int rtl8366rb_reset_chip(struct rtl8366_smi *smi)
221 rtl8366_smi_write_reg(smi, RTL8366RB_RESET_CTRL_REG,
222 RTL8366RB_CHIP_CTRL_RESET_HW);
225 if (rtl8366_smi_read_reg(smi, RTL8366RB_RESET_CTRL_REG, &data))
228 if (!(data & RTL8366RB_CHIP_CTRL_RESET_HW))
233 printk("Timeout waiting for the switch to reset\n");
240 static int rtl8366rb_hw_init(struct rtl8366_smi *smi)
244 /* set maximum packet length to 1536 bytes */
245 REG_RMW(smi, RTL8366RB_SGCR, RTL8366RB_SGCR_MAX_LENGTH_MASK,
246 RTL8366RB_SGCR_MAX_LENGTH_1536);
248 /* enable all ports */
249 REG_WR(smi, RTL8366RB_PECR, 0);
251 /* enable learning for all ports */
252 REG_WR(smi, RTL8366RB_SSCR0, 0);
254 /* enable auto ageing for all ports */
255 REG_WR(smi, RTL8366RB_SSCR1, 0);
258 * discard VLAN tagged packets if the port is not a member of
259 * the VLAN with which the packets is associated.
261 REG_WR(smi, RTL8366RB_VLAN_INGRESS_CTRL2_REG, RTL8366RB_PORT_ALL);
263 /* don't drop packets whose DA has not been learned */
264 REG_RMW(smi, RTL8366RB_SSCR2, RTL8366RB_SSCR2_DROP_UNKNOWN_DA, 0);
269 static int rtl8366rb_read_phy_reg(struct rtl8366_smi *smi,
270 u32 phy_no, u32 page, u32 addr, u32 *data)
275 if (phy_no > RTL8366RB_PHY_NO_MAX)
278 if (page > RTL8366RB_PHY_PAGE_MAX)
281 if (addr > RTL8366RB_PHY_ADDR_MAX)
284 ret = rtl8366_smi_write_reg(smi, RTL8366RB_PHY_ACCESS_CTRL_REG,
285 RTL8366RB_PHY_CTRL_READ);
289 reg = 0x8000 | (1 << (phy_no + RTL8366RB_PHY_NO_OFFSET)) |
290 ((page << RTL8366RB_PHY_PAGE_OFFSET) & RTL8366RB_PHY_PAGE_MASK) |
291 (addr & RTL8366RB_PHY_REG_MASK);
293 ret = rtl8366_smi_write_reg(smi, reg, 0);
297 ret = rtl8366_smi_read_reg(smi, RTL8366RB_PHY_ACCESS_DATA_REG, data);
304 static int rtl8366rb_write_phy_reg(struct rtl8366_smi *smi,
305 u32 phy_no, u32 page, u32 addr, u32 data)
310 if (phy_no > RTL8366RB_PHY_NO_MAX)
313 if (page > RTL8366RB_PHY_PAGE_MAX)
316 if (addr > RTL8366RB_PHY_ADDR_MAX)
319 ret = rtl8366_smi_write_reg(smi, RTL8366RB_PHY_ACCESS_CTRL_REG,
320 RTL8366RB_PHY_CTRL_WRITE);
324 reg = 0x8000 | (1 << (phy_no + RTL8366RB_PHY_NO_OFFSET)) |
325 ((page << RTL8366RB_PHY_PAGE_OFFSET) & RTL8366RB_PHY_PAGE_MASK) |
326 (addr & RTL8366RB_PHY_REG_MASK);
328 ret = rtl8366_smi_write_reg(smi, reg, data);
335 static int rtl8366rb_get_mib_counter(struct rtl8366_smi *smi, int counter,
336 int port, unsigned long long *val)
343 if (port > RTL8366RB_NUM_PORTS || counter >= RTL8366RB_MIB_COUNT)
346 addr = RTL8366RB_MIB_COUNTER_BASE +
347 RTL8366RB_MIB_COUNTER_PORT_OFFSET * (port) +
348 rtl8366rb_mib_counters[counter].offset;
351 * Writing access counter address first
352 * then ASIC will prepare 64bits counter wait for being retrived
354 data = 0; /* writing data will be discard by ASIC */
355 err = rtl8366_smi_write_reg(smi, addr, data);
359 /* read MIB control register */
360 err = rtl8366_smi_read_reg(smi, RTL8366RB_MIB_CTRL_REG, &data);
364 if (data & RTL8366RB_MIB_CTRL_BUSY_MASK)
367 if (data & RTL8366RB_MIB_CTRL_RESET_MASK)
371 for (i = rtl8366rb_mib_counters[counter].length; i > 0; i--) {
372 err = rtl8366_smi_read_reg(smi, addr + (i - 1), &data);
376 mibvalue = (mibvalue << 16) | (data & 0xFFFF);
383 static int rtl8366rb_get_vlan_4k(struct rtl8366_smi *smi, u32 vid,
384 struct rtl8366_vlan_4k *vlan4k)
390 memset(vlan4k, '\0', sizeof(struct rtl8366_vlan_4k));
392 if (vid >= RTL8366RB_NUM_VIDS)
396 err = rtl8366_smi_write_reg(smi, RTL8366RB_VLAN_TABLE_WRITE_BASE,
397 vid & RTL8366RB_VLAN_VID_MASK);
401 /* write table access control word */
402 err = rtl8366_smi_write_reg(smi, RTL8366RB_TABLE_ACCESS_CTRL_REG,
403 RTL8366RB_TABLE_VLAN_READ_CTRL);
407 for (i = 0; i < 3; i++) {
408 err = rtl8366_smi_read_reg(smi,
409 RTL8366RB_VLAN_TABLE_READ_BASE + i,
416 vlan4k->untag = (data[1] >> RTL8366RB_VLAN_UNTAG_SHIFT) &
417 RTL8366RB_VLAN_UNTAG_MASK;
418 vlan4k->member = data[1] & RTL8366RB_VLAN_MEMBER_MASK;
419 vlan4k->fid = data[2] & RTL8366RB_VLAN_FID_MASK;
424 static int rtl8366rb_set_vlan_4k(struct rtl8366_smi *smi,
425 const struct rtl8366_vlan_4k *vlan4k)
431 if (vlan4k->vid >= RTL8366RB_NUM_VIDS ||
432 vlan4k->member > RTL8366RB_PORT_ALL ||
433 vlan4k->untag > RTL8366RB_PORT_ALL ||
434 vlan4k->fid > RTL8366RB_FIDMAX)
437 data[0] = vlan4k->vid & RTL8366RB_VLAN_VID_MASK;
438 data[1] = (vlan4k->member & RTL8366RB_VLAN_MEMBER_MASK) |
439 ((vlan4k->untag & RTL8366RB_VLAN_UNTAG_MASK) <<
440 RTL8366RB_VLAN_UNTAG_SHIFT);
441 data[2] = vlan4k->fid & RTL8366RB_VLAN_FID_MASK;
443 for (i = 0; i < 3; i++) {
444 err = rtl8366_smi_write_reg(smi,
445 RTL8366RB_VLAN_TABLE_WRITE_BASE + i,
451 /* write table access control word */
452 err = rtl8366_smi_write_reg(smi, RTL8366RB_TABLE_ACCESS_CTRL_REG,
453 RTL8366RB_TABLE_VLAN_WRITE_CTRL);
458 static int rtl8366rb_get_vlan_mc(struct rtl8366_smi *smi, u32 index,
459 struct rtl8366_vlan_mc *vlanmc)
465 memset(vlanmc, '\0', sizeof(struct rtl8366_vlan_mc));
467 if (index >= RTL8366RB_NUM_VLANS)
470 for (i = 0; i < 3; i++) {
471 err = rtl8366_smi_read_reg(smi,
472 RTL8366RB_VLAN_MC_BASE(index) + i,
478 vlanmc->vid = data[0] & RTL8366RB_VLAN_VID_MASK;
479 vlanmc->priority = (data[0] >> RTL8366RB_VLAN_PRIORITY_SHIFT) &
480 RTL8366RB_VLAN_PRIORITY_MASK;
481 vlanmc->untag = (data[1] >> RTL8366RB_VLAN_UNTAG_SHIFT) &
482 RTL8366RB_VLAN_UNTAG_MASK;
483 vlanmc->member = data[1] & RTL8366RB_VLAN_MEMBER_MASK;
484 vlanmc->fid = data[2] & RTL8366RB_VLAN_FID_MASK;
489 static int rtl8366rb_set_vlan_mc(struct rtl8366_smi *smi, u32 index,
490 const struct rtl8366_vlan_mc *vlanmc)
496 if (index >= RTL8366RB_NUM_VLANS ||
497 vlanmc->vid >= RTL8366RB_NUM_VIDS ||
498 vlanmc->priority > RTL8366RB_PRIORITYMAX ||
499 vlanmc->member > RTL8366RB_PORT_ALL ||
500 vlanmc->untag > RTL8366RB_PORT_ALL ||
501 vlanmc->fid > RTL8366RB_FIDMAX)
504 data[0] = (vlanmc->vid & RTL8366RB_VLAN_VID_MASK) |
505 ((vlanmc->priority & RTL8366RB_VLAN_PRIORITY_MASK) <<
506 RTL8366RB_VLAN_PRIORITY_SHIFT);
507 data[1] = (vlanmc->member & RTL8366RB_VLAN_MEMBER_MASK) |
508 ((vlanmc->untag & RTL8366RB_VLAN_UNTAG_MASK) <<
509 RTL8366RB_VLAN_UNTAG_SHIFT);
510 data[2] = vlanmc->fid & RTL8366RB_VLAN_FID_MASK;
512 for (i = 0; i < 3; i++) {
513 err = rtl8366_smi_write_reg(smi,
514 RTL8366RB_VLAN_MC_BASE(index) + i,
523 static int rtl8366rb_get_mc_index(struct rtl8366_smi *smi, int port, int *val)
528 if (port >= RTL8366RB_NUM_PORTS)
531 err = rtl8366_smi_read_reg(smi, RTL8366RB_PORT_VLAN_CTRL_REG(port),
536 *val = (data >> RTL8366RB_PORT_VLAN_CTRL_SHIFT(port)) &
537 RTL8366RB_PORT_VLAN_CTRL_MASK;
543 static int rtl8366rb_set_mc_index(struct rtl8366_smi *smi, int port, int index)
545 if (port >= RTL8366RB_NUM_PORTS || index >= RTL8366RB_NUM_VLANS)
548 return rtl8366_smi_rmwr(smi, RTL8366RB_PORT_VLAN_CTRL_REG(port),
549 RTL8366RB_PORT_VLAN_CTRL_MASK <<
550 RTL8366RB_PORT_VLAN_CTRL_SHIFT(port),
551 (index & RTL8366RB_PORT_VLAN_CTRL_MASK) <<
552 RTL8366RB_PORT_VLAN_CTRL_SHIFT(port));
555 static int rtl8366rb_is_vlan_valid(struct rtl8366_smi *smi, unsigned vlan)
557 if (vlan == 0 || vlan >= RTL8366RB_NUM_VLANS)
563 static int rtl8366rb_vlan_set_vlan(struct rtl8366_smi *smi, int enable)
565 return rtl8366_smi_rmwr(smi, RTL8366RB_SGCR, RTL8366RB_SGCR_EN_VLAN,
566 (enable) ? RTL8366RB_SGCR_EN_VLAN : 0);
569 static int rtl8366rb_vlan_set_4ktable(struct rtl8366_smi *smi, int enable)
571 return rtl8366_smi_rmwr(smi, RTL8366RB_SGCR,
572 RTL8366RB_SGCR_EN_VLAN_4KTB,
573 (enable) ? RTL8366RB_SGCR_EN_VLAN_4KTB : 0);
576 static int rtl8366rb_sw_reset_mibs(struct switch_dev *dev,
577 const struct switch_attr *attr,
578 struct switch_val *val)
580 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
582 return rtl8366_smi_rmwr(smi, RTL8366RB_MIB_CTRL_REG, 0,
583 RTL8366RB_MIB_CTRL_GLOBAL_RESET);
586 static int rtl8366rb_sw_get_vlan_enable(struct switch_dev *dev,
587 const struct switch_attr *attr,
588 struct switch_val *val)
590 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
593 if (attr->ofs == 1) {
594 rtl8366_smi_read_reg(smi, RTL8366RB_SGCR, &data);
596 if (data & RTL8366RB_SGCR_EN_VLAN)
600 } else if (attr->ofs == 2) {
601 rtl8366_smi_read_reg(smi, RTL8366RB_SGCR, &data);
603 if (data & RTL8366RB_SGCR_EN_VLAN_4KTB)
612 static int rtl8366rb_sw_get_blinkrate(struct switch_dev *dev,
613 const struct switch_attr *attr,
614 struct switch_val *val)
616 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
619 rtl8366_smi_read_reg(smi, RTL8366RB_LED_BLINKRATE_REG, &data);
621 val->value.i = (data & (RTL8366RB_LED_BLINKRATE_MASK));
626 static int rtl8366rb_sw_set_blinkrate(struct switch_dev *dev,
627 const struct switch_attr *attr,
628 struct switch_val *val)
630 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
632 if (val->value.i >= 6)
635 return rtl8366_smi_rmwr(smi, RTL8366RB_LED_BLINKRATE_REG,
636 RTL8366RB_LED_BLINKRATE_MASK,
640 static int rtl8366rb_sw_set_vlan_enable(struct switch_dev *dev,
641 const struct switch_attr *attr,
642 struct switch_val *val)
644 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
647 return rtl8366rb_vlan_set_vlan(smi, val->value.i);
649 return rtl8366rb_vlan_set_4ktable(smi, val->value.i);
652 static int rtl8366rb_sw_get_learning_enable(struct switch_dev *dev,
653 const struct switch_attr *attr,
654 struct switch_val *val)
656 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
659 rtl8366_smi_read_reg(smi, RTL8366RB_SSCR0, &data);
660 val->value.i = !data;
666 static int rtl8366rb_sw_set_learning_enable(struct switch_dev *dev,
667 const struct switch_attr *attr,
668 struct switch_val *val)
670 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
675 portmask = RTL8366RB_PORT_ALL;
677 /* set learning for all ports */
678 REG_WR(smi, RTL8366RB_SSCR0, portmask);
680 /* set auto ageing for all ports */
681 REG_WR(smi, RTL8366RB_SSCR1, portmask);
687 static const char *rtl8366rb_speed_str(unsigned speed)
701 static int rtl8366rb_sw_get_port_link(struct switch_dev *dev,
702 const struct switch_attr *attr,
703 struct switch_val *val)
705 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
706 u32 len = 0, data = 0;
708 if (val->port_vlan >= RTL8366RB_NUM_PORTS)
711 memset(smi->buf, '\0', sizeof(smi->buf));
712 rtl8366_smi_read_reg(smi, RTL8366RB_PORT_LINK_STATUS_BASE +
713 (val->port_vlan / 2), &data);
715 if (val->port_vlan % 2)
718 if (data & RTL8366RB_PORT_STATUS_LINK_MASK) {
719 len = snprintf(smi->buf, sizeof(smi->buf),
720 "port:%d link:up speed:%s %s-duplex %s%s%s",
722 rtl8366rb_speed_str(data &
723 RTL8366RB_PORT_STATUS_SPEED_MASK),
724 (data & RTL8366RB_PORT_STATUS_DUPLEX_MASK) ?
726 (data & RTL8366RB_PORT_STATUS_TXPAUSE_MASK) ?
728 (data & RTL8366RB_PORT_STATUS_RXPAUSE_MASK) ?
730 (data & RTL8366RB_PORT_STATUS_AN_MASK) ?
733 len = snprintf(smi->buf, sizeof(smi->buf), "port:%d link: down",
737 val->value.s = smi->buf;
743 static int rtl8366rb_sw_set_port_led(struct switch_dev *dev,
744 const struct switch_attr *attr,
745 struct switch_val *val)
747 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
752 if (val->port_vlan >= RTL8366RB_NUM_PORTS)
755 if (val->port_vlan == RTL8366RB_PORT_NUM_CPU) {
756 reg = RTL8366RB_LED_BLINKRATE_REG;
758 data = val->value.i << 4;
760 reg = RTL8366RB_LED_CTRL_REG;
761 mask = 0xF << (val->port_vlan * 4),
762 data = val->value.i << (val->port_vlan * 4);
765 return rtl8366_smi_rmwr(smi, RTL8366RB_LED_BLINKRATE_REG, mask, data);
768 static int rtl8366rb_sw_get_port_led(struct switch_dev *dev,
769 const struct switch_attr *attr,
770 struct switch_val *val)
772 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
775 if (val->port_vlan >= RTL8366RB_NUM_LEDGROUPS)
778 rtl8366_smi_read_reg(smi, RTL8366RB_LED_CTRL_REG, &data);
779 val->value.i = (data >> (val->port_vlan * 4)) & 0x000F;
784 static int rtl8366rb_sw_reset_port_mibs(struct switch_dev *dev,
785 const struct switch_attr *attr,
786 struct switch_val *val)
788 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
790 if (val->port_vlan >= RTL8366RB_NUM_PORTS)
793 return rtl8366_smi_rmwr(smi, RTL8366RB_MIB_CTRL_REG, 0,
794 RTL8366RB_MIB_CTRL_PORT_RESET(val->port_vlan));
797 static int rtl8366rb_sw_reset_switch(struct switch_dev *dev)
799 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
802 err = rtl8366rb_reset_chip(smi);
806 err = rtl8366rb_hw_init(smi);
810 return rtl8366_reset_vlan(smi);
813 static struct switch_attr rtl8366rb_globals[] = {
815 .type = SWITCH_TYPE_INT,
816 .name = "enable_learning",
817 .description = "Enable learning, enable aging",
818 .set = rtl8366rb_sw_set_learning_enable,
819 .get = rtl8366rb_sw_get_learning_enable,
822 .type = SWITCH_TYPE_INT,
823 .name = "enable_vlan",
824 .description = "Enable VLAN mode",
825 .set = rtl8366rb_sw_set_vlan_enable,
826 .get = rtl8366rb_sw_get_vlan_enable,
830 .type = SWITCH_TYPE_INT,
831 .name = "enable_vlan4k",
832 .description = "Enable VLAN 4K mode",
833 .set = rtl8366rb_sw_set_vlan_enable,
834 .get = rtl8366rb_sw_get_vlan_enable,
838 .type = SWITCH_TYPE_NOVAL,
839 .name = "reset_mibs",
840 .description = "Reset all MIB counters",
841 .set = rtl8366rb_sw_reset_mibs,
843 .type = SWITCH_TYPE_INT,
845 .description = "Get/Set LED blinking rate (0 = 43ms, 1 = 84ms,"
846 " 2 = 120ms, 3 = 170ms, 4 = 340ms, 5 = 670ms)",
847 .set = rtl8366rb_sw_set_blinkrate,
848 .get = rtl8366rb_sw_get_blinkrate,
853 static struct switch_attr rtl8366rb_port[] = {
855 .type = SWITCH_TYPE_STRING,
857 .description = "Get port link information",
860 .get = rtl8366rb_sw_get_port_link,
862 .type = SWITCH_TYPE_NOVAL,
864 .description = "Reset single port MIB counters",
865 .set = rtl8366rb_sw_reset_port_mibs,
867 .type = SWITCH_TYPE_STRING,
869 .description = "Get MIB counters for port",
872 .get = rtl8366_sw_get_port_mib,
874 .type = SWITCH_TYPE_INT,
876 .description = "Get/Set port group (0 - 3) led mode (0 - 15)",
878 .set = rtl8366rb_sw_set_port_led,
879 .get = rtl8366rb_sw_get_port_led,
883 static struct switch_attr rtl8366rb_vlan[] = {
885 .type = SWITCH_TYPE_STRING,
887 .description = "Get vlan information",
890 .get = rtl8366_sw_get_vlan_info,
894 static const struct switch_dev_ops rtl8366_ops = {
896 .attr = rtl8366rb_globals,
897 .n_attr = ARRAY_SIZE(rtl8366rb_globals),
900 .attr = rtl8366rb_port,
901 .n_attr = ARRAY_SIZE(rtl8366rb_port),
904 .attr = rtl8366rb_vlan,
905 .n_attr = ARRAY_SIZE(rtl8366rb_vlan),
908 .get_vlan_ports = rtl8366_sw_get_vlan_ports,
909 .set_vlan_ports = rtl8366_sw_set_vlan_ports,
910 .get_port_pvid = rtl8366_sw_get_port_pvid,
911 .set_port_pvid = rtl8366_sw_set_port_pvid,
912 .reset_switch = rtl8366rb_sw_reset_switch,
915 static int rtl8366rb_switch_init(struct rtl8366_smi *smi)
917 struct switch_dev *dev = &smi->sw_dev;
920 dev->name = "RTL8366RB";
921 dev->cpu_port = RTL8366RB_PORT_NUM_CPU;
922 dev->ports = RTL8366RB_NUM_PORTS;
923 dev->vlans = RTL8366RB_NUM_VLANS;
924 dev->ops = &rtl8366_ops;
925 dev->devname = dev_name(smi->parent);
927 err = register_switch(dev, NULL);
929 dev_err(smi->parent, "switch registration failed\n");
934 static void rtl8366rb_switch_cleanup(struct rtl8366_smi *smi)
936 unregister_switch(&smi->sw_dev);
939 static int rtl8366rb_mii_read(struct mii_bus *bus, int addr, int reg)
941 struct rtl8366_smi *smi = bus->priv;
945 err = rtl8366rb_read_phy_reg(smi, addr, 0, reg, &val);
952 static int rtl8366rb_mii_write(struct mii_bus *bus, int addr, int reg, u16 val)
954 struct rtl8366_smi *smi = bus->priv;
958 err = rtl8366rb_write_phy_reg(smi, addr, 0, reg, val);
960 (void) rtl8366rb_read_phy_reg(smi, addr, 0, reg, &t);
965 static int rtl8366rb_mii_bus_match(struct mii_bus *bus)
967 return (bus->read == rtl8366rb_mii_read &&
968 bus->write == rtl8366rb_mii_write);
971 static int rtl8366rb_setup(struct rtl8366_smi *smi)
975 ret = rtl8366rb_reset_chip(smi);
979 ret = rtl8366rb_hw_init(smi);
983 static int rtl8366rb_detect(struct rtl8366_smi *smi)
989 ret = rtl8366_smi_read_reg(smi, RTL8366RB_CHIP_ID_REG, &chip_id);
991 dev_err(smi->parent, "unable to read chip id\n");
996 case RTL8366RB_CHIP_ID_8366:
999 dev_err(smi->parent, "unknown chip id (%04x)\n", chip_id);
1003 ret = rtl8366_smi_read_reg(smi, RTL8366RB_CHIP_VERSION_CTRL_REG,
1006 dev_err(smi->parent, "unable to read chip version\n");
1010 dev_info(smi->parent, "RTL%04x ver. %u chip found\n",
1011 chip_id, chip_ver & RTL8366RB_CHIP_VERSION_MASK);
1016 static struct rtl8366_smi_ops rtl8366rb_smi_ops = {
1017 .detect = rtl8366rb_detect,
1018 .setup = rtl8366rb_setup,
1020 .mii_read = rtl8366rb_mii_read,
1021 .mii_write = rtl8366rb_mii_write,
1023 .get_vlan_mc = rtl8366rb_get_vlan_mc,
1024 .set_vlan_mc = rtl8366rb_set_vlan_mc,
1025 .get_vlan_4k = rtl8366rb_get_vlan_4k,
1026 .set_vlan_4k = rtl8366rb_set_vlan_4k,
1027 .get_mc_index = rtl8366rb_get_mc_index,
1028 .set_mc_index = rtl8366rb_set_mc_index,
1029 .get_mib_counter = rtl8366rb_get_mib_counter,
1030 .is_vlan_valid = rtl8366rb_is_vlan_valid,
1033 static int __init rtl8366rb_probe(struct platform_device *pdev)
1035 static int rtl8366_smi_version_printed;
1036 struct rtl8366rb_platform_data *pdata;
1037 struct rtl8366_smi *smi;
1040 if (!rtl8366_smi_version_printed++)
1041 printk(KERN_NOTICE RTL8366RB_DRIVER_DESC
1042 " version " RTL8366RB_DRIVER_VER"\n");
1044 pdata = pdev->dev.platform_data;
1046 dev_err(&pdev->dev, "no platform data specified\n");
1051 smi = rtl8366_smi_alloc(&pdev->dev);
1057 smi->gpio_sda = pdata->gpio_sda;
1058 smi->gpio_sck = pdata->gpio_sck;
1059 smi->ops = &rtl8366rb_smi_ops;
1060 smi->cpu_port = RTL8366RB_PORT_NUM_CPU;
1061 smi->num_ports = RTL8366RB_NUM_PORTS;
1062 smi->num_vlan_mc = RTL8366RB_NUM_VLANS;
1063 smi->mib_counters = rtl8366rb_mib_counters;
1064 smi->num_mib_counters = ARRAY_SIZE(rtl8366rb_mib_counters);
1066 err = rtl8366_smi_init(smi);
1070 platform_set_drvdata(pdev, smi);
1072 err = rtl8366rb_switch_init(smi);
1074 goto err_clear_drvdata;
1079 platform_set_drvdata(pdev, NULL);
1080 rtl8366_smi_cleanup(smi);
1087 static int rtl8366rb_phy_config_init(struct phy_device *phydev)
1089 if (!rtl8366rb_mii_bus_match(phydev->bus))
1095 static int rtl8366rb_phy_config_aneg(struct phy_device *phydev)
1100 static struct phy_driver rtl8366rb_phy_driver = {
1101 .phy_id = 0x001cc960,
1102 .name = "Realtek RTL8366RB",
1103 .phy_id_mask = 0x1ffffff0,
1104 .features = PHY_GBIT_FEATURES,
1105 .config_aneg = rtl8366rb_phy_config_aneg,
1106 .config_init = rtl8366rb_phy_config_init,
1107 .read_status = genphy_read_status,
1109 .owner = THIS_MODULE,
1113 static int __devexit rtl8366rb_remove(struct platform_device *pdev)
1115 struct rtl8366_smi *smi = platform_get_drvdata(pdev);
1118 rtl8366rb_switch_cleanup(smi);
1119 platform_set_drvdata(pdev, NULL);
1120 rtl8366_smi_cleanup(smi);
1127 static struct platform_driver rtl8366rb_driver = {
1129 .name = RTL8366RB_DRIVER_NAME,
1130 .owner = THIS_MODULE,
1132 .probe = rtl8366rb_probe,
1133 .remove = __devexit_p(rtl8366rb_remove),
1136 static int __init rtl8366rb_module_init(void)
1139 ret = platform_driver_register(&rtl8366rb_driver);
1143 ret = phy_driver_register(&rtl8366rb_phy_driver);
1145 goto err_platform_unregister;
1149 err_platform_unregister:
1150 platform_driver_unregister(&rtl8366rb_driver);
1153 module_init(rtl8366rb_module_init);
1155 static void __exit rtl8366rb_module_exit(void)
1157 phy_driver_unregister(&rtl8366rb_phy_driver);
1158 platform_driver_unregister(&rtl8366rb_driver);
1160 module_exit(rtl8366rb_module_exit);
1162 MODULE_DESCRIPTION(RTL8366RB_DRIVER_DESC);
1163 MODULE_VERSION(RTL8366RB_DRIVER_VER);
1164 MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
1165 MODULE_AUTHOR("Antti Seppälä <a.seppala@gmail.com>");
1166 MODULE_LICENSE("GPL v2");
1167 MODULE_ALIAS("platform:" RTL8366RB_DRIVER_NAME);