2 * B53 register definitions
4 * Copyright (C) 2004 Broadcom Corporation
5 * Copyright (C) 2011-2013 Jonas Gorski <jogo@openwrt.org>
7 * Permission to use, copy, modify, and/or distribute this software for any
8 * purpose with or without fee is hereby granted, provided that the above
9 * copyright notice and this permission notice appear in all copies.
11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
23 /* Management Port (SMP) Page offsets */
24 #define B53_CTRL_PAGE 0x00 /* Control */
25 #define B53_STAT_PAGE 0x01 /* Status */
26 #define B53_MGMT_PAGE 0x02 /* Management Mode */
27 #define B53_MIB_AC_PAGE 0x03 /* MIB Autocast */
28 #define B53_ARLCTRL_PAGE 0x04 /* ARL Control */
29 #define B53_ARLIO_PAGE 0x05 /* ARL Access */
30 #define B53_FRAMEBUF_PAGE 0x06 /* Management frame access */
31 #define B53_MEM_ACCESS_PAGE 0x08 /* Memory access */
34 #define B53_PORT_MII_PAGE(i) (0x10 + i) /* Port i MII Registers */
35 #define B53_IM_PORT_PAGE 0x18 /* Inverse MII Port (to EMAC) */
36 #define B53_ALL_PORT_PAGE 0x19 /* All ports MII (broadcast) */
39 #define B53_MIB_PAGE(i) (0x20 + i)
41 /* Quality of Service (QoS) Registers */
42 #define B53_QOS_PAGE 0x30
45 #define B53_PVLAN_PAGE 0x31
48 #define B53_VLAN_PAGE 0x34
50 /* Jumbo Frame Registers */
51 #define B53_JUMBO_PAGE 0x40
53 /*************************************************************************
54 * Control Page registers
55 *************************************************************************/
57 /* Port Control Register (8 bit) */
58 #define B53_PORT_CTRL(i) (0x00 + i)
59 #define PORT_CTRL_RX_DISABLE BIT(0)
60 #define PORT_CTRL_TX_DISABLE BIT(1)
61 #define PORT_CTRL_RX_BCST_EN BIT(2) /* Broadcast RX (P8 only) */
62 #define PORT_CTRL_RX_MCST_EN BIT(3) /* Multicast RX (P8 only) */
63 #define PORT_CTRL_RX_UCST_EN BIT(4) /* Unicast RX (P8 only) */
64 #define PORT_CTRL_STP_STATE_S 5
65 #define PORT_CTRL_STP_STATE_MASK (0x3 << PORT_CTRL_STP_STATE_S)
67 /* SMP Control Register (8 bit) */
68 #define B53_SMP_CTRL 0x0a
70 /* Switch Mode Control Register (8 bit) */
71 #define B53_SWITCH_MODE 0x0b
72 #define SM_SW_FWD_MODE BIT(0) /* 1 = Managed Mode */
73 #define SM_SW_FWD_EN BIT(1) /* Forwarding Enable */
75 /* IMP Port state override register (8 bit) */
76 #define B53_PORT_OVERRIDE_CTRL 0x0e
77 #define PORT_OVERRIDE_LINK BIT(0)
78 #define PORT_OVERRIDE_FULL_DUPLEX BIT(1) /* 0 = Half Duplex */
79 #define PORT_OVERRIDE_SPEED_S 2
80 #define PORT_OVERRIDE_SPEED_10M (0 << PORT_OVERRIDE_SPEED_S)
81 #define PORT_OVERRIDE_SPEED_100M (1 << PORT_OVERRIDE_SPEED_S)
82 #define PORT_OVERRIDE_SPEED_1000M (2 << PORT_OVERRIDE_SPEED_S)
83 #define PORT_OVERRIDE_RV_MII_25 BIT(4) /* BCM5325 only */
84 #define PORT_OVERRIDE_RX_FLOW BIT(4)
85 #define PORT_OVERRIDE_TX_FLOW BIT(5)
86 #define PORT_OVERRIDE_EN BIT(7) /* Use the register contents */
88 /* Power-down mode control */
89 #define B53_PD_MODE_CTRL_25 0x0f
91 /* IP Multicast control (8 bit) */
92 #define B53_IP_MULTICAST_CTRL 0x21
93 #define B53_IPMC_FWD_EN BIT(1)
94 #define B53_UC_FWD_EN BIT(6)
95 #define B53_MC_FWD_EN BIT(7)
98 #define B53_UC_FLOOD_MASK 0x32
99 #define B53_MC_FLOOD_MASK 0x34
100 #define B53_IPMC_FLOOD_MASK 0x36
102 /* Software reset register (8 bit) */
103 #define B53_SOFTRESET 0x79
105 /* Fast Aging Control register (8 bit) */
106 #define B53_FAST_AGE_CTRL 0x88
107 #define FAST_AGE_STATIC BIT(0)
108 #define FAST_AGE_DYNAMIC BIT(1)
109 #define FAST_AGE_PORT BIT(2)
110 #define FAST_AGE_VLAN BIT(3)
111 #define FAST_AGE_STP BIT(4)
112 #define FAST_AGE_MC BIT(5)
113 #define FAST_AGE_DONE BIT(7)
115 /*************************************************************************
116 * Status Page registers
117 *************************************************************************/
119 /* Link Status Summary Register (16bit) */
120 #define B53_LINK_STAT 0x00
122 /* Link Status Change Register (16 bit) */
123 #define B53_LINK_STAT_CHANGE 0x02
125 /* Port Speed Summary Register (16 bit for FE, 32 bit for GE) */
126 #define B53_SPEED_STAT 0x04
127 #define SPEED_PORT_FE(reg, port) (((reg) >> (port)) & 1)
128 #define SPEED_PORT_GE(reg, port) (((reg) >> 2 * (port)) & 3)
129 #define SPEED_STAT_10M 0
130 #define SPEED_STAT_100M 1
131 #define SPEED_STAT_1000M 2
133 /* Duplex Status Summary (16 bit) */
134 #define B53_DUPLEX_STAT_FE 0x06
135 #define B53_DUPLEX_STAT_GE 0x08
136 #define B53_DUPLEX_STAT_63XX 0x0c
138 /* Revision ID register for BCM5325 */
139 #define B53_REV_ID_25 0x50
141 /* Strap Value (48 bit) */
142 #define B53_STRAP_VALUE 0x70
143 #define SV_GMII_CTRL_115 BIT(27)
145 /*************************************************************************
146 * Management Mode Page Registers
147 *************************************************************************/
149 /* Global Management Config Register (8 bit) */
150 #define B53_GLOBAL_CONFIG 0x00
151 #define GC_RESET_MIB 0x01
152 #define GC_RX_BPDU_EN 0x02
153 #define GC_MIB_AC_HDR_EN 0x10
154 #define GC_MIB_AC_EN 0x20
155 #define GC_FRM_MGMT_PORT_M 0xC0
156 #define GC_FRM_MGMT_PORT_04 0x00
157 #define GC_FRM_MGMT_PORT_MII 0x80
159 /* Device ID register (8 or 32 bit) */
160 #define B53_DEVICE_ID 0x30
162 /* Revision ID register (8 bit) */
163 #define B53_REV_ID 0x40
165 /*************************************************************************
166 * ARL Access Page Registers
167 *************************************************************************/
169 /* VLAN Table Access Register (8 bit) */
170 #define B53_VT_ACCESS 0x80
171 #define B53_VT_ACCESS_9798 0x60 /* for BCM5397/BCM5398 */
172 #define B53_VT_ACCESS_63XX 0x60 /* for BCM6328/62/68 */
173 #define VTA_CMD_WRITE 0
174 #define VTA_CMD_READ 1
175 #define VTA_CMD_CLEAR 2
176 #define VTA_START_CMD BIT(7)
178 /* VLAN Table Index Register (16 bit) */
179 #define B53_VT_INDEX 0x81
180 #define B53_VT_INDEX_9798 0x61
181 #define B53_VT_INDEX_63XX 0x62
183 /* VLAN Table Entry Register (32 bit) */
184 #define B53_VT_ENTRY 0x83
185 #define B53_VT_ENTRY_9798 0x63
186 #define B53_VT_ENTRY_63XX 0x64
187 #define VTE_MEMBERS 0x1ff
188 #define VTE_UNTAG_S 9
189 #define VTE_UNTAG (0x1ff << 9)
191 /*************************************************************************
192 * Port VLAN Registers
193 *************************************************************************/
195 /* Port VLAN mask (16 bit) IMP port is always 8, also on 5325 & co */
196 #define B53_PVLAN_PORT_MASK(i) ((i) * 2)
198 /*************************************************************************
199 * 802.1Q Page Registers
200 *************************************************************************/
202 /* Global QoS Control (8 bit) */
203 #define B53_QOS_GLOBAL_CTL 0x00
205 /* Enable 802.1Q for individual Ports (16 bit) */
206 #define B53_802_1P_EN 0x04
208 /*************************************************************************
209 * VLAN Page Registers
210 *************************************************************************/
212 /* VLAN Control 0 (8 bit) */
213 #define B53_VLAN_CTRL0 0x00
214 #define VC0_8021PF_CTRL_MASK 0x3
215 #define VC0_8021PF_CTRL_NONE 0x0
216 #define VC0_8021PF_CTRL_CHANGE_PRI 0x1
217 #define VC0_8021PF_CTRL_CHANGE_VID 0x2
218 #define VC0_8021PF_CTRL_CHANGE_BOTH 0x3
219 #define VC0_8021QF_CTRL_MASK 0xc
220 #define VC0_8021QF_CTRL_CHANGE_PRI 0x1
221 #define VC0_8021QF_CTRL_CHANGE_VID 0x2
222 #define VC0_8021QF_CTRL_CHANGE_BOTH 0x3
223 #define VC0_RESERVED_1 BIT(1)
224 #define VC0_DROP_VID_MISS BIT(4)
225 #define VC0_VID_HASH_VID BIT(5)
226 #define VC0_VID_CHK_EN BIT(6) /* Use VID,DA or VID,SA */
227 #define VC0_VLAN_EN BIT(7) /* 802.1Q VLAN Enabled */
229 /* VLAN Control 1 (8 bit) */
230 #define B53_VLAN_CTRL1 0x01
231 #define VC1_RX_MCST_TAG_EN BIT(1)
232 #define VC1_RX_MCST_FWD_EN BIT(2)
233 #define VC1_RX_MCST_UNTAG_EN BIT(3)
235 /* VLAN Control 2 (8 bit) */
236 #define B53_VLAN_CTRL2 0x02
238 /* VLAN Control 3 (8 bit when BCM5325, 16 bit else) */
239 #define B53_VLAN_CTRL3 0x03
240 #define B53_VLAN_CTRL3_63XX 0x04
241 #define VC3_MAXSIZE_1532 BIT(6) /* 5325 only */
242 #define VC3_HIGH_8BIT_EN BIT(7) /* 5325 only */
244 /* VLAN Control 4 (8 bit) */
245 #define B53_VLAN_CTRL4 0x05
246 #define B53_VLAN_CTRL4_25 0x04
247 #define B53_VLAN_CTRL4_63XX 0x06
248 #define VC4_ING_VID_CHECK_S 6
249 #define VC4_ING_VID_CHECK_MASK (0x3 << VC4_ING_VID_CHECK_S)
250 #define VC4_ING_VID_VIO_FWD 0 /* forward, but do not learn */
251 #define VC4_ING_VID_VIO_DROP 1 /* drop VID violations */
252 #define VC4_NO_ING_VID_CHK 2 /* do not check */
253 #define VC4_ING_VID_VIO_TO_IMP 3 /* redirect to MII port */
255 /* VLAN Control 5 (8 bit) */
256 #define B53_VLAN_CTRL5 0x06
257 #define B53_VLAN_CTRL5_25 0x05
258 #define B53_VLAN_CTRL5_63XX 0x07
259 #define VC5_VID_FFF_EN BIT(2)
260 #define VC5_DROP_VTABLE_MISS BIT(3)
262 /* VLAN Control 6 (8 bit) */
263 #define B53_VLAN_CTRL6 0x07
264 #define B53_VLAN_CTRL6_63XX 0x08
266 /* VLAN Table Access Register (16 bit) */
267 #define B53_VLAN_TABLE_ACCESS_25 0x06 /* BCM5325E/5350 */
268 #define B53_VLAN_TABLE_ACCESS_65 0x08 /* BCM5365 */
269 #define VTA_VID_LOW_MASK_25 0xf
270 #define VTA_VID_LOW_MASK_65 0xff
271 #define VTA_VID_HIGH_S_25 4
272 #define VTA_VID_HIGH_S_65 8
273 #define VTA_VID_HIGH_MASK_25 (0xff << VTA_VID_HIGH_S_25E)
274 #define VTA_VID_HIGH_MASK_65 (0xf << VTA_VID_HIGH_S_65)
275 #define VTA_RW_STATE BIT(12)
276 #define VTA_RW_STATE_RD 0
277 #define VTA_RW_STATE_WR BIT(12)
278 #define VTA_RW_OP_EN BIT(13)
280 /* VLAN Read/Write Registers for (16/32 bit) */
281 #define B53_VLAN_WRITE_25 0x08
282 #define B53_VLAN_WRITE_65 0x0a
283 #define B53_VLAN_READ 0x0c
284 #define VA_MEMBER_MASK 0x3f
285 #define VA_UNTAG_S_25 6
286 #define VA_UNTAG_MASK_25 0x3f
287 #define VA_UNTAG_S_65 7
288 #define VA_UNTAG_MASK_65 0x1f
289 #define VA_VID_HIGH_S 12
290 #define VA_VID_HIGH_MASK (0xffff << VA_VID_HIGH_S)
291 #define VA_VALID_25 BIT(20)
292 #define VA_VALID_25_R4 BIT(24)
293 #define VA_VALID_65 BIT(14)
295 /* VLAN Port Default Tag (16 bit) */
296 #define B53_VLAN_PORT_DEF_TAG(i) (0x10 + 2 * (i))
298 /*************************************************************************
299 * Jumbo Frame Page Registers
300 *************************************************************************/
302 /* Jumbo Enable Port Mask (bit i == port i enabled) (32 bit) */
303 #define B53_JUMBO_PORT_MASK 0x01
304 #define B53_JUMBO_PORT_MASK_63XX 0x04
305 #define JPM_10_100_JUMBO_EN BIT(24) /* GigE always enabled */
307 /* Good Frame Max Size without 802.1Q TAG (16 bit) */
308 #define B53_JUMBO_MAX_SIZE 0x05
309 #define B53_JUMBO_MAX_SIZE_63XX 0x08
310 #define JMS_MIN_SIZE 1518
311 #define JMS_MAX_SIZE 9724
313 #endif /* !__B53_REGS_H */