target/linux/generic/files/drivers/net/phy/ar8216.c

   1 /*
   2  * ar8216.c: AR8216 switch driver
   3  *
   4  * Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
   5  * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License
   9  * as published by the Free Software Foundation; either version 2
  10  * of the License, or (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  */
  17
  18 #include <linux/if.h>
  19 #include <linux/module.h>
  20 #include <linux/init.h>
  21 #include <linux/list.h>
  22 #include <linux/if_ether.h>
  23 #include <linux/skbuff.h>
  24 #include <linux/netdevice.h>
  25 #include <linux/netlink.h>
  26 #include <linux/bitops.h>
  27 #include <net/genetlink.h>
  28 #include <linux/switch.h>
  29 #include <linux/delay.h>
  30 #include <linux/phy.h>
  31 #include <linux/netdevice.h>
  32 #include <linux/etherdevice.h>
  33 #include <linux/lockdep.h>
  34 #include <linux/ar8216_platform.h>
  35 #include <linux/workqueue.h>
  36 #include <linux/version.h>
  37
  38 #include "ar8216.h"
  39
  40 extern const struct ar8xxx_chip ar8327_chip;
  41 extern const struct ar8xxx_chip ar8337_chip;
  42
  43 #define AR8XXX_MIB_WORK_DELAY   2000 /* msecs */
  44
  45 #define MIB_DESC(_s , _o, _n)   \
  46         {                       \
  47                 .size = (_s),   \
  48                 .offset = (_o), \
  49                 .name = (_n),   \
  50         }
  51
  52 static const struct ar8xxx_mib_desc ar8216_mibs[] = {
  53         MIB_DESC(1, AR8216_STATS_RXBROAD, "RxBroad"),
  54         MIB_DESC(1, AR8216_STATS_RXPAUSE, "RxPause"),
  55         MIB_DESC(1, AR8216_STATS_RXMULTI, "RxMulti"),
  56         MIB_DESC(1, AR8216_STATS_RXFCSERR, "RxFcsErr"),
  57         MIB_DESC(1, AR8216_STATS_RXALIGNERR, "RxAlignErr"),
  58         MIB_DESC(1, AR8216_STATS_RXRUNT, "RxRunt"),
  59         MIB_DESC(1, AR8216_STATS_RXFRAGMENT, "RxFragment"),
  60         MIB_DESC(1, AR8216_STATS_RX64BYTE, "Rx64Byte"),
  61         MIB_DESC(1, AR8216_STATS_RX128BYTE, "Rx128Byte"),
  62         MIB_DESC(1, AR8216_STATS_RX256BYTE, "Rx256Byte"),
  63         MIB_DESC(1, AR8216_STATS_RX512BYTE, "Rx512Byte"),
  64         MIB_DESC(1, AR8216_STATS_RX1024BYTE, "Rx1024Byte"),
  65         MIB_DESC(1, AR8216_STATS_RXMAXBYTE, "RxMaxByte"),
  66         MIB_DESC(1, AR8216_STATS_RXTOOLONG, "RxTooLong"),
  67         MIB_DESC(2, AR8216_STATS_RXGOODBYTE, "RxGoodByte"),
  68         MIB_DESC(2, AR8216_STATS_RXBADBYTE, "RxBadByte"),
  69         MIB_DESC(1, AR8216_STATS_RXOVERFLOW, "RxOverFlow"),
  70         MIB_DESC(1, AR8216_STATS_FILTERED, "Filtered"),
  71         MIB_DESC(1, AR8216_STATS_TXBROAD, "TxBroad"),
  72         MIB_DESC(1, AR8216_STATS_TXPAUSE, "TxPause"),
  73         MIB_DESC(1, AR8216_STATS_TXMULTI, "TxMulti"),
  74         MIB_DESC(1, AR8216_STATS_TXUNDERRUN, "TxUnderRun"),
  75         MIB_DESC(1, AR8216_STATS_TX64BYTE, "Tx64Byte"),
  76         MIB_DESC(1, AR8216_STATS_TX128BYTE, "Tx128Byte"),
  77         MIB_DESC(1, AR8216_STATS_TX256BYTE, "Tx256Byte"),
  78         MIB_DESC(1, AR8216_STATS_TX512BYTE, "Tx512Byte"),
  79         MIB_DESC(1, AR8216_STATS_TX1024BYTE, "Tx1024Byte"),
  80         MIB_DESC(1, AR8216_STATS_TXMAXBYTE, "TxMaxByte"),
  81         MIB_DESC(1, AR8216_STATS_TXOVERSIZE, "TxOverSize"),
  82         MIB_DESC(2, AR8216_STATS_TXBYTE, "TxByte"),
  83         MIB_DESC(1, AR8216_STATS_TXCOLLISION, "TxCollision"),
  84         MIB_DESC(1, AR8216_STATS_TXABORTCOL, "TxAbortCol"),
  85         MIB_DESC(1, AR8216_STATS_TXMULTICOL, "TxMultiCol"),
  86         MIB_DESC(1, AR8216_STATS_TXSINGLECOL, "TxSingleCol"),
  87         MIB_DESC(1, AR8216_STATS_TXEXCDEFER, "TxExcDefer"),
  88         MIB_DESC(1, AR8216_STATS_TXDEFER, "TxDefer"),
  89         MIB_DESC(1, AR8216_STATS_TXLATECOL, "TxLateCol"),
  90 };
  91
  92 const struct ar8xxx_mib_desc ar8236_mibs[39] = {
  93         MIB_DESC(1, AR8236_STATS_RXBROAD, "RxBroad"),
  94         MIB_DESC(1, AR8236_STATS_RXPAUSE, "RxPause"),
  95         MIB_DESC(1, AR8236_STATS_RXMULTI, "RxMulti"),
  96         MIB_DESC(1, AR8236_STATS_RXFCSERR, "RxFcsErr"),
  97         MIB_DESC(1, AR8236_STATS_RXALIGNERR, "RxAlignErr"),
  98         MIB_DESC(1, AR8236_STATS_RXRUNT, "RxRunt"),
  99         MIB_DESC(1, AR8236_STATS_RXFRAGMENT, "RxFragment"),
 100         MIB_DESC(1, AR8236_STATS_RX64BYTE, "Rx64Byte"),
 101         MIB_DESC(1, AR8236_STATS_RX128BYTE, "Rx128Byte"),
 102         MIB_DESC(1, AR8236_STATS_RX256BYTE, "Rx256Byte"),
 103         MIB_DESC(1, AR8236_STATS_RX512BYTE, "Rx512Byte"),
 104         MIB_DESC(1, AR8236_STATS_RX1024BYTE, "Rx1024Byte"),
 105         MIB_DESC(1, AR8236_STATS_RX1518BYTE, "Rx1518Byte"),
 106         MIB_DESC(1, AR8236_STATS_RXMAXBYTE, "RxMaxByte"),
 107         MIB_DESC(1, AR8236_STATS_RXTOOLONG, "RxTooLong"),
 108         MIB_DESC(2, AR8236_STATS_RXGOODBYTE, "RxGoodByte"),
 109         MIB_DESC(2, AR8236_STATS_RXBADBYTE, "RxBadByte"),
 110         MIB_DESC(1, AR8236_STATS_RXOVERFLOW, "RxOverFlow"),
 111         MIB_DESC(1, AR8236_STATS_FILTERED, "Filtered"),
 112         MIB_DESC(1, AR8236_STATS_TXBROAD, "TxBroad"),
 113         MIB_DESC(1, AR8236_STATS_TXPAUSE, "TxPause"),
 114         MIB_DESC(1, AR8236_STATS_TXMULTI, "TxMulti"),
 115         MIB_DESC(1, AR8236_STATS_TXUNDERRUN, "TxUnderRun"),
 116         MIB_DESC(1, AR8236_STATS_TX64BYTE, "Tx64Byte"),
 117         MIB_DESC(1, AR8236_STATS_TX128BYTE, "Tx128Byte"),
 118         MIB_DESC(1, AR8236_STATS_TX256BYTE, "Tx256Byte"),
 119         MIB_DESC(1, AR8236_STATS_TX512BYTE, "Tx512Byte"),
 120         MIB_DESC(1, AR8236_STATS_TX1024BYTE, "Tx1024Byte"),
 121         MIB_DESC(1, AR8236_STATS_TX1518BYTE, "Tx1518Byte"),
 122         MIB_DESC(1, AR8236_STATS_TXMAXBYTE, "TxMaxByte"),
 123         MIB_DESC(1, AR8236_STATS_TXOVERSIZE, "TxOverSize"),
 124         MIB_DESC(2, AR8236_STATS_TXBYTE, "TxByte"),
 125         MIB_DESC(1, AR8236_STATS_TXCOLLISION, "TxCollision"),
 126         MIB_DESC(1, AR8236_STATS_TXABORTCOL, "TxAbortCol"),
 127         MIB_DESC(1, AR8236_STATS_TXMULTICOL, "TxMultiCol"),
 128         MIB_DESC(1, AR8236_STATS_TXSINGLECOL, "TxSingleCol"),
 129         MIB_DESC(1, AR8236_STATS_TXEXCDEFER, "TxExcDefer"),
 130         MIB_DESC(1, AR8236_STATS_TXDEFER, "TxDefer"),
 131         MIB_DESC(1, AR8236_STATS_TXLATECOL, "TxLateCol"),
 132 };
 133
 134 static DEFINE_MUTEX(ar8xxx_dev_list_lock);
 135 static LIST_HEAD(ar8xxx_dev_list);
 136
 137 static inline void
 138 split_addr(u32 regaddr, u16 *r1, u16 *r2, u16 *page)
 139 {
 140         regaddr >>= 1;
 141         *r1 = regaddr & 0x1e;
 142
 143         regaddr >>= 5;
 144         *r2 = regaddr & 0x7;
 145
 146         regaddr >>= 3;
 147         *page = regaddr & 0x1ff;
 148 }
 149
 150 /* inspired by phy_poll_reset in drivers/net/phy/phy_device.c */
 151 static int
 152 ar8xxx_phy_poll_reset(struct mii_bus *bus)
 153 {
 154         unsigned int sleep_msecs = 20;
 155         int ret, elapsed, i;
 156
 157         for (elapsed = sleep_msecs; elapsed <= 600;
 158              elapsed += sleep_msecs) {
 159                 msleep(sleep_msecs);
 160                 for (i = 0; i < AR8XXX_NUM_PHYS; i++) {
 161                         ret = mdiobus_read(bus, i, MII_BMCR);
 162                         if (ret < 0)
 163                                 return ret;
 164                         if (ret & BMCR_RESET)
 165                                 break;
 166                         if (i == AR8XXX_NUM_PHYS - 1) {
 167                                 usleep_range(1000, 2000);
 168                                 return 0;
 169                         }
 170                 }
 171         }
 172         return -ETIMEDOUT;
 173 }
 174
 175 static int
 176 ar8xxx_phy_check_aneg(struct phy_device *phydev)
 177 {
 178         int ret;
 179
 180         if (phydev->autoneg != AUTONEG_ENABLE)
 181                 return 0;
 182         /*
 183          * BMCR_ANENABLE might have been cleared
 184          * by phy_init_hw in certain kernel versions
 185          * therefore check for it
 186          */
 187         ret = phy_read(phydev, MII_BMCR);
 188         if (ret < 0)
 189                 return ret;
 190         if (ret & BMCR_ANENABLE)
 191                 return 0;
 192
 193         dev_info(&phydev->dev, "ANEG disabled, re-enabling ...\n");
 194         ret |= BMCR_ANENABLE | BMCR_ANRESTART;
 195         return phy_write(phydev, MII_BMCR, ret);
 196 }
 197
 198 void
 199 ar8xxx_phy_init(struct ar8xxx_priv *priv)
 200 {
 201         int i;
 202         struct mii_bus *bus;
 203
 204         bus = priv->mii_bus;
 205         for (i = 0; i < AR8XXX_NUM_PHYS; i++) {
 206                 if (priv->chip->phy_fixup)
 207                         priv->chip->phy_fixup(priv, i);
 208
 209                 /* initialize the port itself */
 210                 mdiobus_write(bus, i, MII_ADVERTISE,
 211                         ADVERTISE_ALL | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
 212                 if (ar8xxx_has_gige(priv))
 213                         mdiobus_write(bus, i, MII_CTRL1000, ADVERTISE_1000FULL);
 214                 mdiobus_write(bus, i, MII_BMCR, BMCR_RESET | BMCR_ANENABLE);
 215         }
 216
 217         ar8xxx_phy_poll_reset(bus);
 218 }
 219
 220 static u32
 221 mii_read32(struct ar8xxx_priv *priv, int phy_id, int regnum)
 222 {
 223         struct mii_bus *bus = priv->mii_bus;
 224         u16 lo, hi;
 225
 226         lo = bus->read(bus, phy_id, regnum);
 227         hi = bus->read(bus, phy_id, regnum + 1);
 228
 229         return (hi << 16) | lo;
 230 }
 231
 232 static void
 233 mii_write32(struct ar8xxx_priv *priv, int phy_id, int regnum, u32 val)
 234 {
 235         struct mii_bus *bus = priv->mii_bus;
 236         u16 lo, hi;
 237
 238         lo = val & 0xffff;
 239         hi = (u16) (val >> 16);
 240
 241         if (priv->chip->mii_lo_first)
 242         {
 243                 bus->write(bus, phy_id, regnum, lo);
 244                 bus->write(bus, phy_id, regnum + 1, hi);
 245         } else {
 246                 bus->write(bus, phy_id, regnum + 1, hi);
 247                 bus->write(bus, phy_id, regnum, lo);
 248         }
 249 }
 250
 251 u32
 252 ar8xxx_read(struct ar8xxx_priv *priv, int reg)
 253 {
 254         struct mii_bus *bus = priv->mii_bus;
 255         u16 r1, r2, page;
 256         u32 val;
 257
 258         split_addr((u32) reg, &r1, &r2, &page);
 259
 260         mutex_lock(&bus->mdio_lock);
 261
 262         bus->write(bus, 0x18, 0, page);
 263         usleep_range(1000, 2000); /* wait for the page switch to propagate */
 264         val = mii_read32(priv, 0x10 | r2, r1);
 265
 266         mutex_unlock(&bus->mdio_lock);
 267
 268         return val;
 269 }
 270
 271 void
 272 ar8xxx_write(struct ar8xxx_priv *priv, int reg, u32 val)
 273 {
 274         struct mii_bus *bus = priv->mii_bus;
 275         u16 r1, r2, page;
 276
 277         split_addr((u32) reg, &r1, &r2, &page);
 278
 279         mutex_lock(&bus->mdio_lock);
 280
 281         bus->write(bus, 0x18, 0, page);
 282         usleep_range(1000, 2000); /* wait for the page switch to propagate */
 283         mii_write32(priv, 0x10 | r2, r1, val);
 284
 285         mutex_unlock(&bus->mdio_lock);
 286 }
 287
 288 u32
 289 ar8xxx_rmw(struct ar8xxx_priv *priv, int reg, u32 mask, u32 val)
 290 {
 291         struct mii_bus *bus = priv->mii_bus;
 292         u16 r1, r2, page;
 293         u32 ret;
 294
 295         split_addr((u32) reg, &r1, &r2, &page);
 296
 297         mutex_lock(&bus->mdio_lock);
 298
 299         bus->write(bus, 0x18, 0, page);
 300         usleep_range(1000, 2000); /* wait for the page switch to propagate */
 301
 302         ret = mii_read32(priv, 0x10 | r2, r1);
 303         ret &= ~mask;
 304         ret |= val;
 305         mii_write32(priv, 0x10 | r2, r1, ret);
 306
 307         mutex_unlock(&bus->mdio_lock);
 308
 309         return ret;
 310 }
 311
 312 void
 313 ar8xxx_phy_dbg_write(struct ar8xxx_priv *priv, int phy_addr,
 314                      u16 dbg_addr, u16 dbg_data)
 315 {
 316         struct mii_bus *bus = priv->mii_bus;
 317
 318         mutex_lock(&bus->mdio_lock);
 319         bus->write(bus, phy_addr, MII_ATH_DBG_ADDR, dbg_addr);
 320         bus->write(bus, phy_addr, MII_ATH_DBG_DATA, dbg_data);
 321         mutex_unlock(&bus->mdio_lock);
 322 }
 323
 324 void
 325 ar8xxx_phy_mmd_write(struct ar8xxx_priv *priv, int phy_addr, u16 addr, u16 data)
 326 {
 327         struct mii_bus *bus = priv->mii_bus;
 328
 329         mutex_lock(&bus->mdio_lock);
 330         bus->write(bus, phy_addr, MII_ATH_MMD_ADDR, addr);
 331         bus->write(bus, phy_addr, MII_ATH_MMD_DATA, data);
 332         mutex_unlock(&bus->mdio_lock);
 333 }
 334
 335 static int
 336 ar8xxx_reg_wait(struct ar8xxx_priv *priv, u32 reg, u32 mask, u32 val,
 337                 unsigned timeout)
 338 {
 339         int i;
 340
 341         for (i = 0; i < timeout; i++) {
 342                 u32 t;
 343
 344                 t = ar8xxx_read(priv, reg);
 345                 if ((t & mask) == val)
 346                         return 0;
 347
 348                 usleep_range(1000, 2000);
 349         }
 350
 351         return -ETIMEDOUT;
 352 }
 353
 354 static int
 355 ar8xxx_mib_op(struct ar8xxx_priv *priv, u32 op)
 356 {
 357         unsigned mib_func = priv->chip->mib_func;
 358         int ret;
 359
 360         lockdep_assert_held(&priv->mib_lock);
 361
 362         /* Capture the hardware statistics for all ports */
 363         ar8xxx_rmw(priv, mib_func, AR8216_MIB_FUNC, (op << AR8216_MIB_FUNC_S));
 364
 365         /* Wait for the capturing to complete. */
 366         ret = ar8xxx_reg_wait(priv, mib_func, AR8216_MIB_BUSY, 0, 10);
 367         if (ret)
 368                 goto out;
 369
 370         ret = 0;
 371
 372 out:
 373         return ret;
 374 }
 375
 376 static int
 377 ar8xxx_mib_capture(struct ar8xxx_priv *priv)
 378 {
 379         return ar8xxx_mib_op(priv, AR8216_MIB_FUNC_CAPTURE);
 380 }
 381
 382 static int
 383 ar8xxx_mib_flush(struct ar8xxx_priv *priv)
 384 {
 385         return ar8xxx_mib_op(priv, AR8216_MIB_FUNC_FLUSH);
 386 }
 387
 388 static void
 389 ar8xxx_mib_fetch_port_stat(struct ar8xxx_priv *priv, int port, bool flush)
 390 {
 391         unsigned int base;
 392         u64 *mib_stats;
 393         int i;
 394
 395         WARN_ON(port >= priv->dev.ports);
 396
 397         lockdep_assert_held(&priv->mib_lock);
 398
 399         base = priv->chip->reg_port_stats_start +
 400                priv->chip->reg_port_stats_length * port;
 401
 402         mib_stats = &priv->mib_stats[port * priv->chip->num_mibs];
 403         for (i = 0; i < priv->chip->num_mibs; i++) {
 404                 const struct ar8xxx_mib_desc *mib;
 405                 u64 t;
 406
 407                 mib = &priv->chip->mib_decs[i];
 408                 t = ar8xxx_read(priv, base + mib->offset);
 409                 if (mib->size == 2) {
 410                         u64 hi;
 411
 412                         hi = ar8xxx_read(priv, base + mib->offset + 4);
 413                         t |= hi << 32;
 414                 }
 415
 416                 if (flush)
 417                         mib_stats[i] = 0;
 418                 else
 419                         mib_stats[i] += t;
 420         }
 421 }
 422
 423 static void
 424 ar8216_read_port_link(struct ar8xxx_priv *priv, int port,
 425                       struct switch_port_link *link)
 426 {
 427         u32 status;
 428         u32 speed;
 429
 430         memset(link, '\0', sizeof(*link));
 431
 432         status = priv->chip->read_port_status(priv, port);
 433
 434         link->aneg = !!(status & AR8216_PORT_STATUS_LINK_AUTO);
 435         if (link->aneg) {
 436                 link->link = !!(status & AR8216_PORT_STATUS_LINK_UP);
 437         } else {
 438                 link->link = true;
 439
 440                 if (priv->get_port_link) {
 441                         int err;
 442
 443                         err = priv->get_port_link(port);
 444                         if (err >= 0)
 445                                 link->link = !!err;
 446                 }
 447         }
 448
 449         if (!link->link)
 450                 return;
 451
 452         link->duplex = !!(status & AR8216_PORT_STATUS_DUPLEX);
 453         link->tx_flow = !!(status & AR8216_PORT_STATUS_TXFLOW);
 454         link->rx_flow = !!(status & AR8216_PORT_STATUS_RXFLOW);
 455
 456         speed = (status & AR8216_PORT_STATUS_SPEED) >>
 457                  AR8216_PORT_STATUS_SPEED_S;
 458
 459         switch (speed) {
 460         case AR8216_PORT_SPEED_10M:
 461                 link->speed = SWITCH_PORT_SPEED_10;
 462                 break;
 463         case AR8216_PORT_SPEED_100M:
 464                 link->speed = SWITCH_PORT_SPEED_100;
 465                 break;
 466         case AR8216_PORT_SPEED_1000M:
 467                 link->speed = SWITCH_PORT_SPEED_1000;
 468                 break;
 469         default:
 470                 link->speed = SWITCH_PORT_SPEED_UNKNOWN;
 471                 break;
 472         }
 473 }
 474
 475 static struct sk_buff *
 476 ar8216_mangle_tx(struct net_device *dev, struct sk_buff *skb)
 477 {
 478         struct ar8xxx_priv *priv = dev->phy_ptr;
 479         unsigned char *buf;
 480
 481         if (unlikely(!priv))
 482                 goto error;
 483
 484         if (!priv->vlan)
 485                 goto send;
 486
 487         if (unlikely(skb_headroom(skb) < 2)) {
 488                 if (pskb_expand_head(skb, 2, 0, GFP_ATOMIC) < 0)
 489                         goto error;
 490         }
 491
 492         buf = skb_push(skb, 2);
 493         buf[0] = 0x10;
 494         buf[1] = 0x80;
 495
 496 send:
 497         return skb;
 498
 499 error:
 500         dev_kfree_skb_any(skb);
 501         return NULL;
 502 }
 503
 504 static void
 505 ar8216_mangle_rx(struct net_device *dev, struct sk_buff *skb)
 506 {
 507         struct ar8xxx_priv *priv;
 508         unsigned char *buf;
 509         int port, vlan;
 510
 511         priv = dev->phy_ptr;
 512         if (!priv)
 513                 return;
 514
 515         /* don't strip the header if vlan mode is disabled */
 516         if (!priv->vlan)
 517                 return;
 518
 519         /* strip header, get vlan id */
 520         buf = skb->data;
 521         skb_pull(skb, 2);
 522
 523         /* check for vlan header presence */
 524         if ((buf[12 + 2] != 0x81) || (buf[13 + 2] != 0x00))
 525                 return;
 526
 527         port = buf[0] & 0xf;
 528
 529         /* no need to fix up packets coming from a tagged source */
 530         if (priv->vlan_tagged & (1 << port))
 531                 return;
 532
 533         /* lookup port vid from local table, the switch passes an invalid vlan id */
 534         vlan = priv->vlan_id[priv->pvid[port]];
 535
 536         buf[14 + 2] &= 0xf0;
 537         buf[14 + 2] |= vlan >> 8;
 538         buf[15 + 2] = vlan & 0xff;
 539 }
 540
 541 int
 542 ar8216_wait_bit(struct ar8xxx_priv *priv, int reg, u32 mask, u32 val)
 543 {
 544         int timeout = 20;
 545         u32 t = 0;
 546
 547         while (1) {
 548                 t = ar8xxx_read(priv, reg);
 549                 if ((t & mask) == val)
 550                         return 0;
 551
 552                 if (timeout-- <= 0)
 553                         break;
 554
 555                 udelay(10);
 556         }
 557
 558         pr_err("ar8216: timeout on reg %08x: %08x & %08x != %08x\n",
 559                (unsigned int) reg, t, mask, val);
 560         return -ETIMEDOUT;
 561 }
 562
 563 static void
 564 ar8216_vtu_op(struct ar8xxx_priv *priv, u32 op, u32 val)
 565 {
 566         if (ar8216_wait_bit(priv, AR8216_REG_VTU, AR8216_VTU_ACTIVE, 0))
 567                 return;
 568         if ((op & AR8216_VTU_OP) == AR8216_VTU_OP_LOAD) {
 569                 val &= AR8216_VTUDATA_MEMBER;
 570                 val |= AR8216_VTUDATA_VALID;
 571                 ar8xxx_write(priv, AR8216_REG_VTU_DATA, val);
 572         }
 573         op |= AR8216_VTU_ACTIVE;
 574         ar8xxx_write(priv, AR8216_REG_VTU, op);
 575 }
 576
 577 static void
 578 ar8216_vtu_flush(struct ar8xxx_priv *priv)
 579 {
 580         ar8216_vtu_op(priv, AR8216_VTU_OP_FLUSH, 0);
 581 }
 582
 583 static void
 584 ar8216_vtu_load_vlan(struct ar8xxx_priv *priv, u32 vid, u32 port_mask)
 585 {
 586         u32 op;
 587
 588         op = AR8216_VTU_OP_LOAD | (vid << AR8216_VTU_VID_S);
 589         ar8216_vtu_op(priv, op, port_mask);
 590 }
 591
 592 static int
 593 ar8216_atu_flush(struct ar8xxx_priv *priv)
 594 {
 595         int ret;
 596
 597         ret = ar8216_wait_bit(priv, AR8216_REG_ATU, AR8216_ATU_ACTIVE, 0);
 598         if (!ret)
 599                 ar8xxx_write(priv, AR8216_REG_ATU, AR8216_ATU_OP_FLUSH);
 600
 601         return ret;
 602 }
 603
 604 static u32
 605 ar8216_read_port_status(struct ar8xxx_priv *priv, int port)
 606 {
 607         return ar8xxx_read(priv, AR8216_REG_PORT_STATUS(port));
 608 }
 609
 610 static void
 611 ar8216_setup_port(struct ar8xxx_priv *priv, int port, u32 members)
 612 {
 613         u32 header;
 614         u32 egress, ingress;
 615         u32 pvid;
 616
 617         if (priv->vlan) {
 618                 pvid = priv->vlan_id[priv->pvid[port]];
 619                 if (priv->vlan_tagged & (1 << port))
 620                         egress = AR8216_OUT_ADD_VLAN;
 621                 else
 622                         egress = AR8216_OUT_STRIP_VLAN;
 623                 ingress = AR8216_IN_SECURE;
 624         } else {
 625                 pvid = port;
 626                 egress = AR8216_OUT_KEEP;
 627                 ingress = AR8216_IN_PORT_ONLY;
 628         }
 629
 630         if (chip_is_ar8216(priv) && priv->vlan && port == AR8216_PORT_CPU)
 631                 header = AR8216_PORT_CTRL_HEADER;
 632         else
 633                 header = 0;
 634
 635         ar8xxx_rmw(priv, AR8216_REG_PORT_CTRL(port),
 636                    AR8216_PORT_CTRL_LEARN | AR8216_PORT_CTRL_VLAN_MODE |
 637                    AR8216_PORT_CTRL_SINGLE_VLAN | AR8216_PORT_CTRL_STATE |
 638                    AR8216_PORT_CTRL_HEADER | AR8216_PORT_CTRL_LEARN_LOCK,
 639                    AR8216_PORT_CTRL_LEARN | header |
 640                    (egress << AR8216_PORT_CTRL_VLAN_MODE_S) |
 641                    (AR8216_PORT_STATE_FORWARD << AR8216_PORT_CTRL_STATE_S));
 642
 643         ar8xxx_rmw(priv, AR8216_REG_PORT_VLAN(port),
 644                    AR8216_PORT_VLAN_DEST_PORTS | AR8216_PORT_VLAN_MODE |
 645                    AR8216_PORT_VLAN_DEFAULT_ID,
 646                    (members << AR8216_PORT_VLAN_DEST_PORTS_S) |
 647                    (ingress << AR8216_PORT_VLAN_MODE_S) |
 648                    (pvid << AR8216_PORT_VLAN_DEFAULT_ID_S));
 649 }
 650
 651 static int
 652 ar8216_hw_init(struct ar8xxx_priv *priv)
 653 {
 654         if (priv->initialized)
 655                 return 0;
 656
 657         ar8xxx_phy_init(priv);
 658
 659         priv->initialized = true;
 660         return 0;
 661 }
 662
 663 static void
 664 ar8216_init_globals(struct ar8xxx_priv *priv)
 665 {
 666         /* standard atheros magic */
 667         ar8xxx_write(priv, 0x38, 0xc000050e);
 668
 669         ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CTRL,
 670                    AR8216_GCTRL_MTU, 1518 + 8 + 2);
 671 }
 672
 673 static void
 674 ar8216_init_port(struct ar8xxx_priv *priv, int port)
 675 {
 676         /* Enable port learning and tx */
 677         ar8xxx_write(priv, AR8216_REG_PORT_CTRL(port),
 678                 AR8216_PORT_CTRL_LEARN |
 679                 (4 << AR8216_PORT_CTRL_STATE_S));
 680
 681         ar8xxx_write(priv, AR8216_REG_PORT_VLAN(port), 0);
 682
 683         if (port == AR8216_PORT_CPU) {
 684                 ar8xxx_write(priv, AR8216_REG_PORT_STATUS(port),
 685                         AR8216_PORT_STATUS_LINK_UP |
 686                         (ar8xxx_has_gige(priv) ?
 687                                 AR8216_PORT_SPEED_1000M : AR8216_PORT_SPEED_100M) |
 688                         AR8216_PORT_STATUS_TXMAC |
 689                         AR8216_PORT_STATUS_RXMAC |
 690                         (chip_is_ar8316(priv) ? AR8216_PORT_STATUS_RXFLOW : 0) |
 691                         (chip_is_ar8316(priv) ? AR8216_PORT_STATUS_TXFLOW : 0) |
 692                         AR8216_PORT_STATUS_DUPLEX);
 693         } else {
 694                 ar8xxx_write(priv, AR8216_REG_PORT_STATUS(port),
 695                         AR8216_PORT_STATUS_LINK_AUTO);
 696         }
 697 }
 698
 699 static void
 700 ar8236_setup_port(struct ar8xxx_priv *priv, int port, u32 members)
 701 {
 702         u32 egress, ingress;
 703         u32 pvid;
 704
 705         if (priv->vlan) {
 706                 pvid = priv->vlan_id[priv->pvid[port]];
 707                 if (priv->vlan_tagged & (1 << port))
 708                         egress = AR8216_OUT_ADD_VLAN;
 709                 else
 710                         egress = AR8216_OUT_STRIP_VLAN;
 711                 ingress = AR8216_IN_SECURE;
 712         } else {
 713                 pvid = port;
 714                 egress = AR8216_OUT_KEEP;
 715                 ingress = AR8216_IN_PORT_ONLY;
 716         }
 717
 718         ar8xxx_rmw(priv, AR8216_REG_PORT_CTRL(port),
 719                    AR8216_PORT_CTRL_LEARN | AR8216_PORT_CTRL_VLAN_MODE |
 720                    AR8216_PORT_CTRL_SINGLE_VLAN | AR8216_PORT_CTRL_STATE |
 721                    AR8216_PORT_CTRL_HEADER | AR8216_PORT_CTRL_LEARN_LOCK,
 722                    AR8216_PORT_CTRL_LEARN |
 723                    (egress << AR8216_PORT_CTRL_VLAN_MODE_S) |
 724                    (AR8216_PORT_STATE_FORWARD << AR8216_PORT_CTRL_STATE_S));
 725
 726         ar8xxx_rmw(priv, AR8236_REG_PORT_VLAN(port),
 727                    AR8236_PORT_VLAN_DEFAULT_ID,
 728                    (pvid << AR8236_PORT_VLAN_DEFAULT_ID_S));
 729
 730         ar8xxx_rmw(priv, AR8236_REG_PORT_VLAN2(port),
 731                    AR8236_PORT_VLAN2_VLAN_MODE |
 732                    AR8236_PORT_VLAN2_MEMBER,
 733                    (ingress << AR8236_PORT_VLAN2_VLAN_MODE_S) |
 734                    (members << AR8236_PORT_VLAN2_MEMBER_S));
 735 }
 736
 737 static void
 738 ar8236_init_globals(struct ar8xxx_priv *priv)
 739 {
 740         /* enable jumbo frames */
 741         ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CTRL,
 742                    AR8316_GCTRL_MTU, 9018 + 8 + 2);
 743
 744         /* enable cpu port to receive arp frames */
 745         ar8xxx_reg_set(priv, AR8216_REG_ATU_CTRL,
 746                    AR8236_ATU_CTRL_RES);
 747
 748         /* enable cpu port to receive multicast and broadcast frames */
 749         ar8xxx_reg_set(priv, AR8216_REG_FLOOD_MASK,
 750                    AR8236_FM_CPU_BROADCAST_EN | AR8236_FM_CPU_BCAST_FWD_EN);
 751
 752         /* Enable MIB counters */
 753         ar8xxx_rmw(priv, AR8216_REG_MIB_FUNC, AR8216_MIB_FUNC | AR8236_MIB_EN,
 754                    (AR8216_MIB_FUNC_NO_OP << AR8216_MIB_FUNC_S) |
 755                    AR8236_MIB_EN);
 756 }
 757
 758 static int
 759 ar8316_hw_init(struct ar8xxx_priv *priv)
 760 {
 761         u32 val, newval;
 762
 763         val = ar8xxx_read(priv, AR8316_REG_POSTRIP);
 764
 765         if (priv->phy->interface == PHY_INTERFACE_MODE_RGMII) {
 766                 if (priv->port4_phy) {
 767                         /* value taken from Ubiquiti RouterStation Pro */
 768                         newval = 0x81461bea;
 769                         pr_info("ar8316: Using port 4 as PHY\n");
 770                 } else {
 771                         newval = 0x01261be2;
 772                         pr_info("ar8316: Using port 4 as switch port\n");
 773                 }
 774         } else if (priv->phy->interface == PHY_INTERFACE_MODE_GMII) {
 775                 /* value taken from AVM Fritz!Box 7390 sources */
 776                 newval = 0x010e5b71;
 777         } else {
 778                 /* no known value for phy interface */
 779                 pr_err("ar8316: unsupported mii mode: %d.\n",
 780                        priv->phy->interface);
 781                 return -EINVAL;
 782         }
 783
 784         if (val == newval)
 785                 goto out;
 786
 787         ar8xxx_write(priv, AR8316_REG_POSTRIP, newval);
 788
 789         if (priv->port4_phy &&
 790             priv->phy->interface == PHY_INTERFACE_MODE_RGMII) {
 791                 /* work around for phy4 rgmii mode */
 792                 ar8xxx_phy_dbg_write(priv, 4, 0x12, 0x480c);
 793                 /* rx delay */
 794                 ar8xxx_phy_dbg_write(priv, 4, 0x0, 0x824e);
 795                 /* tx delay */
 796                 ar8xxx_phy_dbg_write(priv, 4, 0x5, 0x3d47);
 797                 msleep(1000);
 798         }
 799
 800         ar8xxx_phy_init(priv);
 801
 802 out:
 803         priv->initialized = true;
 804         return 0;
 805 }
 806
 807 static void
 808 ar8316_init_globals(struct ar8xxx_priv *priv)
 809 {
 810         /* standard atheros magic */
 811         ar8xxx_write(priv, 0x38, 0xc000050e);
 812
 813         /* enable cpu port to receive multicast and broadcast frames */
 814         ar8xxx_write(priv, AR8216_REG_FLOOD_MASK, 0x003f003f);
 815
 816         /* enable jumbo frames */
 817         ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CTRL,
 818                    AR8316_GCTRL_MTU, 9018 + 8 + 2);
 819
 820         /* Enable MIB counters */
 821         ar8xxx_rmw(priv, AR8216_REG_MIB_FUNC, AR8216_MIB_FUNC | AR8236_MIB_EN,
 822                    (AR8216_MIB_FUNC_NO_OP << AR8216_MIB_FUNC_S) |
 823                    AR8236_MIB_EN);
 824 }
 825
 826 int
 827 ar8xxx_sw_set_vlan(struct switch_dev *dev, const struct switch_attr *attr,
 828                    struct switch_val *val)
 829 {
 830         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
 831         priv->vlan = !!val->value.i;
 832         return 0;
 833 }
 834
 835 int
 836 ar8xxx_sw_get_vlan(struct switch_dev *dev, const struct switch_attr *attr,
 837                    struct switch_val *val)
 838 {
 839         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
 840         val->value.i = priv->vlan;
 841         return 0;
 842 }
 843
 844
 845 int
 846 ar8xxx_sw_set_pvid(struct switch_dev *dev, int port, int vlan)
 847 {
 848         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
 849
 850         /* make sure no invalid PVIDs get set */
 851
 852         if (vlan >= dev->vlans)
 853                 return -EINVAL;
 854
 855         priv->pvid[port] = vlan;
 856         return 0;
 857 }
 858
 859 int
 860 ar8xxx_sw_get_pvid(struct switch_dev *dev, int port, int *vlan)
 861 {
 862         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
 863         *vlan = priv->pvid[port];
 864         return 0;
 865 }
 866
 867 static int
 868 ar8xxx_sw_set_vid(struct switch_dev *dev, const struct switch_attr *attr,
 869                   struct switch_val *val)
 870 {
 871         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
 872         priv->vlan_id[val->port_vlan] = val->value.i;
 873         return 0;
 874 }
 875
 876 static int
 877 ar8xxx_sw_get_vid(struct switch_dev *dev, const struct switch_attr *attr,
 878                   struct switch_val *val)
 879 {
 880         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
 881         val->value.i = priv->vlan_id[val->port_vlan];
 882         return 0;
 883 }
 884
 885 int
 886 ar8xxx_sw_get_port_link(struct switch_dev *dev, int port,
 887                         struct switch_port_link *link)
 888 {
 889         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
 890
 891         ar8216_read_port_link(priv, port, link);
 892         return 0;
 893 }
 894
 895 static int
 896 ar8xxx_sw_get_ports(struct switch_dev *dev, struct switch_val *val)
 897 {
 898         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
 899         u8 ports = priv->vlan_table[val->port_vlan];
 900         int i;
 901
 902         val->len = 0;
 903         for (i = 0; i < dev->ports; i++) {
 904                 struct switch_port *p;
 905
 906                 if (!(ports & (1 << i)))
 907                         continue;
 908
 909                 p = &val->value.ports[val->len++];
 910                 p->id = i;
 911                 if (priv->vlan_tagged & (1 << i))
 912                         p->flags = (1 << SWITCH_PORT_FLAG_TAGGED);
 913                 else
 914                         p->flags = 0;
 915         }
 916         return 0;
 917 }
 918
 919 static int
 920 ar8xxx_sw_set_ports(struct switch_dev *dev, struct switch_val *val)
 921 {
 922         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
 923         u8 *vt = &priv->vlan_table[val->port_vlan];
 924         int i, j;
 925
 926         *vt = 0;
 927         for (i = 0; i < val->len; i++) {
 928                 struct switch_port *p = &val->value.ports[i];
 929
 930                 if (p->flags & (1 << SWITCH_PORT_FLAG_TAGGED)) {
 931                         priv->vlan_tagged |= (1 << p->id);
 932                 } else {
 933                         priv->vlan_tagged &= ~(1 << p->id);
 934                         priv->pvid[p->id] = val->port_vlan;
 935
 936                         /* make sure that an untagged port does not
 937                          * appear in other vlans */
 938                         for (j = 0; j < AR8X16_MAX_VLANS; j++) {
 939                                 if (j == val->port_vlan)
 940                                         continue;
 941                                 priv->vlan_table[j] &= ~(1 << p->id);
 942                         }
 943                 }
 944
 945                 *vt |= 1 << p->id;
 946         }
 947         return 0;
 948 }
 949
 950 static void
 951 ar8216_set_mirror_regs(struct ar8xxx_priv *priv)
 952 {
 953         int port;
 954
 955         /* reset all mirror registers */
 956         ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CPUPORT,
 957                    AR8216_GLOBAL_CPUPORT_MIRROR_PORT,
 958                    (0xF << AR8216_GLOBAL_CPUPORT_MIRROR_PORT_S));
 959         for (port = 0; port < AR8216_NUM_PORTS; port++) {
 960                 ar8xxx_reg_clear(priv, AR8216_REG_PORT_CTRL(port),
 961                            AR8216_PORT_CTRL_MIRROR_RX);
 962
 963                 ar8xxx_reg_clear(priv, AR8216_REG_PORT_CTRL(port),
 964                            AR8216_PORT_CTRL_MIRROR_TX);
 965         }
 966
 967         /* now enable mirroring if necessary */
 968         if (priv->source_port >= AR8216_NUM_PORTS ||
 969             priv->monitor_port >= AR8216_NUM_PORTS ||
 970             priv->source_port == priv->monitor_port) {
 971                 return;
 972         }
 973
 974         ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CPUPORT,
 975                    AR8216_GLOBAL_CPUPORT_MIRROR_PORT,
 976                    (priv->monitor_port << AR8216_GLOBAL_CPUPORT_MIRROR_PORT_S));
 977
 978         if (priv->mirror_rx)
 979                 ar8xxx_reg_set(priv, AR8216_REG_PORT_CTRL(priv->source_port),
 980                            AR8216_PORT_CTRL_MIRROR_RX);
 981
 982         if (priv->mirror_tx)
 983                 ar8xxx_reg_set(priv, AR8216_REG_PORT_CTRL(priv->source_port),
 984                            AR8216_PORT_CTRL_MIRROR_TX);
 985 }
 986
 987 int
 988 ar8xxx_sw_hw_apply(struct switch_dev *dev)
 989 {
 990         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
 991         u8 portmask[AR8X16_MAX_PORTS];
 992         int i, j;
 993
 994         mutex_lock(&priv->reg_mutex);
 995         /* flush all vlan translation unit entries */
 996         priv->chip->vtu_flush(priv);
 997
 998         memset(portmask, 0, sizeof(portmask));
 999         if (!priv->init) {
1000                 /* calculate the port destination masks and load vlans
1001                  * into the vlan translation unit */
1002                 for (j = 0; j < AR8X16_MAX_VLANS; j++) {
1003                         u8 vp = priv->vlan_table[j];
1004
1005                         if (!vp)
1006                                 continue;
1007
1008                         for (i = 0; i < dev->ports; i++) {
1009                                 u8 mask = (1 << i);
1010                                 if (vp & mask)
1011                                         portmask[i] |= vp & ~mask;
1012                         }
1013
1014                         priv->chip->vtu_load_vlan(priv, priv->vlan_id[j],
1015                                                  priv->vlan_table[j]);
1016                 }
1017         } else {
1018                 /* vlan disabled:
1019                  * isolate all ports, but connect them to the cpu port */
1020                 for (i = 0; i < dev->ports; i++) {
1021                         if (i == AR8216_PORT_CPU)
1022                                 continue;
1023
1024                         portmask[i] = 1 << AR8216_PORT_CPU;
1025                         portmask[AR8216_PORT_CPU] |= (1 << i);
1026                 }
1027         }
1028
1029         /* update the port destination mask registers and tag settings */
1030         for (i = 0; i < dev->ports; i++) {
1031                 priv->chip->setup_port(priv, i, portmask[i]);
1032         }
1033
1034         priv->chip->set_mirror_regs(priv);
1035
1036         mutex_unlock(&priv->reg_mutex);
1037         return 0;
1038 }
1039
1040 int
1041 ar8xxx_sw_reset_switch(struct switch_dev *dev)
1042 {
1043         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1044         int i;
1045
1046         mutex_lock(&priv->reg_mutex);
1047         memset(&priv->vlan, 0, sizeof(struct ar8xxx_priv) -
1048                 offsetof(struct ar8xxx_priv, vlan));
1049
1050         for (i = 0; i < AR8X16_MAX_VLANS; i++)
1051                 priv->vlan_id[i] = i;
1052
1053         /* Configure all ports */
1054         for (i = 0; i < dev->ports; i++)
1055                 priv->chip->init_port(priv, i);
1056
1057         priv->mirror_rx = false;
1058         priv->mirror_tx = false;
1059         priv->source_port = 0;
1060         priv->monitor_port = 0;
1061
1062         priv->chip->init_globals(priv);
1063
1064         mutex_unlock(&priv->reg_mutex);
1065
1066         return ar8xxx_sw_hw_apply(dev);
1067 }
1068
1069 int
1070 ar8xxx_sw_set_reset_mibs(struct switch_dev *dev,
1071                          const struct switch_attr *attr,
1072                          struct switch_val *val)
1073 {
1074         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1075         unsigned int len;
1076         int ret;
1077
1078         if (!ar8xxx_has_mib_counters(priv))
1079                 return -EOPNOTSUPP;
1080
1081         mutex_lock(&priv->mib_lock);
1082
1083         len = priv->dev.ports * priv->chip->num_mibs *
1084               sizeof(*priv->mib_stats);
1085         memset(priv->mib_stats, '\0', len);
1086         ret = ar8xxx_mib_flush(priv);
1087         if (ret)
1088                 goto unlock;
1089
1090         ret = 0;
1091
1092 unlock:
1093         mutex_unlock(&priv->mib_lock);
1094         return ret;
1095 }
1096
1097 int
1098 ar8xxx_sw_set_mirror_rx_enable(struct switch_dev *dev,
1099                                const struct switch_attr *attr,
1100                                struct switch_val *val)
1101 {
1102         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1103
1104         mutex_lock(&priv->reg_mutex);
1105         priv->mirror_rx = !!val->value.i;
1106         priv->chip->set_mirror_regs(priv);
1107         mutex_unlock(&priv->reg_mutex);
1108
1109         return 0;
1110 }
1111
1112 int
1113 ar8xxx_sw_get_mirror_rx_enable(struct switch_dev *dev,
1114                                const struct switch_attr *attr,
1115                                struct switch_val *val)
1116 {
1117         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1118         val->value.i = priv->mirror_rx;
1119         return 0;
1120 }
1121
1122 int
1123 ar8xxx_sw_set_mirror_tx_enable(struct switch_dev *dev,
1124                                const struct switch_attr *attr,
1125                                struct switch_val *val)
1126 {
1127         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1128
1129         mutex_lock(&priv->reg_mutex);
1130         priv->mirror_tx = !!val->value.i;
1131         priv->chip->set_mirror_regs(priv);
1132         mutex_unlock(&priv->reg_mutex);
1133
1134         return 0;
1135 }
1136
1137 int
1138 ar8xxx_sw_get_mirror_tx_enable(struct switch_dev *dev,
1139                                const struct switch_attr *attr,
1140                                struct switch_val *val)
1141 {
1142         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1143         val->value.i = priv->mirror_tx;
1144         return 0;
1145 }
1146
1147 int
1148 ar8xxx_sw_set_mirror_monitor_port(struct switch_dev *dev,
1149                                   const struct switch_attr *attr,
1150                                   struct switch_val *val)
1151 {
1152         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1153
1154         mutex_lock(&priv->reg_mutex);
1155         priv->monitor_port = val->value.i;
1156         priv->chip->set_mirror_regs(priv);
1157         mutex_unlock(&priv->reg_mutex);
1158
1159         return 0;
1160 }
1161
1162 int
1163 ar8xxx_sw_get_mirror_monitor_port(struct switch_dev *dev,
1164                                   const struct switch_attr *attr,
1165                                   struct switch_val *val)
1166 {
1167         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1168         val->value.i = priv->monitor_port;
1169         return 0;
1170 }
1171
1172 int
1173 ar8xxx_sw_set_mirror_source_port(struct switch_dev *dev,
1174                                  const struct switch_attr *attr,
1175                                  struct switch_val *val)
1176 {
1177         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1178
1179         mutex_lock(&priv->reg_mutex);
1180         priv->source_port = val->value.i;
1181         priv->chip->set_mirror_regs(priv);
1182         mutex_unlock(&priv->reg_mutex);
1183
1184         return 0;
1185 }
1186
1187 int
1188 ar8xxx_sw_get_mirror_source_port(struct switch_dev *dev,
1189                                  const struct switch_attr *attr,
1190                                  struct switch_val *val)
1191 {
1192         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1193         val->value.i = priv->source_port;
1194         return 0;
1195 }
1196
1197 static int
1198 ar8xxx_sw_set_port_reset_mib(struct switch_dev *dev,
1199                              const struct switch_attr *attr,
1200                              struct switch_val *val)
1201 {
1202         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1203         int port;
1204         int ret;
1205
1206         if (!ar8xxx_has_mib_counters(priv))
1207                 return -EOPNOTSUPP;
1208
1209         port = val->port_vlan;
1210         if (port >= dev->ports)
1211                 return -EINVAL;
1212
1213         mutex_lock(&priv->mib_lock);
1214         ret = ar8xxx_mib_capture(priv);
1215         if (ret)
1216                 goto unlock;
1217
1218         ar8xxx_mib_fetch_port_stat(priv, port, true);
1219
1220         ret = 0;
1221
1222 unlock:
1223         mutex_unlock(&priv->mib_lock);
1224         return ret;
1225 }
1226
1227 static int
1228 ar8xxx_sw_get_port_mib(struct switch_dev *dev,
1229                        const struct switch_attr *attr,
1230                        struct switch_val *val)
1231 {
1232         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1233         const struct ar8xxx_chip *chip = priv->chip;
1234         u64 *mib_stats;
1235         int port;
1236         int ret;
1237         char *buf = priv->buf;
1238         int i, len = 0;
1239
1240         if (!ar8xxx_has_mib_counters(priv))
1241                 return -EOPNOTSUPP;
1242
1243         port = val->port_vlan;
1244         if (port >= dev->ports)
1245                 return -EINVAL;
1246
1247         mutex_lock(&priv->mib_lock);
1248         ret = ar8xxx_mib_capture(priv);
1249         if (ret)
1250                 goto unlock;
1251
1252         ar8xxx_mib_fetch_port_stat(priv, port, false);
1253
1254         len += snprintf(buf + len, sizeof(priv->buf) - len,
1255                         "Port %d MIB counters\n",
1256                         port);
1257
1258         mib_stats = &priv->mib_stats[port * chip->num_mibs];
1259         for (i = 0; i < chip->num_mibs; i++)
1260                 len += snprintf(buf + len, sizeof(priv->buf) - len,
1261                                 "%-12s: %llu\n",
1262                                 chip->mib_decs[i].name,
1263                                 mib_stats[i]);
1264
1265         val->value.s = buf;
1266         val->len = len;
1267
1268         ret = 0;
1269
1270 unlock:
1271         mutex_unlock(&priv->mib_lock);
1272         return ret;
1273 }
1274
1275 static const struct switch_attr ar8xxx_sw_attr_globals[] = {
1276         {
1277                 .type = SWITCH_TYPE_INT,
1278                 .name = "enable_vlan",
1279                 .description = "Enable VLAN mode",
1280                 .set = ar8xxx_sw_set_vlan,
1281                 .get = ar8xxx_sw_get_vlan,
1282                 .max = 1
1283         },
1284         {
1285                 .type = SWITCH_TYPE_NOVAL,
1286                 .name = "reset_mibs",
1287                 .description = "Reset all MIB counters",
1288                 .set = ar8xxx_sw_set_reset_mibs,
1289         },
1290         {
1291                 .type = SWITCH_TYPE_INT,
1292                 .name = "enable_mirror_rx",
1293                 .description = "Enable mirroring of RX packets",
1294                 .set = ar8xxx_sw_set_mirror_rx_enable,
1295                 .get = ar8xxx_sw_get_mirror_rx_enable,
1296                 .max = 1
1297         },
1298         {
1299                 .type = SWITCH_TYPE_INT,
1300                 .name = "enable_mirror_tx",
1301                 .description = "Enable mirroring of TX packets",
1302                 .set = ar8xxx_sw_set_mirror_tx_enable,
1303                 .get = ar8xxx_sw_get_mirror_tx_enable,
1304                 .max = 1
1305         },
1306         {
1307                 .type = SWITCH_TYPE_INT,
1308                 .name = "mirror_monitor_port",
1309                 .description = "Mirror monitor port",
1310                 .set = ar8xxx_sw_set_mirror_monitor_port,
1311                 .get = ar8xxx_sw_get_mirror_monitor_port,
1312                 .max = AR8216_NUM_PORTS - 1
1313         },
1314         {
1315                 .type = SWITCH_TYPE_INT,
1316                 .name = "mirror_source_port",
1317                 .description = "Mirror source port",
1318                 .set = ar8xxx_sw_set_mirror_source_port,
1319                 .get = ar8xxx_sw_get_mirror_source_port,
1320                 .max = AR8216_NUM_PORTS - 1
1321         },
1322 };
1323
1324 const struct switch_attr ar8xxx_sw_attr_port[2] = {
1325         {
1326                 .type = SWITCH_TYPE_NOVAL,
1327                 .name = "reset_mib",
1328                 .description = "Reset single port MIB counters",
1329                 .set = ar8xxx_sw_set_port_reset_mib,
1330         },
1331         {
1332                 .type = SWITCH_TYPE_STRING,
1333                 .name = "mib",
1334                 .description = "Get port's MIB counters",
1335                 .set = NULL,
1336                 .get = ar8xxx_sw_get_port_mib,
1337         },
1338 };
1339
1340 const struct switch_attr ar8xxx_sw_attr_vlan[1] = {
1341         {
1342                 .type = SWITCH_TYPE_INT,
1343                 .name = "vid",
1344                 .description = "VLAN ID (0-4094)",
1345                 .set = ar8xxx_sw_set_vid,
1346                 .get = ar8xxx_sw_get_vid,
1347                 .max = 4094,
1348         },
1349 };
1350
1351 static const struct switch_dev_ops ar8xxx_sw_ops = {
1352         .attr_global = {
1353                 .attr = ar8xxx_sw_attr_globals,
1354                 .n_attr = ARRAY_SIZE(ar8xxx_sw_attr_globals),
1355         },
1356         .attr_port = {
1357                 .attr = ar8xxx_sw_attr_port,
1358                 .n_attr = ARRAY_SIZE(ar8xxx_sw_attr_port),
1359         },
1360         .attr_vlan = {
1361                 .attr = ar8xxx_sw_attr_vlan,
1362                 .n_attr = ARRAY_SIZE(ar8xxx_sw_attr_vlan),
1363         },
1364         .get_port_pvid = ar8xxx_sw_get_pvid,
1365         .set_port_pvid = ar8xxx_sw_set_pvid,
1366         .get_vlan_ports = ar8xxx_sw_get_ports,
1367         .set_vlan_ports = ar8xxx_sw_set_ports,
1368         .apply_config = ar8xxx_sw_hw_apply,
1369         .reset_switch = ar8xxx_sw_reset_switch,
1370         .get_port_link = ar8xxx_sw_get_port_link,
1371 };
1372
1373 static const struct ar8xxx_chip ar8216_chip = {
1374         .caps = AR8XXX_CAP_MIB_COUNTERS,
1375
1376         .reg_port_stats_start = 0x19000,
1377         .reg_port_stats_length = 0xa0,
1378
1379         .name = "Atheros AR8216",
1380         .ports = AR8216_NUM_PORTS,
1381         .vlans = AR8216_NUM_VLANS,
1382         .swops = &ar8xxx_sw_ops,
1383
1384         .hw_init = ar8216_hw_init,
1385         .init_globals = ar8216_init_globals,
1386         .init_port = ar8216_init_port,
1387         .setup_port = ar8216_setup_port,
1388         .read_port_status = ar8216_read_port_status,
1389         .atu_flush = ar8216_atu_flush,
1390         .vtu_flush = ar8216_vtu_flush,
1391         .vtu_load_vlan = ar8216_vtu_load_vlan,
1392         .set_mirror_regs = ar8216_set_mirror_regs,
1393
1394         .num_mibs = ARRAY_SIZE(ar8216_mibs),
1395         .mib_decs = ar8216_mibs,
1396         .mib_func = AR8216_REG_MIB_FUNC
1397 };
1398
1399 static const struct ar8xxx_chip ar8236_chip = {
1400         .caps = AR8XXX_CAP_MIB_COUNTERS,
1401
1402         .reg_port_stats_start = 0x20000,
1403         .reg_port_stats_length = 0x100,
1404
1405         .name = "Atheros AR8236",
1406         .ports = AR8216_NUM_PORTS,
1407         .vlans = AR8216_NUM_VLANS,
1408         .swops = &ar8xxx_sw_ops,
1409
1410         .hw_init = ar8216_hw_init,
1411         .init_globals = ar8236_init_globals,
1412         .init_port = ar8216_init_port,
1413         .setup_port = ar8236_setup_port,
1414         .read_port_status = ar8216_read_port_status,
1415         .atu_flush = ar8216_atu_flush,
1416         .vtu_flush = ar8216_vtu_flush,
1417         .vtu_load_vlan = ar8216_vtu_load_vlan,
1418         .set_mirror_regs = ar8216_set_mirror_regs,
1419
1420         .num_mibs = ARRAY_SIZE(ar8236_mibs),
1421         .mib_decs = ar8236_mibs,
1422         .mib_func = AR8216_REG_MIB_FUNC
1423 };
1424
1425 static const struct ar8xxx_chip ar8316_chip = {
1426         .caps = AR8XXX_CAP_GIGE | AR8XXX_CAP_MIB_COUNTERS,
1427
1428         .reg_port_stats_start = 0x20000,
1429         .reg_port_stats_length = 0x100,
1430
1431         .name = "Atheros AR8316",
1432         .ports = AR8216_NUM_PORTS,
1433         .vlans = AR8X16_MAX_VLANS,
1434         .swops = &ar8xxx_sw_ops,
1435
1436         .hw_init = ar8316_hw_init,
1437         .init_globals = ar8316_init_globals,
1438         .init_port = ar8216_init_port,
1439         .setup_port = ar8216_setup_port,
1440         .read_port_status = ar8216_read_port_status,
1441         .atu_flush = ar8216_atu_flush,
1442         .vtu_flush = ar8216_vtu_flush,
1443         .vtu_load_vlan = ar8216_vtu_load_vlan,
1444         .set_mirror_regs = ar8216_set_mirror_regs,
1445
1446         .num_mibs = ARRAY_SIZE(ar8236_mibs),
1447         .mib_decs = ar8236_mibs,
1448         .mib_func = AR8216_REG_MIB_FUNC
1449 };
1450
1451 static int
1452 ar8xxx_id_chip(struct ar8xxx_priv *priv)
1453 {
1454         u32 val;
1455         u16 id;
1456         int i;
1457
1458         val = ar8xxx_read(priv, AR8216_REG_CTRL);
1459         if (val == ~0)
1460                 return -ENODEV;
1461
1462         id = val & (AR8216_CTRL_REVISION | AR8216_CTRL_VERSION);
1463         for (i = 0; i < AR8X16_PROBE_RETRIES; i++) {
1464                 u16 t;
1465
1466                 val = ar8xxx_read(priv, AR8216_REG_CTRL);
1467                 if (val == ~0)
1468                         return -ENODEV;
1469
1470                 t = val & (AR8216_CTRL_REVISION | AR8216_CTRL_VERSION);
1471                 if (t != id)
1472                         return -ENODEV;
1473         }
1474
1475         priv->chip_ver = (id & AR8216_CTRL_VERSION) >> AR8216_CTRL_VERSION_S;
1476         priv->chip_rev = (id & AR8216_CTRL_REVISION);
1477
1478         switch (priv->chip_ver) {
1479         case AR8XXX_VER_AR8216:
1480                 priv->chip = &ar8216_chip;
1481                 break;
1482         case AR8XXX_VER_AR8236:
1483                 priv->chip = &ar8236_chip;
1484                 break;
1485         case AR8XXX_VER_AR8316:
1486                 priv->chip = &ar8316_chip;
1487                 break;
1488         case AR8XXX_VER_AR8327:
1489                 priv->chip = &ar8327_chip;
1490                 break;
1491         case AR8XXX_VER_AR8337:
1492                 priv->chip = &ar8337_chip;
1493                 break;
1494         default:
1495                 pr_err("ar8216: Unknown Atheros device [ver=%d, rev=%d]\n",
1496                        priv->chip_ver, priv->chip_rev);
1497
1498                 return -ENODEV;
1499         }
1500
1501         return 0;
1502 }
1503
1504 static void
1505 ar8xxx_mib_work_func(struct work_struct *work)
1506 {
1507         struct ar8xxx_priv *priv;
1508         int err;
1509
1510         priv = container_of(work, struct ar8xxx_priv, mib_work.work);
1511
1512         mutex_lock(&priv->mib_lock);
1513
1514         err = ar8xxx_mib_capture(priv);
1515         if (err)
1516                 goto next_port;
1517
1518         ar8xxx_mib_fetch_port_stat(priv, priv->mib_next_port, false);
1519
1520 next_port:
1521         priv->mib_next_port++;
1522         if (priv->mib_next_port >= priv->dev.ports)
1523                 priv->mib_next_port = 0;
1524
1525         mutex_unlock(&priv->mib_lock);
1526         schedule_delayed_work(&priv->mib_work,
1527                               msecs_to_jiffies(AR8XXX_MIB_WORK_DELAY));
1528 }
1529
1530 static int
1531 ar8xxx_mib_init(struct ar8xxx_priv *priv)
1532 {
1533         unsigned int len;
1534
1535         if (!ar8xxx_has_mib_counters(priv))
1536                 return 0;
1537
1538         BUG_ON(!priv->chip->mib_decs || !priv->chip->num_mibs);
1539
1540         len = priv->dev.ports * priv->chip->num_mibs *
1541               sizeof(*priv->mib_stats);
1542         priv->mib_stats = kzalloc(len, GFP_KERNEL);
1543
1544         if (!priv->mib_stats)
1545                 return -ENOMEM;
1546
1547         return 0;
1548 }
1549
1550 static void
1551 ar8xxx_mib_start(struct ar8xxx_priv *priv)
1552 {
1553         if (!ar8xxx_has_mib_counters(priv))
1554                 return;
1555
1556         schedule_delayed_work(&priv->mib_work,
1557                               msecs_to_jiffies(AR8XXX_MIB_WORK_DELAY));
1558 }
1559
1560 static void
1561 ar8xxx_mib_stop(struct ar8xxx_priv *priv)
1562 {
1563         if (!ar8xxx_has_mib_counters(priv))
1564                 return;
1565
1566         cancel_delayed_work(&priv->mib_work);
1567 }
1568
1569 static struct ar8xxx_priv *
1570 ar8xxx_create(void)
1571 {
1572         struct ar8xxx_priv *priv;
1573
1574         priv = kzalloc(sizeof(struct ar8xxx_priv), GFP_KERNEL);
1575         if (priv == NULL)
1576                 return NULL;
1577
1578         mutex_init(&priv->reg_mutex);
1579         mutex_init(&priv->mib_lock);
1580         INIT_DELAYED_WORK(&priv->mib_work, ar8xxx_mib_work_func);
1581
1582         return priv;
1583 }
1584
1585 static void
1586 ar8xxx_free(struct ar8xxx_priv *priv)
1587 {
1588         if (priv->chip && priv->chip->cleanup)
1589                 priv->chip->cleanup(priv);
1590
1591         kfree(priv->chip_data);
1592         kfree(priv->mib_stats);
1593         kfree(priv);
1594 }
1595
1596 static int
1597 ar8xxx_probe_switch(struct ar8xxx_priv *priv)
1598 {
1599         const struct ar8xxx_chip *chip;
1600         struct switch_dev *swdev;
1601         int ret;
1602
1603         ret = ar8xxx_id_chip(priv);
1604         if (ret)
1605                 return ret;
1606
1607         chip = priv->chip;
1608
1609         swdev = &priv->dev;
1610         swdev->cpu_port = AR8216_PORT_CPU;
1611         swdev->name = chip->name;
1612         swdev->vlans = chip->vlans;
1613         swdev->ports = chip->ports;
1614         swdev->ops = chip->swops;
1615
1616         ret = ar8xxx_mib_init(priv);
1617         if (ret)
1618                 return ret;
1619
1620         return 0;
1621 }
1622
1623 static int
1624 ar8xxx_start(struct ar8xxx_priv *priv)
1625 {
1626         int ret;
1627
1628         priv->init = true;
1629
1630         ret = priv->chip->hw_init(priv);
1631         if (ret)
1632                 return ret;
1633
1634         ret = ar8xxx_sw_reset_switch(&priv->dev);
1635         if (ret)
1636                 return ret;
1637
1638         priv->init = false;
1639
1640         ar8xxx_mib_start(priv);
1641
1642         return 0;
1643 }
1644
1645 static int
1646 ar8xxx_phy_config_init(struct phy_device *phydev)
1647 {
1648         struct ar8xxx_priv *priv = phydev->priv;
1649         struct net_device *dev = phydev->attached_dev;
1650         int ret;
1651
1652         if (WARN_ON(!priv))
1653                 return -ENODEV;
1654
1655         if (priv->chip->config_at_probe)
1656                 return ar8xxx_phy_check_aneg(phydev);
1657
1658         priv->phy = phydev;
1659
1660         if (phydev->addr != 0) {
1661                 if (chip_is_ar8316(priv)) {
1662                         /* switch device has been initialized, reinit */
1663                         priv->dev.ports = (AR8216_NUM_PORTS - 1);
1664                         priv->initialized = false;
1665                         priv->port4_phy = true;
1666                         ar8316_hw_init(priv);
1667                         return 0;
1668                 }
1669
1670                 return 0;
1671         }
1672
1673         ret = ar8xxx_start(priv);
1674         if (ret)
1675                 return ret;
1676
1677         /* VID fixup only needed on ar8216 */
1678         if (chip_is_ar8216(priv)) {
1679                 dev->phy_ptr = priv;
1680                 dev->priv_flags |= IFF_NO_IP_ALIGN;
1681                 dev->eth_mangle_rx = ar8216_mangle_rx;
1682                 dev->eth_mangle_tx = ar8216_mangle_tx;
1683         }
1684
1685         return 0;
1686 }
1687
1688 static int
1689 ar8xxx_phy_read_status(struct phy_device *phydev)
1690 {
1691         struct ar8xxx_priv *priv = phydev->priv;
1692         struct switch_port_link link;
1693         int ret;
1694
1695         if (phydev->addr != 0)
1696                 return genphy_read_status(phydev);
1697
1698         ar8216_read_port_link(priv, phydev->addr, &link);
1699         phydev->link = !!link.link;
1700         if (!phydev->link)
1701                 return 0;
1702
1703         switch (link.speed) {
1704         case SWITCH_PORT_SPEED_10:
1705                 phydev->speed = SPEED_10;
1706                 break;
1707         case SWITCH_PORT_SPEED_100:
1708                 phydev->speed = SPEED_100;
1709                 break;
1710         case SWITCH_PORT_SPEED_1000:
1711                 phydev->speed = SPEED_1000;
1712                 break;
1713         default:
1714                 phydev->speed = 0;
1715         }
1716         phydev->duplex = link.duplex ? DUPLEX_FULL : DUPLEX_HALF;
1717
1718         /* flush the address translation unit */
1719         mutex_lock(&priv->reg_mutex);
1720         ret = priv->chip->atu_flush(priv);
1721         mutex_unlock(&priv->reg_mutex);
1722
1723         phydev->state = PHY_RUNNING;
1724         netif_carrier_on(phydev->attached_dev);
1725         phydev->adjust_link(phydev->attached_dev);
1726
1727         return ret;
1728 }
1729
1730 static int
1731 ar8xxx_phy_config_aneg(struct phy_device *phydev)
1732 {
1733         if (phydev->addr == 0)
1734                 return 0;
1735
1736         return genphy_config_aneg(phydev);
1737 }
1738
1739 static const u32 ar8xxx_phy_ids[] = {
1740         0x004dd033,
1741         0x004dd034, /* AR8327 */
1742         0x004dd036, /* AR8337 */
1743         0x004dd041,
1744         0x004dd042,
1745         0x004dd043, /* AR8236 */
1746 };
1747
1748 static bool
1749 ar8xxx_phy_match(u32 phy_id)
1750 {
1751         int i;
1752
1753         for (i = 0; i < ARRAY_SIZE(ar8xxx_phy_ids); i++)
1754                 if (phy_id == ar8xxx_phy_ids[i])
1755                         return true;
1756
1757         return false;
1758 }
1759
1760 static bool
1761 ar8xxx_is_possible(struct mii_bus *bus)
1762 {
1763         unsigned i;
1764
1765         for (i = 0; i < 4; i++) {
1766                 u32 phy_id;
1767
1768                 phy_id = mdiobus_read(bus, i, MII_PHYSID1) << 16;
1769                 phy_id |= mdiobus_read(bus, i, MII_PHYSID2);
1770                 if (!ar8xxx_phy_match(phy_id)) {
1771                         pr_debug("ar8xxx: unknown PHY at %s:%02x id:%08x\n",
1772                                  dev_name(&bus->dev), i, phy_id);
1773                         return false;
1774                 }
1775         }
1776
1777         return true;
1778 }
1779
1780 static int
1781 ar8xxx_phy_probe(struct phy_device *phydev)
1782 {
1783         struct ar8xxx_priv *priv;
1784         struct switch_dev *swdev;
1785         int ret;
1786
1787         /* skip PHYs at unused adresses */
1788         if (phydev->addr != 0 && phydev->addr != 4)
1789                 return -ENODEV;
1790
1791         if (!ar8xxx_is_possible(phydev->bus))
1792                 return -ENODEV;
1793
1794         mutex_lock(&ar8xxx_dev_list_lock);
1795         list_for_each_entry(priv, &ar8xxx_dev_list, list)
1796                 if (priv->mii_bus == phydev->bus)
1797                         goto found;
1798
1799         priv = ar8xxx_create();
1800         if (priv == NULL) {
1801                 ret = -ENOMEM;
1802                 goto unlock;
1803         }
1804
1805         priv->mii_bus = phydev->bus;
1806
1807         ret = ar8xxx_probe_switch(priv);
1808         if (ret)
1809                 goto free_priv;
1810
1811         swdev = &priv->dev;
1812         swdev->alias = dev_name(&priv->mii_bus->dev);
1813         ret = register_switch(swdev, NULL);
1814         if (ret)
1815                 goto free_priv;
1816
1817         pr_info("%s: %s rev. %u switch registered on %s\n",
1818                 swdev->devname, swdev->name, priv->chip_rev,
1819                 dev_name(&priv->mii_bus->dev));
1820
1821 found:
1822         priv->use_count++;
1823
1824         if (phydev->addr == 0) {
1825                 if (ar8xxx_has_gige(priv)) {
1826                         phydev->supported = SUPPORTED_1000baseT_Full;
1827                         phydev->advertising = ADVERTISED_1000baseT_Full;
1828                 } else {
1829                         phydev->supported = SUPPORTED_100baseT_Full;
1830                         phydev->advertising = ADVERTISED_100baseT_Full;
1831                 }
1832
1833                 if (priv->chip->config_at_probe) {
1834                         priv->phy = phydev;
1835
1836                         ret = ar8xxx_start(priv);
1837                         if (ret)
1838                                 goto err_unregister_switch;
1839                 }
1840         } else {
1841                 if (ar8xxx_has_gige(priv)) {
1842                         phydev->supported |= SUPPORTED_1000baseT_Full;
1843                         phydev->advertising |= ADVERTISED_1000baseT_Full;
1844                 }
1845         }
1846
1847         phydev->priv = priv;
1848
1849         list_add(&priv->list, &ar8xxx_dev_list);
1850
1851         mutex_unlock(&ar8xxx_dev_list_lock);
1852
1853         return 0;
1854
1855 err_unregister_switch:
1856         if (--priv->use_count)
1857                 goto unlock;
1858
1859         unregister_switch(&priv->dev);
1860
1861 free_priv:
1862         ar8xxx_free(priv);
1863 unlock:
1864         mutex_unlock(&ar8xxx_dev_list_lock);
1865         return ret;
1866 }
1867
1868 static void
1869 ar8xxx_phy_detach(struct phy_device *phydev)
1870 {
1871         struct net_device *dev = phydev->attached_dev;
1872
1873         if (!dev)
1874                 return;
1875
1876         dev->phy_ptr = NULL;
1877         dev->priv_flags &= ~IFF_NO_IP_ALIGN;
1878         dev->eth_mangle_rx = NULL;
1879         dev->eth_mangle_tx = NULL;
1880 }
1881
1882 static void
1883 ar8xxx_phy_remove(struct phy_device *phydev)
1884 {
1885         struct ar8xxx_priv *priv = phydev->priv;
1886
1887         if (WARN_ON(!priv))
1888                 return;
1889
1890         phydev->priv = NULL;
1891         if (--priv->use_count > 0)
1892                 return;
1893
1894         mutex_lock(&ar8xxx_dev_list_lock);
1895         list_del(&priv->list);
1896         mutex_unlock(&ar8xxx_dev_list_lock);
1897
1898         unregister_switch(&priv->dev);
1899         ar8xxx_mib_stop(priv);
1900         ar8xxx_free(priv);
1901 }
1902
1903 #if LINUX_VERSION_CODE >= KERNEL_VERSION(3,14,0)
1904 static int
1905 ar8xxx_phy_soft_reset(struct phy_device *phydev)
1906 {
1907         /* we don't need an extra reset */
1908         return 0;
1909 }
1910 #endif
1911
1912 static struct phy_driver ar8xxx_phy_driver = {
1913         .phy_id         = 0x004d0000,
1914         .name           = "Atheros AR8216/AR8236/AR8316",
1915         .phy_id_mask    = 0xffff0000,
1916         .features       = PHY_BASIC_FEATURES,
1917         .probe          = ar8xxx_phy_probe,
1918         .remove         = ar8xxx_phy_remove,
1919         .detach         = ar8xxx_phy_detach,
1920         .config_init    = ar8xxx_phy_config_init,
1921         .config_aneg    = ar8xxx_phy_config_aneg,
1922         .read_status    = ar8xxx_phy_read_status,
1923 #if LINUX_VERSION_CODE >= KERNEL_VERSION(3,14,0)
1924         .soft_reset     = ar8xxx_phy_soft_reset,
1925 #endif
1926         .driver         = { .owner = THIS_MODULE },
1927 };
1928
1929 int __init
1930 ar8xxx_init(void)
1931 {
1932         return phy_driver_register(&ar8xxx_phy_driver);
1933 }
1934
1935 void __exit
1936 ar8xxx_exit(void)
1937 {
1938         phy_driver_unregister(&ar8xxx_phy_driver);
1939 }
1940
1941 module_init(ar8xxx_init);
1942 module_exit(ar8xxx_exit);
1943 MODULE_LICENSE("GPL");
1944